TW543091B - Electroless-plating solution and semiconductor device - Google Patents

Electroless-plating solution and semiconductor device Download PDF

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Publication number
TW543091B
TW543091B TW091111514A TW91111514A TW543091B TW 543091 B TW543091 B TW 543091B TW 091111514 A TW091111514 A TW 091111514A TW 91111514 A TW91111514 A TW 91111514A TW 543091 B TW543091 B TW 543091B
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electroless plating
plating solution
semiconductor device
semiconductor substrate
item
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TW091111514A
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Chinese (zh)
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Hiroaki Inoue
Kenji Nakamura
Moriji Matsumoto
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Ebara Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1603—Process or apparatus coating on selected surface areas
    • C23C18/1607—Process or apparatus coating on selected surface areas by direct patterning
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1635—Composition of the substrate
    • C23C18/1637—Composition of the substrate metallic substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1646—Characteristics of the product obtained
    • C23C18/165—Multilayered product
    • C23C18/1653—Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
    • C23C18/34—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/52—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating using reducing agents for coating with metallic material not provided for in a single one of groups C23C18/32 - C23C18/50
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemically Coating (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to an e1ectro1ess-plating solution useful for forming a protective film for selectively protecting the surface of the exposed interconnects of a semiconductor device which has such an embedded interconnect structure that an electric conductor, such as copper or silver, is embedded in fine recesses for interconnects formed in the surface of a semiconductor substrate, and to a semiconductor device in which the surface of the exposed interconnects is selectively protected with a protective film. The e1ectro1ess-plating solution contains cobalt ions, a complexing agent and a reducing agent containing no alkali metal.

Description

543091543091

••五、發明說明（1) -[發明說明] [技術領域] 本發明係有關於無電電 之，本發明係有關於用以形 —裝置之曝露之互連線路表面 置具嵌入之互連線路結構， 入於微細凹部作為形成於例 互連線路，並且係有關於一 連線路表面係藉保護膜作選 [··關技術的說明] 包括以金屬（導電體）充 半導體裝置中用以形成互連 程」已臻實用。根據該製程 之金屬，嵌入預先形成於半 線路溝槽及接觸孔。然後以 餘之金屬，使半導體基板之 鍍溶液及半導體裝置。更詳士 成保護膜而選擇性保護半導^ 之無電電鍍溶液，該半導體穿 其中有諸如銅或銀之導電體^ 如半導體基板之基板表面 種半導體裝置，其中曝露万 擇性保護。 填互連線路溝槽及接觸孔之在 線路之所謂「雙金屬鑲嵌製 1係將链或最近之諸如麵I或銀 導體基板之層間電介質之互連 化學機械式拋光（CMP)去除多 表面平坦化。 近年來，取代作為在半導體基板上形成互連線路電路 之材料之铭或紹合金，明顯的趨勢係使用銅，銅具有低電 阻與高抗電遷移（electr〇migrati〇n resistance)。鋼互包 後路之形成，一般係以銅充填於形成在基板表面之微細 凹部。製造如此之銅互連線路，已知有多種技術，包括化 學氣相沈積（CVD)、漉鍍及電鍍。依據任一方法，均係於 —基板之大致上之整體表面形成鋼膜，再以化學機械式拋 (CMP)去除不必要的銅。 工•• V. Description of the invention (1)-[Explanation of the invention] [Technical field] The present invention relates to non-electricity, and the present invention relates to embedded interconnections on the surface of exposed interconnection lines used to shape-device The circuit structure is formed in a micro-recess as an example of an interconnect line, and the surface of a continuous line is selected by a protective film. [• · Description of the technology] Including metal (conductor) filled semiconductor devices to form "Interconnection" has become practical. According to this process, the metal is embedded in the half-channel trenches and contact holes that are formed in advance. Then, the remaining metal is used to form a plating solution for a semiconductor substrate and a semiconductor device. More specifically, an electroless plating solution that is a protective film and selectively protects semiconductors, such as semiconductors, which include conductors such as copper or silver, such as the surface of a semiconductor substrate, is a semiconductor device in which selective protection is exposed. The so-called "bimetal damascene line 1" that fills interconnect trenches and contact holes in the line is a chemical mechanical polishing (CMP) process that removes multiple surfaces from the chain or the nearest interlayer dielectric such as face I or a silver conductor substrate In recent years, instead of the inscriptions or alloys used as materials for forming interconnection circuits on semiconductor substrates, the obvious trend is to use copper, which has low resistance and high resistance to electromigration. Steel The formation of the back-packing path is generally filled with copper in the fine recesses formed on the surface of the substrate. To manufacture such copper interconnects, various techniques are known, including chemical vapor deposition (CVD), hafnium plating, and electroplating. In either method, a steel film is formed on the substantially entire surface of the substrate, and then unnecessary copper is removed by chemical mechanical polishing (CMP).

313734.ptd 第6頁 543091 五、發明說明（2) 以如此之製程形成互連線路時，平坦化處理之後，嵌 入之互連線路會有曝露之表面。當於如此之半導體基板之 互連線路曝露表面上形成另外的嵌入互連線路結構時，可 能會有以下之問題發生。舉例而言，在次一層間電介質之 形成過程中，於新二氧化矽（Si 02)層之形成當中，預先形 成之互連線路之曝露表面，可能遭到氧化。再者，藉由該 二氧化矽（S i 02)層之蝕刻以形成通孔之際，曝露於通孔底 部之預先形成之互連線路，可能會遭到蝕刻劑、已剝離之 阻劑等之污染。 為防止如此之問題，以往的做法不僅於半導體基板之 表面區域（於其中曝露互連線路），並且於該基板之整個表 面，形成諸如氮化矽（SiN)等之保護膜，藉以避免曝露之 互連線路遭受到蝕刻劑等之污染。 然而，在具有嵌入互連線路結構之半導體裝置中，於 半導體基板之整個表面設置氮化矽（S i N )等之保護膜，會 增加該層間電介質之介電常數，因而即使係使用諸如銅或 銀之低電阻金屬作為互連線路，仍會導致互連線路延遲， 以致使該半導體裝置之功能受損。 基於此一觀點，已有提議，利用與諸如銅或銀之互連 線路材料有良好黏合性並且具有低電阻率（p )之合金膜， 選擇性覆蓋於該曝露之互連線路表面，以保護該互連線 路。例如該合金膜係得自無電電鍍。 然而，藉由無電電鍍提供如此之保護合金膜，會有以 下隨著通常用作無電電鍍中之還原劑之次磷酸鈉而來之問313734.ptd Page 6 543091 V. Description of the invention (2) When an interconnection line is formed by such a process, the embedded interconnection line will have an exposed surface after the flattening process. When another embedded interconnection structure is formed on the exposed surface of the interconnection of such a semiconductor substrate, the following problems may occur. For example, during the formation of the next interlayer dielectric, during the formation of a new silicon dioxide (Si 02) layer, the exposed surface of the pre-formed interconnect may be oxidized. Furthermore, when the silicon dioxide (Si 02) layer is etched to form a via hole, a pre-formed interconnect line exposed at the bottom of the via hole may be exposed to an etchant, a stripped resist, etc. Of pollution. In order to prevent such problems, in the past, a protective film such as silicon nitride (SiN) was formed not only on the surface area of the semiconductor substrate (where the interconnections are exposed), but also on the entire surface of the substrate to avoid exposure. Interconnect lines are contaminated by etchant. However, in a semiconductor device having an embedded interconnect circuit structure, providing a protective film such as silicon nitride (SiN) on the entire surface of the semiconductor substrate will increase the dielectric constant of the interlayer dielectric. Or silver low-resistance metal as the interconnection line will still cause the delay of the interconnection line, so that the function of the semiconductor device is impaired. Based on this point of view, it has been proposed to selectively cover the exposed interconnect surface with an alloy film that has good adhesion to interconnect materials such as copper or silver and has a low resistivity (p) to protect The interconnection. The alloy film is obtained, for example, from electroless plating. However, by providing such a protective alloy film by electroless plating, there are the following problems with sodium hypophosphite which is commonly used as a reducing agent in electroless plating.

J13734.ptd 第7頁 543091 •五、發明說明（3) 題： (1 )還原劑含鈉可能導致該半導體裝置遭受鹼金屬污 染。 (2 )當以次磷酸鈉用作還原劑時，無法對銅等施加氧 1匕電流。為此即須於銅等施以鈀觸媒，因而增加過程步驟 之數目，並且降低生產力 (3 )於銅等施以鈀觸媒，原理係以鈀取代銅等底下之 互連線路，造成互連線路内形成空洞，以致於降低互連線 路之可靠度。 _( 4 )由於鈀本質上係會擴散進入銅等，鈀觸媒之施用 使互連線路之電阻升高。 (5 )除形成互連線路之區域以外，電鍍膜亦有可能沉 積於絕緣膜上，致使選擇性電鍍難以執行。 [發明概要] 本發明係有鑑於習知技術中之以上缺點而完成者。因 此，本發明之目的係在提供一種無電電鍍溶液，其足以形 成僅只選擇性覆蓋互連線路表面之電鍍膜（保護膜），並且 保護該曝露之互連線路，而不導致在互連線路之鹼金屬污 染及空洞之形成，並提供一種半導體裝置，其中曝露之互 線路係以保護膜作選擇性保護。 為能達成以上目的，本發明提供一種無電電鍍溶液， 以於具有嵌入互連線路結構之半導體裝置之曝露之互連線 w路表面，選擇性形成電鍍膜，該無電電鍍溶液含有鈷離 子、錯合劑及不含驗金屬之還原劑。J13734.ptd Page 7 543091 • V. Description of the invention (3) Question: (1) The sodium contained in the reducing agent may cause the semiconductor device to suffer from alkali metal pollution. (2) When sodium hypophosphite is used as a reducing agent, it is not possible to apply a current of oxygen to copper or the like. For this purpose, palladium catalyst must be applied to copper, etc., so the number of process steps is increased, and productivity is reduced. (3) The palladium catalyst is applied to copper, etc. The principle is to replace the interconnection lines under copper with palladium, causing mutual Holes are formed in the connecting lines, so that the reliability of the interconnecting lines is reduced. _ (4) Since palladium will diffuse into copper etc. in essence, the application of palladium catalyst will increase the resistance of the interconnection line. (5) In addition to the area where the interconnections are formed, the plating film may also be deposited on the insulating film, making it difficult to perform selective plating. [Summary of the Invention] The present invention has been made in view of the above disadvantages in the conventional technology. Therefore, the object of the present invention is to provide an electroless plating solution, which is sufficient to form a plating film (protective film) that only selectively covers the surface of an interconnection line, and protects the exposed interconnection line without causing a problem in the interconnection line. Alkali metal pollution and the formation of voids, and a semiconductor device is provided in which the exposed interconnections are selectively protected with a protective film. In order to achieve the above object, the present invention provides an electroless plating solution for selectively forming a plating film on an exposed surface of an interconnect line of a semiconductor device having an embedded interconnect circuit structure. The electroless plating solution contains cobalt ions, Mixture and metal-free reducing agent.

313734.ptd 第8頁 543091 五、發明說明（4) 不含鹼金屬之還原劑之使用，可以避免該半導體裝置 遭到驗金屬之污染。 烷基胺硼烷可以使用作為不含鹼金屬之還原劑。如此 的還原劑之使用，導致施加氧化電流於銅或銅合金，或於 銀或銀合金成為可能，如此即可進行直接電鍍。再者，不 含鈉的烷基胺硼烷之使用，可以避免該半導體裝置遭受到 鹼金屬之污染，並且使得不需使用鈀觸媒的無電電鍍之施 行成為可能。 烷基胺硼烷之具體實例有，二曱基胺基硼烷、二乙基 胺基硼烷及三甲基胺基硼烷。 該無電電鍍溶液可進而含有至少一安定劑，其係選自 重金屬化合物及硫化合物、以及界面活性劑之其中之一種 或更多種。 較佳者為，使用不含鹼金屬之pH調整劑調整該無電電 鍍溶液之pH為在於5至14之範圍以内。不含鹼金屬之pH調 整劑，諸如氨水或氫氧化四級銨之使用，可以維持該電鍍 溶液不含鈉。較佳者為，該電鍍溶液之p Η係在6至1 0。 本發明復提供一種無電電鍍溶液，以於具有嵌入互連 線路結構之半導體裝置之曝露之互連線路表面，選擇性形 成電鍍膜，該無電電鍍溶液含有鈷離子、錯合劑、含耐火 金屬之化合物以及不含鹼金屬之還原劑。 至少鎢及鉬之其中之一可以用作該耐火金屬。該還原 劑可用烷基胺硼烷。藉由如此的化合物之使用，該無電電 鍍溶液可提供鈷-鎢-硼（Co-W-B)合金、鈷-鉬-硼313734.ptd Page 8 543091 V. Description of the Invention (4) The use of a reducing agent that does not contain an alkali metal can prevent the semiconductor device from being contaminated by a metal test. Alkylamine borane can be used as a reducing agent which does not contain an alkali metal. The use of such a reducing agent makes it possible to apply an oxidizing current to copper or a copper alloy, or to silver or a silver alloy, so that direct plating can be performed. Furthermore, the use of an alkylamine borane that does not contain sodium can prevent the semiconductor device from being contaminated with alkali metals, and makes it possible to perform electroless plating without using a palladium catalyst. Specific examples of the alkylamine borane include diamidoaminoborane, diethylaminoborane, and trimethylaminoborane. The electroless plating solution may further contain at least one stabilizer, which is one or more selected from the group consisting of a heavy metal compound and a sulfur compound, and a surfactant. Preferably, the pH of the electroless plating solution is adjusted to be within a range of 5 to 14 by using a pH adjusting agent containing no alkali metal. The use of an alkali-free pH adjuster, such as ammonia or quaternary ammonium hydroxide, can maintain the plating solution free of sodium. Preferably, p Η of the plating solution ranges from 6 to 10. The invention further provides an electroless plating solution for selectively forming a plating film on the surface of an exposed interconnect circuit of a semiconductor device having an embedded interconnect structure. The electroless plating solution contains cobalt ions, a complexing agent, and a compound containing a refractory metal. And reducing agents that do not contain alkali metals. At least one of tungsten and molybdenum can be used as the refractory metal. As the reducing agent, an alkylamine borane can be used. By using such a compound, the electroless plating solution can provide cobalt-tungsten-boron (Co-W-B) alloy, cobalt-molybdenum-boron

313734.ptd 第9頁 543091 •五、發明說明（5) (Co -Mo-B)合金或钻-钥-鶴-侧（Co-Mo-W-B)合金之保護 膜，以之覆蓋於曝露之互連線路表面。 、 本發明復提供一種半導體裝置，具有銅、銅合金、銀 或銀合金之嵌入互連線路結構，其中曝露互連線路之表面 1系以保護膜選擇性覆蓋，該保護膜係藉由使用無電電鍍溶 液之無電電鍍過程形成，該過程所用之無電電鍍溶液含有 姑離子、錯合劑及不含驗金屬之還原劑。 因此藉由選擇性覆蓋互連線路之表面，並且以與銅或 銀有良好黏合性並且具有低電阻率（P )之合金保護膜，保 ιφ該互連線路，得以抑制具有嵌入互連線路結構之半導體 裝置之層間電介質之介電常數之升高。再者，以低電阻材 料諸如銀或銅使用作互連線路材料，得以獲致該半導體之 高速化以及高密度化。 本發明復提供一種半導體裝置，具有嵌入互連線路結 構，其中曝露之互連線路表面係以包括鈷之金屬保護膜選 擇性覆蓋。較佳者為，該金屬膜之厚度係在0. 1至5 0 0奈米 之範圍内。 本發明復提供一種半導體裝置，具有嵌入互連線路結 構，其中曝露之互連線路之表面係以包括鈷及耐火金屬之 保護膜作選擇性覆蓋。較佳者為，該耐火金屬係鎢及 鉬之至少其中之一。 本發明提供一種半導體裝置之製造方法，包括：以無 ，電鍍溶液於具有嵌入互連線路結構之半導體基板上進行 無電電鑛’以於該半導體基板之互連線路表面上選擇性形313734.ptd Page 9 543091 • V. Description of the invention (5) (Co-Mo-B) alloy or diamond-key-crane-side (Co-Mo-WB) alloy protective film to cover the exposed mutual Even the surface of the line. The present invention further provides a semiconductor device having a copper, copper alloy, silver, or silver alloy embedded interconnect circuit structure, wherein the surface 1 of the exposed interconnect circuit is selectively covered with a protective film, which is used by using no electricity The electroless plating process of the plating solution is formed. The electroless plating solution used in this process contains ions, complexing agents, and reducing agents that do not contain metal. Therefore, by selectively covering the surface of the interconnection line, and protecting the interconnection line with an alloy protective film that has good adhesion to copper or silver and has a low resistivity (P), the embedded interconnection line structure can be suppressed. The dielectric constant of the interlayer dielectric of a semiconductor device is increased. Furthermore, the use of a low-resistance material such as silver or copper as an interconnect circuit material can achieve high-speed and high-density semiconductors. The present invention further provides a semiconductor device having an embedded interconnection structure, wherein the exposed surface of the interconnection is selectively covered with a metal protective film including cobalt. Preferably, the thickness of the metal film is in the range of 0.1 to 500 nm. The present invention further provides a semiconductor device having an embedded interconnection structure, wherein the exposed surface of the interconnection is selectively covered with a protective film including cobalt and refractory metal. Preferably, the refractory metal is at least one of tungsten and molybdenum. The present invention provides a method for manufacturing a semiconductor device, which comprises: performing electroless mining on a semiconductor substrate having an embedded interconnection circuit structure with an electroless plating solution to selectively shape the surface of the interconnection circuit of the semiconductor substrate.

313734.ptd 第10頁 543091 五、發明說明（6) 成電鍍膜保護層；其中該無電電鍍溶液包含鈷離子、錯合 劑及不含驗金屬之還原劑。 本發明復提供一種半導體裝置之製造方法，包括··以 無電電鍍溶液於具有嵌入互連線路結構之半導體基板上進 行無電電鍍，以於該半導體基板之互連線路表面上選擇性 形成電鍍膜保護層；其中該無電電鍍溶液含有鈷離子、錯 合劑、含耐火金屬之化合物及不含驗金屬之還原劑。 合金之實例包含，鈷-硼（Co-B)合金、鈷-磷（Co-P)合 金、錄-鶴-((]〇-W-B)合金、始-鎢-领（Co-W-P)合金、钻 -钥-侧（C〇_Mo-B)合金、姑-1目-填（C〇-Mo-P)合金、钻-鎮_ 鉬-硼（Co-W-Mo-B)合金、鈷-鎢-鉬-磷（Co-W-Mo-P)合金、 鈷-鈦-硼（Co-Ti-B)合金、鈷-鈦-磷（Co-Ti-P)合金、鈷-鈕-硼（Co-Ta-B)合金、鈷-钽-磷（Co-Ta-P)合金、鈷-鈦-鈕-硼（Co-Ti-Ta-B)合金、鈷-鈦-鈕-磷（Co-Ti-Ta-P)合 金、鈷-鈦-鎢-硼（C〇-T i - W - B )合金、鈷-鈦-鎢-磷 (Co-Ti-W-P)合金、始-鈦-鉑-调（Co-Ti-Mo-B)合金、銘-鈦-鉑-構（Co-Ti-Mo-P)合金、钻-鈦-组-侧（Co-Ti-Ta-B) 合金、始-鈦-组-填（Co-Ti-Ta-P)合金、始-組-鶴-彌 (Co-Ta-W-B)合金、钻-组-鶴-礙（Co-Ta-W-P)合金、钻-#旦 -鉬-硼（Co-Ta-Mo-B)合金、鈷-钽-鉬-磷（Co-Ta-M〇-P)合 金、始-鈦-鶴-鉬-蝴（Co-Ti-W-Mo-B)合金、錄-钦-鶴-鉑-石粦（Co-Ti-W-Mo_P)合金、钻-组-鶴-顧-爛（Co-Ta_W-Mo-B) 合金、钻-组-鎢-鉬-鱗（Co-Ta-W-Mo-P)合金、钻-鈦-组-鎢-鉬-硼（Co-Ti-Ta-W-Mo-B)合金以及鈷-鈦-鈕-鎢-鉬-磷313734.ptd Page 10 543091 V. Description of the invention (6) Forming a plating film protective layer; wherein the electroless plating solution contains cobalt ions, a complexing agent, and a reducing agent containing no metal test. The present invention further provides a method for manufacturing a semiconductor device, which includes: performing electroless plating on a semiconductor substrate having an embedded interconnection circuit structure with an electroless plating solution to selectively form a plating film protection on the surface of the interconnection circuit of the semiconductor substrate Layer; wherein the electroless plating solution contains cobalt ions, a complexing agent, a compound containing a refractory metal, and a reducing agent not containing a test metal. Examples of alloys include cobalt-boron (Co-B) alloy, cobalt-phosphorus (Co-P) alloy, Lu-Crane-(() 〇-WB) alloy, starting-tungsten-collar (Co-WP) alloy, Drill-key-side (C〇_Mo-B) alloy, Gu-1 mesh-filled (C〇-Mo-P) alloy, drill-town _ molybdenum-boron (Co-W-Mo-B) alloy, cobalt -Tungsten-molybdenum-phosphorus (Co-W-Mo-P) alloy, cobalt-titanium-boron (Co-Ti-B) alloy, cobalt-titanium-phosphorus (Co-Ti-P) alloy, cobalt-button-boron (Co-Ta-B) alloy, cobalt-tantalum-phosphorus (Co-Ta-P) alloy, cobalt-titanium-button-boron (Co-Ti-Ta-B) alloy, cobalt-titanium-button-phosphorus (Co -Ti-Ta-P) alloy, cobalt-titanium-tungsten-boron (Co-Ti-W-B) alloy, cobalt-titanium-tungsten-phosphorus (Co-Ti-WP) alloy, starting-titanium-platinum -Co-Ti-Mo-B alloy, Ming-titanium-platinum-structure (Co-Ti-Mo-P) alloy, diamond-titanium-group-side (Co-Ti-Ta-B) alloy, starting -Titanium-Group-Fill (Co-Ti-Ta-P) alloy, Start-Group-Crane-Mi- (Co-Ta-WB) alloy, Diamond-Group-Crane-Co-Co-Ta-WP alloy, Diamond -# Denier-molybdenum-boron (Co-Ta-Mo-B) alloy, cobalt-tantalum-molybdenum-phosphorus (Co-Ta-Mo-P) alloy, starting-titanium-crane-molybdenum-butterfly (Co-Ti -W-Mo-B) alloy, Lu-Qin-he-platinum-stone (Co-Ti-W-Mo_P) alloy, diamond-group-he-gu-rot (Co-Ta_W-Mo-B) alloy, Diamond-group-tungsten-molybdenum-scale (Co-Ta-W-Mo-P) alloy, diamond-titanium-group-tungsten-molybdenum-boron (Co-Ti-Ta-W-Mo-B) alloy and cobalt- Titanium-button-tungsten-molybdenum-phosphorus

313734.ptd 苐11頁 543091 ‘ ·五、發明說明（7) -(Co -Ti-Ta-W-Mo-P)合金。 [較佳實施例之詳細說明] - 以下參照圖式說明本發明之較佳實施例。 第1 A至1 C圖以一系列製程步驟說明在本發明之半導體 裝置内形成銅互連線路之實例。如第1 A圖所示，在導體層 la上沉積二氧化碎（Si〇2)之絕緣膜2，該導體層係形成 .於搭，半導體裝置之半導體基底1之上。於該絕緣膜2内藉 ^微衫、/ ϋ刻技術，形成用以構成互連線路之接觸孔3及溝 °然後’於全體表面上形成氮化钽（TaN)等材質之阻障 暑5 ’、並於該阻障層5之上以濺鍍等方法形成銅晶種層6， 其作為電鍍中之供電層。 +之後’如第圖所示，於半導體基板W之表面上施以 =甩鍍，以將銅充填於該接觸孔3及該溝槽4，同時，於該 去^獏2上、'儿積銅膜7。然後，藉由化學機械式拋光（CMP) 線* σ亥纟巴緣膜2上之該鋼膜7及該阻障層5，以使用於互連 而路之填充在該接觸孔3内及該溝槽4内之該銅獏7之表 圖所與該絕緣膜2之表面大致上位於同一平面内。如第1C 不，由該銅晶種層6以及該銅膜7所構成之互連線路8 又面’因此形成於該絕緣膜2内。 、 二·其次，於該半導體基板W表面上施以無電電鍍，以於 j互連線路8之曝露表面上選擇性形成保護膜9，其係由合 金螟構成，藉以保護該互連線路8。該保護膜9之厚产一二 至5 0 0奈米’較佳者為1至20 0奈采’更佳:;10】 543091 五、發明說明（8) 例如，該保護膜9之形成係利用含鈷離子、錯合劑、p Η緩衝劑、ρ Η調整劑及作為還原劑之烷基胺硼烷之電鍍溶 液，或更含有諸如鎢及鉬之耐火（高熔點）金屬之電鍍溶 液’並將該半導體基板W之表面浸入該電鐘溶液中。 若有必要時，該電鍍溶液可更包含至少一種安定劑， 其係選自重金屬化合物及硫化合物、以及界面活性劑之其 中一種或更多種。再者，該電鍍溶液係例用諸如氨水或四 級銨氫氧化物之ρ Η調整劑，將ρ Η調整於較佳者為5至1 4， 更佳者為6至1 0之範圍内。該電鍍溶液之溫度通常係在3 0 °C至9 0 °C，較佳者為在4 0 °C至8 0 °C之範圍内。 利用該保護膜9之設置以保護該互連線路8即可避免在 次一層間電介質之形成過程中，於其上另再形成一嵌入互 連線路結構之際，在形成一層新的二氧化矽（S i 0 2)當中， 該互連線路表面遭到氧化，並且在該二氧化矽（S i 02)層之 蝕刻當中，避免該互連線路遭受蝕刻劑、剝落之阻劑等之 污染。313734.ptd 页 page 11 543091 ‘Fifth, the description of the invention (7)-(Co -Ti-Ta-W-Mo-P) alloy. [Detailed description of preferred embodiments]-The following describes preferred embodiments of the present invention with reference to the drawings. Figures 1A to 1C illustrate an example of forming copper interconnects in a semiconductor device of the present invention in a series of process steps. As shown in FIG. 1A, an insulating film 2 of silicon dioxide (SiO2) is deposited on a conductor layer 1a, and the conductor layer is formed on a semiconductor substrate 1 of a semiconductor device. In this insulating film 2, micro-shirts and / or engraving techniques are used to form contact holes 3 and trenches for forming interconnect lines, and then a barrier material 5 such as tantalum nitride (TaN) is formed on the entire surface. ', And a copper seed layer 6 is formed on the barrier layer 5 by sputtering or the like as a power supply layer in electroplating. + After ', as shown in the figure, == plating is applied on the surface of the semiconductor substrate W to fill copper in the contact hole 3 and the trench 4, and at the same time, on the surface ^ 2, the铜 膜 7。 Copper film 7. Then, the steel film 7 and the barrier layer 5 on the σ hem line 2 are filled with the chemical mechanical polishing (CMP) line in the contact hole 3 and the The surface of the copper cymbal 7 in the trench 4 and the surface of the insulating film 2 are substantially in the same plane. As in 1C, the interconnection line 8 composed of the copper seed layer 6 and the copper film 7 is formed on the insulating film 2 again. Second, secondly, electroless plating is applied to the surface of the semiconductor substrate W to selectively form a protective film 9 on the exposed surface of the j interconnection line 8, which is composed of an alloy tin to protect the interconnection line 8. The protective film 9 has a thickness of 12 to 500 nanometers, preferably 1 to 200 nanometers, and more preferably; 10] 543091 V. Description of the invention (8) For example, the formation system of the protective film 9 Use a plating solution containing cobalt ions, a complexing agent, a p Η buffer, a ρ Η modifier, and an alkylamine borane as a reducing agent, or a plating solution containing refractory (high melting point) metals such as tungsten and molybdenum 'and The surface of the semiconductor substrate W is immersed in the electric clock solution. If necessary, the plating solution may further include at least one stabilizer, which is one or more selected from the group consisting of a heavy metal compound and a sulfur compound, and a surfactant. In addition, the electroplating solution is exemplified by a pH adjusting agent such as ammonia or quaternary ammonium hydroxide, and ρ ρ is adjusted in the range of preferably 5 to 14 and more preferably 6 to 10. The temperature of the plating solution is usually in the range of 30 ° C to 90 ° C, preferably in the range of 40 ° C to 80 ° C. By using the protection film 9 to protect the interconnection 8, it is possible to avoid forming a new layer of silicon dioxide during the formation of the next interlayer dielectric when another embedded interconnection structure is formed thereon. In (S i 0 2), the surface of the interconnection line is oxidized, and the etching of the silicon dioxide (S i 02) layer prevents the interconnection line from being polluted by an etchant, a peeling resist, and the like.

使用含有鈷離子、錯合劑、pH緩衝劑、pH調整劑以及 作為還原劑之烷基胺硼烷之電鍍溶液，提供鈷-硼（Co-B) 合金膜之保護臈9。利用更含有諸如鎢及鉬之耐火金屬之 電鍍溶液，提供鈷-鎢-硼（Co-W-B)合金膜、鈷-鉬-硼（Co-Mo-B)合金膜或姑-翻-鶴-蝴（Co-Mo-W-B)合金膜之保護膜 9 Q 藉由選擇性覆蓋該互連線路8之表面，並以諸如作為 互連線路材料之對銅具有高度黏合性而且具有低電阻率 （A plating solution containing cobalt ions, a complexing agent, a pH buffering agent, a pH adjusting agent, and an alkylamine borane as a reducing agent is used to provide protection for a cobalt-boron (Co-B) alloy film. 9 Cobalt-tungsten-boron (Co-WB) alloy film, cobalt-molybdenum-boron (Co-Mo-B) alloy film, or gu-turn-crane-butterfly The protective film 9 Q of the (Co-Mo-WB) alloy film selectively covers the surface of the interconnection line 8, and has high adhesion to copper and low resistivity (such as the material of the interconnection line).

313734.ptd 第13頁 543091 •五、發明說明（9) p )之合金膜作為該保護膜9以保護該互連線路8，故得 以抑制具有嵌入互連線路結構之半導體裝置之層間電介質 之介電常數之升高。再者，使用低電阻材料之銅作為互連 線路材料，得以獲致該半導體之高速化以及高密度化。 • 此實例雖係呈示使用銅作為互連線路材料，但亦可用 銅合金、銀或銀合金。 電鍍溶液中所含之鈷離子，可係得自鈷鹽例如硫酸 録、氯化钻或醋酸始。銘離子之含量，通常係在0.001至1 莫耳/公升，較佳者係在0. 0 1至0. 3莫耳/公升之範圍内。 _ 錯合劑之具體例可包含羧酸，諸如醋酸及其鹽類；含 氧羧酸，諸如酒石酸及檸檬酸，及其鹽類；以及氨基含氧 羧酸，諸如氨基醋酸，及其鹽類。這些化合物可以單獨使 用或以二種或以上之混合物使用。該錯合劑之總量一般係 在0 . 0 0 1至1 . 5莫耳/公升，較佳者係在0 . 0 1至1 . 0莫耳/公 升。 至於ρ Η緩衝劑，可使用不含納或其任何它驗金屬之任 何缓衝劑。具體例可舉硫酸銨、氣化銨以及硼酸。該Ρ Η緩 衝劑之用量，通常係在0. 01至1. 5莫耳/公升，較佳者係在 0. 1至1莫耳/公升。 籲至於ρ Η調整劑，可使用不含鈉或其任何它鹼金屬之 任何調整劑。具體例可舉氨水以及氫氧化四曱基銨 （TM A Η )。藉由ρ Η調整劑之使用，該電鍍溶液之ρ Η —般係調整於5 _至14，較佳者為6至10之範圍内。 同樣，該還原劑亦應不含納或任何其它驗金屬。較佳313734.ptd Page 13 543091 • V. The alloy film of the invention description (9) p) is used as the protective film 9 to protect the interconnection line 8, so the dielectric of the interlayer dielectric of the semiconductor device with embedded interconnection structure can be suppressed. Increase of electric constant. Furthermore, the use of copper, which is a low-resistance material, as the material of the interconnection circuit, can achieve high-speed and high-density semiconductors. • Although this example shows the use of copper as the interconnect material, copper alloys, silver, or silver alloys can also be used. The cobalt ions contained in the plating solution may be derived from a cobalt salt such as sulfuric acid, chloride or acetic acid. The content of the ions is usually in the range of 0.001 to 1 mole / liter, and preferably in the range of 0.01 to 0.3 mole / liter. Specific examples of the complexing agent may include carboxylic acids such as acetic acid and salts thereof; oxycarboxylic acids such as tartaric acid and citric acid and salts thereof; and amino oxycarboxylic acids such as aminoacetic acid and salts thereof. These compounds may be used alone or as a mixture of two or more. The total amount of the complexing agent is generally from 0.01 to 1.5 mol / liter, and more preferably from 0.01 to 1.0 mol / liter. As for the p Η buffer, any buffer containing no sodium or any other metal can be used. Specific examples include ammonium sulfate, gasified ammonium, and boric acid. The dosage of the PΗ buffer is usually in the range of 0.01 to 1.5 mol / liter, and more preferably in the range of 0.1 to 1 mol / liter. As for the ρ Η adjusting agent, any adjusting agent containing no sodium or any other alkali metal can be used. Specific examples include ammonia and tetramethylammonium hydroxide (TM A Η). With the use of the ρ Η adjusting agent, the ρ Η of the plating solution is generally adjusted in the range of 5 to 14 and preferably in the range of 6 to 10. Similarly, the reducing agent should also be free of sodium or any other metal detection. Better

313734.ptd 第14頁 543091 五、發明說明（ίο) 者係使用烷基胺硼烷。如同烷基胺硼烷，可提到二甲基胺 硼烷（D M A B )以及二乙基胺硼烷。該還原劑之用量，通常 係在0. 01至1莫耳/公升，較佳者係在0. 0 1至0. 5莫耳/公 升。 含耐火金屬之化合物之實例可包括鎮酸、鉑酸、及其 鹽類；以及異多體酸，諸如鎢磷酸（例如，H3(PW12P4Q) ·313734.ptd Page 14 543091 5. The description of the invention (ίο) uses alkylamine borane. As the alkylamine borane, mention may be made of dimethylamine borane (DMBA) and diethylamine borane. The amount of the reducing agent is usually in the range of 0.01 to 1 mole / liter, and more preferably in the range of 0.01 to 0.5 mole / liter. Examples of the refractory metal-containing compound may include sulphuric acid, platinum acid, and salts thereof; and heteropolyacids such as tungsten phosphoric acid (for example, H3 (PW12P4Q) ·

ηΗ20)、及其鹽類。而當該保護膜並非以無電電鍍形成 時，鈦（丁 i )或钽（Ta )亦可使用。含耐火金屬之化合物，其 用量通常係在（K 0 0 1至1莫耳/公升，較佳者係在0. 0 1至0. 1 莫耳/公升。始/对火金屬合金之實例包含，钻-(Co-B) 合金、始-構（Co-P)合金、始-鶴-调（Co-W-B)合金、钻-鶴 -磷（Co-W-P)合金、鈷-鉬-硼（Co-Mo-B)合金、鈷-鉬-磷（ Co-Mo-P)合金、钻-鶴-钥-刪（Co-W-Mo-B)合金、始-鶴-钥 -罐（Co-W-Mo-P)合金、銘-钦-碼（Co-Ti-B)合金、始-欽_ 石粦（Co-Ti-P)合金、钻-组-侧（Co-Ta-B)合金、始-组-鱗（C -Ta-P)合金、钻-欽-组-爛（Co-Ti-Ta-B)合金、銘-款-组_ 石粦（Co-Ti-Ta-P)合金、始-欽-鶴-觸（Co-Ti-W-B)合金、始 -欽-鶴-構（Co-Ti-W-P)合金、姑-欽-钥-獨（Co-Ti-Mo-B) 合金、始-欽-钥-填（Co-Ti-Μ〇-P)合金、始-欽-组-哪（Co-Ti-Ta-B)合金、钻-鈦-組-填（Co-Ti-Ta-P)合金、始-组-鎢-硼（Co-Ta-W-B)合金、鈷-钽-鎢-磷（Co-Ta-W-P)合金、 始-组-鉬-删（Co-Ta-Mo - B)合金、始-！巨-鉬-填（C〇-Ta-M〇-P)合金、姑-欽-鶴-顧-侧（Co-Ti-W_Mo-B)合金、録-欽-嫣 一 I目一填（Co— 丁 i—W — M〇一P)合金、- Μ -m -m (Co-Ta-W-MηΗ20), and salts thereof. When the protective film is not formed by electroless plating, titanium (butyl i) or tantalum (Ta) can also be used. The amount of the refractory metal-containing compound is usually in the range of (K 0 0 1 to 1 mol / liter, more preferably in the range of 0.01 to 0.1 mol / liter. Examples of the starting / pairing metal alloy include , Diamond- (Co-B) alloy, starting-structural (Co-P) alloy, starting-crane-tuned (Co-WB) alloy, drill-crane-phosphorus (Co-WP) alloy, cobalt-molybdenum-boron ( Co-Mo-B) alloy, cobalt-molybdenum-phosphorus (Co-Mo-P) alloy, drill-crane-key-delete (Co-W-Mo-B) alloy, starting-crane-key-can (Co-Mo-B) W-Mo-P) alloy, Ming-Qin-code (Co-Ti-B) alloy, Si-Qin _ Shi-Jun (Co-Ti-P) alloy, drill-group-side (Co-Ta-B) alloy , Beginning-group-scale (C-Ta-P) alloy, diamond-Qin-group-rotten (Co-Ti-Ta-B) alloy, inscription-section-group _ shichang (Co-Ti-Ta-P) Alloy, Si-Qin-Crane-Contact (Co-Ti-WB) alloy, Si-Qin-Crane-structural (Co-Ti-WP) alloy, Gu-Qin-Key-Duo (Co-Ti-Mo-B) Alloy, Si-Chin-Key-Fill (Co-Ti-Mo-P) alloy, Si-Chin-Group-Wh (Co-Ti-Ta-B) alloy, Diamond-Titanium-Group-Fill (Co-Ti -Ta-P) alloy, starting-group-tungsten-boron (Co-Ta-WB) alloy, cobalt-tantalum-tungsten-phosphorus (Co-Ta-WP) alloy, starting-group-molybdenum-deleted (Co-Ta -Mo-B) alloy, starting-! Giant-molybdenum-filling (C〇-Ta-M〇-P) Alloy, Gu-Qin-He-Gu-Side (Co-Ti-W_Mo-B) alloy, Lu-Qin-Yan-Yi I head and one fill (Co—Ding i—W—M〇—P) alloy,-Μ- m -m (Co-Ta-WM

J13734.ptd 第15頁 543091 •五、發明說明（11) -〇-B)合金 '姑-组-鶴_钥-石粦（C〇 -Ta-W-M〇_P)合金、銘-欽-组-i鳥-姻-刪（Co-Ti-Ta-W-Mo-B)合金及始-欽-组-鶴-翻-，_石粦（Co-Ti-Ta-W-Mo-P)合金。這些之中，依據本發明，較 佳係以使用含鎢及/或鉬之合金於無電電鍍。目前使用含 •硼烷或螢光物質的合金，因其不含鹼金屬。含鈦（Ti)或鈕 (丁 a)之合金，可用於無電電鍍以外之製程。 除上述化合物之外，可將其它已知添加劑添加於該電 鍍溶液。有用的添加劑之實例包括電鍍浴安定劑，其可係 一種重金屬化合物，諸如錯化合物，例如硫代氰酸鹽之硫 合物，或其混合物，以及一種陰離子型、陽離子型或非 離子型界面活性劑。 如上所述，較佳者為使用不含納之烧基胺烧作為還 原劑。烧基胺烧之使用，即可於銅、銅合金、銀或銀合 金施加氧化電流，得以無須導入鈀觸媒，因而使直接無電 電鍍之施行成為可能，並能避免該半導體裝置遭受到鹼金 屬之污染。如此，使用烧基胺烧作為還原劑之該無電電 鍍溶液，使得不導入鈀觸媒，僅藉由將該半導體裝置的表 面浸入該電鍍溶液而進行無電電鍍成為可能。此有助於減 少所須的製程步驟，並提高生產力，避免鈀觸媒所導致之 4該銅互連線路内空洞之形成，並避免鈀擴散所導致之互 連線路處電阻之升高。 再者，亦發現當使用以含烧基胺烧作為還原劑之電 .鍍溶液而施行無電電鍍時，該電鍍膜可選擇性沉積於銅或 銀上。此即使得僅於互連線路區域作選擇性電鍍成為可J13734.ptd Page 15 543091 • V. Description of the invention (11) -〇-B) Alloy 'Gu-Group-Crane-Key-Shiyan (C〇-Ta-WM〇_P) alloy, Ming-Qin-group -i-bird-marriage-deletion (Co-Ti-Ta-W-Mo-B) alloy and Shi-Qin-Group-Crane-Turn-, _Shiyao (Co-Ti-Ta-W-Mo-P) alloy . Among these, according to the present invention, it is preferable to use an alloy containing tungsten and / or molybdenum for electroless plating. Alloys containing borane or fluorescent substances are currently used because they do not contain alkali metals. Alloys containing titanium (Ti) or button (a) can be used in processes other than electroless plating. In addition to the above compounds, other known additives may be added to the plating solution. Examples of useful additives include electroplating bath stabilizers, which can be a heavy metal compound, such as a compound, such as a thiocyanate sulfide, or a mixture thereof, and an anionic, cationic, or nonionic interface activity Agent. As described above, it is preferable to use sodium sulfonylamine as a reducing agent. The use of sintered amines can apply an oxidation current to copper, copper alloys, silver, or silver alloys, without the need to introduce a palladium catalyst, thereby enabling the implementation of direct electroless plating and avoiding the semiconductor device from alkali metals. Of pollution. In this way, the electroless plating solution using sintered amine as a reducing agent makes it possible to perform electroless plating by only immersing the surface of the semiconductor device in the plating solution without introducing a palladium catalyst. This helps reduce the required process steps and improves productivity, avoids the formation of voids in the copper interconnects caused by palladium catalysts, and avoids the increase in resistance at interconnected lines caused by palladium diffusion. Furthermore, it was also found that when electroless plating is performed using an electroplating solution containing a sintered amine as the reducing agent, the electroplated film can be selectively deposited on copper or silver. This makes selective plating possible only in the interconnect area.

313734.ptd 第16頁 543091 五、發明說明（12) 能0 第2圖係無電電鍍設備之構造示意圖。如第2圖所示， 此無電電鍍設備包括固持裝置丨丨，用以固持半導體基板w 於其上表面；堤堰構件（電鍍溶液保持機構）3 i，用以接觸 ，=電鍍之半導體基板W (其以固持裝置丨丨固持以封住周緣 部分）表面（上面表）之周緣部份；以及淋灑頭（一種無電電 錢/谷液（散佈）供給裝置）4 1 ’用以供給電鑛溶液（一種無電 電鍍溶液）於欲予電鍍之該半導體基板w之表面，該半導體 基板之周緣部份以该堤堰構件3 1密封。該無電電鑛設備復 包括，清洗液供給裝置5 1，設置在該固持裝置1 1之上方外 部周緣，用以供給清洗液於欲予電鍍之該半導體基板W之 表面，回收桶61’用以回收棄置之清洗液或其它（電鍍廢 液）；電鍍溶液回收嘴6 5，用以吸取並回收保持於該半導 體基板W上之電鍍溶液；以及馬達（旋轉驅動裝置）μ，用 以旋轉地驅動該固持裝置11。 該固持裝置11於其上表面上具有基板放置部13，用以 放置並固持該半導體基板W。該基板放置部1 3係設置成可 以放置並固定該半導體基板W。詳言之，該基板放置部13 具有真空吸引機構（未顯示），用以藉由真空吸引將該半導 體基板W吸引至其背面上。於該基板放置部1 3之背面上設 置有背面加熱器（加熱裝置）1 5 ’其係平面狀，可對該半導 體基板W之欲予電鍍之表面，從下方加熱而予以保溫。該 背面加熱器1 5，係由例如橡膠加熱器所構成。此固持裝置 11係設置成可以由馬達从旋轉’並藉由升降裝置（未顯示）313734.ptd Page 16 543091 V. Description of the invention (12) Energy 0 The second diagram is a schematic diagram of the structure of electroless plating equipment. As shown in FIG. 2, this electroless plating equipment includes a holding device 丨 丨 for holding the semiconductor substrate w on its upper surface; a bank member (plating solution holding mechanism) 3 i for contacting, = the plated semiconductor substrate W ( It uses a holding device 丨 丨 holding to seal the peripheral edge part) of the surface (above table) of the peripheral edge part; and a shower head (a type of non-electricity electricity / grain liquid (dispersion) supply device) 4 1 'for supplying the electric mining solution (An electroless plating solution) On the surface of the semiconductor substrate w to be plated, a peripheral portion of the semiconductor substrate is sealed with the bank member 31. The electroless power mining equipment further includes a cleaning liquid supply device 51 provided on the outer periphery above the holding device 11 for supplying the cleaning liquid to the surface of the semiconductor substrate W to be plated, and a recovery barrel 61 ′ for Recovery of discarded cleaning liquid or other (electroplating waste liquid); electroplating solution recovery nozzle 65 for sucking and recovering the electroplating solution held on the semiconductor substrate W; and a motor (rotary driving device) μ for rotationally driving The holding device 11. The holding device 11 has a substrate placing portion 13 on an upper surface thereof for placing and holding the semiconductor substrate W. The substrate placing portion 13 is provided so that the semiconductor substrate W can be placed and fixed. In detail, the substrate placing portion 13 has a vacuum suction mechanism (not shown) for suctioning the semiconductor substrate W to its back surface by vacuum suction. A back surface heater (heating device) 15 'is provided on the back surface of the substrate placement portion 13 and is flat, and the surface of the semiconductor substrate W to be plated can be heated from below to be insulated. The back heater 15 is made of, for example, a rubber heater. This holding device 11 is provided so that it can be rotated by a motor 'and by a lifting device (not shown)

313734.ptd 第17頁 543〇9i 五、發明說明（13) 可以垂直移動。 該堤堰構件3 1係圓筒狀，有設置於其下部之密封部 、33 ’用以密封該半導體基板w之外部周緣，並係設置成無 .法自圖示之位置垂直移動。 該淋灑頭4 1之構造係於前端設置有許多喷嘴，用以將 所供給之電鍍溶液散佈成淋灑狀，並以大致上均勻的方式 供給於該半導體基板W之欲予電鍍之表面。該清洗液供給 裝置51具有從該喷嘴53噴出清洗液之構造。 該電鑛溶液回收嘴65，係設置成玎以上下移動並搖 籲，且該電錢溶液回收嘴65之前端係設置成向内低於位於 該半導體基板w之上表面周緣部分之該堤堰構件3丨，並且 用以吸取在該半導體基板界上之電鍍溶液。 其次’說明該無電電鐘設借夕姐} 私艰°又侑之刼作。第一，將該固捭 裝置1 1自圖示狀態下降，以於兮固姓姑班M t 付 %巧固持裝置11與該堤堰構侔 3 1之間形成預先選定大小之間隙，*收上、# 舟1干 ^ ^ t 间|糸亚將半導體基板w放置 與固定在該基板放置部1 3上。例‘ 0 ^ 工例如以8英吋晶圓用作半導 體基板W。 τ守 然後，升高該固持裝置U，以祐甘l ^ Μ使其上表面與該堤 件31之下表面接觸，如第2圖所亍、， 構 M r/r不’亚以 gJP封部3 3，將該半導體基板w之外部 ^ r哔周緣密射。此日#，分 半導體基板w之表面係呈開放狀態。 、 “ 然後’該半導體基板W本身以北 _ 才Μ月面加執哭首接‘ 熱，同時從淋灑頭4 1灑出電錢溶@ 注於該半導體基板w之整體I二液由:將:二 田於该+導體基板W之表313734.ptd Page 17 543〇9i 5. Description of the invention (13) It can move vertically. The bank member 31 is cylindrical, and has a sealing portion 33 'provided at a lower portion thereof to seal the outer peripheral edge of the semiconductor substrate w, and is provided so as not to move vertically from the position shown in the figure. The shower head 41 has a structure in which a plurality of nozzles are provided at the front end to spread the supplied plating solution into a shower shape and to supply the surface of the semiconductor substrate W to be plated in a substantially uniform manner. The cleaning liquid supply device 51 has a structure in which a cleaning liquid is ejected from the nozzle 53. The electric mining solution recovery nozzle 65 is set to move up and down and shake, and the front end of the electric solution recovery nozzle 65 is set to be inwardly lower than the bank member located on the peripheral portion of the upper surface of the semiconductor substrate w. 3 丨, and used to suck the plating solution on the semiconductor substrate boundary. Next, ‘explain that this non-electrical clock is set to borrow Xijie ’s private work. First, the fixing device 11 is lowered from the state shown in the figure, so that a gap of a pre-selected size is formed between the holding device 11 and the dike structure 3 1, and closed. , # 舟 1 乾 ^ ^ t 糸 糸 The semiconductor substrate w is placed and fixed on the substrate placement portion 13. For example, an 8-inch wafer is used as the semiconductor substrate W. τ 守 Then, raise the holding device U to make the upper surface of the holding device U contact with the lower surface of the embankment 31, as shown in Figure 2, the structure M r / r is not sealed with gJP The portion 33 is densely radiated from the outer periphery of the semiconductor substrate w. On this day, the surface of the semiconductor substrate w is in an open state. "Then" The semiconductor substrate W itself is north of the front surface of the semiconductor substrate, and the first connection is made. "At the same time, the electric money is sprayed from the shower head 41, and the entire liquid of the semiconductor substrate w is injected: Will: Erita in the + conductor substrate W table

543091 五、發明說明（14) 面係為該堤堪構件3 1所圍繞，所灌注之電鍍溶液全部保持 在該半導體基板W之表面上。所供給的電鍍溶液之量為少 量’其於该半導體基板W之表面上形成1毫米之深度（約3〇 宅升\。保持在欲予電鍍之表面上之電鍍溶液之深度可為 1 0宅米或以下’甚至可低如本實施例之1毫米。如果所供 給之少篁電鐘溶液即足夠，則可用小型加熱裝置加熱該電 鍍溶液。 如果該半導體基板w本身係設置成可予加熱，則需要 大Ϊ耗能之該電鑛溶液之溫度即可無須大幅提高。此為較 佳的方式’因為能耗可予減少，並且電鍍溶液之變質亦得 以避免、用於加熱該半導體基板W本身之能耗少，而貯存 於該半導體基板W上之電鍍溶液量亦少。利用該背面加熱 器15可易於該半導體基板w保溫，該背面加熱器15之容量 ::小型，設備可為簡潔。如果使用直接冷卻該半導體基 拖以上之裝置，即可在電鍍當中於加熱及冷卻之間作切 電鐘條件。由於該半導體基板上所保持之電鑛溶 液係j置，可作高靈敏度之溫度控制。 欲==導體基板w係由馬達間轉動，以使均勻潤濕於 於靜扩然後該表面之電鍍即在該半導體基板w 10叶pm或以詳言之，該半導體基板$係於 鍍之表面，：鐘’以使該半導體基板W之該欲予電 基板w於靜離Λ 均句地澗濕。然後，保持該半導體 多為時1 ο秒或以下。里之…私电鍍。該瞬間轉動時間最 543091 ，·五、發明說明（15) ----- - 電鍍處理完成之後，降下該電鍍溶液回收嘴65之前 端，以至於接近位在該半導體基板w上之周緣部分之該堤 、堰構件3 1内部之區域，而得以吸取該電鍍溶液。與此同 ，時’如果於例如lOOrpm或以下之轉速將該半導體基板界旋 •轉’則殘留在該半導體基板W上之電鍍溶液，在離'心力之 作用下可集中於位在該半導體基板W上之周緣部分之該堤 堪構件3 1之部分’因此該電鍍溶液即可以高效率與回收率 高而回收。降下該固持裝置11，使該半導體基板W與該堤 堰構件3 1分離。開始該半導體基板W之轉動，從清洗液供 裝置5 1之喷嘴5 3以清洗液（超純水）喷射於該半導體基 板W經電鍍後之表面，以冷卻該經電鍍之表面，同時進行 稀釋及清洗，以使該無電電鍍反應終止。此時，從該喷嘴 5 3噴出之清洗液可供給於該堤堰構件3 1，以同時清洗該堤 堪構件3 1。電鍍廢液此時係回收於回收桶6 1並予棄置。 該電鍍溶液一旦經過使用即不再用，而係加以丟棄。 如上所述，用於本設備之電鍍溶液之量相較於習知技術可 為非常少量。如此，即使不再使用，丟棄之電鑛溶液之量 為少量。在一些情況下，可不裝設電鍍溶液回收嘴6 5，用 過之電鍍溶液可回收而當作廢液，連同清洗液一起回收至 收桶 6 1。 然後，該半導體基板W以該馬達Μ高速旋轉而作旋轉乾 燥，之後從該固持裝置11移除該半導體基板W。 “ 第3圖係另一無電電鍍設備之構造示意圖。第3圖之實 例與第2圖所示之無電電鍍設備不同在於不在固持裝置11543091 V. Description of the invention (14) The surface is surrounded by the embankment member 31, and all the electroplating solution is kept on the surface of the semiconductor substrate W. The amount of the plating solution supplied is a small amount, which forms a depth of 1 mm (about 30 liters) on the surface of the semiconductor substrate W. The depth of the plating solution maintained on the surface to be plated may be 10 liters. Meters or less can even be as low as 1 millimeter in this embodiment. If a small amount of clock solution supplied is sufficient, the plating solution can be heated with a small heating device. If the semiconductor substrate w itself is set to be preheatable, Then the temperature of the power ore solution that requires a large amount of energy consumption can be increased without a large increase. This is a better way because the energy consumption can be reduced, and the deterioration of the plating solution can be avoided and used to heat the semiconductor substrate W itself The energy consumption is small, and the amount of the plating solution stored on the semiconductor substrate W is also small. The semiconductor substrate w can be easily insulated by using the back heater 15. The capacity of the back heater 15 is small and the equipment can be simple. If you use a device that directly cools the semiconductor substrate, it can be used to cut the clock between heating and cooling during electroplating. Because the electric ore dissolved on the semiconductor substrate is dissolved Set j, can be used for high-sensitivity temperature control. To == the conductor substrate w is rotated between the motors, so that evenly wetted in the static expansion and then the surface of the plating is on the semiconductor substrate w 10 leaves pm or more In other words, the semiconductor substrate $ is on the plated surface: bell 'to make the desired substrate w of the semiconductor substrate W wet evenly at a static distance Λ. Then, hold the semiconductor for more than 1 s Or below. Inside ... Private plating. The instantaneous rotation time is 543091. V. Description of the invention (15) ------After the plating process is completed, lower the front end of the plating solution recovery nozzle 65 so that it is close to the position. The area inside the bank and weir member 31 on the peripheral portion of the semiconductor substrate w can be used to suck the plating solution. At the same time, if the semiconductor substrate is rotated and rotated at a rotation speed of, for example, 100 rpm or less, Then, the plating solution remaining on the semiconductor substrate W can be concentrated on the portion of the bank member 31 located on the peripheral portion of the semiconductor substrate W under the action of the centrifugal force. Therefore, the plating solution can be highly efficient. With high recovery rate Close. Lower the holding device 11 to separate the semiconductor substrate W from the bank member 31. Start the rotation of the semiconductor substrate W, and spray the cleaning liquid (ultra-pure water) from the nozzle 53 of the cleaning liquid supply device 51 to the cleaning liquid (ultra-pure water). The electroplated surface of the semiconductor substrate W is cooled to reduce the electroless plating reaction while the electroplated surface is cooled. At this time, the cleaning liquid sprayed from the nozzle 53 can be supplied to the bank member 3 1, to clean the embankment member 31 at the same time. The electroplating waste liquid is recovered in the recovery barrel 61 at this time and discarded. Once the electroplating solution is used, it is no longer used and is discarded. As described above, use The amount of electroplating solution in this equipment can be very small compared with the conventional technology. In this way, even if it is no longer used, the amount of the electroless solution that is discarded is small. In some cases, the plating solution recovery nozzle 6 5 may not be installed, and the used plating solution may be recovered and used as waste liquid, together with the cleaning liquid, and collected in the collecting barrel 61 1. Then, the semiconductor substrate W is rotated and dried by the motor M at high speed, and then the semiconductor substrate W is removed from the holding device 11. "Figure 3 is a schematic diagram of the structure of another electroless plating equipment. The example in Figure 3 is different from the electroless plating equipment shown in Figure 2 in that it is not in the holding device 11

313734.ptd 第20頁 543091 五、發明說明（16) 設置背面加熱器1 5，而係於該固持裝置1 1之上方設置加熱 燈（加熱裝置）1 7，而該加熱燈1 7係與淋灑頭4 1 - 2成為， 體。例如，可同心設置具有不同半徑之多數環狀加熱燈 1 7，並在加熱燈1 7之間之間隙以環形打開該淋灑頭4 1 - 2之 許多喷孔43-2。加熱燈17可由單一螺旋狀燈式加熱器組 成，或由不同的構造及配置之其它燈式加熱器所組成。 即使如此地構成，電鍍溶液可由各該喷孔4 3 - 2大致上 均勻地以淋灑方式供給於該半導體基板W之欲予電鍍之表 面。再者’可藉由該加熱燈1 7，直接均勻地執行該半導體 基板W之加熱及保溫。該加熱燈17不僅加熱該半導體基板从 以及該電鍍溶液，並加熱鄰近之空氣，因而對於該半導體 基板W造成保溫作用。 該半導體基板W藉由該加熱燈17直接加熱，必須要有 相對較大功率消耗之加熱燈1 7。取代如此之加熱燈1 7，可 以併用功率消耗較小之加熱燈1 7以及如第2圖所示之背面 加熱器15’主要藉由該背面加熱器a加熱該半導體基板 W，並且主要藉由該加熱燈丨7作該電鍍溶液以及鄰近空氣 之保溫。如同上述之實施例，可以設置直接或間接冷卻該 半導體基板W之裝置，以施行溫度控制。 第4圖係依據本發明用以製造半導體裝置之半導體製 造没備之貝例之平面圖。該半導體製造設備包含裝載/卸 載段201，其内含卡匣201-1、第一電鍍裝置202、第一機 械手臂203、翻轉裝置205及206、第二清洗裝置207、第二 機械手臂208、第一清洗裝置2〇9、第二電鍍裝置22 7、第313734.ptd Page 20 543091 V. Description of the invention (16) A back heater 15 is provided, and a heating lamp (heating device) 17 is arranged above the holding device 11 and the heating lamp 17 is connected with the shower. The sprinkler 4 1-2 becomes a body. For example, a plurality of ring-shaped heating lamps 17 having different radii may be provided concentrically, and a plurality of nozzle holes 43-2 of the shower head 4 1-2 may be opened in a ring shape between the gaps between the heating lamps 17. The heating lamp 17 may be composed of a single spiral lamp heater or other lamp heaters having different structures and configurations. Even with such a configuration, the plating solution can be supplied from each of the spray holes 4 3-2 to the surface of the semiconductor substrate W to be plated in a substantially uniform manner by showering. Furthermore, the heating and thermal insulation of the semiconductor substrate W can be performed directly and uniformly by the heating lamp 17. The heating lamp 17 not only heats the semiconductor substrate and the plating solution, but also heats the adjacent air, thereby causing a heat preservation effect on the semiconductor substrate W. The semiconductor substrate W is directly heated by the heating lamp 17, and a heating lamp 17 having a relatively large power consumption is required. Instead of such a heating lamp 17, a heating lamp 17 with a small power consumption and a back heater 15 'as shown in Fig. 2 can be used in combination to heat the semiconductor substrate W mainly by the back heater a, and mainly by The heating lamp 7 is used for the insulation of the plating solution and the adjacent air. As in the embodiment described above, a device for directly or indirectly cooling the semiconductor substrate W may be provided to perform temperature control. Fig. 4 is a plan view of an example of a semiconductor manufacturing apparatus for manufacturing a semiconductor device according to the present invention. The semiconductor manufacturing equipment includes a loading / unloading section 201, which contains a cassette 201-1, a first electroplating device 202, a first robot arm 203, a turning device 205 and 206, a second cleaning device 207, a second robot arm 208, First cleaning device 209, second plating device 22 7,

543091 ‘五、發明說明（17) -一拋光裝置210以及第二拋光裝置211。再者’在該第一機 械手臂2 0 3之鄰近處，設置有用以量測電鐘膜在電鍍前以 -及電鍍後之厚度之電鍍前/後膜厚度量測裝置212’及用以 量測該半導體基板W拋光後乾燥狀態下膜之厚度之乾燥狀 '態之膜厚度量測裝置2 1 3。 該第一拋光裝置210有拋光台21〇一1、頂環210-2、頂 環頭2 1 0 - 3、膜厚度量測裝置2 1 0 -4以及推進器2 1 0〜5。該 第二拋光裝置21 1有拋光台21 1-1、頂環2U-2、頂環頭21 i -3、膜厚度量測裝置211 - 4以及推進器211-5。 [讀在說明該設備之製程步驟] 首先’卡匡201-1内含半導體基板W，於各該半導體基 板上形成銅晶種層6(參見第1A圖），該卡匣201-1係放置在 該裝載/卸載段201中之裝載埠上。該半導體基板w以該第 一機械手臂203取出，並以該第一電鍍裝置202形成鋼膜 7(參見第1B圖）。該銅膜7之形成，係經該半導體基板界之 表面之親水性處理後，再經銅電鍍。然後，作沖淋或清 洗。如果時間足夠，可加以乾燥。當該半導體基板W以第 一機械手臂203取出時，以該電鍍前以及電鍍後膜厚度量 測裝置2 1 2量測該電鍍銅膜7之厚度。量測結果記錄為該半 基板W之記錄資料，並亦用於決定該第一電鐘裝置202 之異常。膜厚度量測之後，該第一機械手臂203將該半導 體基板W傳送至翻轉裝置205，於其中將該半導體基板w翻 -轉。 然後，以第二機械手臂2 0 8從該翻轉裝置2 0 5拾起該半543091 ‘fifth, description of the invention (17)-a polishing device 210 and a second polishing device 211. Furthermore, 'a pre- / post-film thickness measurement device 212' is provided in the vicinity of the first robot arm 203 for measuring the thickness of the electric clock film before and after plating, and for measuring A film thickness measuring device 2 1 3 for measuring the dry state of the film thickness in the dry state after polishing the semiconductor substrate W. The first polishing device 210 includes a polishing table 2101, a top ring 210-2, a top ring head 2 1 0-3, a film thickness measuring device 2 1 0-4, and a thruster 2 1 0-5. The second polishing device 21 1 includes a polishing table 21 1-1, a top ring 2U-2, a top ring head 21 i -3, a film thickness measuring device 211-4, and a pusher 211-5. [Read in the description of the process steps of the device] First, 'Ka Kuang 201-1 contains a semiconductor substrate W, and a copper seed layer 6 is formed on each of the semiconductor substrates (see FIG. 1A). The cassette 201-1 is placed there. On the loading port in the loading / unloading section 201. The semiconductor substrate w is taken out by the first robot arm 203, and a steel film 7 is formed by the first plating device 202 (see FIG. 1B). The copper film 7 is formed after being subjected to a hydrophilic treatment on the surface of the boundary of the semiconductor substrate, and then subjected to copper electroplating. Then, shower or rinse. If time is sufficient, it can be dried. When the semiconductor substrate W is taken out by the first robot arm 203, the thickness of the plated copper film 7 is measured by the film thickness measuring device 2 1 2 before and after the plating. The measurement result is recorded as the recording data of the half substrate W, and is also used to determine the abnormality of the first electric clock device 202. After the film thickness is measured, the first robot arm 203 transfers the semiconductor substrate W to the turning device 205, where the semiconductor substrate w is turned-turned. Then, pick up the half from the turning device 2 0 5 with the second robot arm 2 0 8

313734.ptd 第22頁 543091 五、發明說明（18) 導體基板W，將之放置在推進器210-5或211-5上。然後， 頂環2 1 0 - 2或2 1 1 - 2以吸入方式固持該半導體基板w，將之 傳送至拋光台2 1 0 - 1或2 1 1 - 1，並將之按壓抵住該拋光台 210-1或211-1之拋光面以進行拋光。 拋光完成之後，頂環210-2或211-2將該半導體基板W 送返至該推進器210-5或211-5。該第二機械手臂208拾起 該半導體基板W，將之送進第一清洗裝置209。此時，可將 化學液體灑向該推進器210-5或211-5上之該半導體基板 W，以將微粒去除，或使微粒難以附著。 在該第一清洗裝置209内，擦拭及清洗該半導體基板w 之正面及背面。擦拭及清洗該半導體基材板之正面主要係 以P V A捲筒狀泡棉，使用添加界面活性劑、螯合劑 (c h e 1 a t i n g a g e n t)或p Η調整劑於純水之清洗水，以移除 微粒。將諸如DHF之強效化學液體灑向該半導體基板w之背 面，以蝕去擴散之銅。如果銅之擴散不成為問題，則該半 導體基板W之背面可以利用PVA捲筒狀泡棉，使用如同上述 用於正面之化學液體，加以擦拭並清洗。 清洗之後，該第二機械手臂20 8拾起該半導體基板w， 並將之傳送至翻轉裝置20 6,於其中將該半導體基板#翻 轉第二機械手臂2〇8再度拾起該半導體基板^，將之輸 ^=一電鍍裝置227，其係由例如第2圖或第3圖所示之 二ιΓ鍍裝置所構成。於該第二電鍍裝置2 2 7，該半導體 二；^万、έ表+面係/文入如上述之無電電鍍溶液之電鍍溶液， ; &路8之曝露表面上，選擇性形成合金保護膜Θ，313734.ptd Page 22 543091 V. Description of the invention (18) The conductor substrate W is placed on the thruster 210-5 or 211-5. Then, the top ring 2 1 0-2 or 2 1 1-2 holds the semiconductor substrate w by suction, transfers it to the polishing table 2 1 0-1 or 2 1 1-1, and presses it against the polishing The polishing surface of the stage 210-1 or 211-1 is used for polishing. After the polishing is completed, the top ring 210-2 or 211-2 returns the semiconductor substrate W to the pusher 210-5 or 211-5. The second robot arm 208 picks up the semiconductor substrate W and sends it to the first cleaning device 209. At this time, a chemical liquid may be sprinkled on the semiconductor substrate W on the pusher 210-5 or 211-5 to remove particles or make it difficult for particles to adhere. In the first cleaning device 209, the front and back surfaces of the semiconductor substrate w are wiped and cleaned. The front side of the semiconductor substrate is wiped and cleaned mainly with a PVA roll of foam, using a surfactant, a chelating agent (c h e 1 a t i n g a g e n t) or p Η modifier in pure water, to remove particles. A strong chemical liquid such as DHF is sprinkled on the back surface of the semiconductor substrate w to etch away the diffused copper. If the diffusion of copper is not a problem, the back surface of the semiconductor substrate W can be wiped and cleaned by using a PVA roll foam, using a chemical liquid for the front surface as described above. After cleaning, the second robot arm 20 8 picks up the semiconductor substrate w and transfers it to the turning device 20 6, where the semiconductor substrate # flips the second robot arm 208 to pick up the semiconductor substrate again, It is inputted to a plating device 227, which is composed of, for example, a two-layer plating device shown in FIG. 2 or FIG. In the second electroplating device 2 2 7, the semiconductor two; ^ 10,000, + surface system / text into the electroless plating solution as described above, & Road 8 exposed surface, selective alloy protection Film Θ,

543091 ••五、發明說明（19) -以保護該互連線路8 (參見第1 c圖）。之後，該第二機械手 臂2 0 8拾起該半導體基板w，將之傳送至翻轉裝置2 0 6以翻 '轉，然後將該基板傳送至第二清洗裝置2 0 7。在該第二清 洗裝置2 0 了内’將經施以超音波之百萬赫超音波水麗向該 -半導體基板W之正面，以清洗該正面。此時，該正面可用 船筆型泡棉’以添加界面活性劑、螯合劑及pH調整劑於純 水之清洗液清洗。之後，將該半導體基板W利用旋轉乾燥 法加以乾燥。 然後’該第二機械手臂208拾起該半導體基板W，並將 •依原樣傳送至翻轉裝置206。第一機械手臂203拾起在今 翻轉裝。置2〇6上之半導體基板以設置接近於拋光台 210-1或211 —1之膜厚度量測裝置2ι〇 —4或211—4以量 埠ΐ中，半導體基板W由放置在該裝載/卸载段201之子 I ^中之卡匣2〇1接收。當多層膜之膜厚度欲予量測 :離义？狀態下之量測…’該膜厚度係利用乾燥 狀〜、腰尽度量測裝置2 1 3量測一次。 ▲ # = 5圖係依據本發明用以製造半導體裝置之半 又之另一實例之平面圖。如同第4圖所示之美拓 備於=導體製造設備所施行之基板力…包括以下步 嗜基材，、 層6之該半導體基板1上形成銅膜7,拋光 提二帝路以及於互連線路8之上選擇性形成保護膜9，夢以 k，、私路互連線路，於其中該互連二 擇性保護。 0 Λ泛保瞍臊9作選 &此半導體製造設備中 在靠近第一拋光裝置21〇放543091 •• V. Description of the Invention (19)-to protect the interconnection line 8 (see Figure 1c). After that, the second robot arm 208 picks up the semiconductor substrate w, transfers it to the turning device 206 to turn it, and then transfers the substrate to the second cleaning device 207. Within the second cleaning device 20 ′, a megahertz ultrasonic wave having been subjected to ultrasonic waves is applied to the front surface of the semiconductor substrate W to clean the front surface. At this time, the front side can be cleaned with a boat pen type foam 'by adding a surfactant, a chelating agent, and a pH adjusting agent in pure water. Thereafter, the semiconductor substrate W is dried by a spin drying method. Then 'the second robot arm 208 picks up the semiconductor substrate W and transfers it to the turning device 206 as it is. The first robot arm 203 is picked up and flipped. The semiconductor substrate on the 206 is set to set a film thickness measuring device 20 to 4 or 211-4 close to the polishing table 210-1 or 211-1. The semiconductor substrate W is placed on the loading / The cassette 201 in the child of the unloading section 201 is received. When the film thickness of a multilayer film is to be measured: Separation? Measurement in the state ... 'This film thickness is measured once using a dry state ~, waist end measurement device 2 1 3. ▲ # = 5 is a plan view of another example of a semiconductor device for manufacturing a semiconductor device according to the present invention. As shown in FIG. 4, the substrate is applied by the substrate manufacturing force of the conductor manufacturing equipment. The substrate includes the following steps: a copper film 7 is formed on the semiconductor substrate 1 of the layer 6; A protective film 9 is selectively formed on the circuit 8, and the dream circuit is interconnected with a private circuit, in which the interconnection is selectively protected. 0 Λ 保 保 瞍 臊 9 to choose & in this semiconductor manufacturing equipment, close to the first polishing device 21〇 put

第24頁 543091 五、發明說明（20) 置推進器索引器225，以及各於靠近第二清洗裝置207以及 第二電鍍裝置227放置第二拋光裝置211與基板放置台 221、222，並於靠近第二電鍍裝置227以及第一電鍍裝置 202放置機械手臂223(此後稱之為第二機械手臂223)。再 者，於靠近第一清洗裝置209以及第二清洗裝置207、放置 機械手臂224(此後稱之為第三機械手臂224)，並於靠近裝 载/卸載段2 0 1以及第一機械手臂2 0 3放置乾燥狀態膜厚度 量測裝置2 1 3。 該第一機械手臂203從放置在該裝載/卸載段2〇1之裝 載璋上之卡匣201-1，取出具有晶種層6之半導體基板w， 並將之放置於基板放置台221上。然後，以該第二機械手 臂223將該半導體基板W輸送至該第一電鍍裝置2〇2，於該 處形成銅膜7(參見第1B圖）。該第二機械手臂223傳送該形 成有銅膜7之該半導體基板，以藉由該電鑛前以及電鑛後 膜厚度量測裝置2 1 2量測該鋼膜7之厚度。量測膜厚度以 後，將該半導體基板送入該推進器索引器2 2 5。 頂環2 1 〇 - 2或2 1 1 - 2藉吸引以固持在該推進器索引器 225上之該半導體基板W’將之傳送至拋光台210 — 1或 2 1卜1，以進行拋光。拋光以後，該頂環2丨0 — 2或2 1 1 - 2將 該半導體基板W傳送至膜厚度量測裝置210 — 4或211-4，以 量測該獏之厚度。然後，以該頂環21 〇-2或211-2將該半導 體基板W傳送至該推進器索引器2 25，並將半導體基板W放 置於其上。 然後，第三機械手臂224從該推進器索引器225拾起該Page 24 543091 V. Description of the invention (20) The propeller indexer 225 is placed, and the second polishing device 211 and the substrate placing tables 221 and 222 are placed near the second cleaning device 207 and the second plating device 227, and close to The second electroplating device 227 and the first electroplating device 202 place a robot arm 223 (hereinafter referred to as a second robot arm 223). Furthermore, a robot arm 224 (hereinafter referred to as a third robot arm 224) is placed near the first cleaning device 209 and the second cleaning device 207, and near the loading / unloading section 2 01 and the first robot arm 2 0 3 Place the film thickness measuring device 2 1 3 in a dry state. The first robot arm 203 takes out the semiconductor substrate w having the seed layer 6 from the cassette 201-1 placed on the loading frame of the loading / unloading section 201, and places it on the substrate placing table 221. Then, the semiconductor substrate W is transported to the first electroplating apparatus 200 by the second robot arm 223, and a copper film 7 is formed there (see FIG. 1B). The second robot arm 223 transfers the semiconductor substrate formed with the copper film 7 to measure the thickness of the steel film 7 by the film thickness measuring device 2 1 2 before and after the power ore. After measuring the film thickness, the semiconductor substrate is fed into the pusher indexer 2 2 5. The top ring 2 1 0-2 or 2 1 1-2 transfers the semiconductor substrate W 'held on the pusher indexer 225 to the polishing table 210-1 or 21 1 by suction for polishing. After polishing, the top ring 2 丨 0 — 2 or 2 1 1-2 transfers the semiconductor substrate W to a film thickness measuring device 210 — 4 or 211-4 to measure the thickness of the ridge. Then, the semiconductor substrate W is transferred to the thruster indexer 25 with the top ring 21 0-2 or 211-2, and the semiconductor substrate W is placed thereon. Then, the third robot arm 224 picks up the thruster indexer 225 from the

313734.ptd 第25頁 543091 五、發明說明（21) 半導體基板並將之送入第—清洗裝置2〇9。於該第一产 之該半導體基板w，；之；機；：臂224拾起經清洗後 - 之运入弟一電鍍裝置227並於該虛以 藉: 3於互連線路8之表面形成保護膜9，藉此 •保護該互連線路8(參見第ic圖其後，該第三機械手猎臂此 m將該+導體基板w送入第二清洗裝置2〇7，以作清洗並 乾煉，亚將經清洗後之該半導體基板w放置於基板放置台 222之士。纟次’③帛一機械手臂2 0 3拾起該半導體基板口 亚、/之迗入乾燥狀態膜厚度量測裝置2 1 3以量測膜厚 Γ之卡sm-Μ 該裝載/卸載段2(31之卸載埠 〇::圖又係,依據/發明用以製造半導體裝置之半導體製 仏汉備之又另一 Λ例之平面圖。此半導體製造設備 阻=形成單元⑴、晶種層形成單元u ==火ίί114、第一清洗單元115、斜面及背面清 ΐ Z t 如第2圖或第3圖所示之無電電鍍裝置 之頂套电鍍早儿117、第二清洗單元118、第一對準哭及膜 = 、第二對準器及膜厚度量測儀142、第-基 二翻轉”，二基板翻轉裝置144、基板暫置台 \二膜厚度I測儀1 4 6、裝載/卸載單元1 2 0、第一拋 地=莆121、第二拋光設備122、第一機械手 =:”32、第三機械手臂133、第四機械手臂134。該 .=^:儀141、142、146與其它單元（電鍍、清洗、 ，火早兀專）具相同之正面尺寸，因而得以互換。313734.ptd page 25 543091 V. Description of the invention (21) The semiconductor substrate is sent to the cleaning device 209. The semiconductor substrate w in the first production; the machine; the arm 224 picks up the washed-in-a-plating device 227 and uses this to: 3 form a protection on the surface of the interconnection 8 Membrane 9 to protect the interconnecting line 8 (see Figure ic thereafter, the third robotic hunter arm m sends the + conductor substrate w to the second cleaning device 207 for cleaning and drying After the cleaning, the semiconductor substrate w is placed on the substrate placing table 222. After that, '③, a robotic arm 2 0 3 picks up the semiconductor substrate, and measures the thickness of the film in the dry state. The device 2 1 3 measures the card sm-M of the film thickness Γ. The loading / unloading section 2 (31 of the unloading port 0 :: Figure is again, based on / inventing the semiconductor system used to manufacture semiconductor devices. A plan view of an example. This semiconductor manufacturing equipment resistance = forming unit ⑴, seed layer forming unit u = = fire ί114, first cleaning unit 115, inclined surface and back surface cleaning Z t as shown in FIG. 2 or 3 Top electroplating device of the electroless plating device 117, second cleaning unit 118, first alignment film and film =, second alignment device and film Measurer 142, first-base-two inversion ", two substrate inverting device 144, substrate temporary stand \ two film thickness I tester 1 4 6, loading / unloading unit 1 2 0, first throwing ground = 莆 121, first Two polishing equipment 122, first manipulator =: "32", third manipulator arm 133, fourth manipulator arm 134. The. = ^: Instrument 141, 142, 146 and other units (plating, cleaning, special equipment) ) Have the same front dimensions and are therefore interchangeable.

543091 五、發明說明（22) 在此實施例中，可將無電釕（Ru)電鍍設備用作該阻障 層形成單元1 1 1，將無電銅電鍍設備用作該晶種層形成單 元1 1 2，並將電鍍設備用作該電鍍膜形成單元1 1 3。 [現在說明此設備之製程步驟] 首先，以第一機械手臂131從放置於裝載/卸載單元 120上之卡匣120a取出半導體基板，將之置於第一對準器 及膜厚度量測儀1 4 1，使欲電鍍之表面朝上。為設定膜厚 度量測所處位置之參考點，對膜厚度量測施行缺口對準， 然後獲取銅膜形成前在該半導體基板之膜厚度資料。 然後，以第一機械手臂1 3 1將該半導體基板輸送至該 阻障層形成單元11 1。該阻障層形成單元11 1係藉由無電釕 (Ru)電鍍而用於在半導體基板上形成阻障層之設備，並且 該阻障層形成單元111形成釕（Ru)膜，以作為防止銅之擴 散進入半導體裝置之層間絕緣（例如S i 02)膜。在清洗及乾 燥步驟以後釋出之半導體基板，由第一機械手臂131輸送 至第一對準器及膜厚量測儀1 4 1，於其中量測該半導體基 板之膜厚，亦即該阻障層之膜厚。 在膜厚度量測以後該半導體基板由第二機械手臂1 3 2 送入晶種層形成單元112，並且藉由無電銅電鍍於該阻障 層上形成晶種層6(參見第1A圖）。在將該半導體基板輸送 至電鍍膜形成單元113之前，在清洗及乾燥步驟以後釋出 之半導體基板，由第二機械手臂132輸送至第二對準器及 膜厚度量測儀1 4 2以決定缺口位置，然後作銅電鍍之缺口 對準。必要時，在銅膜形成之前可於第二對準器及膜厚度543091 V. Description of the invention (22) In this embodiment, electroless ruthenium (Ru) electroplating equipment can be used as the barrier layer forming unit 1 1 1 and electroless copper electroplating equipment can be used as the seed layer forming unit 1 1 2, and a plating apparatus is used as the plating film forming unit 1 1 3. [Now explain the process steps of this equipment] First, take the semiconductor substrate from the cassette 120a placed on the loading / unloading unit 120 with the first robot arm 131, and place it on the first aligner and the film thickness measuring instrument 1 4 1. Make the surface to be plated up. In order to set the reference point of the film thickness measurement position, perform notch alignment on the film thickness measurement, and then obtain the film thickness data of the semiconductor substrate before the copper film formation. Then, the semiconductor substrate is transported to the barrier layer forming unit 11 1 by the first robot arm 1 3 1. The barrier layer forming unit 111 is a device for forming a barrier layer on a semiconductor substrate by electroless ruthenium (Ru) electroplating, and the barrier layer forming unit 111 forms a ruthenium (Ru) film to prevent copper It diffuses into the interlayer insulation (eg Si 02) film of the semiconductor device. The semiconductor substrate released after the cleaning and drying steps is transported by the first robot arm 131 to the first aligner and the film thickness measuring instrument 1 4 1, in which the film thickness of the semiconductor substrate is measured, that is, the resistance The thickness of the barrier layer. After the film thickness measurement, the semiconductor substrate is fed into the seed layer forming unit 112 by the second robot arm 1 3 2, and a seed layer 6 is formed on the barrier layer by electroless copper plating (see FIG. 1A). Before the semiconductor substrate is transported to the plating film forming unit 113, the semiconductor substrate released after the cleaning and drying steps are transported by the second robot arm 132 to the second aligner and the film thickness measuring instrument 1 4 2 to determine The position of the notch is then aligned with the notch of the copper plating. If necessary, the second aligner and film thickness can be obtained before the copper film is formed.

313734.ptd 第27頁 543091 五、發明說明（23) •量測儀1 4 2再次量測該半導體基板之膜厚度。 完成缺口對準以後，以第三機械手臂1 3 3將該半導體 '基板輸送至電鍍膜形成單元113，於其中對該半導體基板 施行銅電鍍。在清洗及乾燥步驟以後釋出之該半導體基 •板，以第三機械手臂133輸送至斜面及背面清洗單元116, 於其中移除位於該半導體基板之周圍部份之不必要的銅膜 (晶種層）。在該斜面及背面清洗單元Π 6，斜面以預設時 間蝕刻，而黏著於該半導體基板之背面之銅則以諸如氫氟 酸之化學液體清洗。此時，在將該半導體基板輸送至該斜 #及背面清洗單元Π 6以前，可以藉由第二對準器及膜厚 度量測儀1 4 2量測該半導體基板之膜厚度，以取得電鍍形 成的銅膜之厚度值，而根據所取得之結果，即可任意改變 斜面蝕刻時間，以進行蝕刻。斜面蝕刻所蝕刻之區域，係 對應於該基板之周緣部份且無電路形成之區域，或雖有電 路形成但最終仍不使用作晶片之區域。斜面部亦包含在此 區域之内。 在該斜面及背面清洗單元1 1 6中經清洗及乾燥步驟以 後釋出之半導體基板，以第三機械手臂133輸送至基板翻 轉裝置143。當該半導體基板藉由該基板翻轉裝置143翻轉 i#使電鍍面朝下之後，利用第四機械手臂134將該半導體 基板送入退火單元114，藉以穩定互連線路部份。在退火 處理之前及/或之後，將該半導體基板送入第二對準器及 .膜厚度量測儀1 4 2，於其中量測形成於該半導體基板上之 銅膜7(參見第1B圖）之膜厚度。然後，以第四機械手臂313734.ptd Page 27 543091 V. Description of the Invention (23) • The measuring instrument 1 4 2 measures the film thickness of the semiconductor substrate again. After the notch alignment is completed, the semiconductor substrate is transported to the plating film forming unit 113 by the third robot arm 1 3 3, and the semiconductor substrate is subjected to copper plating. The semiconductor substrate and board released after the cleaning and drying steps are transported to the bevel and backside cleaning unit 116 by a third robot arm 133, in which unnecessary copper films (crystals) located around the semiconductor substrate are removed. Seed layer). On the inclined surface and the back surface cleaning unit Π 6, the inclined surface is etched at a preset time, and the copper adhered to the back surface of the semiconductor substrate is cleaned with a chemical liquid such as hydrofluoric acid. At this time, before the semiconductor substrate is transported to the oblique # and backside cleaning unit Π 6, the film thickness of the semiconductor substrate can be measured by a second aligner and a film thickness measuring instrument 1 42 to obtain electroplating. The thickness of the formed copper film can be arbitrarily changed for the etching time of the bevel according to the obtained result. The area etched by the oblique etching is an area corresponding to the peripheral portion of the substrate and no circuit is formed, or an area that is not used as a wafer despite the formation of a circuit. Oblique faces are also included in this area. The semiconductor substrate released after the cleaning and drying steps in the inclined surface and back surface cleaning unit 1 16 is conveyed to the substrate turning device 143 by the third robot arm 133. After the semiconductor substrate is turned over by the substrate inverting device 143 i # so that the plating surface faces downward, the semiconductor substrate is sent to the annealing unit 114 by the fourth robot arm 134 to stabilize the interconnection line portion. Before and / or after the annealing process, the semiconductor substrate is sent to a second aligner and a film thickness measuring instrument 1 4 2 in which a copper film 7 formed on the semiconductor substrate is measured (see FIG. 1B). ) Film thickness. Then with the fourth robot arm

313734.ptd 第28頁 543091 五、發明說明（24) 134將該半導體基板送入第一抛光設備hi，於其中將該半 導體基板之銅膜7以及晶種層6(參見第1A圖）加以拋光。 此時，使用所欲之所磨粒等，但亦可使用固定研磨 劑’以防基板正面之凹陷（dishing)並且提升平坦度。完 成主要的拋光之後，以該第四機械手臂134將該半導體基 板送入第一清洗單元1 1 5並於該處加以清洗。此清洗乃係 擦拭清洗，其中將具有長度大致上相等於該半導體基板之 直徑之滾筒放置於該半導體基板之正面以及背面，轉動該 半導體基板及該滾筒，灌流以純水或去離子水，藉此、、主= 該半導體基板。 θ / 完成主要的清洗之後，以該第四機械手臂！ 3 4將該 ‘體基板送入第二抛光沒備122，於其中將該半導體夷 上之阻障層5撤光。此時，可以使用所欲之研磨粒等，曰 亦可用固定研磨劑，以防基板正面之凹陷（dishi 、’但 且提升平坦度。完成次要的拖光以後，以該第四1ng ’並 134將該半導體基板再度送入該第一清洗單元调顿手臂 施以擦拭清洗。完成清洗後，以該第捸 於其中 半導體基板輸送至第二基板翻轉裝置144，於其 4將該 導體基板加以翻轉，而使經電鍍之表面鈿^中將該半 三機械手臂1 3 3將該半導體基板放置於基批新m'、、笑’以第 以第二機械手臂1 3 2從基板暫置台} 4 5將該半* 。 輸送至頂套電鍍單元117，於互連線路8之矣I 導體基板 、衣面施以合 -硼電鍍（頂套電鍍），以防止銅於大氣中氧化 A例如鎳 體基板，於其中已經藉由頂套電鍍於互遠綠妨 該半導 連線路8之表面形313734.ptd Page 28 543091 V. Description of the invention (24) 134 The semiconductor substrate is sent to the first polishing device hi, where the copper film 7 and the seed layer 6 of the semiconductor substrate (see FIG. 1A) are polished. . At this time, a desired abrasive grain or the like is used, but a fixed abrasive 'can also be used to prevent dishing on the front surface of the substrate and improve flatness. After the main polishing is completed, the semiconductor substrate is sent to the first cleaning unit 1 15 by the fourth robot arm 134 and cleaned there. This cleaning is wiping cleaning, in which a roller having a length substantially equal to the diameter of the semiconductor substrate is placed on the front and back of the semiconductor substrate, the semiconductor substrate and the roller are rotated, and pure water or deionized water is perfused. Here, main = the semiconductor substrate. θ / After completing the main cleaning, take this fourth robotic arm! The substrate is sent to the second polishing device 122, in which the barrier layer 5 on which the semiconductor is lifted is removed. At this time, you can use the desired abrasive particles, etc. You can also use a fixed abrasive to prevent the front surface of the substrate from sinking (dishi, 'but to improve the flatness. After the completion of the secondary drag, use the fourth 1ng' and 134 sends the semiconductor substrate into the first cleaning unit again, and adjusts the arm for wiping and cleaning. After the cleaning is completed, the semiconductor substrate is transported to the second substrate inverting device 144 using the first substrate, and the conductor substrate is applied at 4 Turn over, so that the semi-three robotic arms 1 3 3 are placed on the surface of the electroplated surface, and the semiconductor substrate is placed on a new batch of substrates m ′, and laugher. The second robotic arm 1 3 2 is removed from the substrate temporary table} 4 5 This half * is transported to the top cover electroplating unit 117, and the conductor substrate and the upper surface of the interconnection 8 are coated with boron plating (top cover plating) to prevent copper from oxidizing in the atmosphere. A such as nickel Body substrate, in which the surface shape of the semiconducting circuit 8 has been electroplated on top of each other by a top sleeve.

313734.ptd 第29頁 543091 ‘五、發明說明（25) 成保°蔓膜9(參見第1C圖），以第二機械手臂Μ?傳送至第三 膜厚度量測儀1 46，於其中量測銅膜之厚度。之後，以第 •一機械手臂1 3 1將該半導體基板傳送至第二清洗單元丨丨8， 於其中以純水或去離子水清洗該基板。將清洗後之半導體 基板送返在裝載/卸載單元120内之卡匣i2〇a。 實例 具有大小為p 〇_ 5微米χ〇_ 5微米深（縱橫比：丨· 〇)之 孔形成於纟巴緣膜内之預定間距。以銅充填於該孔之後，表 面以化學機械式拋光（CMP)處理以製備大小為^公分以公^ Λ 6圖案之形成）之樣本（半導體晶圓）。以浴量2〇〇毫二^ 曰曰片利用具有如下表1之組成之電鍍溶液，對該樣本施 以無電電鍍。 表1313734.ptd Page 29, 543091 'V. Description of the invention (25) Cheng Bao ° Manmbrane 9 (see Figure 1C), transferred by the second robotic arm M? To the third film thickness measuring instrument 1 46, in which Measure the thickness of the copper film. After that, the semiconductor substrate is transferred to the second cleaning unit with the first robot arm 1 31, and the substrate is cleaned with pure water or deionized water. The cleaned semiconductor substrate is returned to the cassette i20a in the loading / unloading unit 120. Example A hole having a size of p 5-5 μm 5 5 μm deep (aspect ratio: 丨 · 〇) was formed at a predetermined pitch in the diaphragm. After filling the hole with copper, the surface was treated with chemical mechanical polishing (CMP) to prepare a sample (semiconductor wafer) having a size of ^ cm in a pattern of ^ Λ 6). The sample was subjected to electroless plating using a plating solution having a composition of Table 1 below with a bath volume of 200 milligrams. Table 1

CoS〇4.7H20 28·1克/公升 L-酒石酸 82·5克/公升 (NH4)2S04 %，6克/公升 DMAB L5克/公升 ΤΜΑΗ(2 7%) 455毫升/公升 H2W〇4 5· 〇克/公升 pH 9.0 溫度 —_ 80 °C 無電電鍍完成後’將該樣本洗滌並乾燥。以掃描電子CoS4.7H20 28.1 g / L L-tartaric acid 82.5 g / L (NH4) 2S04%, 6 g / L DMAB L5 g / L TMA (2 7%) 455 ml / L H2W04 5 · G / L pH 9.0 Temperature — 80 ° C After electroless plating is complete 'wash the sample and dry. To scan electrons

313734.ptd 第30頁 543091 五、發明說明（26) 顯微鏡（SEM)觀察該樣本時發現，於_安 a敗 ^ % 於圖案形成區域有鈷一鎢 -硼（Co-W-B)電鍍膜選擇性長成。該雷 战•功 又似* 成电鍍犋長速率係 約1 0 0奈米/分鐘；而該電鍍膜之分析如下· 钻（Co):約 98_4wt%，鹤（w)·的·！ n 瑪 ·約 1. 〇wt%，硼（β) ··約 0 . 6 w t % 第7 A及7 B圖係該樣本之掃描雷：淑 、评梅也子顯微鎊相Μ之 圖式。如圖所示，於形成在絕緣層1 Q t _ ^ ^ 深㉟1 υ之孔1 2内所嵌入的銅 膜1 4内沒有空洞之形成。再者，僅口兮〜 ^ ^ ^ ^ +有僅/、該鋼獏14之表面，亦 即互連線路處之表面，有鈷—鎢—硼ίΓη w n、 μ进w 仏於 野朋α〇 —w —B)電鍍膜之保護 膜16覆盍。並無鈷—鎢—硼（Co-W-B)暄、v拉本 νυϋ w 15)膜，儿積於該絕緣層1〇之 表面，顯見該電鐘具有向度選擇性。 生較例 製備如同實例之樣本。在25t首先將樣本浸入以口？ (0_0 0 5克^公升）+ HCl(0.2毫升/公升）之溶液内丨分鐘，以 將鈀觸媒導入該樣本。其次，在9〇。。將經導入鈀觸媒之該 樣本浸入組成如下表2所示之電鍍溶液，以浴量2〇〇毫升/ 晶片施以無電電鍍。 表2313734.ptd Page 30 543091 V. Description of the invention (26) When the sample was observed under a microscope (SEM), it was found that _ an a ^% in the pattern formation area there is cobalt-tungsten-boron (Co-WB) plating film selectivity grow into. This lightning warfare is similar to the long-term plating rate system of about 100 nanometers / minute; and the analysis of the plating film is as follows: Drill (Co): about 98_4wt%, crane (w) ...! n Ma · about 1. 0 wt%, boron (β) · · about 0.6 wt% Figures 7 A and 7 B are scanning samples of this sample: Shu, Ping Meiye microscopic phase M . As shown in the figure, no cavity is formed in the copper film 14 embedded in the hole 12 formed in the insulating layer 1 Q t ^ ^ deep ㉟ 1 υ. In addition, only the word ~ ^ ^ ^ ^ + There is only /, the surface of the steel 貘 14, that is, the surface at the interconnection line, there are cobalt-tungsten-boron Γη wn, μ 进 w 野 野 朋 α〇 —W —B) The protective film 16 of the plating film is covered. There are no cobalt-tungsten-boron (Co-W-B) 暄, v Raben νυϋ w 15) films, which are accumulated on the surface of the insulating layer 10, and it is obvious that the electric clock has a directional selectivity. Comparison Examples Prepare samples like the examples. First immerse the sample in the mouth at 25t? (0_0 0 5 g ^ liter) + HCl (0.2 ml / L) in a solution for 1 minute to introduce a palladium catalyst into the sample. Second, at 90. . The sample introduced with the palladium catalyst was immersed in a plating solution having a composition shown in Table 2 below, and electroless plating was performed at a bath volume of 200 ml / wafer. Table 2

CoC12.6H2〇（克/公） 30 (>^4)2104(克/公升） 10 Na3C6H507.2H20^^升） 80 NaH2P02-H20(^/^} 20 pH 以N a 0 Η调至p Η = 10CoC12.6H2〇 (g / L) 30 (> ^ 4) 2104 (g / L) 10 Na3C6H507.2H20 ^^ L) 80 NaH2P02-H20 (^ / ^) 20 pH is adjusted to N 0 0 to p Η = 10

313734.ptd 第31頁 543091 五、發明說明（27) 無電電鍍完成後，將該樣本洗滌並乾燥。以掃描電子 顯微鏡（SEM)觀察該樣本時發現，於圖案形成區域有鈷-鎢 磷（Co-W-P)電鍍膜選擇性長成。該電鍍膜之生長速率係 約70奈米/分鐘；而該電鍍膜之分析如下： 始（Co):約 89wt%，鎢⑻··約 5wt%，填（P):約 6wt% 第8 A及8 B圖係該樣本之掃描電子顯微鏡（SEM)相片 之圖式。如圖所示，在形成於絕緣層1 0之孔1 2内所嵌入之 銅膜14内，有空洞V形成。再者，不僅該銅膜14之表面， 亦即互連線路之表面，有鈷-鎢-磷（Co-W-P)電鍍合金膜之 #護膜1 6覆蓋，而合金膜1 6 a亦沉積於環繞該孔1 2之該絕 緣層1 0之表面上，亦即無須保護之區域，因而顯見該電鍍 之不良選擇性。 根據本發明，如上所述，使用不含鈉之烷基胺硼烷作 為還原劑，即可於例如銅、銅合金、銀、或銀合金施加氧 化電流，藉此避免鈀觸媒之導入，因而可作直接無電電 鍍，並能避免半導體裝置之遭到鹼金屬污染。此可減少所 需的製程步驟，而且提高生產力，並防止在互連線路内形 成空洞，因而能提升可靠度，並避免因鈀擴散導致互連線 路電阻升高。 # 此外，使用含烷基胺硼烷作為還原劑之電鍍溶液，使 僅於互連線路區域之選擇性電鍍成為可能。313734.ptd Page 31 543091 V. Description of the invention (27) After the electroless plating is completed, the sample is washed and dried. When the sample was observed with a scanning electron microscope (SEM), it was found that a cobalt-tungsten-phosphorus (Co-W-P) plating film was selectively grown in the pattern formation area. The growth rate of the electroplated film is about 70 nanometers / minute; and the analysis of the electroplated film is as follows: Initial (Co): about 89wt%, tungsten rhenium ... about 5wt%, filling (P): about 6wt% 8A Figure 8B is a scanning electron microscope (SEM) photograph of the sample. As shown in the figure, a cavity V is formed in the copper film 14 embedded in the hole 12 formed in the insulating layer 10. In addition, not only the surface of the copper film 14 but also the surface of the interconnection is covered with a # protective film 16 of a cobalt-tungsten-phosphorus (Co-WP) plating alloy film, and an alloy film 16a is also deposited on On the surface of the insulating layer 10 surrounding the hole 12, that is, the area that does not need to be protected, the poor selectivity of the electroplating is evident. According to the present invention, as described above, by using an alkylamine borane containing no sodium as a reducing agent, an oxidation current can be applied to, for example, copper, a copper alloy, silver, or a silver alloy, thereby preventing the introduction of a palladium catalyst. Can be used for direct electroless plating, and can avoid the semiconductor device from being polluted by alkali metals. This reduces the number of process steps required, improves productivity, and prevents voids from forming in the interconnects, thereby increasing reliability and avoiding increased interconnect resistance due to palladium diffusion. # In addition, the use of an electroplating solution containing an alkylamine borane as a reducing agent enables selective electroplating only in the area of the interconnection line.

313734.ptd 第32頁 543091 圖式簡單說明 [圖式之簡單說明] 第1 A至1 C圖以一系列製程步驟說明，依據本發明形成 在半導體裝置内之銅互連線路之實例。 第2圖係無電電鍍裝置之實例之示意圖。 第3圖係另一無電電鍍裝置實例之示意圖。 第4圖係依據本發明用以製造半導體裝置之半導體製 造設備之實例之平面圖。 第5圖係另一依據本發明用以製造半導體裝置之半導 體製造設備之實例之平面圖。 第6圖係又另一依據本發明用以製造半導體裝置之半 導體製造設備之實例之平面圖。 第7A及7B圖係實施例中所得測試樣本之掃描電子顯微 鏡（SEM)相片之圖式。 第8 A及8 B圖係比較例中所得測試樣本之掃描電子顯微 鏡（S E Μ )相片之圖式。 [符號說明] 1 半 導 體 基底 1 a 導 體 層 2 絕 緣 膜 3 接 觸 孔 4 溝 槽 5 阻 障 層 6 銅 晶 種 層 7 銅 膜 8 互 連 線 路 9 保 護 膜 10 絕 緣 層 11 固 持 裝 置 12 孔 13 基 板 放 置 部 14 銅 膜 15 背 面 加 熱 器313734.ptd Page 32 543091 Brief Description of Drawings [Simplified Description of Drawings] Figures 1A to 1C illustrate a series of process steps, and an example of a copper interconnection line formed in a semiconductor device according to the present invention. Fig. 2 is a schematic diagram of an example of an electroless plating device. Figure 3 is a schematic diagram of another example of an electroless plating device. Fig. 4 is a plan view of an example of a semiconductor manufacturing apparatus for manufacturing a semiconductor device according to the present invention. Fig. 5 is a plan view of another example of a semiconductor manufacturing apparatus for manufacturing a semiconductor device according to the present invention. Fig. 6 is a plan view of still another example of a semiconductor manufacturing apparatus for manufacturing a semiconductor device according to the present invention. Figures 7A and 7B are scanning electron microscopy (SEM) photographs of the test samples obtained in the examples. Figures 8A and 8B are scanning electron microscopy (SEM) photographs of the test samples obtained in the comparative example. [Symbol description] 1 semiconductor substrate 1 a conductor layer 2 insulating film 3 contact hole 4 trench 5 barrier layer 6 copper seed layer 7 copper film 8 interconnection line 9 protective film 10 insulating layer 11 holding device 12 hole 13 substrate placement Part 14 Copper film 15 Back heater

313734.ptd 第33頁 543091 B式簡單說明 16 保護 膜 16a 合 金 膜 17 加熱 燈 31 堤 堰 構 件 ,3 3 密封 部 41 > 41-2 淋 灑 頭 43-2 喷孔 51 清 洗 液 供 給 裝置 53 喷嘴 61 回 收 桶 65 電鍍 溶 液 回 收 嘴 111 阻 障 層 形 成 早兀 112 晶種 層 形 成 單 元 113 電 鍍 膜 形 成 α 口 —* 早兀 114 退火 單 元 115 第 一 清 洗 單 元 116 斜面 及 背 面 清 洗 單 元 117 頂 套 電 鍍 單 元 •8 第二 清 洗 單 元 120 裝 載 /卸載單元 120a 卡匣 121 第 一 搬 光 設 備 122 第二 搬 光 5又 備 131 > 203 第 — 機 械 手 臂 132 > 223 第 二 機 械 手 臂 133 > 224 第 二 機 械 手 臂 134 第四 機 械 手 臂 141 第一 對 準 器 及 膜 厚 度， 量測儀 142 第二 對 準 器 及 膜 厚 度- I:測儀 143 第一 基 板 翻 轉 裝 置 144 第二 基 板 翻 轉 裝 置 • 基板 暫 置 台 146 第 二 膜 厚 度 量測儀 201 裝載 /卸載段 201- 1卡匣 202 第 • 電 鍍 裝 置 2 0 5 > 206 基 板 放 置 台 207 第二 清 洗 裝 置 208 第 _—— 機 械 手 臂313734.ptd Page 33 543091 Brief description of type B 16 Protective film 16a Alloy film 17 Heating lamp 31 Bank member, 3 3 Seal 41 > 41-2 Shower head 43-2 Nozzle 51 Cleaning liquid supply device 53 Nozzle 61 Recycling barrel 65 Plating solution recovery nozzle 111 Barrier layer formation early 112 Seed layer formation unit 113 Electroplated film formation α port— * Zao 114 Annealing unit 115 First cleaning unit 116 Bevel and back cleaning unit 117 Top set plating unit • 8 Second cleaning unit 120 Loading / unloading unit 120a Cassette 121 First light moving device 122 Second light moving 5 and 131 > 203 first-robot arm 132 > 223 second robot arm 133 > 224 second machine Arm 134 Fourth robotic arm 141 First aligner and film thickness, measuring instrument 142 Second aligner and film thickness-I: measuring instrument 143 first substrate turning device 144 second Substrate turning device • Substrate temporary table 146 Second film thickness measuring instrument 201 Loading / unloading section 201-1 Cassette 202 Section • Plating device 2 0 5 > 206 Substrate placement table 207 Second cleaning device 208 Section _—— Machinery Arm

313734.ptd 第34頁 543091 圖式簡單說明 209 第 一 清 洗 裝 置 210 第 一 拋 光 裝 置 210-1 > 21 1- 1 拋 光 台 210 -2 > 21 1- 2 頂 環 210 -3、 21 1- 3 頂 環 頭 210 -4、 21 1- 4 膜 厚 度 量 測 裝置 210 -5 ^ 21 1- 5 推 進 器 21 1 第 -- 拋 光 裝 置 212 電 鍍 前 /後膜厚度' 量測裝置 213 乾 燥 狀 態 之 膜厚度 量測裝置 221 、m 基 板 放 置 台 225 推 進 器 索 引 器 227 第 二 電 鍍 裝 置 Μ 馬 達 W 半 導 體 基 板313734.ptd Page 34 543091 Brief description of the drawings 209 First cleaning device 210 First polishing device 210-1 > 21 1- 1 Polishing table 210 -2 > 21 1- 2 Top ring 210 -3, 21 1- 3 Top ring head 210 -4, 21 1- 4 Film thickness measurement device 210 -5 ^ 21 1- 5 Thruster 21 1st-Polishing device 212 Film thickness before / after plating 'Measurement device 213 Film in dry state Thickness measuring device 221, m substrate placement table 225 pusher indexer 227 second plating device M motor W semiconductor substrate

313734.ptd 第35頁313734.ptd Page 35

Claims (1)

543091 矢、申請專利範圍 ^ 1. 一種無電電鍍溶液，係在用以具有嵌入互連線路結構 之半導體裝置之曝露之互連線路表面上選擇性形成電 ' 鍍膜，該無電電鍍溶液包括鈷離子、錯合劑及不含鹼 ^ 金屬之還原劑。 *2.如申請專利範圍第1項之無電電鍍溶液，其中，該還原 劑包括烷基胺硼烷。 3.如申請專利範圍第1項之無電電鍍溶液，其中，復包括 至少一安定劑，其係選自重金屬化合物及硫化合物、 以及界面活性劑中之一種或更多種。 #如申請專利範圍第1項之無電電鍍溶液，其中，該無電 電鍍溶液之ρ Η係利用不含鹼金屬之ρ Η調整劑調整為在5 至1 4之範圍内。 5. 一種無電電鍍溶液，係用以在具有嵌入互連線路結構 之半導體裝置之曝露之互連線路表面上選擇性形成電 鍍膜，該無電電鍍溶液包括鈷離子、錯合劑、含耐火 金屬之化合物、以及不含鹼金屬之還原劑。 6. 如申請專利範圍第5項之無電電鍍溶液，其中，該耐火 金屬包括鎢及鉑之至少其中之一。 7. 如申請專利範圍第5項之無電電鍍溶液，其中，該還原 _劑包括烧基胺爛烧。 8. 如申請專利範圍第5項之無電電鍍溶液，其中，復包括 至少一安定劑，其係選自重金屬化合物及硫化合物、 . 以及界面活性劑中之一種或更多種。 9. 如申請專利範圍第5項之無電電鍍溶液，其中，該無電543091 Application scope of patent ^ 1. An electroless plating solution, which is used to selectively form an electroplating film on the surface of an exposed interconnect circuit for a semiconductor device having an embedded interconnect circuit structure. The electroless plating solution includes cobalt ions, Complexing agent and reducing agent without alkali ^ metal. * 2. The electroless plating solution according to item 1 of the application, wherein the reducing agent includes an alkylamine borane. 3. The electroless plating solution according to item 1 of the patent application scope, further comprising at least one stabilizer, which is one or more selected from the group consisting of a heavy metal compound and a sulfur compound, and a surfactant. #The electroless plating solution according to item 1 of the patent application range, wherein the ρ Η of the electroless plating solution is adjusted to be within a range of 5 to 14 by using a ρ Η modifier containing no alkali metal. 5. An electroless plating solution for selectively forming a plating film on the surface of an exposed interconnect circuit of a semiconductor device having an embedded interconnect circuit structure. The electroless plating solution includes cobalt ions, a complexing agent, and a compound containing a refractory metal. And reducing agent without alkali metal. 6. The electroless plating solution according to item 5 of the patent application, wherein the refractory metal includes at least one of tungsten and platinum. 7. The electroless plating solution according to item 5 of the application, wherein the reducing agent includes calcined amine. 8. The electroless plating solution according to item 5 of the patent application scope, further comprising at least one stabilizer, which is one or more selected from the group consisting of a heavy metal compound and a sulfur compound, and a surfactant. 9. If the electroless plating solution of item 5 of the patent application scope, wherein the electroless plating solution 313734.ptd 第36頁 543091 六、申請專利範圍 電鍍溶液之pH係利用不含鹼金屬之pH調整劑調整為在5 至1 4之範圍内。 10. —種半導體裝置，係具有銅、銅合金、銀、或銀合金 之嵌入互連線路結構，其中曝露之互連線路表面係以 保護膜選擇性覆蓋，該保護膜係使用無電電鍍溶液以 無電電鍍過程形成，該無電電鍍溶液包括鈷離子、錯 合劑及不含鹼金屬之還原劑。 1 1 .如申請專利範圍第1 0項之半導體裝置，其中，該還原 劑包括烧基胺觸烧。 1 2.如申請專利範圍第1 0項之半導體裝置，其中，該無電 電鍍溶液復包括至少一安定劑，其係選自重金屬化合 物及疏化合物、以及界面活性劑中之一種或更多種。 1 3.如申請專利範圍第1 0項之半導體裝置，其中，該無電 電鍍溶液之p Η係利用不含驗金屬之p Η調整劑調整為在 5至1 4之範圍内。 14. 一種半導體裝置，其係具有銅、銅合金、銀、或銀合 金之嵌入互連線路結構，其中，曝露之互連線路表面 係以保護膜作選擇性覆蓋，該保護膜係使用無電電鍍 溶液以無電電鍍過程形成，該無電電鍍溶液包括鈷離 子、錯合劑、含耐火金屬之化合物、以及不含驗金屬 之還原劑。 1 5.如申請專利範圍第1 4項之半導體裝置，其中，該耐火 金屬包括鎮及钥之至少其中之一。 16.如申請專利範圍第14項之半導體裝置，其中，該還原313734.ptd Page 36 543091 6. Scope of patent application The pH of the plating solution is adjusted to be within the range of 5 to 14 by using a pH adjusting agent containing no alkali metal. 10. A semiconductor device having an embedded interconnection circuit structure of copper, copper alloy, silver, or silver alloy, wherein the exposed interconnection circuit surface is selectively covered with a protective film which uses an electroless plating solution to The electroless plating process is formed. The electroless plating solution includes cobalt ions, a complexing agent, and a reducing agent containing no alkali metal. 1 1. The semiconductor device according to item 10 of the patent application scope, wherein the reducing agent comprises an alkylamine. 1 2. The semiconductor device according to item 10 of the application, wherein the electroless plating solution further comprises at least one stabilizer, which is one or more selected from the group consisting of heavy metal compounds and phosgene compounds, and a surfactant. 1 3. The semiconductor device according to item 10 of the patent application range, wherein the p Η of the electroless plating solution is adjusted to be within a range of 5 to 14 by using a p Η modifier that does not contain a test metal. 14. A semiconductor device having an embedded interconnection circuit structure of copper, copper alloy, silver, or silver alloy, wherein the surface of the exposed interconnection circuit is selectively covered with a protective film, which uses electroless plating The solution is formed by an electroless plating process. The electroless plating solution includes cobalt ions, a complexing agent, a compound containing a refractory metal, and a reducing agent containing no metal. 15. The semiconductor device according to item 14 of the patent application scope, wherein the refractory metal includes at least one of a town and a key. 16. The semiconductor device according to item 14 of the application, wherein the reduction 313734.ptd 第37頁 543091 六、申請專利範圍 劑包括烧基胺硼烧。 17. 如申請專利範圍第14項之半導體裝置，其中，該無電 電鍍溶液復包括至少一安定劑，其係選自重金屬化合 物及硫化合物、以及界面活性劑中之一種或更多種。 18. 如申請專利範圍第14項之半導體裝置，其中，該無電 電鍍溶液之pH係利用不含鹼金屬之pH調整劑調整為在5 至1 4之範圍内。 1 9. 一種半導體裝置，係具有嵌入互連線路結構，其中， 曝露之互連線路表面係以包括鈷之金屬之保護膜作選 ®擇性覆蓋。 2 〇.如申請專利範圍第1 9項之半導體裝置，其中，該保護 膜之厚度係在0.1至500奈米之範圍内。 21, —種半導體裝置，係具有嵌入互連線路結構，其中曝 露之互連線路表面係以包括鈷及耐火金屬之合金之保 護膜作選擇性覆蓋。 2 2.如申請專利範圍第2 1項之半導體裝置，其中，該耐火 金屬包括鎢及鉬之至少其中之一。 2 3.如申請專利範圍第2 1項之半導體裝置，其中，該保護 膜之厚度係在0.1至500奈米之範圍内。 _•一種製造半導體裝置之方法，包括： 利用無電電鍍溶液，於具有嵌入互連線路結構之 半導體基板上施行無電電鍍，以於該半導體基板之互 連線路之表面上，選擇性形成電鍍膜之保護層； 其中該無電電鍍溶液包括鈷離子、錯合劑以及不313734.ptd Page 37 543091 6. Scope of Patent Application The agent includes stilbylamine boron. 17. The semiconductor device according to item 14 of the application, wherein the electroless plating solution includes at least one stabilizer, which is one or more selected from the group consisting of a heavy metal compound and a sulfur compound, and a surfactant. 18. The semiconductor device according to item 14 of the patent application range, wherein the pH of the electroless plating solution is adjusted to be within a range of 5 to 14 by using a pH adjusting agent containing no alkali metal. 1 9. A semiconductor device having an embedded interconnect structure, wherein the exposed interconnect surface is selectively covered with a protective film of a metal including cobalt. 20. The semiconductor device according to item 19 of the scope of patent application, wherein the thickness of the protective film is in the range of 0.1 to 500 nm. 21. A semiconductor device having an embedded interconnect circuit structure, wherein the surface of the exposed interconnect circuit is selectively covered with a protective film including an alloy of cobalt and a refractory metal. 2 2. The semiconductor device according to item 21 of the patent application scope, wherein the refractory metal includes at least one of tungsten and molybdenum. 2 3. The semiconductor device as claimed in claim 21, wherein the thickness of the protective film is in the range of 0.1 to 500 nm. _ • A method for manufacturing a semiconductor device, comprising: using an electroless plating solution to perform electroless plating on a semiconductor substrate having an embedded interconnection circuit structure so as to selectively form a plating film on the surface of the interconnection circuit of the semiconductor substrate A protective layer; wherein the electroless plating solution includes cobalt ions, a complexing agent, and 313734.ptd 第38頁 543091 六、申請專利範圍 含驗金屬之還原劑。 2 5.如申請專利範圍第2 4項之方法，其中，該還原劑包括 烷基胺硼烷。 2 6.如申請專利範圍第2 4項之方法，其中，復包括至少一 安定劑，其係選自重金屬化合物及硫化合物、以及界 面活性劑中之一種或更多種。 2 7.如申請專利範圍第2 4項之方法，其中，該無電電鍍溶 液之pH係利用不含鹼金屬之pH調整劑調整為在5至14之 範圍内。 28. —種製造半導體裝置之方法，包括： 利用無電電鍍溶液，於具有嵌入互連線路結構之 半導體基板上施行無電電鐘’以於該半導體基板之互 連線路表面上，選擇性形成電鍍膜之保護層； 其中，該無電電鍍溶液包括鈷離子、錯合劑、含 耐火金屬之化合物、及不含鹼金屬之還原劑。 2 9.如申請專利範圍第2 8項之方法，其中，該耐火金屬包 括鎢及鉬之至少其中之一。 3 〇.如申請專利範圍第2 8項之方法，其中，該還原劑包括 烷基胺硼烷。 3 1 .如申請專利範圍第2 8項之方法，其中，復包括至少一 安定劑，其係選自重金屬化合物及硫化合物、以及界 面活性劑中之一種或更多種。 3 2.如申請專利範圍第2 8項之方法，其中，該無電電鍍溶 液之pH係利用不含鹼金屬之pH調整劑調整為在5至14之313734.ptd Page 38 543091 6. Scope of patent application Reducing agent containing metal test. 25. The method of claim 24, wherein the reducing agent comprises an alkylamine borane. 26. The method of claim 24, wherein the method includes at least one stabilizer, which is one or more selected from the group consisting of a heavy metal compound and a sulfur compound, and a surfactant. 2 7. The method according to item 24 of the scope of patent application, wherein the pH of the electroless plating solution is adjusted to be within a range of 5 to 14 by using a pH adjusting agent containing no alkali metal. 28. A method for manufacturing a semiconductor device, comprising: using an electroless plating solution to perform an electroless clock on a semiconductor substrate having an embedded interconnection circuit structure to selectively form a plating film on the surface of the interconnection circuit of the semiconductor substrate A protective layer; wherein the electroless plating solution includes cobalt ions, a complexing agent, a compound containing a refractory metal, and a reducing agent not containing an alkali metal. 29. The method of claim 28, wherein the refractory metal includes at least one of tungsten and molybdenum. 30. The method of claim 28, wherein the reducing agent comprises an alkylamine borane. 31. The method of claim 28, wherein the method further comprises at least one stabilizer, which is one or more selected from the group consisting of a heavy metal compound and a sulfur compound, and a surfactant. 3 2. The method according to item 28 of the scope of patent application, wherein the pH of the electroless plating solution is adjusted to 5 to 14 by using a pH adjusting agent containing no alkali metal. 313734.ptd 第39頁 543091 ^、申請專利範圍 範圍内1 313734.ptd 第40頁 iiii313734.ptd page 39 543091 ^, within the scope of patent application 1 313734.ptd page 40 iiii
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