TW536828B - Bottom gate type thin film transistor, its manufacturing method and liquid crystal display device using the same - Google Patents
Bottom gate type thin film transistor, its manufacturing method and liquid crystal display device using the same Download PDFInfo
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- TW536828B TW536828B TW090118205A TW90118205A TW536828B TW 536828 B TW536828 B TW 536828B TW 090118205 A TW090118205 A TW 090118205A TW 90118205 A TW90118205 A TW 90118205A TW 536828 B TW536828 B TW 536828B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000010409 thin film Substances 0.000 title claims abstract description 16
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 22
- 239000010408 film Substances 0.000 claims abstract description 68
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 30
- 238000012545 processing Methods 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 241000196324 Embryophyta Species 0.000 claims 1
- 239000003990 capacitor Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 36
- 239000002344 surface layer Substances 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 description 22
- 239000000463 material Substances 0.000 description 10
- 239000011521 glass Substances 0.000 description 8
- 239000004575 stone Substances 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000002131 composite material Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- FGRBYDKOBBBPOI-UHFFFAOYSA-N 10,10-dioxo-2-[4-(N-phenylanilino)phenyl]thioxanthen-9-one Chemical compound O=C1c2ccccc2S(=O)(=O)c2ccc(cc12)-c1ccc(cc1)N(c1ccccc1)c1ccccc1 FGRBYDKOBBBPOI-UHFFFAOYSA-N 0.000 description 1
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 238000003775 Density Functional Theory Methods 0.000 description 1
- -1 Nitrogen ions Chemical class 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- YZCKVEUIGOORGS-NJFSPNSNSA-N Tritium Chemical compound [3H] YZCKVEUIGOORGS-NJFSPNSNSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000009529 body temperature measurement Methods 0.000 description 1
- 238000010411 cooking Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 150000004767 nitrides Chemical group 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052722 tritium Inorganic materials 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Nonlinear Science (AREA)
- Manufacturing & Machinery (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
536828536828
發明之背景 發明之領域 本^月係關於—種薄膜電晶體（TFT)以及-種方法用以 造此TFT。牿兄，丨s 丄々 、 ⑺疋’本發明係關係於一種底閘型TFT應用至 主動式陣列型液晶顯示裝置’與-種製造此TFT的方法。 t么明也關於一種包含此底閘型TFTs之液晶|頁示裝置。 先如技術說明 今;1:::體一般用於電子裝置，如液晶顯示(lcd)裝置與 & — i ’、為。特別是，根據像素資訊，主動式陣列型液晶 顯示面板，使用丁FTS每一者包含一源極電極，一汲極； 極，與一通道區域當成元素，用以提供適當電壓至像素電 極。-些穿透式主動式陣列型LCDS提供一遮光膜給每一 TFT，來切斷可能進入TFT的光線，特別是_面板背側之 背光到通道區域。 舉例而言，當TFT受控制於保持於完全“關閉，，狀態時’若 光線進入ϋ道區i或’會減少源極肖汲極電極之間的絕緣程 度’因此發生漏電流。此更進-步導致像素電極連接至及 極電極之不必要電位變動，丨進一步惡化所顯示之影像品 質。為了避免如此漏電流，已有提供一種傳統解決方法提 供一遮光膜覆蓋LCD面板背光側上通道區域，用以防止通 道區域受到光照。 非 此TFT製造方法揭示於曰本專利申請公開案號 13 1021/ 95，包含於一玻璃基板上沉積一摻雜磷之矽膜當作b 遮光膜，並且在此矽膜上表面形成氧化石夕膜。然後，、田 -4 - 536828BACKGROUND OF THE INVENTION Field of the Invention This month is about a thin film transistor (TFT) and a method for manufacturing the TFT. Brother, s 丄 々, ⑺ 疋 ′ The present invention relates to the application of a bottom-gate TFT to an active-array liquid crystal display device and a method for manufacturing the TFT. tmeming also relates to a liquid crystal display device including such bottom-gate TFTs. First, as described in the technology, the 1: 1 :: body is generally used in electronic devices, such as liquid crystal display (lcd) devices and & — i ′. In particular, according to the pixel information, the active-array liquid crystal display panel uses DFTs, each of which includes a source electrode, a drain electrode, and a channel region as elements to provide an appropriate voltage to the pixel electrode. -Some transmissive active-array LCDS provide a light-shielding film to each TFT to cut off the light that may enter the TFT, especially the backlight on the back side of the panel to the channel area. For example, when the TFT is controlled to remain completely "off," the state of 'if light enters the channel area i or' will reduce the degree of insulation between the source and drain electrodes' and therefore leakage current occurs. -The step leads to unnecessary potential changes of the pixel electrode connected to the electrode, further deteriorating the displayed image quality. In order to avoid such a leakage current, a conventional solution has been provided to provide a light shielding film to cover the channel area on the backlight side of the LCD panel In order to prevent the channel area from being exposed to light, this TFT manufacturing method is disclosed in Japanese Patent Application Publication No. 13 1021/95, which includes depositing a silicon film doped with phosphorus on a glass substrate as a b-shielding film, and A silicon oxide film is formed on the upper surface of this silicon film. Then, Tian-4-536828
::膜於氧化贿表嘯’其將在稍後步驟形成源極 二極，汲極電極與通道區域。之後，於非晶矽膜上，另一 氧化石夕膜與紹膜依序沉積 '然後形成—堆疊層，、藉由 阻處理（光罩處理）與蝕刻處理之圖形定義處理，成為比盆 :層=小之島狀’並且由㈣，氧切膜與非晶石夕膜組 成。然後，將氮離子植入至堆疊層以外的氧化石夕膜與摻雜 鱗之石夕膜區域。因此本方法只在氧切膜與摻雜鱗之石夕膜 上離子佈植部分執行_次退火處理，使得氮化物部分透明 化0 所以’以上所參考的，已知方法在想要的部分執行透明 化&以及給予堆疊層下方部分之摻雜叙錢-種遮光膜 功月匕後來，-氧化石夕膜在非晶石夕膜上形成問極絕緣層， 以及一圍繞著閘極電極之圖形定義閘極電極與的氧化層更 進步在閘極絕緣層上形成。在問極部分形成之後，碟離 子使用閘極部分當作料植人非晶②膜，以形成㈣源極與 及極區域。結果’閘極部分τ方之非晶部分成為通道形成 區域，以及其他非晶部分形成Ν型源極與汲極區域。因為自 玻璃基板外表面側進入源極，汲極與通道區域的光線可藉 由遮光膜切斷，其可能阻止背光系統的光線進入所完成的 通道區域’所以引起上述之漏電流。 然而’因為使用離子植入處理形成最終源極與汲極電 極，如此傳統方法需要昂貴的植入設備。由於在離子佈植 處理之則，使用電漿CVD設備以非晶矽膜在基板上形成源 極，汲極與通道區域，傳統方法也需要一自電漿cVD設備 ____-5- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 536828 A7 _____ B7 五、發明説明（3 ) 到離子植入設備的處理基板組合傳送系統；亦即是，需要 處理腔體之間的傳送。因此，傳統方法的缺點為處理複 雜，其處理的環境分立，並且基板組合需小心處置以避免 灰塵，破壞等等。結果趨向於大負荷的TFT製造成本，以及 造成昂貴的製造成本。 更進一步地說，傳統方法以所謂頂閘型TFTs揭示，其中 遮光膜放置在通道區域底側（遠離液晶介質一侧，即lCD面 板後側或背光側）’以及閘極電極放在通道區域上側。然 而，底閘型TFTs (其中閘極電極放在通道區域底側）更優於 應用至牙透式液晶顯示裝置。那是因為放置在底閘型通 道區域底側之閘極電極，有另一個在穿透式液晶顯示裝置 通道區域遮光的功能。因此，穿透式液晶顯示裝置不需供 應遮光膜，以及不需要其製造步驟，同時降低TFT製造處理 的負荷。因此，底閘型TFT結構，性能以及製造處理的改進 可以明顯地對於穿透式液晶顯示裝置成本降低與能力提昇 有明顯的貢獻。 發明之摘要 觀察上述背景，本發明的一個目標為提供一良好的底閘 型TFT與其製造方法，並且製造處理負荷與製造成本能夠降 低。 本發明的另一個目標為提供一底閘型TF丁與其製造方法， 並且適用於穿透式液晶顯示裝置。 為了達到上述目標，本發明提供一底閘型TFT，其中依序 玫置一基礎層，一閘極電極層，一閘極絕緣膜與源極以及 —一 -6 -:: Film in the oxidation table ’It will form the source diode, the drain electrode and the channel region in a later step. After that, on the amorphous silicon film, another stone oxide film and a shaw film were sequentially deposited and then formed-a stacked layer, and through the pattern definition processing of the resist processing (mask processing) and the etching processing, it became a specific basin: The layer = Konoshima-like 'and is composed of tritium, oxygen-cut film, and amorphous stone film. Nitrogen ions are then implanted into the oxidized stone scale and doped scale stone scale areas outside the stacked layers. Therefore, this method only performs _second annealing treatment on the ion implanted part on the oxygen-cut film and the doped scale stone film to make the nitride part transparent. So 'the above referenced, known methods are performed on the desired part Transparentization & doping to the lower part of the stacked layer-after a kind of light-shielding film, the oxide stone film forms an interlayer insulating layer on the amorphous stone film, and a layer surrounding the gate electrode The figure defines that the gate electrode and the oxide layer are formed more on the gate insulation layer. After the interrogation part is formed, the dish ion uses the gate part as a material to implant an amorphous film to form a source and an electrode region. As a result, the amorphous portion of the gate portion τ becomes a channel formation region, and other amorphous portions form N-type source and drain regions. Since the light enters the source from the outer surface side of the glass substrate, the light in the drain and channel regions can be cut off by the light-shielding film, which may prevent the light of the backlight system from entering the completed channel region ', thus causing the above-mentioned leakage current. However, because the final source and drain electrodes are formed using an ion implantation process, such traditional methods require expensive implantation equipment. As the ion implantation process, plasma CVD equipment is used to form the source, drain and channel regions on the substrate with an amorphous silicon film. The traditional method also requires a self-plasma cVD equipment ____- 5- This paper size Applicable to China National Standard (CNS) A4 specification (210X297 mm) 536828 A7 _____ B7 V. Description of the invention (3) Combination processing system for processing substrates to ion implantation equipment; that is, transfer between processing chambers is required. Therefore, the disadvantages of the traditional method are that the processing is complicated, the processing environment is separate, and the substrate assembly needs to be handled carefully to avoid dust, damage, and so on. As a result, the TFT manufacturing cost tends to be heavy load, and it causes expensive manufacturing cost. Furthermore, the traditional method is disclosed with so-called top-gate TFTs, in which the light-shielding film is placed on the bottom side of the channel area (the side away from the liquid crystal medium, that is, the rear side of the LCD panel or the backlight side) and the gate electrode is placed on the upper side of the channel area . However, bottom-gate TFTs (where the gate electrode is placed on the bottom side of the channel area) are better than those applied to dental transmissive liquid crystal display devices. That is because the gate electrode placed on the bottom side of the bottom gate type channel area has another function of shielding light in the channel area of the transmissive liquid crystal display device. Therefore, the transmissive liquid crystal display device does not need to be supplied with a light-shielding film, and its manufacturing steps are not required, and at the same time, the load of the TFT manufacturing process is reduced. Therefore, improvements in the structure, performance, and manufacturing process of the bottom-gate TFT can obviously contribute to the cost reduction and capacity improvement of the transmissive liquid crystal display device. SUMMARY OF THE INVENTION In view of the above background, an object of the present invention is to provide a good bottom-gate TFT and a manufacturing method thereof, and the manufacturing processing load and manufacturing cost can be reduced. Another object of the present invention is to provide a bottom gate type TF and its manufacturing method, which is suitable for a transmissive liquid crystal display device. In order to achieve the above object, the present invention provides a bottom-gate TFT, in which a base layer, a gate electrode layer, a gate insulating film and a source are sequentially disposed, and a-6-
本度適用t國國家標準(CNS) A4規格(ϋ〇Χ297公酱) 536828 五、發明説明（4 ) 及極電極，此電晶體包含一半導體通道層與介於源極以及 汲極電極之間曝露的閘極絕緣膜接觸，而個別地與源極以 及/及極電極之相反側接觸，並且相對應於問極電極形成， 通道層在源極以及汲極電極上側，自交錯相反一端橋接到 另一端，ϋ道層肖源極以及没極電極接觸㉝分形成 觸表面層。 以此結構，在該源極以及及極電極形成後，相同電浆 CVD設備可以-致地不僅使用於形成通道層處理，也可用 於源極以及汲極電極和通道層之間形成歐姆接觸的處理， 使得能夠獲得不需處理腔體之間傳送的簡化處理。此外， 所要的源極/汲極電流路徑更優於底閘型結構下形成。 更甚的是’電晶體中’在通道層底部形成一通道，並且 結合源極與汲極電極之剖視角度形成_直線型電流路徑。 、此外’閘極電極可由遮光材f形成，其可遮斷可能進入 通這層的光線。此情形之下，此問極電極也可以利用為一 遮光膜，其相當適用於穿透式液晶顯示裝置。 本發明也料強化穿透式液晶顯示裝置有所供獻’盆中 機射系統放置在基礎層後側，並且其像素由此底問 溥膜電晶體所驅動。 - i 本發明更進-步提供一種製造薄膜電晶體的方法。 ::包含··-前置步驟依序在基礎層上形成閉極電極；極 緣膜，以及源極與汲極電極；藉由電焚摻雜處理，以# 原子對：極與汲極電極表層進行電毁摻雜之磷處理7 亚且接者通道形成步驟’使得半導體通道層接觸源極與汲 -7- 本紙張尺度適财_家標準(CNS) Ali"格(21〇X297公茇） 536828 A7This standard applies to the national standard (CNS) A4 specification (ϋ〇 × 297 公 酱) 536828 V. Description of the invention (4) and the electrode, the transistor includes a semiconductor channel layer and is interposed between the source and drain electrodes The exposed gate insulating film is in contact with the source and / or the opposite side of the electrode individually, and is formed corresponding to the interrogation electrode. The channel layer is above the source and drain electrodes and bridges from the opposite end of the stagger to At the other end, the source electrode and the non-polar electrode of the channel layer are in contact with each other to form a contact surface layer. With this structure, after the source electrode and the electrode electrode are formed, the same plasma CVD equipment can be used not only for forming a channel layer process, but also for forming an ohmic contact between the source electrode and the drain electrode and the channel layer. Processing makes it possible to obtain simplified processing without the need to transfer between processing chambers. In addition, the desired source / drain current path is better than that formed in a bottom-gate structure. What's more, a channel is formed at the bottom of the channel layer in the 'transistor', and a linear current path is formed by combining the cross-sectional angles of the source and drain electrodes. In addition, the gate electrode may be formed of a light shielding material f, which can block light that may enter this layer. In this case, the interrogation electrode can also be used as a light-shielding film, which is quite suitable for a transmissive liquid crystal display device. The present invention also expects that a reinforced transmissive liquid crystal display device is provided. The machine-emitting system is placed on the rear side of the base layer, and its pixels are driven by the bottom film transistor. -i The present invention further provides a method for manufacturing a thin film transistor. :: Contains ·· -Preliminary steps to form a closed electrode on the base layer in sequence; a polar edge film, and a source and a drain electrode; by electro-doping treatment, #atomic pair: the electrode and the drain electrode The surface layer is electrolyzed and doped with phosphorous. 7 Sub- and subsequent channel formation steps' make the semiconductor channel layer contact the source and drain -7- This paper is suitable for financial standards_CNS Ali " 格 (21〇X297 公 茇) ) 536828 A7
:電極之間曝露之閘極絕緣膜部分’而與個別源極-沒極· 乂錯相反端接觸，且相對應於間極電極形成，通 源極與没極電極上表面交錯相反端之一橋接到另一端、曰 特別較佳地，所發明方法中料理步驟與通道層 驟是以相同電漿CVD設備執行。 乂 y 本發明這些與其他方面可參考務後所提實施例說明與明 附圖之簡明說明 圖1為顯示器面板基板組合部分切面圖，列出根據本發明 所提第一實施例之TFT結構。 圖2為一個第一流程圖，列出圖j之丁F丁製造程序前半部 分0 圖3為一個第二流程圖，列出圖j之TFT製造程序後半部 分。 圖4為一切面圖’展列圖2與3所列流程第一製造階段，部 分TFT的中間結構。 圖5為一切面示意圖，展列圖2與3所列流程第二製造階 段，部分TFT的中間結構。 圖6為一切面視圖，展列圖2與3所列流程第三製造階段， 部分TFT的中間結構。 圖7為一 TFT部分切面，放大視圖，列出填處理製程。 圖8為一切面視圖，展列圖2與3所列流程第四製造階段， 部分TFT的中間結構。 圖9為一切面視圖，展列圖2與3所列流程第五製造階段， 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 536828 A7 B7 五、發明説明（6 部分TFT的中間結構。 圖10為一切面視圖，展列圖2與3所列流程第六製造階 段，部分TFT的中間結構。 圖11為顯示裔面板基板組合部分切面圖，列出根據本發 明所提第二實施例之TFT結構。 圖12為根據第一與第二實施例之TFT部分切面視圖，展列 此TFT源極與汲極電極間的電流路徑。 圖1 3為根據不同於第一與第二實施例之範例所提TFT部分 切面視圖，展列此TF丁源極與汲極電極間的電流路徑。 較佳實施例之說明 圖1展列根據本發明一實施例TFT (薄膜電晶體）的切面示 意圖。 圖1所列之TFT用於主動式陣列型穿透式液晶顯示裝置的 顯示面板中。此執行影像之光調變的液晶介質Lc封存在兩 組合板100 ’ 200之間，每一者使用玻璃基板為基礎層，並 且TFT在一組合板1〇〇之玻璃基板丨形成。來自放置在玻璃基 板1後側光線放射系統之背光BL，透過玻璃基板1而進入液 晶介質，部分TF丁在基板與像素電極上表面形成，受到光調 變而透過其他組合板200導入外部顯示螢幕。 閘極2由遮光材料形成，其也可以當作一種遮光膜，放置 在玻璃基板1的上表面，亦即是在基板液晶介質LC側。然 而，可能形成一絕緣膜’例如，一種包含氧化矽（SiOx)當 作基板1與閘極2之間的基礎層位於基板1上表面。此外，基 板1之上’一種閘極絕緣層3如SiNx形成且覆蓋在閘極2。然 -9 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐): The part of the gate insulating film exposed between the electrodes is in contact with the opposite end of the individual source-polar electrode, and it is formed corresponding to the intermediate electrode. Bridged to the other end, it is particularly preferred that the cooking step and the channel step in the invented method are performed using the same plasma CVD equipment.这些 y For these and other aspects of the present invention, reference may be made to the description and description of the embodiments mentioned later. Brief description of the drawings FIG. 1 is a sectional view of a display panel substrate assembly, listing a TFT structure according to the first embodiment of the present invention. FIG. 2 is a first flowchart showing the first half of the manufacturing process of FIG. J and FIG. 0. FIG. 3 is a second flowchart showing the second half of the TFT manufacturing process of FIG. Fig. 4 is a plan view showing all the intermediate structures of a part of the TFTs in the first manufacturing stage of the processes listed in Figs. Fig. 5 is a schematic view of all planes, showing the second manufacturing stage of the processes listed in Figs. 2 and 3, and the intermediate structure of some TFTs. FIG. 6 is a plan view of the whole, showing the third manufacturing stage of the processes listed in FIGS. 2 and 3, and the intermediate structure of some TFTs. FIG. 7 is a partial cut-away view of a TFT, showing an enlarged view and listing a filling process. FIG. 8 is a plan view of the whole, showing the intermediate structure of some TFTs in the fourth manufacturing stage of the processes listed in FIGS. 2 and 3. Figure 9 is an all-encompassing view, showing the fifth manufacturing stage of the processes listed in Figures 2 and 3. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 536828 A7 B7 V. Description of the invention (Section 6 Intermediate structure of TFT. Fig. 10 is an all-surface view showing the sixth manufacturing stage of the processes listed in Figs. 2 and 3. Some intermediate structures of TFTs are shown in Fig. 11. Fig. 11 is a cut-away view showing a combination of panel substrates. The TFT structure of the second embodiment is mentioned. Fig. 12 is a partial cross-sectional view of the TFT according to the first and second embodiments, showing the current path between the source and the drain electrode of the TFT. A cross-sectional view of a portion of the TFT mentioned in the example of the second embodiment shows the current path between the TF source and the drain electrode. Description of the Preferred Embodiment FIG. 1 shows a TFT (thin-film electrode) according to an embodiment of the present invention. (Crystal). The TFTs listed in Figure 1 are used in the display panel of an active-array transmissive liquid crystal display device. This liquid crystal medium Lc, which performs light modulation of the image, is sealed between the two composite boards 100'200. , Each using a glass substrate The base layer and the TFT are formed on a glass substrate of a composite board 100. The backlight BL from the light emission system placed on the rear side of the glass substrate 1 passes through the glass substrate 1 and enters the liquid crystal medium, and a part of the TF is on the substrate and the pixel electrode. The upper surface is formed, and is subjected to light modulation and is introduced into an external display screen through other combination boards 200. The gate 2 is formed of a light-shielding material, which can also be used as a light-shielding film and placed on the upper surface of the glass substrate 1, that is, on the substrate The LC side of the liquid crystal medium. However, an insulating film may be formed, for example, a base layer containing silicon oxide (SiOx) as the base layer between the substrate 1 and the gate 2 is located on the upper surface of the substrate 1. In addition, a gate is formed on the substrate 1 The electrode insulation layer 3 is formed of SiNx and covers the gate electrode 2. Ran-9-This paper size is applicable to China National Standard (CNS) A4 (210X297 mm)
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536828 A7 B7 五、發明説明（8 緣層8上表面延伸，使得像素電極9可以接觸汲極電極5。對 應至閘極接端（未列出）之絕緣層8部分也可以移除，而形成 接觸孔以閘極電極2接觸間極接端。在此穿透式顯示裝置實 施例中，像素電極9為以如IT〇 (銦錫氧化物）所組成之透明 傳導膜。 應注意的是：當作源極匯流排線的源極電極4 (金屬層叫 在顯示面板的有效顯示區域垂直延伸，但不在此列出；並 且當作閘極匯流排線的閘極電極2在顯示面板的有效顯示區 域水平延伸。同樣地，像素電極9設計為在圖〗中更向右延 伸而未列出。此延伸區域貢獻像素區域或引用電壓區域給 液晶層LC。 雖然在像素電極9更上層一側提供一或多層LC對準層，為 了釐清本發明所述而不在此說明。 現在，將說明製造具有圖！展列薄膜電晶體的方式。圖2 與3以流程圖形式展列製造方法程序’並且圖仁⑺展列個別 製造階段所處理TFT的切面結構。 參考圖2，首先準備一玻璃基板丨（步驟，然後一種包 含鋁或鋁合金材質當作閘極電極藉由濺鍍處理沉積在基板夏 上（步驟S2)。接著如圖4所列形狀對所沉積膜圖形定義，來 形成閘極區域2 (步驟S3)。另一方面，閘極2可為一種堆疊 結構包含至少一種低阻值材料。步驟“之圖形定義處理= 含具有光阻之遮罩處理，曝光與顯影處理，以及蝕刻與移 除處理。 ' 更進一步地說，閘極絕緣膜3藉由濺鍍處理沉積一種材料 -11 -536828 A7 B7 V. Description of the invention (8 The upper surface of the edge layer 8 extends so that the pixel electrode 9 can contact the drain electrode 5. The portion of the insulating layer 8 corresponding to the gate terminal (not listed) can also be removed and formed The contact hole is terminated with the gate electrode 2 in contact. In this embodiment of the transmissive display device, the pixel electrode 9 is a transparent conductive film composed of IT0 (indium tin oxide). It should be noted that: The source electrode 4 as the source bus line (the metal layer is called to extend vertically in the effective display area of the display panel, but it is not listed here; and the gate electrode 2 as the gate bus line is effective in the display panel The display area extends horizontally. Similarly, the pixel electrode 9 is designed to extend further to the right in the figure and is not listed. This extended area contributes the pixel area or the reference voltage area to the liquid crystal layer LC. Although it is on the upper side of the pixel electrode 9 One or more LC alignment layers are provided in order to clarify what is described in the present invention and are not described here. Now, a method for manufacturing a thin film transistor will be described! A method for manufacturing a thin film transistor is shown. Figures 2 and 3 show a flowchart of a manufacturing method program. and Figure 2 shows the cross-section structure of TFTs processed in individual manufacturing stages. Referring to Figure 2, first prepare a glass substrate (step, then a material containing aluminum or aluminum alloy as the gate electrode is deposited on the substrate by sputtering process). (Step S2). Next, the deposited film pattern is defined as shown in the shape shown in FIG. 4 to form the gate region 2 (Step S3). On the other hand, the gate 2 may be a stacked structure including at least one low-resistance material . The process of pattern definition of step "= includes mask processing with photoresist, exposure and development processing, and etching and removal processing. 'Furthermore, the gate insulating film 3 deposits a material by sputtering processing-11 -
536828 A7536828 A7
536828 A7 B7 五、發明説明（10 ^ ' ' ------ 一 原子基本上傾向於盥 一電乳傳導物質結合，而不與電氣絕緣 物貝結合。因此所挑i r 5政之磷分佈在圖6放大之圖7中點所列 的源極與汲極表層部分。 現在’參考圖3回到掣 衣矛王4刀，一半導體材料包含如非晶 石夕a- Si當作通道區域6，u 防与 以及一、纟巴緣材料包含如SiNx當作絕 緣膜7依序沉積在湄4 、 原極4與汲極5上表面（步驟S9與步驟 S1 〇)。此沉積處理佶u^ ” 使用上述之相同電漿CVD設備。然後， 在所沉積膜上進行相同圖形定義處理，使得島型之通道形 成區域包含半導體膜6與絕緣膜7如圖8所展列相對應於閉極 2形成（步驟S 1 1)。 此處，由於CVD設備電漿與高溫氣氛效應，-些鱗自接 $表面擴政至源極4與汲極5而進入傳導膜6，使得n型半導 n a Si非g薄，而在傳導膜6和源極4與汲極$接觸部分形 成。此n+a-Si薄膜成為上述歐姆接觸層6c。值得注意，存在 於大邛刀源極4與汲極5曝露部分之磷可以在半導體膜^與絕 緣膜7圖形定義處理期間（乾式蝕刻）消失。 步驟S11之後，一種材料如SiNx沉積在源極4與汲極5，而 2全覆蓋島型通道形成區域(步驟S12)，並且執行相同圖形 定義處理（步驟S13)。此圖形定義如圖9所列形成保護膜8， 其在相對於汲極金屬層5m所只需曝露部分之接觸孔8〇移除 (步驟S 13)。 之後，一相對應於顯示面板像素之像素電極的透明傳導 材料如ITO (銦錫氧化物），沉積於接觸孔8〇底層與孔壁， 以及絕緣膜8上表面（步驟S14)。在所沉積之Ιτ〇上執行相同 - 13- ^36828 11 五、發明説明（ =定ίί理，以形成適當形狀與位置之像素電極(步驟 觸;：二…10所展列，像素電極9與没極電極5接 亚 正個具有孔80預定區域的保護膜8 〇 薄膜電晶體方法中’可能使用簡單的濺鑛處理 與没極5之前置階段。同樣地，電毁㈣設 離子^植^成+導體膜6°所以不需用昂貴的處理設備如 後 雷、=’來形成這些膜。此外，形成源極與沒極之 可破μ/kcvd設備的處理腔體不僅形成半導體膜，也 牛=处理以形成歐姆接觸。因此，不需上述傳統腔體536828 A7 B7 V. Description of the invention (10 ^ '' ------ An atom basically tends to combine with an electric milk conductive substance, but not with electrical insulators. Therefore, the selected phosphorous is distributed in Figure 6 enlarges the source and drain surface parts listed at the point shown in Figure 7. Now, referring back to Figure 3, return to the King of Blades, a semiconductor material containing amorphous silicon a-Si as the channel region 6 U and the first and second edge materials, such as SiNx as an insulating film 7 are sequentially deposited on the upper surface of Mae 4, source 4 and drain 5 (step S9 and step S1). This deposition process 佶 u ^ "The same plasma CVD equipment is used. Then, the same pattern definition process is performed on the deposited film, so that the island-shaped channel formation area contains the semiconductor film 6 and the insulating film 7 as shown in Fig. 8 corresponding to the closed electrode 2 Formation (step S 1 1). Here, due to the plasma and high-temperature atmosphere effect of the CVD equipment, some scales enter the conductive film 6 from the surface expansion to the source 4 and the drain 5 so that the n-type semiconducting na Si is not thin, but is formed in the contact portion between the conductive film 6 and the source 4 and the drain $. This n + a-Si film becomes the above The ohmic contact layer 6c. It is worth noting that the phosphorus existing in the exposed portions of the source 4 and the drain 5 of the large trowel can disappear during the pattern definition processing (dry etching) of the semiconductor film ^ and the insulating film 7. After step S11, a material such as SiNx is deposited on the source 4 and the drain 5, and 2 completely covers the island-shaped channel formation area (step S12), and performs the same pattern definition process (step S13). This pattern definition forms a protective film 8 as listed in FIG. 9, which The contact hole 80 which is only required to be exposed to the drain metal layer 5m is removed (step S13). Then, a transparent conductive material such as ITO (indium tin oxide) corresponding to the pixel electrode of the display panel pixel is removed. , Deposited on the bottom layer and hole wall of the contact hole 8 and the upper surface of the insulating film 8 (step S14). The same is performed on the deposited Ιτ〇-13- ^ 36828 11 V. Description of the invention (= 定 ίί 理, to form Pixel electrodes of appropriate shape and position (steps; 2 ... 10), the pixel electrode 9 and the non-electrode electrode 5 are connected to each other. A protective film 8 with a predetermined area of the hole 80 is used. 〇It may be simple to use in the thin film transistor method. Splattering and no 5 before the pre-stage. Similarly, the electrical destruction of the ion implantation + implantation + conductor film 6 ° so no need to use expensive processing equipment such as post-thunder, = 'to form these films. In addition, the formation of source and imperfect electrode The processing cavity of the breakable μ / kcvd device not only forms a semiconductor film, but also processes to form an ohmic contact. Therefore, the conventional cavity described above is not required
制、土二！達成f'早且連續之處理環境。因此，對於TFT 衣k負何M J造成本降低有所貢獻。 此：-因為此實施例改善底閘型丁打，並且其製造方法 對二/域較低側給予問極2額外之遮光獏功能，它也 獻。、 透式液晶顯示裝置價格與其性能改善有所貢 動Ϊ:以St薄膜電晶體之說明已延伸至形成-像素驅 列二°夕涛胰電晶體每一者包含獨立通道區域，以陣 方式形成’㈣應至液晶顯示裝置每-像素。 :見在’參考圖"，將說明本發明第二實施例：圖“中與 圖1裡相同組件以相同參考數字表示。 /透=相異之處為’其不需形成第-實施例中相對應 ;=膜9的層次’因為没極5,本身可當成-像素電 ^广Τ Α極電極5,只包含-透明傳導膜，透過 β先而面向液晶側。其他特點基本上與第—實施例相同， 本紙張尺度·巾® s家標準(CNS) 536828 A7 ^_ B7 五、發明説明（彳2 ) 使侍此貫施例具有與第一實施例相同的優點。第二實施例 可更進一步因為無透明傳導膜9，而有助於減少圖形定義處 理次數至四次。 真更進一步地說，根據本發明之薄膜電晶體結構除了上述 k點之外，另具有獨特與明顯的優點，並且如下說明。 ^圖12展列流經第一與第二實施例中通道區域電流狀態。 田所考慮之薄膜電晶體處於“開啟，，狀態時，電流“ i”自源極 電極4流至沒極電極5，自於閘極電位冑成通道區域，問極 側表面阻值最後在半導體膜6通道區域變得最低。這種情形 =下，如圖12所示源極與汲極電極4 , 5與半導體膜6底部兩 =之半導體膜6底部直接接觸，並且接觸部分為歐姆接觸。 結果，當半導體膜6處於“開啟，，狀態時，電流路徑（通道）在 源極電極4與汲極電極5之間，以直線最短距離形成。 相對比於此，薄膜電晶體傳統結構如圖1 3所列，半導體 膜26形成通道區域，在閘極22上方的閘極絕緣膜23之上延 展，並且源極電極24與汲極電極25相對應於閘極22，而在 半導體膜26上形成。 此傳統結構中，電流“丨”自源極電極24流至汲極電極乃， 可以形成後續掃出（通道）。其自源極電極24導向半導體膜 26閘極側表面（圖中朝下方向），通過半導體膜％内側，然 後沿著半導體膜26底部朝向汲極電極側’再一次通過半導 體膜26内側，最後往上朝向汲極電極25 (圖中朝上方向）。 根據圖13展列之電流路徑，源極電極24與汲極電極”每 一側之半導體膜26厚度引起串聯電阻R。因此源極與汲極之 -— 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 536828 A7System, soil two! Achieve f 'early and continuous processing environment. Therefore, it contributes to the reduction in the cost of the TFT clothing. This: -Because this embodiment improves the bottom gate type ding, and its manufacturing method gives the pole 2 an extra light-shielding function on the lower side, it also contributes. The price of transmissive liquid crystal display devices and their performance improvements have contributed: The description of the St thin film transistor has been extended to the formation-pixel drive two ° Xitao pancreatic transistor each includes an independent channel area, formed in a matrix manner 'Each pixel per LCD. : See 'Reference drawing ", the second embodiment of the present invention will be explained: the same components in FIG. 1 as those in FIG. 1 are indicated by the same reference numerals. Corresponds to the level of = 9; because it has no pole 5, it can be regarded as a -pixel electrode 广 A pole electrode 5, which only contains-a transparent conductive film, which first faces the liquid crystal side through β. Other features are basically the same as the first —The embodiment is the same, this paper size · skins standard (CNS) 536828 A7 ^ _ B7 V. Description of the invention (彳 2) This embodiment has the same advantages as the first embodiment. The second embodiment It can further help to reduce the number of times of pattern definition processing to four times because there is no transparent conductive film 9. In fact, in addition to the above-mentioned k-point, the thin-film transistor structure according to the present invention has unique and obvious characteristics. The advantages are as follows. ^ Figure 12 shows the state of the current flowing through the channel region in the first and second embodiments. The thin film transistor considered by Tian is in the "on," state, and the current "i" flows from the source electrode 4 To the electrode 5, it is turned on from the gate potential. In the track region, the interfacial surface resistance value finally becomes the lowest in the 6-channel region of the semiconductor film. In this case, as shown in FIG. 12, the source and drain electrodes 4, 5 and the bottom of the semiconductor film 6 are directly in contact with each other, and the contact portion is an ohmic contact. As a result, when the semiconductor film 6 is in the "on," state, a current path (channel) is formed between the source electrode 4 and the drain electrode 5 with a shortest straight line. In contrast, the conventional structure of a thin film transistor is shown in Fig. As listed in FIG. 13, the semiconductor film 26 forms a channel region, and extends over the gate insulating film 23 above the gate electrode 22, and the source electrode 24 and the drain electrode 25 correspond to the gate electrode 22, and on the semiconductor film 26 In this traditional structure, the current “丨” flows from the source electrode 24 to the drain electrode, which can form a subsequent sweep-out (channel). It leads from the source electrode 24 to the gate-side surface of the semiconductor film 26 (toward the figure). (Downward direction), passing through the inside of the semiconductor film%, and then along the bottom of the semiconductor film 26 toward the drain electrode side again passes through the inside of the semiconductor film 26, and finally upwards toward the drain electrode 25 (upward direction in the figure). According to FIG. 13 In the current path shown, the thickness of the semiconductor film 26 on each side of the source electrode 24 and the drain electrode causes a series resistance R. Therefore, the source and drain--This paper size applies to China National Standard (CNS) A4 (210X297 mm) 536828 A7
此高阻值R狀 間阻值與薄膜電晶體“開啟，，電阻會變得較高 況然盈於功率消耗減少及/或高溫測量。 電極5之電流並不以厚度方，， 、兒° 到汲極 个乂与庋方向，叫疋線性地沿著 問靖面流入半導體膜6内部。因此，源極與汲極之間電 阻與溥版電晶體“開啟，，電阻可以變低。結果，本發明對： 改善驅動像素電極效率，降低薄膜電晶體功率消耗"制 發熱有所貢獻。 雖然穿透式液晶顯示裝置已經參考以上說明，本發明並 不限於此型式。本發明基本上也可應用到反射型式^晶顯 示裝置，。在此情形之下，基板(可不需為透明的，像素電極 9及/或汲極電極5'除了電極以外，可使用由某些光學反射材 料甚至於是一些貢獻反射層形成。 此外，雖然以上說明參考一種結構，其基板具有TFh位 於顯示面板後側，基板可以放置在顯示面板前侧。 此處展列較佳實施例，並且無所限制，發明之領域由所 附申請專利範圍事項所指明。並且所有來自申請專利範圍 事項變化，將包含在其中。 -16- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）This high-resistance R-shaped inter-resistance value and the thin-film transistor "turn on, and the resistance will become higher. However, it may be due to reduced power consumption and / or high temperature measurement. The current of electrode 5 is not in terms of thickness. The directions of the poles 庋 and 庋 are called linearly flowing into the semiconductor film 6 along the interfacial plane. Therefore, the resistance between the source and the drain and the 溥 -type transistor are turned on, and the resistance can be lowered. As a result, the present invention contributes to: improving the efficiency of driving the pixel electrode and reducing the power consumption of the thin film transistor " heat generation. Although the transmissive liquid crystal display device has been referred to the above description, the present invention is not limited to this type. The present invention can also be basically applied to a reflective crystal display device. In this case, the substrate (which does not need to be transparent, the pixel electrode 9 and / or the drain electrode 5 ′ can be formed using some optical reflective materials or even some contributing reflective layers in addition to the electrodes. In addition, although the above description Referring to a structure, the substrate has TFh on the rear side of the display panel, and the substrate can be placed on the front side of the display panel. The preferred embodiments are shown here without limitation, and the field of invention is specified by the scope of the attached patent application. And all changes from the scope of the patent application will be included. -16- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000190765A JP2002026326A (en) | 2000-06-26 | 2000-06-26 | Bottom gate type thin film transistor, its manufacturing method, and liquid crystal display device using it |
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| TW536828B true TW536828B (en) | 2003-06-11 |
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| TW090118205A TW536828B (en) | 2000-06-26 | 2001-07-25 | Bottom gate type thin film transistor, its manufacturing method and liquid crystal display device using the same |
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| EP (1) | EP1297568A2 (en) |
| JP (1) | JP2002026326A (en) |
| KR (1) | KR20020062276A (en) |
| CN (1) | CN1401135A (en) |
| TW (1) | TW536828B (en) |
| WO (1) | WO2002001603A2 (en) |
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| GB0210065D0 (en) * | 2002-05-02 | 2002-06-12 | Koninkl Philips Electronics Nv | Electronic devices comprising bottom gate tft's and their manufacture |
| JP4403354B2 (en) * | 2002-09-11 | 2010-01-27 | ソニー株式会社 | Thin film circuit board |
| DE602004005685T2 (en) * | 2003-03-07 | 2007-12-27 | Koninklijke Philips Electronics N.V. | METHOD FOR PRODUCING AN ELECTRONIC ARRANGEMENT |
| KR100977229B1 (en) * | 2003-12-30 | 2010-08-23 | 엘지디스플레이 주식회사 | Organic Thin Film Transistor And Method For Fabricating The Same, And Liguid Crystal Display Device By The Same |
| CN101278403B (en) | 2005-10-14 | 2010-12-01 | 株式会社半导体能源研究所 | Semiconductor device and manufacture method thereof |
| JP2007248956A (en) * | 2006-03-17 | 2007-09-27 | Epson Imaging Devices Corp | Electro-optical device and electronic equipment |
| CN100449716C (en) * | 2006-03-20 | 2009-01-07 | 友达光电股份有限公司 | Thin film transistor and manufacturing method thereof |
| KR101265331B1 (en) * | 2006-06-28 | 2013-05-23 | 엘지디스플레이 주식회사 | Thin film transistor and method for fabricating thereof and method for fabricating liquid crystal display device having thereof |
| KR100965260B1 (en) * | 2008-01-25 | 2010-06-22 | 삼성모바일디스플레이주식회사 | Thin film transistor, fabricating method for the same, and organic light emitting diode display device comprising the same |
| KR101545460B1 (en) * | 2008-09-12 | 2015-08-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and manufacturing method thereof |
| US20100253902A1 (en) * | 2009-04-07 | 2010-10-07 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and manufacturing method thereof |
| JP2011071476A (en) | 2009-08-25 | 2011-04-07 | Canon Inc | Thin film transistor, display device using the same, and method of manufacturing thin film transistor |
| TWI471946B (en) * | 2010-11-17 | 2015-02-01 | Innolux Corp | Thin film transistors |
| CN102176413A (en) * | 2011-03-25 | 2011-09-07 | 信利半导体有限公司 | Thin-film transistor forming method and thin-film transistor |
| JP5447996B2 (en) * | 2011-10-14 | 2014-03-19 | ソニー株式会社 | THIN FILM TRANSISTOR, METHOD FOR PRODUCING THIN FILM TRANSISTOR, AND ELECTRONIC DEVICE |
| KR101427477B1 (en) * | 2012-10-11 | 2014-08-08 | 하이디스 테크놀로지 주식회사 | Liquid crystal display device |
| KR102300402B1 (en) | 2015-01-09 | 2021-09-09 | 삼성디스플레이 주식회사 | Organic light emitting diode display |
| CN108695394A (en) * | 2017-04-06 | 2018-10-23 | 京东方科技集团股份有限公司 | Thin film transistor (TFT), preparation method, array substrate and display device |
| US11908911B2 (en) * | 2019-05-16 | 2024-02-20 | Intel Corporation | Thin film transistors with raised source and drain contacts and process for forming such |
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| KR100193348B1 (en) * | 1996-02-12 | 1999-07-01 | 구자홍 | Fabrication method of thin film transistor for lcd |
| JP2757850B2 (en) * | 1996-04-18 | 1998-05-25 | 日本電気株式会社 | Thin film transistor and method of manufacturing the same |
| GB9919913D0 (en) * | 1999-08-24 | 1999-10-27 | Koninkl Philips Electronics Nv | Thin-film transistors and method for producing the same |
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- 2001-06-25 WO PCT/EP2001/007189 patent/WO2002001603A2/en not_active Application Discontinuation
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| KR20020062276A (en) | 2002-07-25 |
| WO2002001603A3 (en) | 2002-08-08 |
| CN1401135A (en) | 2003-03-05 |
| EP1297568A2 (en) | 2003-04-02 |
| JP2002026326A (en) | 2002-01-25 |
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