TW529088B - Manufacturing method of stacked gate flash memory device - Google Patents

Abstract

A manufacturing method of stacked gate flash memory device comprises the following steps: providing a substrate; forming many stacked gates on the substrate, each stacked gate consisting of a first insulated layer, a first gate layer on the first insulated layer, a second insulated layer on the first gate layer, a second gate layer on the second insulated layer and a third insulated layer on the second gate layer; making many source/drain doped areas on the substrate among the stacked gates; forming spacers on the sidewalls of the stacked gates and filling a first conductive layer in the stacked gates spacing; making a forth insulated layer on the first conductive layer for being connected to the source doped area; depositing a second conductive layer that is connected to the first conductive layer above the drain doped area and is isolated from the first conductive layer above the source doped area by the forth insulated layer.

Description

529088529088

記恃ΐ t月係有關於一種堆疊閘極（stacking gate)快閃 跖Γ:田之製造方法，特別有關於一種可縮短堆疊閘極間 距之堆登間極快閃記憶裝置之製造方法。 中所〜8C圖/員示了中華民國第9012〇49〇號專利申請案 m &〔路之堆豐閘極快閃記憶裝置之製造方法。其中，Μ 回’、、，=圖，而XB、xc圖係XA圖中沿XX,及γγ，之剖面圖。 石々其=9n如第1A、1B&1C圖所示，提供一矽基底20，在 上依序儿積一氧化層21、氮化層22、氧化層23、Note: The month t is related to a manufacturing method of stacking gate flash (跖 Γ: Tian), and more particularly to a method of manufacturing a stack memory flash memory device that can shorten the stack gate distance. Figure 8C of the Institute shows the method for manufacturing a flash memory device of Lu Zhidui Fengzha Gate Patent Application m & Among them, M times', ,, and = diagrams, and XB and xc diagrams are cross-sectional views along XX, and γγ in the XA diagram. Shi Qiqi = 9n As shown in Figures 1A, 1B & 1C, a silicon substrate 20 is provided, on which an oxide layer 21, a nitride layer 22, an oxide layer 23,

麻9(1 :，並蝕刻該些沉積層及矽基底20而形成深及矽基 ：中、做為淺溝隔離（STI)用之凹槽261。沿凹槽261之 二二及:1壁生成一襯氧化層⑴ning oxide)25，並在以凹 槽261中填滿絕緣用之氧化層26。 接著，如第2A、2B、2C圖所示，利用蝕刻步驟移除氮 化層24及氧化層23,由於在進行氧化層23之餘刻時多= 層26亦會被蝕刻，因此部份氧化層26之侧壁同時被移除。 如此，使彳于氧化層26在YY，方向之剖面上形成一梯狀 側壁。 然後，如第3A、3B、3C圖所示，再利用蝕刻步驟將氮 化層22、氧化層21移除，形成曝露主動區（active 矽基底20表面之凹槽262，而完成一具有梯狀侧壁氧化芦 之淺溝隔離結構。 a 再來，如第4A、4B、4C圖所示，在被曝露之矽基底2〇 表面生成二閘極氧化層27。再沉積一多晶矽層28。由於氧 化層2 6之梯狀側壁，使得多晶矽層2 8在凹槽2 6 2上方形成He 9 (1 :, and etch the deposition layers and silicon substrate 20 to form deep and silicon-based: middle and deep grooves 261 for shallow trench isolation (STI). Along the grooves 261 bis and: 1 wall A lining oxide layer 25 is formed, and an oxide layer 26 for insulation is filled in the groove 261. Next, as shown in Figs. 2A, 2B, and 2C, the nitride layer 24 and the oxide layer 23 are removed by an etching step. Since the oxide layer 23 is etched in the rest of the time, the layer 26 is also etched, so part of the oxide The sidewalls of layer 26 are removed at the same time. Thus, a stepped sidewall is formed on the cross section of the oxide layer 26 in the YY direction. Then, as shown in FIGS. 3A, 3B, and 3C, the etching step is used to remove the nitride layer 22 and the oxide layer 21 to form an exposed active region (the groove 262 on the surface of the active silicon substrate 20), thereby completing a ladder-like structure. A shallow trench isolation structure with oxidized reeds on the sidewalls. A Then, as shown in Figures 4A, 4B, and 4C, a two-gate oxide layer 27 is formed on the surface of the exposed silicon substrate 20. A polycrystalline silicon layer 28 is then deposited. The ladder-shaped sidewall of the oxide layer 26 causes the polycrystalline silicon layer 2 8 to be formed above the groove 2 6 2

^29088 « 五 、發明說明（2) ---------- 「V」字型之凹陷。 接著，如第5A、5B、R % 一 殘留部份於凹槽262中，也I圖所不，回蝕多晶矽層28，僅 層28在凹槽262上方有「文為汙接閘極之用。由於多晶矽 ^ 有v」型凹陷，使得回蝕之結果，將 然後，如第6Α、Β、出二成/端部281。 ，再將部份側壁移除而使多，；二對氧化層26進行姓刻 在多晶石夕層28表面生成= 之尖端部281露出。 3〇，以做為控制閉極Ϊ用開；層29 ’沉積-多晶，石夕層 部282，因此在栌制門搞夕士由夕晶矽層28中間具有凹陷 聶之嗓垃4^ 3極之相對處會形成突出部3 0 1。對堆 :凹孔302及二閘極進行蝕刻’而形成曝露矽基底20表面 之凹孔3G2及303，以將每—條堆疊閘極切判。 、、聋261再/ ’Λ第7A、7B、7C圖所示，對氧化層26及隔離淺 形成-么襯:J化層25進行蝕刻，使同一行之凹孔302連通 /成條曝路矽基底20表面之凹槽302，。利用離子 :’在凹槽302’、凹孔303底部之矽基底2〇中分別 條共同源極摻雜區201、及多個汲極摻 =;隱再經過一回火(一n步驟，使其捧雜中離： 向外擴散至浮接閘極2 8之下方。 最後，如第8A、8B、8C圖所示，沉積一介電 層）31，並在介電層31中形成介層孔311。沉積並 為導線及插塞用之金屬層32，使同一列記、 義—做 區電性連接。 歹“己隐胞之汲極摻雜^ 29088 «V. Description of the Invention (2) ---------- Depression of" V "shape. Next, as shown in Figures 5A, 5B, and R%, the remaining part is in the groove 262, which is not shown in the figure. The polycrystalline silicon layer 28 is etched back, and only the layer 28 has a "text contamination gate" function above the groove 262. Because the polycrystalline silicon has a v ″ -shaped depression, the result of the etch-back will then be as follows: 6A, B, and 20% / end 281. Then, remove part of the side wall to make more; Second, the oxide layer 26 is engraved on the surface of the polycrystalline stone layer 28, and the tip portion 281 is exposed. 30. It is used to control the closed-electrode opening; layer 29 'deposit-polycrystalline, Shixi layer section 282, so there is a depression Nie's voice in the middle of the gate of Xiyuyou***g of the hidden cell

529088 五、發明說明（3) 然而，在上述之堆疊閘極快閃記憶裝置之製造方法中 ’由於使用金屬插塞擷取源、汲極之信號，使得兩個堆聂 閘極間之間距因受介層孔之影響而很難縮短；同時，汲二 =電壓亦必需從基底中之汲極區直接耦合至浮接閘極， 付汲極區之兩側必需擴展至浮接閘極下方。 憶裝= Ϊ問題，ί發明提供—種堆疊閉極快閃記 I 、W方法，使用多晶矽層做為插塞，可縮短堆聂 I "之間距，且汲極摻雜區不需向外擴展至浮接閘極下方 之製的在於提供一種堆疊閉極快閃記憶裝置 門：括：下步驟。提供-基底。在該基底上形 該第-絕緣層上之一第一間極層丄η『二位於 -第二絕緣層、位於該第二絕緣層上之」；：：上之 位於該第二閘極層上之第三第一閘極層以及 瓜成在《底中之複數源極及汲極 ：㈣，間 極側壁形成一間隙壁。在今此 i堆豐閘 層。在與該源極摻雜區間；間填滿-第-導電 絕緣層。沉積-第二以之導電層上形成-第四 區上方之第一導電層連^二=，電層與該没極摻雜 摻雜區上方之第一導電層絕=猎4第四絕緣層與該源極 本發明之另一目的在於提 置之製造方法’包括以下步驟。提；極，閃記憶裝 依序沉積-第-及第二沉積層。在；第基底第在該基底上 乐一第一沉積層及529088 V. Description of the invention (3) However, in the above-mentioned manufacturing method of the stacked gate flash memory device, 'the reason for the distance between the two stacked gates is that the metal plug is used to capture the signal of the source and the drain. It is difficult to shorten due to the influence of the hole of the dielectric layer. At the same time, the drain voltage must be directly coupled from the drain region in the substrate to the floating gate, and both sides of the auxiliary drain region must be extended below the floating gate. Remembrance = Ϊ problem, ί invention provides-a method of stacked closed-pole flash memory I, W method, using polycrystalline silicon layer as a plug, can shorten the distance between the reactor I ", and do not need to expand the doped region The system to the floating gate is to provide a stacked closed-pole flash memory device door: including: the next step. Provide-substrate. One of the first interlayers on the first insulating layer is formed on the substrate, “two are located on the second insulating layer, and are located on the second insulating layer”; The third first gate layer above and a plurality of source and drain electrodes formed in the bottom: ㈣, the side wall of the intermediate electrode forms a gap wall. Today I pile the Fengzha layer. The doping interval with the source is filled with a -first-conductive insulating layer. Deposition-the second conductive layer is formed-the first conductive layer above the fourth region is continuously connected, the electrical layer and the first conductive layer above the non-doped doped region must be equal to the fourth insulating layer With the source, another object of the present invention is to provide a manufacturing method 'including the following steps. Raised; polar, flash memory equipment sequentially deposited-first-and second deposited layers. The first base layer on the base, a first deposited layer and

0503-6914TWF ； TSMC2001-0760 ； Vincnet.ptd 第6頁 529088 五、發明說明（4) :基底中形成一深及該基底中之 第一凹槽之第一絕緣層。移除嗜二槽。形成一填滿該 絕緣層側，。蝕刻該第一沉積乂及積層而露出該第一 第一絕緣層形成-梯狀側壁，並移m絕緣層，而在該 一曝露該基底之第二凹槽。在該曝露—沉積層而形成 二絕緣層。沉積一第—閘極層並回蝕而二底表面形成一第 於該第二凹槽中且在該第一閘極層中門第一閘極層位 凹陷部及尖端部。蝕刻該第一絕緣層側邊分別形成一 尖端部露*。在該第-閘極層表面；成一閘極層： 積一第二閘極層填滿該第二凹槽。兮二絕緣層。沉 :第四絕緣層。依序蝕刻該第二絕緣層;閘1層ί沉積 第二絕緣層、肖第一閘極層及該第二絕-閘j : ·、该 =之複數第三㈣。在被該些第三凹槽 第三凹槽之兩側側壁形成至土：列記憶胞。在該 -第-導電層。*成㈣壁。在該第三凹槽中填滿 藉此，本發明在控制閑極與浮接閘極 知部與凹陷部，有利於熱電子由浮接閘極穿之尖 (抹±除時)或由控制閘極穿隧到浮接閘極(寫入時)：=極 同枯，將汲極摻雜區擴大至浮接閘極下、2:運動， 合至浮接閘極，幫助控制閑極產生吸引熱電子運：：：； 區電位之不同，可以-次僅抹除-個記憶胞精由及極摻雜 以下，就圖式說明本發明之一種堆疊間極快閃記憶裝0503-6914TWF; TSMC2001-0760; Vincnet.ptd page 6 529088 5. Description of the invention (4): A first insulating layer deep in the substrate and a first groove in the substrate is formed. Remove the second tank. A side is formed to fill the insulating layer. The first deposition layer and the buildup layer are etched to expose the first first insulation layer-ladder-shaped sidewall, and the m insulation layer is moved, and the second groove of the substrate is exposed in the first. On this exposure-deposition layer, two insulating layers are formed. A first-gate layer is deposited and etched back, and two bottom surfaces form a first recessed portion and a tip portion of the first gate layer in the second groove and in the first gate layer. Each of the sides of the first insulating layer is etched to form a tip portion exposed *. On the surface of the first gate layer; forming a gate layer: A second gate layer is accumulated to fill the second groove. Xi two insulation layers. Shen: The fourth insulation layer. The second insulating layer is sequentially etched; the gate 1 layer is deposited, the second insulating layer, the first gate electrode layer, and the second gate-gate j: ·, the third plural number of =. The third grooves are formed on the two side walls of the third groove to the soil: column memory cells. In the -s- conductive layer. * Into the wall. The third groove is filled with this, so that the invention controls the idler and floating gate knowing part and recessed part, which is beneficial for the hot electrons to pass through the tip of the floating gate (when erasing ±) or by controlling Gate tunneling to floating gate (when writing): = poles are dry, expand the doped region of the drain to below the floating gate, 2: move, close to the floating gate to help control the generation of idler Attraction of hot electron transport ::: The difference in the region potential can be-erased only once-a memory cell essence and extremely doped. The following is a schematic illustration of a stack flash memory device according to the present invention.

529088 五、發明說明（5) 置製造方法之實施例。 圖式簡單說明 第1 A〜8C圖顯示了 一傳統堆疊閘極快閃記憶裝置之結 構； 第9A〜1 5C圖顯示了本發明一實施例中堆疊閘極快閃記 憶裝置之製造方法。 [符號說明] 20、40〜石夕基底； 2 0 1、4 0 1〜汲極摻雜區； 2 0 2、4 0 2〜源極摻雜區； 21 、23 、25 、26 、27 、29 、31 、41 、43 、45 、46 、47 、49 、51 、55〜氧4匕層； 28、48〜浮接閘極； 3 0、5 0〜控制閘極； 3 2〜金屬層； 22、24、42、44、52〜氮化層; 261 > 262 、 461 、 462〜凹槽；529088 V. Description of the invention (5) An embodiment of the manufacturing method. Brief Description of the Drawings Figs. 1A to 8C show the structure of a conventional stacked gate flash memory device; Figs. 9A to 15C show a method for manufacturing the stacked gate flash memory device according to an embodiment of the present invention. [Explanation of symbols] 20, 40 ~ Shi Xi substrate; 2 0 1, 4 0 1 ~ Drain doped region; 2 0 2, 4 0 2 ~ Source doped region; 21, 23, 25, 26, 27, 29, 31, 41, 43, 45, 46, 47, 49, 51, 55 ~ 4 layers of oxygen; 28, 48 ~ floating gates; 30, 50 ~ control gates; 3 ~ 2 metal layers; 22, 24, 42, 44, 52 ~ nitride layers; 261 > 262, 461, 462 ~ grooves;

302 、303 、502 、 503〜凹子L 281、 481〜浮接閘極尖端部 Φ 282、 481〜浮接閘極凹陷部 3 0 1、5 0 1〜控制閘極突出部； 3 11〜介層孔； 5 3〜間隙壁； 5 4、5 6〜多晶石夕層。302, 303, 502, 503 to female L 281, 481 to floating gate tip Φ 282, 481 to floating gate recess 3 0 1, 5 0 1 to control gate protrusion; 3 11 to Layer holes; 5 3 ~ spacer wall; 5 4,5 6 ~ polycrystalline stone layer.

0503-6914TWF ； TSMC2001-0760 ： Vincnet.ptd 第8頁 529088 五、發明說明（6) " 實施例 第9 A〜1 5C圖顯示了本發明一實施例中堆疊閘極快閃記 隐裝置之製造方法。其中，X A圖係上視圖，而X b、X ◦圖係 XA圖中沿XX’及γγ，之剖面圖。 首先，如第9A、9B及9C圖所示，提供一矽基底4〇，在 石夕基底40上依序沉積一氧化層41、氮化層42、氧化層43、 氮化層44，並蝕刻該些沉積層及矽基底4〇而形成深及石夕基 底40中、做為淺溝隔離（STI)用之凹槽461。沿凹槽461之 底部及側壁生成一襯氧化層（lining 〇xide)45，並在以凹 槽461中填滿絕緣用之氧化層46。 斤接著，如第10A、10B、10C圖所示，利用蝕刻步驟移 ，氮化層44及氧化層43，由於在進行氧化層43之蝕刻時， 氧化層46亦會被蝕刻，因此部份氧化層46之側壁同時被移 除。如此，使得氧化層46在YY，方向之剖面上形成一梯狀 側壁。 片然後，如第11A、11B、11C圖所示，再利用蝕刻步驟 將虱化層42、氧化層41移除，形成曝露主動區（active area)矽基底40表面之凹槽462，而完成一具有梯狀側壁氧 化層之淺溝隔離結構。 再來，如第12A、12B、12C圖所示，在被曝露之矽基 底巧表面生成一閘極氧化層47。再沉積一多晶矽層48。由 於氧化層46之梯狀側壁，使得多晶矽層48在凹槽462上方 形成「V」字型之凹陷。 接著，如第13A、13B、13C圖所示，回蝕多晶矽層480503-6914TWF; TSMC2001-0760: Vincnet.ptd Page 8 529088 V. Description of the Invention (6) " Embodiment 9A ~ 1 5C shows the manufacturing of a stacked gate flash memory device in an embodiment of the present invention method. Among them, X A diagram is a top view, and X b and X ◦ diagrams are cross-sectional views along XX ′ and γγ, in XA diagram. First, as shown in FIGS. 9A, 9B, and 9C, a silicon substrate 40 is provided, and an oxide layer 41, a nitride layer 42, an oxide layer 43, and a nitride layer 44 are sequentially deposited on the stone evening substrate 40, and then etched. The deposited layers and the silicon substrate 40 form deep grooves 461 in the deep and stone substrate 40 as shallow trench isolation (STI). A lining oxide layer 45 is formed along the bottom and side walls of the groove 461, and the insulating oxide layer 46 is filled in the groove 461. Next, as shown in FIGS. 10A, 10B, and 10C, the etching step is used to move the nitride layer 44 and the oxide layer 43. When the oxide layer 43 is etched, the oxide layer 46 is also etched, so part of the oxide is oxidized. The sidewalls of layer 46 are removed at the same time. In this way, the oxide layer 46 is formed with a stepped sidewall on a cross section in the YY direction. Then, as shown in FIGS. 11A, 11B, and 11C, the etched layer 42 and the oxide layer 41 are removed by an etching step to form a recess 462 that exposes the surface of the active area silicon substrate 40 to complete a Shallow trench isolation structure with ladder-like sidewall oxide layer. Further, as shown in Figs. 12A, 12B, and 12C, a gate oxide layer 47 is formed on the surface of the exposed silicon substrate. A polycrystalline silicon layer 48 is deposited. Due to the stepped sidewalls of the oxide layer 46, the polycrystalline silicon layer 48 forms a "V" shaped depression over the groove 462. Next, as shown in FIGS. 13A, 13B, and 13C, the polycrystalline silicon layer 48 is etched back

529088529088

0503-6914TW ； TSMC2001-0760 ； Vincnet.ptd 第10頁 ^^9088 L、發明說明（8) — 間極，因此，汲極摻命 此，i n 雜&便不而擴展至浮接閘極下方。因 卜例可以在堆疊問極間具 之寬 ： °己憶胞之面積縮小。 Λ使 以ΡΡ雖然本發明已以一較佳實施例揭露如纟，然其並非用 神/ Ϊ t發明，任何熟習此技藝者，在不脫離本發明之精 甲和乾圍内，當可作此畔之#翻ώ 護笳m A、a β』1卞二卉之更動與潤飾，因此本發明之保 曼軏圍當視後附之申請專利範圍所界定者為準。0503-6914TW; TSMC2001-0760; Vincnet.ptd Page 10 ^^ 9088 L. Description of the invention (8)-Intermediate pole, therefore, the drain is dominated by this, and the in impurity & will not extend below the floating gate. . For example, the width between stacking poles can be as follows: ° The area of Jiyi cell has been reduced. Although the present invention has been disclosed in a preferred embodiment, such as 纟, but it is not invented by God / Ϊ t, any person skilled in this art can be used without departing from the fine armor and stem of the present invention. The changes and retouchings of this #turning # 翻 保 笳 m A, a β 』1 卞 II Hui, therefore, the Baomanwei of the present invention shall be subject to the definition of the scope of the attached patent.

0503-6914TW ； TSMC2001-0760 ； Vincnet .ptd $ 11頁0503-6914TW; TSMC2001-0760; Vincnet.ptd $ 11 pages

Claims (1)

529088 六、申請專利範圍 步驟丨··· 一種堆疊閘極快閃記憶裝置之製造方法， 提供一基底； 在該基底上形成複數堆疊閘極，每一堆疊 今；絕ίί声T於該第一絕緣層上之一第-閘極 ^ 弟一、、、巴緣層、位於該第二絕 一弟二閘極層以及位於_ m 弟一閘極層上之第三絕 極換些堆疊閘極之間形成在該基底中之複數 在該些堆疊閘極側壁形成一間隙壁； 在該些堆疊閘極間填滿一第一導電層； 绍络ί與該源極摻雜區連接之該第-“層上形 絕緣層；以及 >儿積一第二導電層，該第二導電層與該汲極 方之第-導電層連接，纟藉由該第四絕緣層與該 區上方之第一導電層絕緣。 2· —種堆疊閘極快閃記憶裝置之製造方法， 步驟： 包括以下 極包括一 層、位於 緣層上之 緣層； 源極及沒 成一第 四 摻雜區上 源極摻雜 包括以下 提供一基底； 在该基底上依序沉積一第/及第二沉積層； 在該第二、第一沉積層及該基底中形成一深及該基底 中之第一凹槽； 形成一填滿該第一凹槽之第一絕緣層； 移除該第二沉積層而露出該第一絕緣層側壁；529088 VI. Steps for applying patent scope 丨 ·· A method of manufacturing a stacked gate flash memory device, providing a substrate; forming a plurality of stacked gates on the substrate, each stacked today; absolutely no sound T at the first One of the first gates on the insulation layer, the first, second and third gates, the third and second gates on the second and third gates, and the stacked gates A plurality of gaps formed in the substrate form a gap wall on the side walls of the stacked gates; a first conductive layer is filled between the stacked gates; the first connection layer connected to the source doped region -"Layer-shaped insulating layer; and > a second conductive layer is connected to the first conductive layer of the drain side, and the fourth insulating layer is connected to the first conductive layer above the region A conductive layer is insulated. 2. A method for manufacturing a stacked gate flash memory device, including the following steps: including the following electrodes including a layer on the edge layer; a source electrode and a source electrode on a fourth doped region; The inclusions include the following: providing a substrate; sequentially depositing a substrate on the substrate / And a second deposited layer; forming a deep and first groove in the substrate in the second and first deposited layers and the substrate; forming a first insulating layer filling the first groove; removing The second deposited layer exposes the sidewall of the first insulating layer; 529088 六、申請專利範圍 I虫刻該 第一沉積層及該第一絕緣層，而在該第一絕緣 層形成一梯狀側壁，並移除該第一沉積層而形成一曝露該 凹槽； 露之基底表面形成一第二絕緣層； 第一閘極層並回餘而使該第一閘極層位於該第 在該第一閘極層中間及側邊分別形成一凹陷部 基底之第二 在該曝 沉積一 二凹槽中且 及尖端部； 蝕刻該 在該第 沉積一 在該第 依序兹 該第一閘 第 -凹槽； 在被該 摻雜區，而 在該第 在該第 3. 如申 置之製造方 蝕刻該 在該些 雜區。 4. 如申 第一絕緣層而使該第一閘極層之尖端部露出； 一閘極層表面形成一第三絕緣層； 第二閘極層填滿該第二凹槽； _ 二閘極層上沉積一第四絕緣層； 刻該第四絕緣層、第二閘極層、該第三絕緣層 極層及該第二絕緣層，形成曝露該基底之複數 些第三凹槽曝露之該基底中形成一汲極及源極 形成至少一列記憶胞； 三凹槽之兩側側壁形成一間隙壁；以及 三凹槽中填滿一第一導電層。 請專利範圍第2項所述之堆疊閘極快閃記憶裝 法，其中更包括以下步驟： · 第一絕緣層，使該些第三凹槽連通；以及 連通之第三凹槽曝露之該基底中形成該源極摻 請專利範圍第3項所述之堆疊閘極快閃記憶裝529088 6. The scope of the patent application I worms the first deposition layer and the first insulation layer, and forms a ladder-shaped side wall on the first insulation layer, and removes the first deposition layer to form an exposed groove; A second insulating layer is formed on the exposed surface of the substrate; the first gate layer is left over so that the first gate layer is located on the second and second sides of the first gate layer respectively forming a recessed base substrate Depositing one or two grooves and the tip portion in the exposure; etching the first-deposited groove in the first-deposited sequence in the first-deposited area; in the doped area, and in the first-deposited area 3. The etched area should be etched by the manufacturer. 4. If the first insulating layer is applied, the tip of the first gate layer is exposed; a third insulating layer is formed on the surface of a gate layer; the second gate layer fills the second groove; _ two gates A fourth insulating layer is deposited on the layer; the fourth insulating layer, the second gate layer, the third insulating layer, and the second insulating layer are etched to form a plurality of third grooves exposed to expose the substrate. A drain and a source are formed in the substrate to form at least one row of memory cells; a sidewall is formed on both side walls of the three grooves; and a first conductive layer is filled in the three grooves. The stacked gate flash memory mounting method described in item 2 of the patent, further includes the following steps: a first insulating layer to communicate the third grooves; and the substrate exposed by the connected third grooves In the formation of the source, the stacked gate flash memory device described in item 3 of the patent scope is incorporated. 0503-6914TWF ； TSMC2001-0760 ； Vincnet.ptd 第13頁 529088 六、申請專利範圍 置之製造方法，其中更包括以下步驟： 在與該源極摻雜區連接之該第一導電層上形成一第五 絕緣層；以及 沉積一第二導電層，該第二導電層與該汲極摻雜區上 方之第一導電層連接，並藉由該第五絕緣層與該源極摻雜 區上方之第一導電層絕緣。 5. 如申請專利範圍第2項所述之堆疊閘極快閃記憶裝 置之製造方法，其中該導電層係多晶矽層。 6. 如申請專利範圍第2項所述之堆疊閘極快閃記憶裝 置之製造方法，其中該基底係一矽基底。 7. 如申請專利範圍第2項所述之堆疊閘極快閃記憶裝 置之製造方法，其中該第一及第二閘極層係多晶矽層。 8. 如申請專利範圍第2項所述之堆疊閘極快閃記憶裝 置之製造方法，其中該第一沉積層係氧化層。 9. 如申請專利範圍第2項所述之堆疊閘極快閃記憶裝 置之製造方法，其中該第二沉積層係氮化層。 1 0.如申請專利範圍第2項所述之堆疊閘極快閃記憶裝 置之製造方法，其中該第一、第二及第三絕緣層係氧化 層。 11.如申請專利範圍第2項所述之堆疊閘極快閃記憶裝 置之製造方法，其中該第四絕緣層係一氧化層及一氮化 層00503-6914TWF; TSMC2001-0760; Vincnet.ptd Page 13 529088 6. The manufacturing method of the patent application scope, which further includes the following steps: forming a first on the first conductive layer connected to the source doped region Five insulating layers; and depositing a second conductive layer, the second conductive layer is connected to the first conductive layer above the drain doped region, and through the fifth insulating layer and the first conductive layer above the source doped region A conductive layer is insulated. 5. The method for manufacturing a stacked gate flash memory device according to item 2 of the scope of patent application, wherein the conductive layer is a polycrystalline silicon layer. 6. The manufacturing method of the stacked gate flash memory device according to item 2 of the scope of patent application, wherein the substrate is a silicon substrate. 7. The method for manufacturing a stacked gate flash memory device according to item 2 of the scope of patent application, wherein the first and second gate layers are polycrystalline silicon layers. 8. The method for manufacturing a stacked gate flash memory device as described in item 2 of the patent application scope, wherein the first deposited layer is an oxide layer. 9. The method for manufacturing a stacked gate flash memory device according to item 2 of the scope of patent application, wherein the second deposited layer is a nitride layer. 10. The method for manufacturing a stacked gate flash memory device according to item 2 of the scope of the patent application, wherein the first, second and third insulating layers are oxide layers. 11. The method for manufacturing a stacked gate flash memory device according to item 2 of the scope of the patent application, wherein the fourth insulating layer is an oxide layer and a nitride layer. 0503-6914TWF ； TSMC2001-0760 ； Vincnet.ptd 第14頁0503-6914TWF; TSMC2001-0760; Vincnet.ptd page 14