527652 A7 B7 五、發明説明（） 發明領域： 本發明係有關於一種半導體元件及製程，特別是有關 於一種分閘式（sPllt-§ate)快閃記憶胞之選擇閘極的製作方 法。 發明背景： 典型地’電腦中之資料儲存媒體大致可分為揮發性 (Volatile)記憶體及非揮發性（N〇nv〇Utile)記憶體兩類。揮 發性記憶體包含有動態隨機存取記憶體（DRAM)及靜態隨 機存取記憶體（SRAM) ’其所存入的資料會因電源中斷而消 失，故主要應用於暫時性的資料存取，而非揮發性記憶體 在電源關閉之後’仍然可維持所儲存的資料，因而可應用 於各種不同場合的資料儲存。非揮發性記憶體依資料存取 方式又可區分為·罩幕唯讀記憶體（Mask R〇M)、可抹除唯 讀記憶體（EPROM)、電子可抹除唯讀記憶體（EEpR〇M)及快 閃記憶體（Flash EEPROM)等。 自從25 6K的快閃記憶體在1 987年展露頭角以來，快 閃§己憶體已經逐漸成為非揮發性記憶體的發展主流。快閃 記憶體為結合EPROM與EEPROM之優點所發展出來的高 度在、§己憶體’具有非揮發性、可重複讀寫、高密度及耐久 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) ---^.......... * (請先閲讀背面之注意事項再填寫本頁) 、νά> 經濟部智慧財產局員工消費合作社印製 527652 A7 B7 五 、發明說明（ 性等優越特色，十 .^ 卞刀適合應用於可攜式電腦及電信工繁 甚有學者預十恤pq 呆’ 〇 、岣圮憶體將成為帶動下一階段丰導辦岔 的主守遐革命 了見快閃記憶體在半導體工業中占舉足輕 位。 工至 < 地 經濟部智慧財產局員工消費合作社印製 /、型地，快閃記憶體依結構方式可區 (Split-gate)快閃1 局刀閘式 )門§己憶體與®閘式（Stack-gate)快閃記 兩種，JL中合艘 、 式快閃記憶體之資料抹除的速度較疊 快閃記恃、辦，沐，& Θ式 ^體K 故為現今半導體業界重用。一般分閘 閃記情胎έ士堪治a 式快 "'，Ό & —由閘極氧化層/複晶矽層/氧化屛細 一 。毒、一控制閘極/選擇閘極及一形成 懸浮閘極纟士構盘、誇 '° 一 ^制閘極/選擇閘極之間的間複晶矽 層，由於該懸浮間極結構之複晶石夕層沒有與任何電極電卜4 相連’故稱為懸浮聞極。快閃記憶體的資料抹除及寫入私 作可藉由在㈣Ul a、源極、没極及基材施加不同 組合，而蔣雪不、、+ 电藥 二 、 在入或移出懸浮閘極。為了使分閘式伊 :憶體正確地操作，選擇閘極必需至少覆蓋汲極區(或源： 區）與懸汙閘極之間的距離，即由汲極區或源極區至懸浮^ 極之間必需保持適當的距離以作為電子通道。若通道長Z 太短時’易發生短通道效應（Short Channel Effects)，而通 道長度太長時’則會使寫入效率變差。 隨著半導體積集度（111^§1：“丨〇11)與日益增，元件尺寸已 -Γ:-,.........mw.........訂.........線·...... j f請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 527652 A7 B7 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 因應趨勢縮小至次微米或是深次微米卜·35 # m)範圍。由於 快閃記憶雔需要有適當的通道長度’致使製作微縮尺寸之 分閘式快閃記憶體有其困難度’因此需要發展一種新的具 微縮尺寸且可保持通道長度之分閘式快閃記憶體結構，以 解決上述問題。 發明目的及概述： 鑒於上述習知快閃記憶體中之源極/汲極與懸浮閘極 之間需保持適當的通道長度，致使快閃記憶體結構之尺寸 縮小不易等問題，本發明係提出一種分閘式快閃記憶胞之 選擇閘極的製作方法，於半導體基材之溝渠側壁形成選擇 閘極，以縮小選擇閘極之橫向尺寸及保持通道長度。 經濟部智慧財產局員工消費合作社印製 本發明的主要目的之一為提供一種分閘式快閃記憒、胞 之選擇閘極的製作方法，係應用於一半導體基材上，該半 導體基材上已形成至少一具有閘極氧化層/複晶石夕層/第 一氧化層之懸浮閘極結構及一源極區，該方法至少包含下 列步驟：形成一溝渠於該懸浮閘極結構之一側的該半導體 基材中，該溝渠係位於該源極區之相對側；形成一間複曰 矽介電層於該懸浮閘極結構及該溝渠之側壁上；形成—複 晶矽間隙壁於該間複晶矽介電層側壁上以作為選擇問極. 及形成一汲極區於該溝渠相鄰該懸浮閘極結構的半導體爲 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) —---— 527652 A7 B7 五、發明説明（） 材中。 (請先閲讀背面之注意事項再填寫本頁) 本發明的另一目的為提供一種分閘式快閃記憶胞之製 作方法，該方法至少包含下列步驟：形成一閘極氧化層於 一半導體基材上；形成一複晶矽層於該閘極氧化層上；形 成一氮化矽層於該複晶矽層上；形成一溝渠於該氮化矽層 中並暴露出該複晶矽層之部分上表面，以定義一懸浮閘極 區；形成一第一氧化層於該溝渠中；形成一共源極插塞於 兩相鄰的該懸浮閘極區之間；進行蝕刻製程以移除該氮化 矽層及未被該第一氧化層覆蓋之該複晶矽層及該閘極氧化 層，以形成一懸浮閘極結構；形成一基材溝渠於該懸浮閘 極結構一側之半導體基材中，該基材溝渠係位於該共源極 插塞之相對側；形成一間複晶矽介電層於該懸浮閘極結構 及該基材溝渠之側壁；形成一複晶矽間隙壁於該間複晶矽 介電層側壁以作為選擇閘極；及形成一汲極區於該溝渠相 鄰該懸浮閘極結構的半導體基材中。 經濟部智慧財產局員工消費合作社印製 本發明的再一目的為提供一種分閘式快閃記憶胞結 構，該結構至少包含有：一懸浮閘極結構，形成於一半導 體基材上，該懸浮閘極結構具有由下至上依序堆疊之一閘 極氧化層、一複晶石夕層及一第一氧化層，該懸浮閘極結構 之一側的該半導體基材中具有一溝渠；一間複晶矽介電 層，形成於該懸浮閘極結構及該溝渠之側壁上；一複晶矽 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 527652 A 7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 間隙壁，形成於該間複晶矽介電層之側壁上以作為選擇閘 極；一汲極，形成於該溝渠之半導體基材中，該汲極區係 與該選擇閘極相鄰；及一源極，形成於相對於該溝渠之半 導體基材中。 利用本發明之方法所形成的分閘式快閃記憶胞結構， 不僅可有效地縮減選擇閘極之橫向尺寸並保持通道長度， 而且可產生彈道熱電子沿著半導體基材溝渠側壁之選擇閘 極通道衝注至懸浮閘極，可增進資料寫入效率及降低寫入 電壓，達到深次微米製程之分閘式快閃記憶胞的高存取速 度及低功率損耗之需求。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述，其中： 第1〜6圖為繪示本發明之分閘式快閃記憶胞的製程 剖面示意圖；以及 經濟部智慧財產局員工消費合作社印製 第7圖為顯示一根據本發明之分閘式快閃記憶胞陣列 佈局之局部平面圖。 圖號對照說明： 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 527652 A7 B7 五、發明説明（） 10 基材 20 閘極氧化層 30 複晶矽層/懸浮閘極 40 氮化矽層 50 第一氧化層 60 光阻層 70 間隙壁 80 共源極插塞 90 第二氧化層 100 基材溝渠 110 間複晶矽介電層 120 複晶矽間隙壁/選擇閘極 200 隔離區 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 發明詳細說明： 本發明係揭露一種分閘式快閃記憶胞結構及其製作方 法，其中該分閘式快閃記憶胞之選擇閘極係形成於半導體 基材溝渠的側壁上，利用基材溝渠側壁作為選擇閘極通 道，可保持通道長度並縮小選擇閘極之橫向尺寸，且此種 通道結構可產生彈道熱電子，增進資料寫入效率及降低寫 入電壓。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 527652 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 首先請參照第1圖，其係繪示根據本發明之方法製作 一分閘式快閃記憶胞的初始結構。如第1圖所示，記憶胞 1包含有一半導體基材1 0、一閘極氧化層2 0、一複晶矽層 3 0及一氮化矽層40。較佳地，基材1 0可使用結晶方向為 < 1 00>之單晶半導體材料，而閘極氧化層20可以利用溫度 在8 00〜1 000 °C之間的高溫熱氧化法於基材10上形成厚度 約為5 0〜1 5 0埃的氧化層，亦可利用傳統之化學氣相沉積 法形成該閘極氧化層2 0。複晶矽層3 0可使用低壓化學氣 相沉積法（LPCVD)或是其它習知的適當方式形成於閘極氧 化層20上，且複晶矽層3 0可選擇摻雜多晶矽或是同步摻 雜多晶矽以形成厚度約為3 00〜3 000埃之導體。由於複晶 矽層3 0沒有與任何其它導體相連，故稱為懸浮閘極，可用 於儲存電荷。氮化矽層40可使用低壓化學氣相沉積法沉積 於複晶矽層30上，厚度約為500〜5 000埃。 經濟部智慧財產局員工消費合作社印製 接著，一第一光阻層（未圖示）係形成於氮化石夕層40上 以定義出懸浮閘極區，隨後進行乾蝕刻製程，蝕刻未覆蓋 第一光阻層的氮化矽層4 0直到暴露出複晶矽層3 0。接著， 再次使用蝕刻製程以於暴露的複晶矽層 3 0之上表面形成 兩尖端向上的結構，之後去除第一光阻層。 參照第2圖，再以化學氣相沉積法形成第一氧化層5 0 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 527652 A7 B7 五、發明説明（） 於暴露的複晶矽層3 0上，並施以回蝕或是化學機械研磨 (Chemical Mechanical Polishing)製程，以使氮化矽層 4〇 與第一氧化層50之上表面共平面。 參照第3圖，接著形成第二光阻層6 0於氮化石夕層4 0 上以定義共源極區，再進行姓刻製程以去除未被第二光阻 層60覆盖的氮化石夕層40、第一氧化層50、複晶石夕層3〇 及閘極氧化層20直到暴露出基材1 〇的部分表面。其中各 層的蝕刻製程例如可使用熱磷酸鹽去除氮化矽層4〇，使用 濕蝕刻浸沾方式（Dip)去除第一氧化層50,使用含氣之電聚 蝕刻劑去除複晶矽層3 0，及使用含氟化碳的電漿對閑極氧 化層2 0進行乾蝕刻。隨後，施以一離子佈植製程以 牧恭路 的基材1 0中形成共源極區。用於形成共源極區之松 b滩材料 係視基材1 0之材料種類而定。例如，若基材1 0為v P义時， 可在基材1 0中摻雜一 n型摻質（例如磷）以形成共源極區· 若基材1 0為η型時，則可在基材1 〇中摻離一 ρ型摻質（例 如硼）以形成共源極區。之後再移去第二光阻層60。 ......…费： (請先閲讀背面之注意事項再填寫本頁} 、一=口 經濟部智慧財產局員工消費合作社印製 旧 虱化 層於共源極區之表面，再對該氧化層進行蝕刻萝 取枉以形成 共源極區間隙壁（s p a c e r) 7 0。該共源極區間隙壁7 Π及热 τ 土 , υ係覆蓋 部分的第一氧化層5 0、複晶矽層3 0及閘極氧化芦9 3 ζ υ之側 壁，以隔離兩相鄰記憶胞之懸浮閘極。接著，沉 々買另一複 本紙張尺度適用中國國家標準(CNS)A4規格(210Χ 297公釐） 527652 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 晶矽層於共源極區間隙壁7 0及共源極區上以形成複晶矽 插塞8 0，並施以回蝕或化學機械研磨製程，以氮化矽層4 0 作為終止層。 參照第5圖，以熱氧化法形成第二氧化層9 0於共源極 插塞8 0上，接著以乾蝕刻法或濕蝕刻法移除氮化矽層40， 再以第一氧化層5 0及第二氧化層90作為硬式罩幕對複晶 矽層30及閘極氧化層20進行蝕刻製程，直到暴露出基材 1 0之表面。此時係完成懸浮閘極結構及共源極插塞之製 作。 經濟部智慧財產局員工消費合作社印製 接下來將參照第6圖說明選擇閘極之製作方式。如第 6圖所不’以第1〜5圖所完成之懸浮閘極結構的第一及第 二氧化層5 0及9 0作為硬式罩幕對基材1 0進行蝕刻製程， 以形成複數個基材溝渠1 00於懸浮閘極結構兩側，例如可 採用例如C12、HBr、SF6或SiC14為蝕刻電漿源對基材10 進行乾蝕刻製程。該等基材溝渠1 00鄰接該浮閘極結構之 側壁為一傾斜側壁，溝渠的深度及溝渠側壁之斜度可依實 際需求而定。接著，以低壓化學氣相沉積法沉積一間複晶 矽介電層1 1 0於懸浮閘極結構及基材溝渠1 0 0之側壁表面 上，該間複晶矽介電層1 1 0係作為分閘式快閃記憶胞各懸 浮閘極與控制閘極/選擇閘極之間的絕緣材料，故可使用 介電性質較佳的氧化矽/氮化矽或是氧化矽/氮化矽/氧 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐) 527652 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 化矽（ΟΝΟ)之複合層結構。接著，沉積另一複晶矽層於間 複晶矽介電層1 1 0上，再施以蝕刻製程以形成複晶矽間隙 壁1 2 0於間複晶矽介電層11 0的側壁上，該複晶矽間隙壁 1 20係作為分閘式快閃記憶胞的選擇閘極。該複晶矽間隙 壁可使用傳統之化學氣相沉積法或是其它適當方法形成， 較佳地，其厚度約為5 00〜3 000埃之間。該第二複晶矽層 可由摻雜複晶矽或同步摻雜多晶矽而形成導體，且該第二 複晶矽亦可由摻雜複晶矽及矽化鎢形成複晶矽化金屬，該 材質為目前最廣用之一種閘極導電層材料。接著，可利用 傳統的離子植入或是擴散法摻雜雜質於基材溝渠1 00中以 形成汲極區。較佳地，用於形成汲極區之摻雜材料係與源 極區之換雜材料相同’而且係取決於半導體基材1 0所形成 之材料類型。此時係完成分閘式快閃記憶胞之製作。 經濟部智慧財產局員工消費合作社印製 第7圖係顯示一記憶胞陣列之局部平面圖，其中繪示 有複數個根據本發明之分閘式快閃記憶胞及用於隔離毗鄰 記憶胞列的隔離區2 0 0。該隔離區2 0 0之形成方式可利用 乾蝕刻製程在半導體基材1 0中蝕刻出複複條溝渠，然後依 序填入二氧化矽及多晶矽等材質而形成淺溝渠隔離區 (Shallow Trench Isolation，STI)，或者可使用區域氧化法 (Local Oxidation，LOCOS)。為了使圖示清晰明確，僅繪示 該記憶胞陣列之部分結構。 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 527652 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 典型地，分閘式快閃記憶胞的資料寫入係藉由在Ί 極、源極及複晶矽層（選擇閘）之間施加適當的電壓而將電 子入射至由複晶矽層所形成之懸浮閘極。在強電場作用 下，熱電子係撞擊矽原子而發生散射，進而穿過閘極氧化 層入射至懸浮閘極。記憶胞的資料抹除係藉由改變汲極、 源極與複晶矽層（選擇閘）之間的電壓，以將電子從懸浮閘 極經由側壁介電層移出至由複晶矽層所形成的選擇閘極。 由於熱電子在通道内的電場運動係藉由散射作用而注入懸 浮閘極，因此需施加足夠大的電壓及配合散射作用才能將 電子注入懸浮閘達成資料寫入。在根據本發明之方法形成 的分閘式快閃記憶胞結構中，其選擇閘極係形成於基材溝 渠側壁上，縮小了選擇閘極的橫向尺寸並同時保留相同的 通道長度，因此在施加適當的電壓於汲極、源極及選擇閘 以進行資料寫入時，熱電子係沿著基材溝渠側壁通道直接 注入至懸浮閘極中，如第6圖中之箭號方向所示。此種熱 電子直接由汲極/源極衝注至懸浮閘極的方式稱為彈道 (B a 11 i s t i c)熱電子注入，其寫入效率係較傳統藉由散射作用 注入熱電子的方式佳，且可降低施加於汲極、源極及選擇 閘之間的電壓。 經濟部智慧財產局員工消費合作社印製 綜上所述，本發明係揭露一種分閘式快閃記憶胞結構 及其製作方式，在半導體基材之溝渠側壁形成選擇閘極以 微縮快閃記憶胞之尺寸並保持通道長度。當施加適當的電 本紙張尺度適用中國國家標準(CNS)A4規格(210X297公釐) 527652 A7 B7 五、發明説明（） 壓於汲極、源極及選擇閘極時，彈道熱電子沿著溝渠側壁 之通道衝注至懸浮閘極，相較於傳統熱電子沿著水平方向 移動經散射才注入懸浮閘極之方式而言，本發明之快閃記 憶胞所獲致的寫入效率較佳及可降低寫入電壓。 以上所述僅為本發明之較佳實施例而已，並非用以限 定本發明之申請專利範圍，凡其它未脫離本發明所揭示之 精神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 13 本紙張尺度適用中國國家標準(CNS)A4規格(210X 297公釐)527652 A7 B7 V. Description of the invention () Field of the invention: The present invention relates to a semiconductor device and manufacturing process, and particularly to a method for manufacturing a gate of a selective flash memory cell of a sPllt-§ate flash memory cell. Background of the invention: The data storage media in a typical computer can be roughly divided into two types: volatile (Volatile) memory and non-volatile (Nonv0Utile) memory. Volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). The stored data will disappear due to power interruption, so it is mainly used for temporary data access. The non-volatile memory can still maintain the stored data even after the power is turned off, so it can be used for data storage in various occasions. Non-volatile memory can be further divided into: • Mask ROM (Mask ROM), EPROM (Erasable Read Only Memory), and Erasable Electronic Readable Memory (EEpR). M) and Flash EEPROM. Since 25 6K flash memory appeared in 1987, flash memory has gradually become the mainstream of the development of non-volatile memory. The flash memory is developed to combine the advantages of EPROM and EEPROM. The 己 memory body 'has non-volatile, repeatable read and write, high density and durability. This paper is applicable to the Chinese National Standard (CNS) A4 specification ( 210X297 mm) --- ^ .......... * (Please read the precautions on the back before filling out this page), νά > Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs 527652 A7 B7 V. Description of the invention (excellent features such as sex, etc.). 卞 The knife is suitable for portable computers and telecommunications. There are scholars who pre-decade shirts. 〇, 岣 圮 memory will become the driving force for the next stage. Leading the revolution and seeing that flash memory plays a decisive role in the semiconductor industry. To work < Printed by the consumer co-operatives of the Intellectual Property Bureau of the Ministry of Land Economy, and type, land, flash memory can be distinguished by structure ( Split-gate) Fast flash 1 round knife gate) § Self-memory body and ® Gate-style (Stack-gate) flash memory恃 恃, Do, Mu, & Θ type ^ body K is therefore reused in today's semiconductor industry. General opening of the gate, flash memory, kanji a-style fast " ', Ό & — by the gate oxide layer / polycrystalline silicon layer / thin oxide. Poison, a control gate / selection gate, and a suspension gate to form a structure of a warrior, and an inter-layered silicon layer between the gate and the selection gate. Due to the complex structure of the suspension gate The spar evening layer is not connected to any of the electrodes, so it is called a floating sensation electrode. Flash memory data can be erased and written into private works by applying different combinations to ㈣Ul a, source, electrode, and substrate, while Jiang Xuebu ,, + Electrochemical II, and floating gates in or out . In order for the split gate I: memory to operate correctly, the gate selection must cover at least the distance between the drain region (or source: region) and the suspended gate, that is, from the drain region or source region to the suspension ^ An appropriate distance must be maintained between the poles as an electron channel. If the channel length Z is too short, 'Short Channel Effects' are prone to occur, and when the channel length is too long, the writing efficiency will be deteriorated. With the increasing degree of semiconductor accumulation (111 ^ §1: "丨 〇11) and increasing, the size of components has been -Γ:-, ......... mw ......... order. ........ line · ...... jf Please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 527652 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) Reduce to the sub-micron or deep sub-micron (35 #m) according to the trend. Due to the flash memory, an appropriate channel length is required ' As a result, it is difficult to make a miniature flash memory with a small size. Therefore, it is necessary to develop a new flash memory structure with a small size and can maintain the channel length to solve the above problems. : In view of the problem that the proper channel length needs to be maintained between the source / drain and the floating gate in the conventional flash memory, which makes it difficult to reduce the size of the flash memory structure, the present invention proposes a split-gate type A method for fabricating a selection gate of a flash memory cell, forming a selection gate on a side wall of a trench of a semiconductor substrate to Reduce the horizontal dimension of the selected gate and maintain the length of the channel. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. One of the main objectives of the present invention is to provide a method for making a gate of the selected gate of the flash gate. On a semiconductor substrate, at least one suspended gate structure having a gate oxide layer / polycrystalline stone layer / first oxide layer and a source region have been formed on the semiconductor substrate. The method includes at least the following steps: A trench is formed in the semiconductor substrate on one side of the floating gate structure, and the trench is located on the opposite side of the source region; a silicon dielectric layer is formed on the floating gate structure and the trench. On the side wall; forming-a polycrystalline silicon spacer on the side wall of the inter-crystalline silicon dielectric layer as a selective interrogator; and a semiconductor forming a drain region adjacent to the floating gate structure adjacent to the trench is applicable to the paper standard China National Standard (CNS) A4 Specification (210X297 mm) —————— 527652 A7 B7 V. Description of the Invention () (Please read the precautions on the back before filling this page) Another purpose of this invention is provide A method for manufacturing a gated flash memory cell, the method includes at least the following steps: forming a gate oxide layer on a semiconductor substrate; forming a polycrystalline silicon layer on the gate oxide layer; forming a nitride A silicon layer is formed on the polycrystalline silicon layer; a trench is formed in the silicon nitride layer and a part of the upper surface of the polycrystalline silicon layer is exposed to define a suspended gate region; a first oxide layer is formed on the trench Forming a common source plug between two adjacent floating gate regions; performing an etching process to remove the silicon nitride layer and the polycrystalline silicon layer and the gate not covered by the first oxide layer An oxide layer to form a suspended gate structure; a substrate trench is formed in a semiconductor substrate on one side of the suspended gate structure, and the substrate trench is located on the opposite side of the common source plug; A polycrystalline silicon dielectric layer is formed on the floating gate structure and the sidewall of the substrate trench; a polycrystalline silicon spacer is formed on the side wall of the polycrystalline silicon dielectric layer as a selection gate; and a drain region is formed on The trench is adjacent to the semiconductor substrate of the floating gate structure. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, another object of the present invention is to provide a split-type flash memory cell structure, which at least includes: a suspended gate structure formed on a semiconductor substrate, and the suspended The gate structure has a gate oxide layer, a polycrystalline stone layer, and a first oxide layer sequentially stacked from bottom to top. The semiconductor substrate on one side of the suspended gate structure has a trench; one A polycrystalline silicon dielectric layer is formed on the floating gate structure and the side wall of the trench; a polycrystalline silicon paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 527652 A 7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) The spacer is formed on the side wall of the polycrystalline silicon dielectric layer as a selection gate; a drain is formed in the semiconductor substrate of the trench The drain region is adjacent to the selection gate; and a source is formed in a semiconductor substrate opposite to the trench. The split-type flash memory cell structure formed by the method of the present invention can not only effectively reduce the lateral size of the selection gate and maintain the channel length, but also can generate ballistic hot electrons along the semiconductor substrate trench sidewall. Channel injection to the floating gate can improve the data writing efficiency and reduce the writing voltage, and achieve the requirements of high access speed and low power loss of the split-type flash memory cell in the deep sub-micron process. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory texts with the following figures, where: Figures 1 to 6 show the split-type flash memory cell of the present invention Figure 7 is a schematic cross-sectional view of the manufacturing process; and printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 7 is a partial plan view showing the layout of a flash memory cell array according to the present invention. Description of drawing number comparison: This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 527652 A7 B7 V. Description of the invention () 10 substrate 20 gate oxide layer 30 polycrystalline silicon layer / suspended gate 40 nitrogen Siliconized layer 50 First oxide layer 60 Photoresist layer 70 Spacer wall 80 Common source plug 90 Second oxide layer 100 Substrate trench 110 Polycrystalline silicon dielectric layer 120 Polycrystalline silicon spacer / select gate 200 Isolation (Please read the notes on the back before filling this page) Detailed description of the invention printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: The present invention discloses a switch-type flash memory cell structure and its manufacturing method. The selection gate of the flash memory cell is formed on the sidewall of the semiconductor substrate trench. The sidewall of the substrate trench is used as the selection gate channel to maintain the channel length and reduce the lateral size of the selection gate. Generate ballistic hot electrons to improve data writing efficiency and reduce writing voltage. This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 527652 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) Please refer to Figure 1 first, which is a drawing According to the method of the present invention, an initial structure of a split-type flash memory cell is manufactured. As shown in FIG. 1, the memory cell 1 includes a semiconductor substrate 10, a gate oxide layer 20, a polycrystalline silicon layer 30, and a silicon nitride layer 40. Preferably, the substrate 10 can be a single crystal semiconductor material with a crystal orientation of < 1 00 >, and the gate oxide layer 20 can be subjected to a high temperature thermal oxidation method at a temperature between 800 to 1 000 ° C. An oxide layer having a thickness of about 50˜150 angstroms is formed on the substrate 10, and the gate oxide layer 20 can also be formed by a conventional chemical vapor deposition method. The polycrystalline silicon layer 30 can be formed on the gate oxide layer 20 using low pressure chemical vapor deposition (LPCVD) or other known appropriate methods, and the polycrystalline silicon layer 30 can be doped with polycrystalline silicon or synchronously doped with silicon. Polycrystalline silicon is doped to form a conductor having a thickness of about 300 to 3,000 angstroms. Since the polycrystalline silicon layer 30 is not connected to any other conductor, it is called a floating gate and can be used to store charge. The silicon nitride layer 40 can be deposited on the polycrystalline silicon layer 30 using a low-pressure chemical vapor deposition method, and has a thickness of about 500 to 5,000 angstroms. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Next, a first photoresist layer (not shown) is formed on the nitride nitride layer 40 to define a floating gate region, and then a dry etching process is performed. A photoresistive silicon nitride layer 40 is exposed until the polycrystalline silicon layer 30 is exposed. Next, an etching process is used again to form a two-pointed structure on the upper surface of the exposed polycrystalline silicon layer 30, and then the first photoresist layer is removed. Referring to Figure 2, the first oxide layer was formed by chemical vapor deposition method. 5 This paper size is in accordance with Chinese National Standard (CNS) A4 (210X297 mm) 527652 A7 B7. 5. Description of the invention () Exposed compound The silicon layer 30 is subjected to an etch-back or chemical mechanical polishing process to make the silicon nitride layer 40 coplanar with the upper surface of the first oxide layer 50. Referring to FIG. 3, a second photoresist layer 60 is then formed on the nitride nitride layer 40 to define a common source region, and then a surname process is performed to remove the nitride nitride layer not covered by the second photoresist layer 60. 40. The first oxide layer 50, the polycrystalline stone layer 30 and the gate oxide layer 20 until a part of the surface of the substrate 10 is exposed. The etching process of each layer can be, for example, removing the silicon nitride layer 40 with hot phosphate, removing the first oxide layer 50 with a wet etching dip method (Dip), and removing the polycrystalline silicon layer with a gas-containing electropolymeric etchant. , And dry etching of the anode oxide layer 20 using a plasma containing carbon fluoride. Subsequently, an ion implantation process is performed to form a common source region in the substrate 10 of Mugong Road. The materials used to form the shoal of the common source region depend on the type of material of the substrate 10. For example, if the substrate 10 is v P, a n-type dopant (such as phosphorus) can be doped in the substrate 10 to form a common source region. If the substrate 10 is n-type, A p-type dopant (such as boron) is doped from the substrate 10 to form a common source region. After that, the second photoresist layer 60 is removed. ...... Fees: (Please read the precautions on the back before filling out this page} 、 1 = Print the old lice layer on the surface of the common source area by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs The oxide layer is etched to form a spacer 70 in the common source region. The spacer 7 in the common source region and the thermal τ soil, the first oxide layer 50 covered by υ, and the polycrystal The silicon layer 30 and the gate oxide reed 9 3 ζ υ side walls to isolate the floating gates of two adjacent memory cells. Then, Shen Min bought another copy of paper with the standard of China National Standard (CNS) A4 (210 × 297) (Mm) 527652 A7 B7 V. Description of the invention () (Please read the notes on the back before filling this page) A crystalline silicon layer is formed on the common source region gap wall 70 and the common source region to form a polycrystalline silicon plug 80, and an etch-back or chemical mechanical polishing process is performed, and a silicon nitride layer 40 is used as a stop layer. Referring to FIG. 5, a second oxide layer 90 is formed on the common source plug 80 by a thermal oxidation method. Then, the silicon nitride layer 40 is removed by dry etching or wet etching, and then the first oxide layer 50 and the second oxide layer 90 are used as The hard mask performs an etching process on the polycrystalline silicon layer 30 and the gate oxide layer 20 until the surface of the substrate 10 is exposed. At this time, the fabrication of the floating gate structure and the common source plug is completed. The intellectual property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives The following will describe the method of selecting the gate electrode with reference to Fig. 6. As shown in Fig. 6, the first and second oxide layers 5 of the suspended gate structure completed in Figs. 1 to 5 0 and 9 0 are used as a hard mask to etch the substrate 10 to form a plurality of substrate trenches 100 on both sides of the floating gate structure. For example, C12, HBr, SF6 or SiC14 can be used as the etching plasma source. A dry etching process is performed on the substrate 10. The sidewalls of the substrate trenches 100 adjacent to the floating gate structure are inclined sidewalls, and the depth of the trenches and the slope of the trench sidewalls can be determined according to actual needs. Then, low-pressure chemistry The vapor deposition method deposits a polycrystalline silicon dielectric layer 1 10 on the surface of the side wall of the floating gate structure and the substrate trench 100. The polycrystalline silicon dielectric layer 1 10 is used as a split-gate type. Between the floating gate of the flash memory cell and the control gate / selection gate Insulating material, so silicon oxide / silicon nitride or silicon oxide / silicon nitride / oxygen with better dielectric properties can be used. The paper size is applicable to Chinese National Standard (CNS) A4 specification (210X 297 mm) 527652 A7 B7 5 2. Description of the invention () (Please read the precautions on the back before filling this page) The compound layer structure of siliconized silicon (NO). Next, deposit another polycrystalline silicon layer on the inter-crystalline silicon dielectric layer 1 1 0, Then, an etching process is performed to form a polycrystalline silicon spacer wall 120 on the sidewall of the intercrystalline silicon dielectric layer 110. The polycrystalline silicon spacer wall 120 is used as a selection gate of the flash memory cell of the split type. . The polycrystalline silicon spacer can be formed using a conventional chemical vapor deposition method or other suitable methods. Preferably, the thickness is between about 500 and 3,000 angstroms. The second polycrystalline silicon layer may be formed of a doped polycrystalline silicon or a doped polycrystalline silicon to form a conductor, and the second polycrystalline silicon layer may also be formed of doped polycrystalline silicon and tungsten silicide to form a polycrystalline silicide metal. A widely used gate conductive layer material. Then, a conventional ion implantation or diffusion method can be used to dope impurities into the substrate trench 100 to form a drain region. Preferably, the doping material used to form the drain region is the same as the doping material of the source region 'and depends on the type of material formed by the semiconductor substrate 10. At this point, the production of the split-type flash memory cell is completed. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 7 is a partial plan view showing a memory cell array, in which a plurality of flash memory cells according to the present invention are opened and used to isolate adjacent memory cell rows. District 2 0 0. The isolation region 200 can be formed by using a dry etching process to etch multiple trenches in the semiconductor substrate 10 and then sequentially filling materials such as silicon dioxide and polycrystalline silicon to form a shallow trench isolation region (Shallow Trench Isolation). (STI), or Local Oxidation (LOCOS) can be used. In order to make the illustration clear, only a part of the structure of the memory cell array is shown. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 527652 A7 B7 V. Description of the invention () (Please read the precautions on the back before filling this page) Typically, the flash memory Data is written by applying an appropriate voltage between the ytterbium, the source, and the polycrystalline silicon layer (selective gate) to inject electrons into the floating gate formed by the polycrystalline silicon layer. Under the action of a strong electric field, the hot electrons collide with silicon atoms and scatter, and then pass through the gate oxide layer and enter the suspended gate. Data erasure of the memory cell is performed by changing the voltage between the drain, source, and the polycrystalline silicon layer (selective gate) to remove electrons from the floating gate through the sidewall dielectric layer to the polycrystalline silicon layer. Selection gate. Since the electric field motion of the hot electrons in the channel is injected into the floating gate electrode by scattering, a sufficient voltage must be applied and the scattering effect must be applied to inject electrons into the floating gate to write data. In the split-type flash memory cell structure formed according to the method of the present invention, the selection gate is formed on the side wall of the substrate trench, which reduces the lateral size of the selection gate while retaining the same channel length. When the appropriate voltage is applied to the drain, source, and selection gates for data writing, the hot electrons are directly injected into the suspended gates along the side channel of the substrate trench, as shown by the arrow direction in FIG. 6. This method of injecting hot electrons directly from the drain / source to the suspension gate is called ballistic (B a 11istic) hot electron injection, and its writing efficiency is better than the traditional method of injecting hot electrons by scattering. And can reduce the voltage applied between the drain, source and selection gate. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In summary, the present invention discloses a split flash memory cell structure and a manufacturing method thereof, and a selective gate is formed on a side wall of a trench of a semiconductor substrate to miniaturize the flash memory cell. Size and maintain channel length. When the appropriate electrical paper size is applied to the Chinese National Standard (CNS) A4 specification (210X297 mm) 527652 A7 B7 V. Description of the invention () When it is pressed on the drain, source and selection gate, the ballistic thermoelectrons run along the trench The channel of the side wall is injected to the suspension gate, compared with the traditional method in which the hot electrons move in a horizontal direction and are injected into the suspension gate after scattering, the write efficiency obtained by the flash memory cell of the present invention is better and can be achieved. Reduce the write voltage. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Any other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of patent application. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 13 This paper size applies to China National Standard (CNS) A4 (210X 297 mm)