TW507372B - Manufacturing method of stacked gate flash memory - Google Patents

Abstract

A manufacturing method of stacked gate flash memory is disclosed. It comprises the following steps. First, form doping areas and pad oxide layer on the semiconductor substrate. Then form a masking layer on the pad oxide layer. Second, pattern the mask layer, pad oxide layer and semiconductor substrate to form trenches. Then fill stuff materials in the trenches and covering the semiconductor substrate. Third, remove a part of the stuff material till exposing the masking layer surface. Then remove the masking layer and form a first conductive layer on the surface of substrate. Forth, remove a fraction of the first conductive layer to expose the upper surface of stuff material and then form a dielectric layer on the first conductive layer. Finally, form a second conductive layer on the dielectric layer.

Description

507372 五、發明說明（1) 發明領域 本發明係有關於半導體元件，特別是一種製造快 閃記憶體之方法。 發明背景·· /半導體工業已經進步到極大型積體電路（ULSI)的 技術領域。非揮發性記憶體也配合著元件大小降低 $趨勢而製造。且非揮發性記憶體包含許多不同型 ，的疋件，例如：可電修改唯讀記憶體（EAR0M ) 、 · 可電除且可程式唯讀記憶體（EEPR0M )、可電除且 可程式唯讀記憶體—可電修改唯讀記憶體 f EEPRQM~EAR0Ms )與非揮發性靜態隨機存取記憶體 (SRAMs)。隨著每一階段記憶體的特定應用需求， 不同型態的元件之發展。這些已發展的部分是 $中在高耐力與高速度的需求上。各式各樣快閃記 體已經揭露在傳統的技術中，例如：Mi tchel lx所 的，、有自對準平面的陣列晶胞（planar array cel 1 )之EPROMs。在這個技術裡，埋藏擴散自對準 ^elf-ailgned)浮置閘極之大量注射m〇s電晶體是 一 餅進作為位元線。十字形點陣列技術已經揭露。自 2準之源極與汲極可以允許元件有效的進行更進一 '的編制程序（programming)速度。參閱ΑΤ·507372 V. Description of the invention (1) Field of the invention The present invention relates to a semiconductor device, and particularly to a method for manufacturing a flash memory. BACKGROUND OF THE INVENTION The semiconductor industry has advanced to the technical field of very large integrated circuits (ULSI). Non-volatile memory is also manufactured in conjunction with the trend to reduce component size. And non-volatile memory contains many different types of files, such as: electrically modifiable read-only memory (EAR0M), · electrically erasable and programmable read-only memory (EEPR0M), electrically erasable and programmable only Read Memory—Read-only memory f EEPRQM ~ EAR0Ms) and non-volatile static random access memory (SRAMs) can be modified. With the specific application requirements of memory at each stage, different types of components are developed. These developed parts are the demand for high endurance and high speed. A variety of flash memories have been disclosed in traditional technologies, such as EPROMs by Mitchel lx, which have a self-aligned planar array cell (planar array cel 1). In this technique, buried diffusion self-aligned ^ elf-ailgned) floating injection of a large number of injected MOS transistors is a piezo as a bit line. Cross-shaped dot array technology has been revealed. The source and drain of the standard can allow the device to perform further programming speed. See AT

第5頁 507372 五、發明說明（2)Page 5 507372 V. Description of the invention (2)

Mitchel lx於 IEDM，Tech· ρρ· 54 8-553, 1 987所提出的" 一種新的超高密度EPROMs之自對準平面晶胞"。 快閃記憶體是非揮發性記憶體元件部分的一 種。此種元件包括一儲存電荷之浮置閘極與一電性 地置放電荷於其上與從浮置閘極去除電荷之要素 (element)。快閃記憶體的一個應用是電腦的 B I 0 S。典型的咼密度的非揮發性記憶體可以應用作 為手提式終端機（portable handy terminals)、 數位照相機（solid state camera)與PC卡的大量 存儲之用。這是由於非揮發性記憶體表現很多的優 點，例如：快速的讀取時間、低能量損耗。再者， 它也能用來取代磁碟記憶體。提出另一個 應用於手提式電腦使用與電信 (telecommunications)之晶胞陣列，其刊在BEE Trans·電子元件，νο 1· ED-43, P. 1510, 1996 ,Mitchel lx in IEDM, Tech · ρρ · 54 8-553, 1 987, " A new ultra-high density EPROMs self-aligned planar cell ". Flash memory is one of the non-volatile memory element parts. Such elements include a floating gate that stores electric charges and an element that electrically places the electric charges thereon and removes the electric charges from the floating gate. One application of flash memory is the computer's B I 0 S. Typical high density non-volatile memory can be used for mass storage of portable handy terminals, solid state cameras, and PC cards. This is due to the many advantages of non-volatile memory, such as fast read times and low energy consumption. Furthermore, it can be used to replace disk memory. Proposed another cell array for portable computer use and telecommunications, published in BEE Trans · Electronic Components, νο 1. · ED-43, P. 1510, 1996,

Bergmont等人提出之"低電壓NVGTH: 一種應用於手 提式電腦使用與電信之新的高性能3V/5V快閃記憶體 技術"。這個晶胞結構引進了具有快速存取時間 (access time)之低電壓 N0R 虛接地（N〇R virtual ground : NVG )快閃記憶體。在這快閃記憶體陣列圖 中’ ％氧化層（FOX)形成於每一晶胞之間，使得延 伸在每一晶胞FOX上的多晶矽層提供了適當的耦合 率。Bergmont也提及了手提式電腦使用與電信已經 篇文章中，存取時間對於低電絲2驅動力。在這 時間之㈣’其係藉由單二擇广件來達成快速存取 先充電（pre-charge )時間而非全位元線。· 非 速的存 統的應 置閘極 緣用的 麗的快 電壓約 )在充 隧穿致 須隨著 揮發性記 取的發展 用所必須 一段長的 介電質需 閃記憶體 3V或 5V 〇 電或放電 率，浮置 供應電壓 憶體的形 方向，因 的。快閃 時間。因 要有很高 是應用於 由習知技 中是一種 閘極與底 的降低而 成是朝向低供應電源、快 為這些需求是行動電腦系 記憶體需要電荷儲存在浮 此，應用於浮置閘極中絕 的品質表現。目前，低電 浮置閘極充電或放電期間 術可知，隧穿（tunnel ing 基本的技術。為了達到高 材之間的介電層的厚度必 降低。 美國專利6, 180,459名稱為"製造具有淺溝渠隔離 之快閃記憶體方法11，已經由Sheu於1 999年1月8日 提出申請（f i 1 ed )。習知技術揭露了包括形成淺溝 渠隔離結構之快閃記憶體製造方法也形成於此方法 中。 Chen等人在美國專利號6, 1 72, 395中揭露了 一個名稱為"自對準浮置閘極、快閃記憶晶胞與元件 於中製造之方法"，並且讓度（assigned)到Taiwan 507372 五、發明說明（4)Bergmont et al. Proposed "low-voltage NVGTH: a new high-performance 3V / 5V flash memory technology for handheld computer use and telecommunications". This cell structure introduces a low-voltage NOR virtual ground (NVG) flash memory with a fast access time. In this flash memory array diagram, a '% oxide layer (FOX) is formed between each cell, so that the polycrystalline silicon layer extending on each cell FOX provides a proper coupling rate. Bergmont also mentioned the use of laptops and telecommunications in a previous article on access time for low wire 2 driving forces. At this moment of time, it is achieved by single-choice and wide-selection to achieve fast access. Pre-charge time instead of full bit line. · The fast voltage of the non-fast storage system should be set at the gate edge.) During the tunneling process, a long dielectric must be used with the development of volatility. Flash memory 3V or 5V is required Electricity or discharge rate, due to the shape direction of the floating supply voltage memory. Flash time. Because it is very high, it is used to reduce the gate and the bottom in the conventional technology, and it is oriented towards a low power supply. For these needs, the memory of the mobile computer system needs charge to be stored in the float, and it is used in the float. Excellent performance in the gate. At present, it is known during the charging or discharging of low-electricity floating gates that tunneling is a basic technology. In order to achieve the thickness of the dielectric layer between high materials, the thickness of the U.S. Patent 6,180,459 is named " Manufactured by Shallow trench isolation flash memory method 11 has been filed by Sheu on January 8, 1999 (fi 1 ed). Conventional technology has revealed that flash memory manufacturing methods including the formation of shallow trench isolation structures are also formed. In this method, Chen et al., In US Patent No. 6, 1 72, 395, disclosed a method named "Self-Aligned Floating Gate, Flash Memory Cell, and Device in China", and Assigned degree to Taiwan 507372 V. Description of invention (4)

Semi conductor Manufacturing Company (Hsin-Chu， TW) 〇 發明目的及概述： 本發明之目的係在於形成一堆疊閘極之快閃記憶 體。 本發明之另一目的係在於形成一高耦合率之快閃記 憶體。 «丨 本發明揭露一種疊閘快閃記憶體之製造方法，其 包 括以下步驟··形成摻雜區域於半導體底材之内，形 成一 塾氧化層於半導體底材之上，形成一罩幕層在墊氧 化層 之上，圖案化罩幕層、墊氧化層與半導體底材，以 在其 令形成一溝渠，形成一填充物質於溝渠之内，使填 充物 _ 質覆蓋於半導體底材之上’去除一部分填充物質， 直到 ' 罩幕層上表面暴露出來，接著，去除罩幕層，形成Semi conductor Manufacturing Company (Hsin-Chu, TW) ○ Purpose and summary of the invention: The purpose of the present invention is to form a flash memory with stacked gates. Another object of the present invention is to form a flash memory with a high coupling ratio. «丨 The present invention discloses a method for manufacturing a stacked flash memory, which includes the following steps: forming a doped region in a semiconductor substrate, forming an oxide layer on the semiconductor substrate, and forming a mask layer Above the pad oxide layer, a patterned mask layer, pad oxide layer and semiconductor substrate are patterned to form a trench, and a filling substance is formed in the trench, so that the filler material covers the semiconductor substrate 'Remove a portion of the filling material until the top surface of the mask layer is exposed, and then remove the mask layer to form

507372 五、發明說明（5) 一第 一導電層於底材之表面，然後，去除一部分第一導 電層 ，以暴露出填充物質上表面，形成一介電層於第一 導電 層之上，最後，形成一第二導電層於介電層之上。 本發明揭露一種記憶體佈局，包含一記憶體陣 列具有列、行結構，上述行結構形成於基板中以溝 渠填充物隔離，其中上述行結構係為源極/汲極，並 且由浮置閘極所分離；由膜層形成之字元線（word Φ 1 i ne : L )，係構成上述之列結構用來當作控制閘 極，該膜層係為圖案化的導電層構成記憶體陣列之 控制閘極與字元線，元件的源極/汲極則構成了該記 憶體陣列之位元線（b i t 1 i ne : BL )。 發明詳細說明： 本發明提出一種新穎的方法以製造非揮發性快 閃記憶體。在此方法中，其耦合率（coupling r a t i 〇 )可以藉由姓刻填滿在溝渠内的物質來提高， 詳細的描述如下。507372 V. Description of the invention (5) A first conductive layer is on the surface of the substrate, and then a part of the first conductive layer is removed to expose the upper surface of the filling material to form a dielectric layer on the first conductive layer. Finally, A second conductive layer is formed on the dielectric layer. The invention discloses a memory layout including a memory array having a column and a row structure. The row structure is formed in a substrate and separated by a trench filler. The row structure is a source / drain and a floating gate. Separated; word line (word Φ 1 i ne: L) formed by the film layer, which constitutes the above-mentioned structure and is used as a control gate, and the film layer is a patterned conductive layer forming a memory array. The gate and the word line are controlled, and the source / drain of the component constitutes a bit line (bit 1 i ne: BL) of the memory array. Detailed description of the invention: The present invention proposes a novel method for manufacturing non-volatile flash memory. In this method, the coupling ratio (coupling r a t i 〇) can be increased by filling the material in the trench with the last name, as described in detail below.

第9頁 507372 五、發明說明（6) 本發明首先提供一個半導體底材，在一較佳實 施例中其中，如圖一所示，其為具有結晶方向<100 >或<111>之單晶秒底材2。上述底材2包括了内含 隔離的源極/沒極區域6之主動區域4。而主動區域4 與源極/沒極區域6可以藉由執行離子佈植來形成， 其係植入摻雜物（dopants)到底材2内部。接著於 底材2上面形成一包含二氧化矽之薄的介電層8,以 作為墊氧化層（pad oxide ) 8。典型的氧化層8可以 用氧氣環繞在溫度釣700〜1000 °C的環境之下形成。 另一個方法，也可以利用化學氣相沉積（chemical vapor deposition ;CVD)來形成氧化層8。在本實 蛛 施例中，二氧化矽層8的厚度約為5 0〜5 0 0埃 (angstroms)。接著，罩幕層1〇形成於墊氧化層8 之上。其中形成罩幕層1〇的適當物質包括由化學氣 相沉積方法沉積的氮化矽，而厚度約為5〇〇〜3〇〇〇 埃。此外，氮化矽層1 〇還可以利用其他適當的方法 來形成’例如：低壓化學氣相沉積（LPCVD )、電漿 化學氣相沉積（PECVD )或高密度電漿化學氣相沉積 (HDPCVD )等。在本實施例中，形成氮化矽層的反 應氣體包括：SiHi、NHi、N洤或 SiHICll、NHi、N【。 接著，請參考圖二。進行一微影、蝕刻步驟，以 蚀刻罩幕層10、介電層8與底材2至一深度，而在底 材2内形成溝渠1 2。在此步驟中，源極與汲極6即由Page 9 507372 V. Description of the invention (6) The present invention first provides a semiconductor substrate. In a preferred embodiment, as shown in FIG. 1, it has a crystal orientation < 100 > or < 111 > The single crystal second substrate 2. The substrate 2 includes an active region 4 including an isolated source / dead region 6. The active region 4 and the source / animated region 6 can be formed by performing ion implantation, which are implanted with dopants inside the substrate 2. Then, a thin dielectric layer 8 containing silicon dioxide is formed on the substrate 2 as a pad oxide layer 8. A typical oxide layer 8 can be formed under the environment of 700 ~ 1000 ° C with oxygen. Alternatively, chemical oxide deposition (CVD) may be used to form the oxide layer 8. In the present embodiment, the thickness of the silicon dioxide layer 8 is about 50 to 500 angstroms. Next, a mask layer 10 is formed on the pad oxide layer 8. A suitable material for forming the mask layer 10 includes silicon nitride deposited by a chemical vapor deposition method and has a thickness of about 500 to 300 Angstroms. In addition, the silicon nitride layer 10 can be formed by other appropriate methods, such as: low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition (PECVD), or high density plasma chemical vapor deposition (HDPCVD). Wait. In this embodiment, the reaction gas for forming the silicon nitride layer includes: SiHi, NHi, N 洤, or SiHIC11, NHi, N [. Next, please refer to Figure 2. A lithography and etching step is performed to etch the mask layer 10, the dielectric layer 8 and the substrate 2 to a depth, and a trench 12 is formed in the substrate 2. In this step, the source and drain 6 are

IIMI IBM 第10頁 507372IIMI IBM Page 10 507372

溝渠1 2所分離。 之後，於溝渠12内選擇性的形成一絕緣層14 (^sulatmg iayer)。形成絕緣層14的適當物質 ^括經由熱氧化過程形成之氧化物。絕緣層14去除 時會由於執行溝渠蝕刻步驟期間所利用的高能量離 子轟擊（ion bombardment)而產生毀損（damage )°然後’填充物質1 6填入溝渠1 2，以作為絕緣之 作用。上述填充物質16例如是由化學氣相沉積（cvd )系統所形成之乳化物’也就是所謂的CVD-oxide。 而形成氧化層16的最佳溫度範圍大約在400〜600 。 麵^ 接者’進行一化學機械研磨（chemical mechanical polishing; CMP)技術，以去除上面之CVD - oxide 16，直到氮化矽層10表面曝露出來為止，請參考圖 三。之後，以熱磷酸溶液（hot phosphorus acid solution)去除氮化梦廣1〇’請參考圖四。 請參考圖五。接著’以評或B 〇 E溶·邱-堂氧 化層8。氧化層8去除之後’ 一閘極介電層18形成於 底材2之上。然後，一掺雜多晶矽層20沉積在暴露的 墊氧化層8與氧化層16之上。一般而言，多晶矽層20 是從摻雜多晶矽或同步（in —situ)多晶矽形成。對 於本實施例而言，摻雜多晶矽層2 0是利用磷來進行 沉積，而磷之來源為PH3。接著，利用一化學機械研 麵 第11頁 507372 五、發明說明（8) 磨來研磨多晶石夕層2 〇，直到暴露出填充氧化層1 β之 上表面21為止，如圖六所示。 本發明的關鍵步驟是蝕刻填充氧化層1 6，其係 利用氧化物與多晶矽之間的高蝕刻選擇性。往下餘 刻氧化層1 6，由此而暴露出多晶矽層2 〇的側壁表 面°顯然的，多晶矽層20的耦合表面區域是增加 的，請參考圖七。接著，形成一内層多晶梦介電層 (inter polysilicon dielectric ： I PD) 22於浮置 閘極之上，以作為絕緣之作用。上述内層多晶石夕介 電層22組成包含但不限定於是氧化物/氮化物/氧化 物（oxide/nitride/oxide: 0N0)或氮化物 / 氧化物 (Ν0)。最後，一導電層，例如是摻閘多晶石夕層或 金屬24，形成於IDP介電層22之上，以作為控制閑。 摻閘多晶矽層24可以從摻雜多晶矽或同步（in —situ )多晶矽形成。此外，金屬或合金層也可以用來作 為導電層。 在本發明的製程中，由於本發明之浮置閘極形成 於隔離溝渠上的高等級的突起氧化層上面，因此可 以得到更高的耦合率。多晶矽層2 0的侧壁是暴露 的0 接著’請參考圖八、圖九’其顯不根據本發明之The ditch 1 2 is separated. After that, an insulating layer 14 (^ sulatmg iayer) is selectively formed in the trench 12. Suitable materials for forming the insulating layer 14 include oxides formed through a thermal oxidation process. When the insulating layer 14 is removed, damage is generated due to the high energy ion bombardment used during the trench etching step. Then, the filling material 16 is filled into the trench 12 to serve as insulation. The filler 16 is, for example, an emulsion formed by a chemical vapor deposition (cvd) system, that is, a so-called CVD-oxide. The optimal temperature range for forming the oxide layer 16 is about 400 ~ 600 °. The surface ^ connector is subjected to a chemical mechanical polishing (CMP) technique to remove the CVD-oxide 16 above, until the surface of the silicon nitride layer 10 is exposed, please refer to FIG. 3. After that, the hot phosphoric acid solution is used to remove the nitriding Mengguang 10 ′. Please refer to FIG. 4. Please refer to Figure 5. Next, the "Qiu-tang oxide layer 8 was evaluated by B or E. After the oxide layer 8 is removed ', a gate dielectric layer 18 is formed on the substrate 2. Then, a doped polycrystalline silicon layer 20 is deposited on the exposed pad oxide layer 8 and the oxide layer 16. Generally speaking, the polycrystalline silicon layer 20 is formed from doped polycrystalline silicon or in-situ polycrystalline silicon. For this embodiment, the doped polycrystalline silicon layer 20 is deposited using phosphorus, and the source of phosphorus is PH3. Next, use a chemical mechanical surface. Page 11 507372 V. Description of the invention (8) Grind the polycrystalline stone layer 20 until the upper surface 21 filled with the oxide layer 1 β is exposed, as shown in FIG. 6. The key step of the present invention is to etch the filled oxide layer 16 which utilizes the high etch selectivity between the oxide and the polycrystalline silicon. The oxide layer 16 is etched further down, thereby exposing the sidewall surface of the polycrystalline silicon layer 20. Obviously, the coupling surface area of the polycrystalline silicon layer 20 is increased, please refer to FIG. Next, an inter polysilicon dielectric (IPD) layer 22 is formed on the floating gate to serve as insulation. The composition of the above-mentioned polycrystalline silicon dielectric layer 22 includes, but is not limited to, oxide / nitride / oxide (oxide / nitride / oxide: 0N0) or nitride / oxide (NO). Finally, a conductive layer, such as a gate-doped polycrystalline silicon layer or a metal 24, is formed on the IDP dielectric layer 22 as a control layer. The gate-doped polycrystalline silicon layer 24 may be formed from doped polycrystalline silicon or in-situ polycrystalline silicon. In addition, a metal or alloy layer may be used as the conductive layer. In the process of the present invention, since the floating gate of the present invention is formed on a high-level protruding oxide layer on the isolation trench, a higher coupling rate can be obtained. The polysilicon layer 20 has its side walls exposed 0. Then, please refer to FIG. 8 and FIG.

第12頁 507372 五、發明說明（9) 記 憶體陣列。其記憶體陣列包括列、行結構。形成於 溝渠 中之每一源極/沒極6是作為位元線（bit Une : BL )，並 且其係由浮置閘極20所分離。然後，由層24形成之 字元 線（word line : WL),係用來當作控制閘極。也就 是說 ’圖案化的第二導電層2 4構成記憶體陣列之控制閘 極與 字元線。而元件的源極/汲極則構成了記憶體陣列之 位元 線0 對熟悉此領域技藝者，本發明雖以一較佳實例 闡明如上，然其並非用以限定本發明精神。在不脫 離本發明之精神與範圍内所作之修改與類似的安 排，均應包含在下述之申請專利範圍内，這樣的範 圍應該與覆蓋在所有修改與類似結構的最寬廣的古全 釋一致。因此，闡明如上的本發明一較佳實例，^ 用來鑑別不脫離本發明之精神與範圍内所作 改變。 谷禋Page 12 507372 V. Description of the invention (9) Memory array. Its memory array includes column and row structures. Each source / inverter 6 formed in the trench is used as a bit line (bit Une: BL), and is separated by a floating gate 20. Then, a word line (WL) formed by the layer 24 is used as a control gate. In other words, the patterned second conductive layer 24 constitutes the control gates and word lines of the memory array. The source / drain of the element constitutes the bit line 0 of the memory array. For those skilled in the art, although the present invention is illustrated above with a preferred example, it is not intended to limit the spirit of the present invention. Modifications and similar arrangements made without departing from the spirit and scope of the present invention should be included in the scope of patent applications described below. Such a scope should be consistent with the broadest ancient interpretation covering all modifications and similar structures. Therefore, a preferred embodiment of the present invention as explained above is used to identify changes made without departing from the spirit and scope of the present invention. Gu Yan

507372 圖式簡單說明 圖式簡單說明： 藉由以下詳細之描述結合所附圖示，將可輕易的了 解上述内容及此項發明之諸多優點，其中： 圖一為半導體晶圓截面圖，顯示根據本發明形成源 極與汲極、電氧化層與氮化層於半導體底材内之步 圖二為半導體晶圓截面圖，顯示根據本發明形成溝 渠於半導體體底材内之步驟。 圖三為半導體晶圓截面圖，顯示根據本發明形成溝 渠隔離之步驟。 圖四為半導體晶圓截面圖，顯示根據本發明去除氮 化層之步驟。 圖五為半導體晶圓截面圖，顯示根據本發明形成多 晶碎之步驟。 圖六為半導體晶圓截面圖，顯示根據本發明形成介 電層之步驟。 圖七為半導體晶圓截面圖，顯示根據本發明形成控 制閘之步驟。 圖八為顯示根據本發明之記憶晶胞之佈局（1 ay out 圖九為顯示根據本發明之記憶晶胞之佈局507372 Schematic illustration of the diagram Schematic description of the diagram: The above-mentioned content and many advantages of this invention can be easily understood through the following detailed description combined with the attached drawings, where: Figure 1 is a cross-sectional view of a semiconductor wafer, showing the basis for Steps of forming a source and a drain, an electro-oxidation layer, and a nitride layer in a semiconductor substrate according to the present invention. FIG. 2 is a cross-sectional view of a semiconductor wafer, showing the steps of forming trenches in a semiconductor substrate according to the present invention. FIG. 3 is a cross-sectional view of a semiconductor wafer, showing a step of forming trench isolation according to the present invention. FIG. 4 is a cross-sectional view of a semiconductor wafer, showing a step of removing a nitride layer according to the present invention. Fig. 5 is a cross-sectional view of a semiconductor wafer showing the steps of forming polycrystalline fragments according to the present invention. FIG. 6 is a cross-sectional view of a semiconductor wafer, showing a step of forming a dielectric layer according to the present invention. FIG. 7 is a cross-sectional view of a semiconductor wafer, showing a step of forming a control gate according to the present invention. FIG. 8 is a layout showing a memory cell according to the present invention (1 ay out FIG. 9 is a layout showing a memory cell according to the present invention

第14頁 507372 圖式簡單說明 符號對照表 底材2 主動區域4 源極/汲極區域6 介電層8、18 氧化層8 罩幕層10 氮化秒層1 0 溝渠12 絕緣層1 4 填充物質1 6 氧化層1 6 摻雜多晶矽層20、24 上表面21 内層多晶矽介電層22 第二導電層24Page 14 507372 Illustration of simple symbol comparison table Substrate 2 Active area 4 Source / drain area 6 Dielectric layer 8, 18 Oxide layer 8 Mask layer 10 Nitride second layer 1 0 Trench 12 Insulating layer 1 4 Fill Substance 1 6 Oxide layer 16 Doped polycrystalline silicon layer 20, 24 Upper surface 21 Inner polycrystalline silicon dielectric layer 22 Second conductive layer 24

第15頁Page 15

Claims (1)

川7372 六、申請專利範圍 申請專利範圍： 1 · 一種在半導體底材上製造非揮發性記憶體之方 法，包括以下步驟： 形成摻雜區域於該半導體底材之内； 开3成一塾氧化層於該半導體底材之上； 形成一罩幕層在該墊氧化層之上； 圖案化該罩幕層、該墊氧化層與該半導體底材，以 在其 中形成一溝渠； 形成一填充物質於該溝渠之内，使該填充物質覆蓋 於該 半導體底材之上； 去除一部分該填充物質，直到該罩幕層上表面暴露 出來； 去除該罩幕層； 形成一第一導電層於底材之表面； 去除一部分該第一導電層，以暴露出該填充物質上 表面； 形成一介電層於該第一導電層之上；以及 形成一第二導電層於該介電層之上。 2·如申請專利範圍第1項之半導體底材上製造非揮發 性記憶體方法，其中上述罩幕層包含氮化物。 第16頁 507372 六、申請專利範圍 3. 如申請專利範圍第2項之半導體底材上製造非揮發 性記憶體方法，其中上述罩幕層由熱磷酸溶液去 除。 4. 如申請專利範圍第1項之半導體底材上製造非揮發 性記憶體方法，其中上述介電層包含氧化梦。 5. 如申請專利範圍第1項之半導體底材上製造非揮發 性記憶體方法，其中上述介電層包含氧化物/氮化物 /氧化物。 礞I 6. 如申請專利範圍第1項之半導體底材上製造非揮發 性記 憶體方法，其中上述介電層包含氧化物/氮化物。 7. 如申請專利範圍第1項之半導體底材上製造非揮發 性記 憶體方法，其中上述第一導電層包含多晶矽。 8. 如申請專利範圍第1項之半導體底材上製造非揮發 性記 憶體方法，其中上述第二導電層包含多晶矽。Chuan 7372 6. Scope of patent application Patent application scope: 1 · A method for manufacturing non-volatile memory on a semiconductor substrate, including the following steps: forming a doped region in the semiconductor substrate; opening a 30% oxide layer On the semiconductor substrate; forming a mask layer on the pad oxide layer; patterning the mask layer, the pad oxide layer and the semiconductor substrate to form a trench therein; forming a filling material on Within the trench, the filling material is covered on the semiconductor substrate; a part of the filling material is removed until the upper surface of the mask layer is exposed; the mask layer is removed; a first conductive layer is formed on the substrate A surface; removing a portion of the first conductive layer to expose the upper surface of the filling substance; forming a dielectric layer on the first conductive layer; and forming a second conductive layer on the dielectric layer. 2. The method for manufacturing a non-volatile memory on a semiconductor substrate according to item 1 of the application, wherein the mask layer includes a nitride. Page 16 507372 6. Scope of patent application 3. For the method of manufacturing non-volatile memory on the semiconductor substrate of the scope of patent application item 2, the above mask layer is removed by a hot phosphoric acid solution. 4. The method for manufacturing non-volatile memory on a semiconductor substrate according to item 1 of the patent application, wherein the dielectric layer includes an oxide dream. 5. The method for manufacturing a non-volatile memory on a semiconductor substrate according to item 1 of the application, wherein the dielectric layer includes an oxide / nitride / oxide.礞 I 6. The method for manufacturing a non-volatile memory on a semiconductor substrate according to item 1 of the patent application scope, wherein the dielectric layer includes an oxide / nitride. 7. The method for manufacturing a non-volatile memory on a semiconductor substrate according to item 1 of the application, wherein the first conductive layer includes polycrystalline silicon. 8. The method for manufacturing a non-volatile memory on a semiconductor substrate according to item 1 of the application, wherein the second conductive layer includes polycrystalline silicon. 第17頁 507372 六、申請專利範圍 9·如申請專利範圍第1項之半導體底材上製造非揮發 性記 憶體方法，其中上述填充物質是由化學機械研磨來 去除。 10. 如申請專利範圍第1項之半導體底材上製造非揮 發性記 憶體方法，其中上述第一多晶矽層是由化學機械研 磨來 去除。 11. 一種在半導體底材上製造非揮發性記憶體疊閘之 方 法，包括以下步驟： 形成摻雜區域於該半導體底材之内； 形成一墊氧化層於該半導體底材之上； 形成一罩幕層在該墊氧化層之上； 圖案化該罩幕層、該墊氧化層與該半導體底材，以 在其 中形成一溝渠； 形成一填充物質於該溝渠之内，使該填充物質覆蓋 於該 半導體底材之上； 去除一部分該填充物質，直到該罩幕層上表面暴露Page 17 507372 VI. Scope of patent application 9. The method for manufacturing non-volatile memory on the semiconductor substrate of the first scope of patent application, wherein the above-mentioned filling substance is removed by chemical mechanical grinding. 10. For example, the method for manufacturing a non-volatile memory on a semiconductor substrate according to item 1 of the application, wherein the first polycrystalline silicon layer is removed by chemical mechanical grinding. 11. A method for manufacturing a non-volatile memory stack gate on a semiconductor substrate, comprising the following steps: forming a doped region in the semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a The mask layer is on the pad oxide layer; the mask layer, the pad oxide layer and the semiconductor substrate are patterned to form a trench therein; a filling substance is formed in the trench to cover the filling substance On the semiconductor substrate; removing a portion of the filling material until the upper surface of the mask layer is exposed 六、申請專利範圍 出來； 去除該罩幕層； 形成一第一導電層於底材之表面；以及 去除一部分該第一導電層，以暴露出該填充物質上 表面。 12·如申請專利範圍第η項之半導體底材上製造非揮 發性 記憶體疊閘方法，其中上述罩幕層包含氮化物。 13·如申請專利範圍第12項之半導體底材上製造非揮 發性 記憶體疊閘方法，其中上述罩幕層由熱磷酸溶液去 除。 14·如申請專利範圍第η項之半導體底材上製造非揮 發性 記憶體疊閘方法，其中上述填充物質是由化學機械 研 磨來去除。 15.如申請專利範圍第η項之半導體底材上製造非揮 發性 記憶體疊閘方法，其中上述第一多晶矽層是由化學6. The scope of the patent application comes out; removing the cover layer; forming a first conductive layer on the surface of the substrate; and removing a part of the first conductive layer to expose the upper surface of the filling material. 12. The method for manufacturing a non-volatile memory stack gate on a semiconductor substrate according to item η of the patent application scope, wherein the mask layer includes nitride. 13. The method of manufacturing a non-volatile memory stack on a semiconductor substrate as claimed in claim 12 in which the above-mentioned mask layer is removed by a hot phosphoric acid solution. 14. A method for manufacturing a non-volatile memory stack gate on a semiconductor substrate according to item η of the patent application, wherein the above-mentioned filling substance is removed by chemical mechanical grinding. 15. A method for manufacturing a non-volatile memory stack gate on a semiconductor substrate according to item η of the patent application, wherein the first polycrystalline silicon layer is made of chemical 第19頁 507372 六、申請專利範圍 機 械研磨來去除。 1 6. —種記憶體佈局，包含一記憶體陣列具有列、行 結構，上述行結構形成於基板中以溝渠填充物隔 離，其中上述行結構係為源極/汲極，並且由浮置閘 極所分離；由膜層形成之字元線（word line: WL )，係構成上述之列結構用來當作控制閘極，該膜 層係為圖案化的導電層構成記憶體陣列之控制閘極 與字元線，元件的源極/汲極則構成了該記憶體陣列 之位元線（bit line: BL)。Page 19 507372 VI. Scope of patent application Mechanical grinding to remove. 16. A memory layout comprising a memory array having a column and row structure. The row structure is formed in a substrate and separated by a trench filler. The row structure is a source / drain and is floating gated. The electrode lines are separated; the word line: WL formed by the film layer is used as the control gate to form the above-mentioned structure, and the film layer is a patterned conductive layer to form the control gate of the memory array. Poles and word lines, and the source / drain of the components constitute the bit line (BL) of the memory array. 第20頁Page 20