525226 A7 B7 五、發明説明（1 ) 發明領域 本發明係關於一種半導體元件之微影法，特別是關於一 種深次微米半導體元件之電子束微影法。 發明背景 微影（Lithography)製程於半導體之發展扮演著一舉足輕 重的角色，其直接關係到後續蝕刻製程之品質好壞，且影 響每一世代之演進。從之前使用4 3 6 0埃波長的G -1 i n e光 阻、波長為3 6 5 0埃的I -1 i n e光阻到目前0 · 2 5微米製程中 使用波長為2 4 8 0埃及0 . 1 8微米製程中使用波長為1 9 3 0埃 之深紫外線（deep UV)光阻，即可看出每個世代所使用光阻 之演變。越小線寬的半導體元件需要使用越小波長的光 源，以符合其高解析度需求。 以目前最常採用的以傳統光學技術產生曝光光源之投影 式（Projection)微影技術，其中牵涉到其最終光阻成型之主 要因素可概括整理為兩項，即最小特徵尺寸（resolution)及 聚焦深度（Depth OF Focus ; DOF)，其可分別以下列公式表 示，最小特徵尺寸等於ATI」-，= Κ2—^—τ·。其中尺7及 ΝΑ (ΝΑ)2 為與該光阻有關的常數，；ι為該曝光光源之波長，而 則為曝光機鏡片系統的數值孔隙（Numerical Aperture ; ΝΑ)的 大小。由上述之公式可知，A越小則最小特徵尺寸越小， 即有較高的解析度，可應用於較小尺寸的圖案，此由半導 體世代微影技術使用波長之演進可充分印證。但此時仍必 須考慮由光繞射所導致的近距效應（proximity effect)，而使 得圖案失真。相對地，A越小將造成其D 0 F較小，而造成 H:\Hu\tys\NDL 中說\76013\760丨3修正_l.doc ~ 4 ~ 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 525226 A7 B7 五、發明説明（2 ) 光阻曝光時之困難。一般為了滿足在深次微米世代蝕刻的 高深寬比（High Aspect Ratio ; HAR)的需求，光阻厚度有時必 須大於一微米，以防止蝕刻時因光阻選擇比不足所產生的 問題。此外，再加上於動態隨機存取記憶體（DRAM)及快 閃記憶體（flash memory)常會遇到的高低差（topography)現 象，使得對該D 0 F的要求更為嚴苛。因此解析度與D 0 F之 相互牽制（trade off)，已成為目前微影製程發展的一大瓶 頸，且深遠地影響到整個半導體的製程整合（process integration) 〇 基於晶圓產能（throughput)之考量，化學增幅型光阻 (chemical amplified resist)由於其中包含的光酸可產生化學連 鎖反應，所以可減少曝光所需之劑量（dose)，進而可有效 縮短曝光所需的時間，因此在2 4 8奈米以下之製程已被廣 泛採用，尤其適合應用於以X光或電子束（electron beam)進 行微影的製程。但目前廣泛應用於半導體業界的化學增幅 型的深紫外線光阻由於D 0 F的限制，並不適用於1 0 0奈米 以下之製程，除非搭配提高解析度的技術，如相位移光罩 (Phase Shift Mask ; PSM)、光學近距修正（Optical Proximity Correction ; OPC)和偏軸照明（Off Axis Illumination ; OAI)技 術，再加上嚴格的製程控制才能達成。 J. Η. Chung，S.J. Choi，Υ. Kan, S. G. Woo and J. Τ· Moon發表 之 ’’A novel resist material for sub· lOOnm contact hole pattern”， Proc· SPIE 3999，第 3 0 5 頁，揭露一熱流（thermal flow)法，用 以形成臨界尺寸（Critical Dimension ; C.D·)小於1 0 0奈米之接 H:\Hu\tys\NDL 中說\76013\76013修正_l.doc 一 5 一 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 525226 A7 __B7 五、發明説明（3 ) 觸洞（contact hole)圖案，以克服上述的化學增幅型光阻所遭 遇的圖案尺寸不易縮小的瓶頸。但此一技術先前僅有在深 紫外線微影術曹被提及’本發明則進一步將此一技術應用 至電子束微影技術’使取小線寬甚至可以小於5 〇奈米。 發明之簡要說明 本發明的目的係提供一微影法，用以適用臨界尺寸小於 1 0 0奈米之圖案’以克服目前深紫外線曝光技術遭遇的瓶 頸。其係利用電子束進行曝光，後續再加上一熱流步驟， 使光阻再流動（reflow)，進而達到縮小臨界尺寸的目的。 由於電子束並不是採用傳統微影技術的光學原理，而是 利用一電子槍產生電子束，再經由偏角線圈（alignment coil)、聚光透鏡（condensed len)等裝置將電子束聚焦至直徑 0.0 1至0 . 1微米。電子束微影的優點為可於光阻上製作微 米及次微米尺寸大小的幾何圖形，並可高度自動化與精確 地控制操作，其DOF較深紫外線曝光為大，且可不經過光 罩直接於半導體晶圓上對光阻進行曝光，但由於其產能偏 低，一般必須配合化學增幅型光阻使用。 本發明之較佳實施例之半導體元件之電子束微影法，包 含下列步驟·（ 1 )覆蓋一光阻層於一基板；（2 )加熱該光阻 層’以去除該光阻層中之溶劑；（3)以電子束對該光阻層 進行曝光；（4 )對該光阻層進行顯影，形成所需之圖案； 以及（5 )加熱該光阻層，使該光阻層流動，藉此縮小該圖 案之臨界尺寸。 本發明可藉由控制光阻經旋塗（spin on)後之覆蓋後烘烤 H:\Hu\tys\NDL 中說\76013\76013修正J d〇c 一 g — 本紙張尺錢财關视格(21GX297公釐i 525226525226 A7 B7 V. Description of the Invention (1) Field of the Invention The present invention relates to a lithography method for a semiconductor device, and more particularly to an electron beam lithography method for a deep submicron semiconductor device. BACKGROUND OF THE INVENTION Lithography plays a pivotal role in the development of semiconductors. It directly affects the quality of subsequent etching processes and affects the evolution of each generation. From the previous G-1ine photoresist with a wavelength of 4 3 60 angstroms and the I -1 ine photoresist with a wavelength of 3 650 angstroms to the current wavelength of 2 4 8 0 Egypt 0 in the 0.5 μm process. In the 18-micron process, a deep UV photoresist with a wavelength of 1930 angstroms is used, and the evolution of the photoresist used in each generation can be seen. Semiconductor devices with smaller line widths require smaller wavelength light sources to meet their high-resolution requirements. Projection lithography, which is the most commonly used conventional light technology to generate exposure light sources, can be summarized into two main factors that involve its final photoresist molding, namely the minimum feature size (resolution) and focus. Depth of focus (DOF), which can be respectively expressed by the following formula, the minimum feature size is equal to ATI "-, = Κ2 — ^ — τ ·. Among them, ruler 7 and ΝΑ (ΝΑ) 2 are constants related to the photoresist, ι is the wavelength of the exposure light source, and is the size of the numerical aperture (NAA) of the lens system of the exposure machine. It can be known from the above formula that the smaller the A, the smaller the minimum feature size, that is, a higher resolution, which can be applied to a pattern of a smaller size. This can be fully confirmed by the evolution of the wavelength used by the semiconductor lithography technology. However, at this time, it is still necessary to consider the proximity effect caused by the light diffraction, so that the pattern is distorted. In contrast, the smaller A will cause its D 0 F to be smaller, which will cause H: \ Hu \ tys \ NDL to say \ 76013 \ 760 丨 3 amendment_l.doc ~ 4 ~ This paper standard applies to the Chinese National Standard (CNS ) A4 size (210 X 297 mm) 525226 A7 B7 5. Description of the invention (2) Difficulties in photoresist exposure. Generally, in order to meet the needs of high aspect ratio (HAR) etching in deep sub-micron generations, the thickness of the photoresist must sometimes be greater than one micron to prevent problems caused by insufficient photoresist selection ratio during etching. In addition, coupled with the phenomenon of topography often encountered in dynamic random access memory (DRAM) and flash memory, the requirements for D 0 F are more stringent. Therefore, the trade-off between resolution and D 0 F has become a major bottleneck in the current development of lithographic processes, and has profoundly affected the process integration of the entire semiconductor. Based on the throughput of wafers, In consideration, the chemically amplified photoresist (chemical amplified resist) contains a photo-acid which can produce a chemical chain reaction, so the dose required for exposure can be reduced, and the time required for exposure can be effectively reduced. Processes below 8 nanometers have been widely used, and are particularly suitable for lithography processes using X-rays or electron beams. However, the chemically amplified deep ultraviolet photoresist, which is widely used in the semiconductor industry, is not suitable for processes below 100 nanometers due to the D 0 F limitation, unless it is equipped with a technology that improves resolution, such as a phase shift mask ( Phase Shift Mask (PSM), Optical Proximity Correction (OPC) and Off Axis Illumination (OAI) technologies, plus strict process control can be achieved. J. Η. Chung, SJ Choi, Υ. Kan, SG Woo and J. T. Moon, "A novel resist material for sub · 100nm contact hole pattern", Proc. SPIE 3999, p. A thermal flow method used to form a critical dimension (Critical Dimension; CD ·) of less than 100 nanometers. H: \ Hu \ tys \ NDL says \ 76013 \ 76013 amendment_l.doc 1 5 1 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 525226 A7 __B7 V. Description of the invention (3) Contact hole pattern to overcome the size of the pattern encountered by the above chemically amplified photoresist Reducing the bottleneck. However, this technology was previously mentioned only in deep ultraviolet lithography. “The present invention further applies this technology to the electron beam lithography technology” so that the small line width can be even smaller than 50 nm. Brief description of the invention The object of the present invention is to provide a lithography method for applying a pattern having a critical size of less than 100 nanometers to overcome the bottleneck encountered by the current deep ultraviolet exposure technology. It uses electron beam for exposure, and subsequent Plus a heat The flow step reflows the photoresist to reduce the critical size. Because the electron beam does not use the optical principle of traditional lithography technology, it uses an electron gun to generate the electron beam and passes the deflection coil (alignment). coil), condenser lens (condensed len) and other devices focus the electron beam to a diameter of 0.01 to 0.1 micron. The advantage of electron beam lithography is that micron and submicron size geometric figures can be made on the photoresist, and Can be highly automated and precise control operation, its DOF is larger than the deep UV exposure, and it can directly expose the photoresist on the semiconductor wafer without going through the mask. However, because of its low production capacity, it is generally necessary to cooperate with chemically amplified photoresist The electron beam lithography method for a semiconductor device according to a preferred embodiment of the present invention includes the following steps: (1) covering a photoresist layer on a substrate; (2) heating the photoresist layer 'to remove the photoresist layer (3) exposing the photoresist layer with an electron beam; (4) developing the photoresist layer to form a desired pattern; and (5) heating the photoresist layer so that the The photoresist layer flows, thereby reducing the critical size of the pattern. The present invention can control the photoresist by spin-on coating and bake after H: \ Hu \ tys \ NDL said \ 76013 \ 76013 correction J d〇c 1g — this paper rule money and wealth grid (21GX297mm i 525226
(Post Apphed Bake ; PAB)或稱為軟烤（S0ft bake)及其後續所進 行的硬烤（hard bake)之製程變數，如溫度和加熱時間，以取 得一最佳製程條件，進而得到適當的光阻熱流製程窗口 (process window)以及圖案的臨界尺寸之縮小比例。 ϋ之簡單說明 本發明將依後附圖式進行說明·· 圖1(a)至圖l(e)係本發明之半導體元件之電子束微影法 之製作流程； 圖2係深紫外線光阻及電子束光阻之敏感性曲線圖； 圖3係在不同的ΡΑΒ溫度條件下，光阻熱流溫度和圖案 的臨界尺寸的關係曲線圖；以及 圖4係光阻熱流時間及圖案的臨界尺寸的關係曲線圖。 立件符號說明 12基板 1 6區域 20電子束 10半導體元件 14光阻 1 8開口 較佳實施例說明 圖1(a)至圖l(e)顯示本發明之半導體元件之電子束微影 法之製作流程。參照圖1(昀，一半導體元件1〇包含一基2 12及覆蓋於該基板12表面之一光阻層“，接著進存PAR 以去除該光阻層14中之溶劑，並以一電子束針對該光阻層 14進行曝光，而於該光阻層14中形成一經曝光之區域 !6,如圖1(b)及圖1(c)所示。參照圖i(d)，該光阻層η 經顯影（development)將該區域16移除，而形成_開口 η。 H:\Hu\tys\NDL 中說\76013\76013修正_J.doc - η(Post Apphed Bake; PAB) or so-called bake (S0ft bake) and its subsequent hard bake process variables, such as temperature and heating time, to obtain an optimal process conditions, and then get the appropriate The reduction ratio of the photoresistive heat flow process window and the critical dimension of the pattern. Brief description of the present invention The present invention will be described in accordance with the following drawings. Figure 1 (a) to Figure 1 (e) are the manufacturing process of the electron beam lithography method of the semiconductor device of the present invention; Figure 2 is a deep ultraviolet photoresist And the sensitivity curve of the electron beam photoresist; Figure 3 is the relationship between the photoresist heat flow temperature and the critical size of the pattern under different PAB temperature conditions; and Figure 4 is the photoresist heat flow time and the critical size of the pattern Relationship graph. Description of Standing Symbols 12 Substrate 1 6 Area 20 Electron Beam 10 Semiconductor Element 14 Photoresistor 1 8 Opening Preferred Embodiment Description FIG. 1 (a) to FIG. 1 (e) show the fabrication of the electron beam lithography method of the semiconductor element of the present invention Process. Referring to FIG. 1 (ie, a semiconductor device 10 includes a substrate 2 12 and a photoresist layer covering the surface of the substrate 12 ”, and then a PAR is stored to remove the solvent in the photoresist layer 14 and an electron beam is used. The photoresist layer 14 is exposed, and an exposed area is formed in the photoresist layer 14 as shown in FIG. 1 (b) and FIG. 1 (c). Referring to FIG. I (d), the photoresist Layer η removes this area 16 through development, and forms _opening η. H: \ Hu \ tys \ NDL says \ 76013 \ 76013 modified_J.doc-η
本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 525226This paper size applies to China National Standard (CNS) Α4 specification (210 X 525226
最後於進行硬烤時，加熱使該光阻層14流動，而縮小該開 口 1 8，如圖1 ( e )所示。 圖2為深紫外線光阻及電子束光阻經4 0千電子伏特之加 速電壓的電子束曝光之敏感性曲線（sensitivity curve)。由圖 2可知，當電子束曝光的劑量大於約每平方公分6微庫侖 (SpC/cm2)時，不論是傳統的化學增幅型深紫外線光阻或是 電子束光阻均可達到曝開光阻所需之劑量。一般來說，化 學增幅型深紫外線光阻的成本遠低於電子束光阻，因此本 發明亦可應用於化學增幅型深紫外線光阻而有效地降低製 造成本。 奴而化學增幅型光阻之側壁形狀（pr〇file)明顯地 文到曝光後烘烤（post Exp〇sure Bake ; pEB)條件之影響，因 此本實施例的P E B條件固定於1 3 5 t烘烤9 0秒。 圖3顯示在不同的PAB溫度條件下，硬烤溫度（即光阻熱 流溫度）和圖案的臨界尺寸的關係。由圖3可知，較低的 P A B 度（1 2 〇 c )對該臨界尺寸較敏感，也就是說可以得 到較小的臨界尺寸，但當光阻熱流溫度大於丨6 2 t時，將 使得臨界尺寸急遽下降至零，即造成圖1(e)中的開口 18封 口，且其臨界尺寸於5 °C的範圍内即會產生急遽之變化， 因此將導致製程穩定度控制上的困難，即過小的製程窗 口。而當PAB於15(TC進行時，其臨界尺寸與光阻熱流溫 度的關係相對較穩定，但卻有臨界尺寸不易縮小的缺點。 因此必須選取適當的PAB溫度，例如本實施例所採用的 1 3 5 C ’以得到所需之臨界尺寸並配合較大的製程窗口。Finally, during the hard baking, the photoresist layer 14 is heated to flow, and the opening 18 is reduced, as shown in FIG. 1 (e). FIG. 2 is a sensitivity curve of a deep ultraviolet photoresist and an electron beam photoresist exposed to an electron beam at an acceleration voltage of 40 kV. It can be seen from FIG. 2 that when the electron beam exposure dose is greater than about 6 microcoulombs per square centimeter (SpC / cm2), whether it is a conventional chemically amplified deep ultraviolet photoresist or an electron beam photoresist, it can reach the exposure photoresistance. The required dose. In general, the cost of a chemically amplified deep ultraviolet photoresist is much lower than that of an electron beam photoresist. Therefore, the present invention can also be applied to a chemically amplified deep ultraviolet photoresist to effectively reduce the manufacturing cost. The shape of the sidewall of the photoresistive photoresist (pr0file) is obviously affected by the post exposure bake (peB) conditions. Therefore, the PEB conditions of this embodiment are fixed at 1 3 5 t bake. Bake for 90 seconds. Figure 3 shows the relationship between the hard baking temperature (ie, the photoresistance heat flow temperature) and the critical size of the pattern under different PAB temperature conditions. It can be seen from Fig. 3 that a lower PAB degree (1 2 0c) is more sensitive to the critical size, that is, a smaller critical size can be obtained, but when the photoresistance heat flow temperature is greater than 6 2 t, it will make the critical If the size drops sharply to zero, it will cause the opening 18 in Figure 1 (e) to be sealed, and its critical size will change sharply within the range of 5 ° C. Therefore, it will cause difficulties in the stability control of the process, that is, too small. Process window. When PAB is performed at 15 ° C, the relationship between the critical size and the photoresistive heat flow temperature is relatively stable, but it has the disadvantage that the critical size is not easy to shrink. Therefore, an appropriate PAB temperature must be selected, such as 1 used in this embodiment. 3 5 C 'to get the required critical size and fit a larger process window.
525226 A7 _— B7 五、發明説明（6 ) 圖4顯示光阻熱流時間（硬烤時間）及臨界尺寸的關係， 當光阻熱 >見時間增長，其臨界尺寸的下降曲線會逐漸趨 平’而且過長的光阻熱流時間（如超過1 2 0秒）將造成光阻 側壁形狀的劣化，因此光阻熱流時間有其上限。 本貝她例可經由6至2〇 μ C/cm2之電子束曝光、於丨2 5和 1 5 0 °C間加熱6 〇秒之p ab以及其後續於丨5 5至丨6 5它加熱 6 0秒的硬烤使光阻流動，可成功地將〇 · 2微米的接觸洞之 臨界尺寸縮小至8 0奈米甚至5 0奈米以下。 本發明不僅可應用於正光阻，而且亦可利用相同的原理 應用於負光阻。此外，本發明並不限定於接觸洞，舉凡形 成介層洞（via)、由多晶矽（polysilicon)所構成之字元線（w〇rd line)和金屬線（metal iine)等各種需使用光阻之半導體製程， 皆可藉由本發明而達到深次微米世代所需的臨界尺寸。 本發明之技術内容及技術特點巳揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修飾。因此，本發明之保護範圍 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 H:\Hu\tys\NDL 中說\76013\76013修正_J.doc — 9 本紙張尺度適财@ g家鮮(CNS) M規格(_ χ挪公董)525226 A7 _— B7 V. Explanation of the invention (6) Figure 4 shows the relationship between the photoresistance heat flow time (hard baking time) and the critical size. As the photoresistance heat increases, the decreasing curve of the critical size will gradually flatten. 'And too long the photoresist heat flow time (such as more than 120 seconds) will cause the shape of the photoresist sidewall to deteriorate, so the photoresist heat flow time has its upper limit. Benbeiter can be exposed by electron beam exposure at 6 to 20 μ C / cm 2, p ab heated at 25 ° and 150 ° C for 60 seconds, and subsequent heating at 5 5 to 6 5 The 60-second hard baking allows the photoresist to flow, and can successfully reduce the critical size of the contact hole of 0.2 micron to 80 nm or even 50 nm or less. The present invention can be applied not only to a positive photoresist, but also to a negative photoresist using the same principle. In addition, the present invention is not limited to contact holes. For example, a photoresist is used to form a via, a polyline (polysilicon) word line, a metal line, and a metal iine. All semiconductor processes can achieve the critical size required by the deep sub-micron generation by the present invention. The technical content and technical features of the present invention are disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention, and are covered by the following patent application scope. H: \ Hu \ tys \ NDL says \ 76013 \ 76013 correction_J.doc — 9 paper size suitable for financial @ g 家 鲜 (CNS) M specifications (_ χ Norwegian public director)