TW522539B - Multi-metal-layer interconnect structure and method for testing strength of intermetal dielectric layer - Google Patents
Multi-metal-layer interconnect structure and method for testing strength of intermetal dielectric layer Download PDFInfo
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522539522539
發明領域 本發明係關於半導 體中金屬層間介電層龜 構。 體結構，特別有關於一種預防半導 裂（crack)之多重金屬層内連線結 發明背景 % π Ϊ ί導體晶片中，M〇S電晶體結構中通常會沈積氧化 ^間電氧化物，作為絕緣層或保護層。而其中， 於至屬層間的介電材料，則為金屬層間介電氧化物層 nterMetal Dielectric oxide， IMD oxide)，主要用於 夕層金屬層間的間隙充填（g a p f丨1 1)及平坦化等。 而在主要電路區域形成多重金屬層内連線的同時，亦 ，上述週邊的接合墊（b〇nding pad)區域形成大面積的 夕重金屬層構造。此形成於最外側之多層金屬層，主要用 於打線機（bonder)以金屬線將該金屬層連接於導架（lead f rame )之相對應的導腳。因此，最外側 號、接地信號、或輸入/輸出信號等外接信號。 接著參見第la與lb圖，說明一般接合墊區域之多重金 屬層内連線結構。第la圖中，在具有若干半導體元件（未 顯示）所構成之電路矽基底10上，形成12A、12B、12C、 12D與12T的金屬層，而其中12T則是為作為接合墊之頂層 金屬（top metal)，12 A〜12D之金屬層間，分別以層間介 電層IMD 10A〜10D隔絕，並藉由矩陣式排列的金屬插塞14 (metal plug)導通金屬層’形成五層金屬層、四層插塞的FIELD OF THE INVENTION The present invention relates to a metal interlayer dielectric layer structure in a semiconductor. Background of the Invention In particular, a multi-metal layer interconnection for preventing semiconductor cracking is a background of the invention.% Π Ϊ In a conductor wafer, an oxide intermetallic oxide is usually deposited in a MOS transistor structure as Insulation or protective layer. Among them, the dielectric material between the sub-layers is a metal interlayer dielectric oxide layer (nterMetal Dielectric oxide, IMD oxide), which is mainly used for gap filling (g a p f 1 11) and planarization of the metal layers. While the multiple metal layer interconnects are formed in the main circuit area, a large area heavy metal layer structure is also formed in the above-mentioned peripheral bonding pad area. The multilayer metal layer formed on the outermost side is mainly used for a bonder to connect the metal layer to a corresponding guide leg of a lead frame using a metal wire. Therefore, external signals such as outermost signals, ground signals, or input / output signals. Next, referring to Figures 1a and 1b, the multiple metal layer interconnection structure in the general bonding pad area will be described. In FIG. 1a, a metal layer 12A, 12B, 12C, 12D, and 12T is formed on a circuit silicon substrate 10 having a plurality of semiconductor elements (not shown), and 12T is a top metal serving as a bonding pad ( top metal), between the metal layers of 12 A to 12D, are separated by interlayer dielectric layers IMD 10A to 10D, and the metal layers are formed by metal plugs 14 arranged in a matrix to form five metal layers, four Layer plug
0503-6862TWF ； TSMC2001-0671 ； peggy.ptd0503-6862TWF; TSMC2001-0671; peggy.ptd
522539522539
結構。其中金屬插塞群1 4通常由藉 層之間的介電層中之介層洞(vlah:le= = = 是使上下金屬層’以及與下方基底10中的電路未主要目的 連通形成電性連接。參見第丨13圖，其中u愈 未4不） 組五層式金屬插塞陣列，而兩组全屬 ^ ^別代表兩 間介電層區域16，往往無法支撐兩組間的應 、:： 生第la圖中的裂縫16。 # π i 然而，這種金屬層間介電氧化物層（1〇 〇xide)的破 裂或裂縫（crack)會造成半導體晶片的可靠度 (reliability)下降。在電子產品運作時，=片執行所產 生的面溫容易使裂縫因冷縮熱脹而增大，進而影塑到晶片 本身的穩定性。由於晶片的裂縫可能造成電性上的不穩定 ，連帶使電子產品的功能不正常甚至損壞。因此在丨c晶片 的生產中，金屬層間介電氧化物層裂縫所形成的潛在風險 ，都是半導體製造中所力求避免的目標。 為了解決I MD裂縫，一種常見的方式是改變丨MD材料， 例如將以高密度電漿化學氣相沉積（Higtl Density Plasma Chemical Vapor Deposition，HDPCVD)取代半大氣壓化學 氣相沈積（semi-atmospheric pressure chemical vapor deposition, SACVD)，以生成更緻密（compressive)的 IMD 層。然而光是改變I M D層材料的部分性質，並無法完全解 決I M D裂縫的問題。以〇 · 2 5微米製程為例，I M D裂縫常常發 生。在以上述方式改變材料之後，I MD裂縫仍然發生。而 IMD裂縫發生的位置與金屬插塞陣列（met a 1 via array)的structure. Among them, the metal plug group 1 4 is generally formed by the vias in the dielectric layer between the borrow layers (vlah: le = = = is to make the upper and lower metal layers' and to communicate with the circuit in the underlying substrate 10 without the main purpose to form electrical properties. See Figure 丨 13, where u is not 4) A five-layer metal plug array, and the two groups are all ^ ^ stands for the two dielectric layer regions 16, often unable to support the two, ::: The crack 16 in the la figure is generated. # π i However, the cracking or cracking of the metal interlayer dielectric oxide layer (100xide) causes the reliability of the semiconductor wafer to decrease. During the operation of electronic products, the surface temperature generated by the chip implementation can easily cause cracks to expand due to cold shrinkage and thermal expansion, and then affect the stability of the chip itself. Because the cracks in the chip may cause electrical instability, the electronic products may malfunction or even be damaged. Therefore, in the production of c wafers, the potential risk of crack formation in the interlayer dielectric oxide layer is a goal that is sought to be avoided in semiconductor manufacturing. In order to solve the I MD cracks, a common way is to change the MD material. For example, high density plasma chemical vapor deposition (Higtl Density Plasma Chemical Vapor Deposition (HDPCVD)) will be used instead of semi-atmospheric pressure chemical vapor deposition. vapor deposition (SACVD) to produce a more compact IMD layer. However, simply changing some properties of the material of the I M D layer cannot completely solve the problem of the I M D crack. Taking the 0.25 micron process as an example, I M D cracks often occur. After changing the material in the manner described above, I MD cracks still occur. The location of IMD cracks is similar to that of the metal plug array (met a 1 via array).
0503-6862TWF ; TSMC2001-0671 ; peggy.ptd 第 6 頁 522539 五、發明說明（3) 佈局設計有關，某些形式的接觸窗陣列的佈局發生I Μ裂縫 的機率普遍偏高。 發明簡述 為了避免上述金屬層間介電層間出現裂縫，本發明的 一個目的在於提供一種可以評估兩組比鄰之金屬雙鑲嵌結 構間，其金屬層間介電層強度的方法，可以評估所選擇使 用的金屬層間介電材料的強度。 本發明的再一個目的在於提供一種多重金屬層内連線 結構，可以利用兩組比鄰之金屬雙鑲嵌結構之金屬層互相 間隔之設計，以避免金屬層間介電層的裂缝產生。 本發明的另一個目的在於多重金屬層内連線結構，在 於讓兩組比鄰之金屬雙鑲嵌結構保持一大於或等於3微米 的距離，以避免金屬層間介電層的裂缝產生。 根據本發明之一種測試金屬層間介電層強度的方法， 適用至少兩組金屬雙鑲嵌結構之間，乃先於一半導體基底 上形成相同線寬之第一與一第二金屬線層，其中第一金屬 線層大體平行於第二金屬線層。而在第一與第二金屬線層 上分別定義相同面積之方形第一區域與第二區域，而方形 之邊長約等於金屬線之線寬，而第一與第二區域以對角線 方式排列。接著沈積一介電層於第一與第二金屬線層上， 並於第一與第二區域之介電層上分別形成n xm個第一與第 二插塞，分別與第一與第二金屬線層形成電性連接，m與η 為自然數，而第一與第二插塞分別以等距離方式，由第一 與第二區域之相鄰之一邊排列為η X m之矩陣。接著在該介0503-6862TWF; TSMC2001-0671; peggy.ptd page 6 522539 V. Description of the invention (3) Layout design is related to the possibility of I M cracks in some forms of contact window array layout. Brief description of the invention In order to avoid the occurrence of cracks between the above-mentioned metal interlayer dielectric layers, an object of the present invention is to provide a method for evaluating the strength of the metal interlayer dielectric layer between two sets of adjacent metal dual damascene structures. The strength of the interlayer dielectric material. It is still another object of the present invention to provide a multi-metal layer interconnect structure, which can use two adjacent metal double-mosaic structures to design the metal layers spaced apart from each other to avoid cracks in the dielectric layer between the metal layers. Another object of the present invention is a multiple metal layer interconnect structure, in order to maintain a distance of 3 micrometers or more between two sets of adjacent metal dual damascene structures, so as to avoid cracks in the dielectric layer between the metal layers. According to a method for testing the strength of a metal interlayer dielectric layer according to the present invention, it is applicable to at least two sets of metal dual damascene structures. First, a first and a second metal line layer having the same line width are formed on a semiconductor substrate. A metal wire layer is substantially parallel to the second metal wire layer. On the first and second metal line layers, a square first area and a second area of the same area are respectively defined, and the sides of the square are approximately equal to the line width of the metal line, and the first and second areas are diagonal. arrangement. Next, a dielectric layer is deposited on the first and second metal line layers, and n × m first and second plugs are formed on the dielectric layers of the first and second regions, respectively. The metal wire layer forms an electrical connection, m and η are natural numbers, and the first and second plugs are respectively arranged in a matrix of η X m in an equidistant manner from an adjacent edge of the first and second regions. Then in the introduction
0503-6862TWF ； TSMC2001-0671 ； peggy.ptd 第7頁 522539 五、發明說明（4) 電層上形成第三金屬線與第四金屬線，其中該第三與第四 金屬線分別正對於該第一與第二金屬線，以在該第一與第 二區域各形成一組金屬雙鑲嵌結構。最後檢視第一與第二 區域間之介電層是否有裂缝，當有裂縫產生時，表示該介 電層強度低於標準。 其中，本發明更可在第三與第四金屬線上，重複形成 金屬雙鑲嵌結構，以形成二重以上之多金屬層内連線結 構，並檢查其間的金屬層間介電層是否有裂缝產生。 為了避免金屬層間介電層間產生裂缝，本發明提出一 種多重金屬層内連線結構，設置於一具有電路之半導體基 底上，該結構包括：至少一介電層，沈積於該半導體基底 之上；一第一金屬線層與一第二金屬線層，分別鑲嵌於該 介電層中，其中該第一金屬線層以一距離d，平行於該第 二金屬線層；複數第一與第二插塞，分別設置於該介電層 中與該第一與第二金屬線層連接，與該半導體基底之電路 構成電性連接；以及一第三金屬線層與一第四金屬線層， 大體位於該第一與第二金屬線層上方，與該等第一與第二 插塞間分別形成金屬雙鑲嵌結構，其中，該第三金屬線層 相鄰於該第四金屬線層之一邊，大於下方該第一與第二金 屬線層間1 / 2 d之位置，而該第四金屬線層以該距離d，大 體平行於該第三金屬線層。 根據本發明，另一種避免金屬層間介電層間產生裂縫 的多重金屬層内連線結構，亦設置於一具有電路之半導體 基底上，包括：至少一介電層，沈積於該半導體基底之上0503-6862TWF; TSMC2001-0671; peggy.ptd page 7 522539 5. Description of the invention (4) A third metal line and a fourth metal line are formed on the electrical layer, wherein the third and fourth metal lines are respectively facing the first A first metal line and a second metal line to form a set of metal dual damascene structures in each of the first and second regions. Finally, check whether there is a crack in the dielectric layer between the first and second regions. When cracks occur, it means that the strength of the dielectric layer is lower than the standard. Among them, the present invention can also repeatedly form a metal dual damascene structure on the third and fourth metal lines to form a multi-metal layer interconnect structure with more than two layers, and check whether there is a crack in the metal interlayer dielectric layer therebetween. In order to avoid cracks between the dielectric layers between the metal layers, the present invention proposes a multiple metal layer interconnect structure, which is disposed on a semiconductor substrate having a circuit. The structure includes: at least one dielectric layer deposited on the semiconductor substrate; A first metal line layer and a second metal line layer are respectively embedded in the dielectric layer, wherein the first metal line layer is parallel to the second metal line layer at a distance d; a plurality of first and second A plug is respectively disposed in the dielectric layer and connected to the first and second metal line layers, and is electrically connected to the circuit of the semiconductor substrate; and a third metal line layer and a fourth metal line layer are generally A metal dual damascene structure is formed above the first and second metal line layers and between the first and second plugs, wherein the third metal line layer is adjacent to one side of the fourth metal line layer, It is larger than the position of 1/2 d between the first and second metal wire layers below, and the fourth metal wire layer is substantially parallel to the third metal wire layer with the distance d. According to the present invention, another multiple metal layer interconnect structure that avoids cracks between dielectric layers between metal layers is also provided on a semiconductor substrate having a circuit, including: at least one dielectric layer deposited on the semiconductor substrate
0503-6862TWF ； TSMC2001-0671 ； peggy.ptd 第8頁 522539 五、發明說明（5) •，一第一金屬線層與一第二金屬線層，分別鑲澈於該介電 層中，其中第一金屬線層以大於或等於3微米之距離，大 體平行於第二金屬線層；複數第一與第二插塞，設置於該 介電層中與第一與第二金屬線層連接，與半導體基底之電 路構成電性連接；以及一第三金屬線層與一第四金屬線層 ，大體位於第一與第二金屬線層上方，與該等第一與第二 插塞間形成分別形成兩組金屬雙鑲嵌結構，其中第三金屬 線層以大於或等於3微米之距離，大體平行於第四金屬線 層。 上述本發明之本發明避免金屬層間介電層間產生裂缝 的多重金屬層内連線結構，更可在第三與第四金屬線上， 重複形成金屬雙鑲嵌結構，以形成二重以上之多金屬層内 連線結構。 為了讓本發明之上述目的、特徵、及優點能更明顯易 懂，以下配合所附圖式，作詳細說明如下： 圖式簡單說明 第la與lb圖所示為習知之接合墊區域之多重金屬層内 連線結構。 第2圖所示為根據本發明之一實施例中的第一種多重 金屬層金屬插塞陣列設計之上視圖。 第3圖所示為根據本發明之一實施例中的第二種多重 金屬層金屬插塞陣列設計之上視圖。 第4圖所示為根據本發明之一實施例中的第三種多重 金屬層金屬插塞陣列設計之上視圖。0503-6862TWF; TSMC2001-0671; peggy.ptd page 8 522539 V. Description of the invention (5) • A first metal wire layer and a second metal wire layer are embedded in the dielectric layer, respectively. A metal wire layer is substantially parallel to the second metal wire layer at a distance greater than or equal to 3 microns; a plurality of first and second plugs are disposed in the dielectric layer and connected to the first and second metal wire layers, and The circuit of the semiconductor substrate constitutes an electrical connection; and a third metal line layer and a fourth metal line layer are generally located above the first and second metal line layers, and are formed separately from the first and second plugs. Two sets of metal dual damascene structures, in which the third metal wire layer is substantially parallel to the fourth metal wire layer at a distance greater than or equal to 3 microns. The multi-layer metal interconnect structure of the present invention, which avoids cracks between the dielectric layers between the metal layers, can also repeatedly form a metal dual damascene structure on the third and fourth metal lines to form a multi-metal layer with more than two layers. Interconnection structure. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following detailed description is given in conjunction with the accompanying drawings: The drawings briefly illustrate the multiple metals shown in the conventional bonding pad area in FIGS. 1a and 1b. In-layer wiring structure. FIG. 2 is a top view of a first multi-metal layer metal plug array design according to an embodiment of the present invention. Figure 3 shows a top view of a second multi-metal layer metal plug array design according to an embodiment of the present invention. Figure 4 shows a top view of a third multi-metal layer metal plug array design according to an embodiment of the present invention.
0503-6862TWF ； TSMC2001-0671 ； peggy.ptd 第9頁 522539 五、發明說明（6) 第5圖所示為根據本發明之一實施例中的第四種多重 金屬層設計之上視圖。 第6a與6b圖所示為根據本發明一實施例中之一種測試 金屬層間介電層強度的方法。 第7圖所示為根據本發明一實施例中之一種多重金屬 層内連線結構。 第8圖所示為根據本發明一實施例中之另一種多重金 屬層内連線結構。 符號說明 10〜包含電路之矽基底； 10A〜10D〜層間介電層； 12A 、 12B 、 12C 、 12D 與12T〜金屬層； 1 4〜並金屬插塞； 1 A與1 B〜五層式金屬插塞陣列； 1 6〜裂縫； 2A與2B〜金屬插塞區域； 2 1〜金屬插塞； 2 2〜金屬線層； 2 3〜迴避區域； 2 4〜金屬線層； 2 5〜迴避區域； X〜距離； 3A與3B〜金屬插塞區域； 3 1〜金屬插塞；0503-6862TWF; TSMC2001-0671; peggy.ptd page 9 522539 V. Description of the invention (6) Figure 5 shows an upper view of a fourth multiple metal layer design according to an embodiment of the present invention. Figures 6a and 6b show a method for testing the strength of a metal interlayer dielectric layer according to an embodiment of the present invention. FIG. 7 shows an interconnection structure of a multiple metal layer according to an embodiment of the present invention. FIG. 8 shows another interconnection structure of multiple metal layers according to an embodiment of the present invention. Explanation of symbols 10 ~ silicon substrate containing circuit; 10A ~ 10D ~ interlayer dielectric layer; 12A, 12B, 12C, 12D and 12T ~ metal layer; 1 4 ~ parallel metal plug; 1 A and 1 B ~ five-layer metal Plug array; 16 ~ crack; 2A and 2B ~ metal plug area; 2 1 ~ metal plug; 2 2 ~ metal wire layer; 2 3 ~ avoidance area; 2 4 ~ metal wire layer; 2 5 ~ avoidance area ; X ~ distance; 3A and 3B ~ metal plug area; 3 1 ~ metal plug;
0503-6862TWF ； TSMC2001-0671 ； peggy.ptd 第10頁 522539 五、發明說明（7) 3 2〜金屬線層； 3 4〜金屬線層； h〜兩金屬插塞間距離； 4A與4B〜金屬插塞區域； 4卜金屬插塞； 4 2〜金屬線層； 4 4〜金屬線層； Z〜長度； Y〜寬度； 5A與5B〜金屬插塞區域； 5 1〜金屬插塞； 5 2〜金屬線層； 5 4〜金屬線層； d〜兩金屬線層距離； 6A〜第一區域； 6B〜第二區域； 60〜半導體基底； 60A〜介電層； 6 1〜金屬插塞； 62A〜第一金屬線層； 62B〜第二金屬線層； 64A〜第三金屬線層； 64B〜第四金屬線層； I、I I與I I I〜金屬插塞區域；0503-6862TWF; TSMC2001-0671; peggy.ptd Page 10 522539 V. Description of the invention (7) 3 2 ~ metal wire layer; 3 4 ~ metal wire layer; h ~ distance between two metal plugs; 4A and 4B ~ metal Plug area; 4 metal plug; 4 2 ~ metal wire layer; 4 4 ~ metal wire layer; Z ~ length; Y ~ width; 5A and 5B ~ metal plug area; 5 1 ~ metal plug; 5 2 ~ Metal wire layer; 5 4 ~ metal wire layer; d ~ distance between two metal wire layers; 6A ~ first area; 6B ~ second area; 60 ~ semiconductor substrate; 60A ~ dielectric layer; 6 1 ~ metal plug; 62A ~ first metal line layer; 62B ~ second metal line layer; 64A ~ third metal line layer; 64B ~ fourth metal line layer; I, II and III ~ metal plug area;
0503-6862TWF ； TSMC2001-0671 ； peggy.ptd 第11頁 522539 五、發明說明（8) 7 A〜第一區域； 7B〜第二區域； 70〜半導體基底； 70A與70B〜介電層； 71A與71B〜金屬插塞； 72A〜第一金屬線層； 72B〜第二金屬線層； 74A〜第三金屬線層； 74B〜第四金屬線層； d〜第一與第二金屬線層間之距離； 8A〜第一區域； 8B〜第二區域； 80〜半導體基底； 80A與80B〜介電層； 81A與81B〜金屬插塞； 82A〜第一金屬線層； 82B〜第二金屬線層； 8 4 A〜第三金屬線層； 84B〜第四金屬線層。 實施例 為了改善金屬層間介電層所可能產生的裂縫，因此發 明人等設計四種多重金屬層内連線中的金屬插塞群的陣列 結構佈局，藉以分別測試不銅的金屬插塞陣列對於金屬層 間介電層強度的影響。0503-6862TWF; TSMC2001-0671; peggy.ptd Page 11 522539 V. Description of the invention (8) 7 A ~ first area; 7B ~ second area; 70 ~ semiconductor substrate; 70A and 70B ~ dielectric layer; 71A and 71B ~ metal plug; 72A ~ first metal wire layer; 72B ~ second metal wire layer; 74A ~ third metal wire layer; 74B ~ fourth metal wire layer; d ~ distance between first and second metal wire layer 8A ~ first area; 8B ~ second area; 80 ~ semiconductor substrate; 80A and 80B ~ dielectric layer; 81A and 81B ~ metal plug; 82A ~ first metal line layer; 82B ~ second metal line layer; 8 4 A to the third metal line layer; 84B to the fourth metal line layer. Example In order to improve the cracks that may occur in the interlayer dielectric layer, the inventors designed the array structure layout of the metal plug groups in the interconnections of the four types of multiple metal layers, so as to test the metal plug arrays that are not copper. The influence of interlayer dielectric layer strength.
0503-6862TWF ； TSMC2001-0671 ； peggy.ptd 第12頁 5225390503-6862TWF; TSMC2001-0671; peggy.ptd page 12 522539
芩見第2圖，說明第一種多重金屬層金屬插塞陣列μ 計2視圖。在一具有電路之半導體基底i，形成兩； 之至屬線層22與24，兩金屬線之線寬均為5〇微米，而 間相鄰G. 8微米。#著平坦覆蓋—介電層，做為隔離之用 。而在金屬線層2 2與2 4分別上選擇以對角線排列的兩 金屬插塞區域2Α與2Β，而在該區域中以方形矩陣方二 電層中形成等距排列之金屬插塞2丨。而在第一組設計；，丨 其特點在於在兩區域2A與2B相鄰的對角線角落，以言 X/2的方式在兩區域中各界定出一等腰三角形之迴避"區… 23與25。而在三角形區域23與25中，不設置任何全扞 21。其中，分別以X為1〇、20、35與5〇微米，形成不同之土 區域大小之迴避三角形。並可以此設計依序往上堆疊 不同層數的多重金屬層内連線結構。 設計二 翏見3圖，說明第二種多重金屬層金屬插塞陣列設計 之上視圖。在一具有電路之半導體基底上，形成兩平行之 金屬線層32與34，兩金屬線之線寬均為5〇微米，而兩^ 相鄰0 · 8微米。接著平坦覆蓋一介電層，做為隔離之A用。 而在金屬線層32與34分別上選擇以對角線排列的兩方形\ 域3 A與3 B，而在該區域中以方形矩陣方式在介電層中形2 專距排列之金屬插塞3 1。而在第二組設計中，其特點在於 控制金屬插塞3 1彼此之間距離h，分別為0 · 4、〇 . 7、〇 9、 1 · 2、1 · 5、1. 8、2 · 0與3 · 0微米，八種距離進行試驗。並芩 See FIG. 2 for a view of the first multi-metal layer metal plug array μ meter. In a semiconductor substrate i with a circuit, two are formed; the line layers 22 and 24 belong to each other, and the line widths of the two metal lines are both 50 μm, and adjacent G. 8 μm. # 着 平面 covering—dielectric layer for isolation. On the metal wire layers 22 and 24, two metal plug regions 2A and 2B arranged in a diagonal line are selected, respectively. In this region, the metal plugs 2 are arranged in an equidistant arrangement in a square matrix square electric layer.丨. In the first group of designs ;, which is characterized by the diagonal corners of 2A and 2B adjacent to the two regions, and an isosceles triangle avoidance region is defined in the two regions by X / 2. 23 and 25. In the triangular areas 23 and 25, no full defense 21 is set. Among them, X is 10, 20, 35, and 50 microns, respectively, to form avoidance triangles with different sizes of soil regions. And this design can sequentially stack up multiple metal layer interconnect structures with different layers. Design 2 (See Figure 3), which illustrates the top view of the second multi-metal layer metal plug array design. On a semiconductor substrate having a circuit, two parallel metal line layers 32 and 34 are formed, and the line widths of the two metal lines are both 50 μm, and two ^ adjacent to each other are 0.8 μm. Then, a dielectric layer is covered flatly for the purpose of isolation A. On the metal line layers 32 and 34, respectively, two squares arranged in a diagonal line are used. The domains 3 A and 3 B are arranged in the area in a square matrix in the dielectric layer. 3 1. In the second group of designs, it is characterized by controlling the distance h between the metal plugs 3 1 from each other, which are 0 · 4, 0.7, 〇9, 1 · 2, 1 · 5, 1.8, 2 · 0 and 3.0 micrometers were tested at eight distances. and
522539 五、發明說明（10) 可以此設計依序往上堆疊形成不同層數的多重金屬層内連 線結構。 苓見第4圖’說明第三種多重金屬層金屬插塞陣列設 計之上視圖。在一具有電路之半導體基底上，形成兩平行 之金屬線層42與44，兩金屬線之線寬均為5〇微米，而兩者 間相鄰0 · 8微米。接著平坦覆蓋一介電層，做為隔離之用 。而在金屬線層42與44分別上選擇以對角線排列的兩方形 區域4A與4B，而在該區域中以方形矩陣方式在介電層中形 成等距排列之金屬插塞2 1。而在第三組設計中，其特點在 於金屬插塞41並不完全塞滿4A與4B區域，而是由兩金屬線 層相鄰之一端啟异’在長為Z寬為γ的區域中，以間隔〇 4 微米的距離以矩陣方式設置金屬插塞41群，其中採取可 (Z，Y)(微米 / 微米）=(3〇/4〇)、（ 30 /50 )、（ 20 / 5 0 )、 (10/50)、（40/40 )、（ 3 0 / 3 0 )、（ 2 0 / 2 0 )與（10/10)等八組 區域以設置金屬插塞4 1。接著以此方式依序堆疊形成多重 金屬層内連線結構。 設計四 參見苐5圖’說明第四種多重金屬層金屬插塞陣列設 計之上視圖。在一具有電路之半導體基底上，形成兩平行 之金屬線層5 2與5 4，兩金屬線之線寬均為1 〇 〇微米，而兩 者間相鄰距離d。接著平坦覆蓋一介電層，做為隔離之用 。而在金屬線層52與54分別上選擇以對角線排列的兩方形 區域5A與5B，而在該區域中以方形矩陣方式在介電層中形522539 V. Description of the invention (10) This design can be stacked in order to form multiple metal layer interconnect structures with different layers. See Figure 4 'for a top view of a third multi-metal layer metal plug array design. On a semiconductor substrate having a circuit, two parallel metal line layers 42 and 44 are formed. The line widths of the two metal lines are both 50 μm, and the two are adjacent to each other by 0.8 μm. Then, a dielectric layer is covered flat for isolation. On the metal wire layers 42 and 44, two square regions 4A and 4B arranged diagonally are selected, and metal plugs 21 are formed in the dielectric layer at an equidistant arrangement in the dielectric layer in the form of a square matrix. In the third group of designs, the feature is that the metal plug 41 does not completely fill the 4A and 4B areas, but is different by the adjacent end of the two metal wire layers. In the area of length Z and width γ, 41 groups of metal plugs are arranged in a matrix manner at a distance of 0 μm, in which (Z, Y) (μm / μm) = (3〇 / 4〇), (30/50), (20/50) ), (10/50), (40/40), (3 0/3 0), (2 0/2 0) and (10/10) and other eight groups of areas to set the metal plug 41. Then, a multi-layer metal interconnect structure is sequentially stacked in this manner. Design 4 Refer to Figure 5 'for a top view of a fourth multi-metal layer metal plug array design. On a semiconductor substrate having a circuit, two parallel metal line layers 5 2 and 54 are formed, and the line widths of the two metal lines are 100 μm, and the two are adjacent to each other by a distance d. Then, a dielectric layer is covered flat for isolation. On the metal line layers 52 and 54 respectively, two square areas 5A and 5B arranged in a diagonal line are selected, and in this area, the dielectric layer is shaped in a square matrix manner.
0503-6862TWF ； TSMC2001-0671 ; 第14頁 522539 五、發明說明（11) 成等距排列之金屬插塞5 1。而在第四組設計中，其特點在 於兩金屬線層間的距離d設計為0 · 8、1. 0、1. 2、2、3、4 、5、6、8、1 0與1 5微米等多種距離，以瞭解拉寬兩金屬 線層間的距離，對於金屬層間介電層的影響。 接著參見第一表，說明已採用上述四種設計之九種不 同金屬層數與I MD層材料的架構。 第一^ 架 mm I II III IV V VI VII VIII IX V V V V V HKOT54PEIE〇e V V V V 多內 6厝念思届/5届念展 V V V V 4展余展届/3届念圈 V V V V V #: s ami-atmospheric pressure d^enical vapor dep〇siticn, wm ft: Hi^i Derei ty Plasm Chemical ^por Depoe iticnJ 高膜 *:plasma eriifljnced traeti^lorthosilicate，四乙肇®^ 分別將第一表中的上述九種結構，以四種設計進行製 造，並實際檢驗其完成成品的金屬層間介電層是否有裂缝 產生，而各種組合的成品結果分析參見第二表。0503-6862TWF; TSMC2001-0671; Page 14 522539 V. Description of the invention (11) Metal plugs 5 equidistantly arranged. In the fourth group of designs, the characteristic d is that the distance d between the two metal wire layers is designed to be 0 · 8, 1. 0, 1. 2, 2, 3, 4, 5, 6, 8, 10, and 15 microns. Wait for multiple distances to understand the effect of widening the distance between the two metal line layers on the dielectric layer between the metal layers. Next, referring to the first table, the structure of the nine different metal layer numbers and the I MD layer materials of the four designs mentioned above has been described. The first ^ frame mm I II III IV V VI VII VIII IX VVVVV HKOT54PEIE〇e VVVV Donne 6th chanting session / 5th session exhibition VVVV 4th exhibition exhibition session / 3rd session circle VVVVV #: s ami-atmospheric pressure d ^ enical vapor dep〇siticn, wm ft: Hi ^ i Derei ty Plasm Chemical ^ por Depoe iticnJ high film *: plasma eriifljnced traeti ^ lorthosilicate, tetraethyl Zhao® ^ The above nine structures in the first table are divided into Four designs are manufactured, and actual inspection is performed to see whether cracks occur in the interlayer dielectric layer of the finished product. For the analysis of the finished product results of various combinations, see the second table.
0503-6862TWF ； TSMC2001-0671 ； peggy.ptd 第15頁 5225390503-6862TWF; TSMC2001-0671; peggy.ptd page 15 522539
由 VIII、 塞的緩 構中， 屬結構 免金屬 於不同 而 由第二 成的介 離，則 所形成 善多層 在 分佈位 設計一之結果可以看出，層數少的架構 I X )可以藉由在相鄰的兩區域2 a與2 b '門的 I IV、 衝空間2 3與2 5，而避免裂縫的產生。然、％置無插 即使採用HDPCVD + PETEOS所形成的介電、屬而在多層結 中，仍須保留X值大於35微米的迴避區在6層金 層間介電層的裂縫，顯示增加迴避區域’〜才能避 IMD材料的改善仍有侷限之處。 _的範圍，對 ，主要拉寬金屬插塞彼此之間的距離， 表中3、、、°果可以看出，當採用HDPCVD + PETEOS所形 電，日守、則/、要金屬插塞間保持大於〇 · 7微米的距 可兀全避免金屬裂縫的產生。然而在sacvd + pete〇s 的Μ電層中，僅拉見金屬插塞間的距離，仍無法改 金屬層結構，如έ士；I：接ν也π τ 4 >二 再戈、、、口構V與VI，的介電質裂縫。 "又计一中，主要改變兩金屬線層上的金屬插塞群的 置，可以明顯看出，在六層結構I巾，當採用From the slow structure of VIII and plug, the metal structure is free from the difference of dissociation by the second component, and the result of the design of the good multi-layer at the distribution position can be seen that the structure with a small number of layers IX) can be obtained by In the two adjacent areas 2 a and 2 b ′, the gate I IV and the punching spaces 23 and 25 can avoid cracks. However, even if the dielectric layer formed by HDPCVD + PETEOS is used in the multi-layer junction, the avoidance area with an X value greater than 35 micrometers must be retained. The crack in the dielectric layer between the 6 gold layers shows an increase in the avoidance area. '~ To avoid the improvement of IMD materials, there are still limitations. The range of _, right, mainly widens the distance between the metal plugs. As shown in 3, 3, and ° in the table, when using HDPCVD + PETEOS to form electricity, the sun guard, rule, and / or metal plug Maintaining a distance greater than 0.7 microns can completely avoid the occurrence of metal cracks. However, in the M electrical layer of sacvd + pete〇s, only by seeing the distance between the metal plugs, the structure of the metal layer cannot be changed, such as 士士; I: then ν also π τ 4 > Erzago ,,, Dielectric cracks in the mouth structure V and VI. " In another plan, the position of the metal plug group on the two metal wire layers is mainly changed. It can be clearly seen that in the six-layer structure I towel, when using
522539 五、發明說明（13) HDPCVIHPETEOS所形成的介電層時，金屬線層的金屬插塞 分佈區域小於1 Ο X 1 0微米，而在五層金屬層的結構中，必 須小於20 X 20微米時，才能避免金屬層間介電層裂縫的產 生。而採用SACVD + PETEOS時，則多層結構¥盥¥1均益法避 免裂縫產生。而由設計三中可以看出，除了在低層數的多 重金屬層結構中，設計二中採用的區域大小改變的設計， 對於金屬層間介電層承受的應力要求最高，即使採用 HDPCVD + PETEOS所形成的介電層，仍然必須將金屬線層内 的金屬插塞群縮小在2 0 X 2 0微米，甚至1 〇 X 1 〇微米之内， 必須侷限在相當小的面積中，才能避免裂縫的產生。 而在設計四中，顯示除了低層數的結構不受影響外， 其他無論是HDPCVD + PETEOS或SACVD + PETEOS時，只要將兩 金屬線層間的距離拉大至3微米以上，則金屬層間介電層 均可以有效地避免裂縫的產生。 因此’根據上述實驗結果，發明人等根據設計三之精 神，提供一種測試金屬層間介電層強度的方法，並參見第 6 a與6 b圖加以說明方法流程。 參見第6a圖’在一半導體基底60上形成線寬5〇微米之 第一與第二金屬線層62A與62B，其中兩金屬線層大體互相 平行上。接著，在第一與第二金屬線層62A與62B上上分別 定義第一區域6A與第二區域6B，其中第一與第二區域6A與 6 B為方形’而其邊長即等於金屬線之線寬5 0微米，而第一 區域與該第二區域6A與6B以對角線方式排列。 仍參見第6a圖，接著在金屬線層62A與62B與基質60上522539 V. Description of the invention (13) In the dielectric layer formed by HDPCVIHPETEOS, the metal plug distribution area of the metal wire layer is less than 10 × 10 micron, and in the structure of the five metal layer, it must be less than 20 × 20 micron In order to avoid cracks in the dielectric layer between the metal layers. In the case of SACVD + PETEOS, the multi-layer structure ¥ 1, ¥ 1 is used to avoid cracks. As can be seen from Design 3, except for the low-layer multiple metal layer structure, the design of the area changed in Design 2 requires the highest stress on the interlayer dielectric layer, even if formed by HDPCVD + PETEOS. Dielectric layer, the metal plug group in the metal line layer must still be reduced to 20 × 20 microns, or even 10 × 10 microns, and must be confined to a relatively small area to avoid cracks. . In Design 4, it is shown that in addition to the structure with a low number of layers, no matter whether it is HDPCVD + PETEOS or SACVD + PETEOS, as long as the distance between the two metal wire layers is increased to more than 3 microns, the interlayer dielectric layer Both can effectively avoid the occurrence of cracks. Therefore, according to the above experimental results, the inventors and others provide a method for testing the strength of the interlayer dielectric layer according to the spirit of design three, and the method flow is described with reference to FIGS. 6a and 6b. Referring to Fig. 6a ', first and second metal line layers 62A and 62B with a line width of 50 micrometers are formed on a semiconductor substrate 60, wherein the two metal line layers are substantially parallel to each other. Next, a first region 6A and a second region 6B are defined on the first and second metal line layers 62A and 62B, respectively, where the first and second regions 6A and 6B are square and their side lengths are equal to the metal lines. The line width is 50 micrometers, and the first area and the second area 6A and 6B are arranged diagonally. Still referring to Figure 6a, then on the metal wire layers 62A and 62B and the substrate 60
0503-6862TWF ; TSMC2001-0671 ; peggy.ptd 第 17 頁 522539 五、發明說明（14) 沈積一介電材料，以形成平坦之介電層6〇八。而在第一與 第二區域6A與6B上之介電層上分別形成n x m個第一與第二 插塞61 ’分別與第一與第二金屬線層62A與62B形成電性連 接，m與η為自然數且可為相同或不同，如形成9 X 9 = 81個 金屬插塞。而第一與第二插塞分別以等距離方式，由第一 與第二區域6Α與6Β對角之頂點排列為^ X m之矩陣。 在 第二區 10x10 第一與 之一， 接 金屬線 對於該 層中， 金屬插 上 層或銅 鎢金屬 但本發 本發明一較佳實施例中，可參見第6 b圖，在第一與 域6 A與6B中選擇I、π與III等三組面積，其中I為 微米、I I為2 0 X 0微米，而I丨！則為5 〇 X 5 〇微米，與 ，二區域之全面積相同。選擇I、π、丨丨丨三組面積 ，以在介電層60Α中，形成金屬插塞群61。 著，在介電層60Α上，形成第三金屬線層64Α與第四 ，6 4Β，其中該第三與第四金屬線64Α與64β分別正 第一與第二金屬線，以在該第一與第二區域的 ^別形成[金屬層64Α+金屬插塞61]與[金屬層W寬 塞Η ]所組成的兩組金屬雙鑲嵌結構。 第一、第三與第四金屬線層可採用鋁金 孟屬層。而上述金屬插塞可採用銅金屬、鋁全屬， 。而介電層可採用低介電值之含甲基之匕：或 明並非以此為限。 Μ勿， 上述金屬雙鑲嵌結構可 金屬層内連線結構，如第6a 該結構完成後，可藉由光學 金屬雙鑲嵌結構中，金屬層 依需要建構多層，以形成多重 圖中者為三層金屬層結構。卷 顯微鏡或電子顯微鏡檢查兩: 間介電層是否有裂縫產生。ί0503-6862TWF; TSMC2001-0671; peggy.ptd page 17 522539 5. Description of the invention (14) A dielectric material is deposited to form a flat dielectric layer 608. And nxm first and second plugs 61 ′ are formed on the dielectric layers on the first and second regions 6A and 6B, respectively, to form electrical connections with the first and second metal line layers 62A and 62B, respectively. η is a natural number and can be the same or different, such as forming 9 X 9 = 81 metal plugs. The first and second plugs are arranged at equal distances, and the vertices of the diagonals of the first and second regions 6A and 6B are arranged in a matrix of ^ X m. In the second area 10x10, the first and the first, connect the metal wires. In this layer, the metal is inserted into the layer or copper-tungsten metal. However, in a preferred embodiment of the present invention, see FIG. 6b. 6 A and 6B select three groups of areas: I, π, and III, where I is micrometer and II is 20 × 0 micrometer, and I 丨! It is 50 × 50 μm, which is the same as the total area of the two regions. Three sets of areas I, π, 丨 丨 丨 are selected to form a metal plug group 61 in the dielectric layer 60A. Then, on the dielectric layer 60A, a third metal line layer 64A and a fourth, 64B are formed, wherein the third and fourth metal lines 64A and 64β are respectively first and second metal lines, so that Two sets of metal dual damascene structures composed of [metal layer 64A + metal plug 61] and [metal layer W wide plug Η] are formed separately from the second region. The first, third, and fourth metal wire layers may be aluminum metallurgical layers. The above metal plugs can be made of copper metal or aluminum. The dielectric layer may use a low-dielectric methyl-containing dagger: this is not limited. Do not use the metal double damascene structure as described above. After the structure is completed as described in Section 6a, the optical metal double damascene structure can be used to construct multiple layers of metal layers to form multiple layers. Metal layer structure. Roll microscope or electron microscope to check two: whether there are cracks in the dielectric layer. ί
522539 五、發明說明（15) ___ 有衣縫產生時，表示該介電層強度低於 咕 由於上述本發明之測試金屬層間介^屎改不付需要。 ^在第-與第二區域中，選擇不同對的方法’ :同分佈的金屬插塞群之多重金屬層内：=’：建構 在相同金屬線寬與相同金屬插塞面積下，。並比較 =到的應力影響。由於對角線結構。m層 e力作用最明顯，因此藉由上述本發明十：=間：電層的 知到關於介電層在金屬層間的強度資料之方法，可以快速522539 V. Description of the invention (15) ___ When there is a seam, it means that the dielectric layer has a lower strength than the above. Due to the above-mentioned test of the present invention, the interlayer dielectric is not necessary. ^ In the first and second regions, select different pairs of methods ′: In the multiple metal layers of the same group of metal plugs: = ’: Constructed under the same metal line width and the same metal plug area. And compare the stress effects to. Thanks to the diagonal structure. The m-layer e-force has the most obvious effect. Therefore, by using the above method of the present invention, the method of knowing the strength data of the dielectric layer between the metal layers can be quickly obtained.
種多屬層間介電層的裂縫，本發明更提出-圖，在：=連線結構’並以第7圖加以說明。參見第7 ，一具有電路之半導體基底7〇上，沈積一介電層“A 7〇:弟鑲Si，與第二金屬線層72B，、分別位“底 鎮肷於§亥介電層7〇A中，其中第—金屬線層以一距 ,置//於該第二金屬線層。而複數第—金屬插塞川， 二=二電層m中與該第一金屬線層72A連接，與該半導 麥二&中之電路構成電性連接。而複數第二插塞7ΐβ，設 该介電層70中與第二金屬線層72B連接，與該半導體 之電路構成電性連接。而第三金屬線層74Λ與第四金 屬，層74Bj則位於該第—與第二金屬線層上方，與第〆 人第一插基7 1 A與7 1 B間形成金屬雙鑲嵌結構。其中，該第 一孟屬線層74A相鄰於該第四金屬線層之一邊mb，大於下 方第一與第二金屬線層間1/2d之位置，而第四金屬線層 74B仍保持距離d，平行於第三金屬線層74八。 在一較佳貫施例中，上述交錯式金屬雙鑲嵌結構可依 0503-6862TWF ； TSMC2001-0671 ； peggy.ptd 第19頁 522539 五、發明說明（16) 需要建構多層，以形成多重金屬層内連線結構。而上述第 一、第二、第三與第四金屬線層72A、72B、74A與74B，可 採用鋁金屬層戒銅金屬層。而上述金屬插塞71A與71B可採 用鋼金屬、鋁金屬或鎢金屬。而介電層可採用低介電值之 含甲基之矽氧化物，但本發明並非以此為限。 而上述之多重内連線結構，第一與第二金屬插塞71 a 與7 1 B，可以設置於第一與第二金屬線層的對角線之方形 區域中，更可為矩陣式均勻排列。 根據本發明之金屬層間的交錯式設計，其優點在於兩 組金屬雙鑲嵌詰構中，不會出現連續的金屬層間介電層通 道’如第7圖所示，金屬層間介電層已被分割為片段，曰因 此消除了多層金屬所產生的強大應力，有效的避免的金屬 層間介電層產生裂缝。 " 而根據前述四組設計之貫驗結果，本發明中更提出另 一種多重金屬層内連線結構，參見第8圖加以說 圖中，在一具有電路之半導體基底80上，沈積— 80A，而第一金屬線層82A與第二金屬線層82B ,別': 基底80上，鑲嵌於該介電層80A中，其中第一人 j位於 持大於或等於3微米之距離平行於該第二金屬1 線層保 數第一金屬插塞81A，設置於介電層8〇A一中與談層一。而複 層82A連接，與該半導體基底中之電路構成、電性弟—金屬線 複數第二插塞81B，設置於該介電層8〇中與 $接。而 82B連接，與該半導體基底之電路構成電性連:金屬，層 金屬線層84A與第四金屬線層84B，則位於〃。而第三 、 ；〜弟一與第二金The present invention further proposes a crack of a multi-generic interlayer dielectric layer, which is illustrated in FIG. 7 with a connection structure. Referring to No. 7, a semiconductor substrate 70 having a circuit is deposited with a dielectric layer "A 70: Si inlaid, and a second metal wire layer 72B, respectively" at the bottom of the dielectric layer 7 In OA, the first metal line layer is placed at a distance from the second metal line layer. The plurality of metal plugs are connected to the first metal line layer 72A in the second electrical layer m, and are electrically connected to the circuits in the semiconductor two. The plurality of second plugs 7ΐβ are provided in the dielectric layer 70 to be connected to the second metal line layer 72B, and are electrically connected to the semiconductor circuit. The third metal wire layer 74Λ and the fourth metal, and the layer 74Bj are located above the first and second metal wire layers, and a metal dual damascene structure is formed between the first metal inserts 7 1 A and 7 1 B. Wherein, the first Monsoon line layer 74A is adjacent to one side mb of the fourth metal line layer, which is larger than the position 1 / 2d between the first and second metal line layers below, and the fourth metal line layer 74B still maintains a distance d. , Parallel to the third metal line layer 74. In a preferred embodiment, the above staggered metal dual damascene structure may be 0503-6862TWF; TSMC2001-0671; peggy.ptd page 19 522539 5. Description of the invention (16) Multi-layer construction is required to form multiple metal layers. Connection structure. The first, second, third, and fourth metal line layers 72A, 72B, 74A, and 74B may be aluminum metal layers or copper metal layers. The metal plugs 71A and 71B may be made of steel, aluminum, or tungsten. The dielectric layer may use a low-dielectric methyl-containing silicon oxide, but the present invention is not limited thereto. In the above-mentioned multiple interconnection structure, the first and second metal plugs 71 a and 7 1 B can be arranged in the square areas of the diagonal lines of the first and second metal wire layers, and can be matrix-uniform. arrangement. According to the staggered design of the metal layers of the present invention, the advantage is that in two sets of metal dual damascene structures, there will not be continuous metal interlayer dielectric layer channels. As shown in FIG. 7, the metal interlayer dielectric layer has been divided. It is a fragment, so that the strong stress generated by multilayer metal is eliminated, and cracks in the interlayer dielectric layer are effectively avoided. " According to the results of the previous four sets of designs, another multi-metal layer interconnect structure is proposed in the present invention. Refer to FIG. 8 for illustration. In a figure, a semiconductor substrate 80 with a circuit is deposited—80A. And the first metal line layer 82A and the second metal line layer 82B, don't: the substrate 80 is embedded in the dielectric layer 80A, where the first person j is located at a distance greater than or equal to 3 microns in parallel to the first The first metal plug 81A of the two-metal 1 wire layer is disposed in the dielectric layer 80A-1 and the talk layer-1. The multi-layer 82A is connected to the second substrate plug 81B, which is the circuit configuration and the electric property-metal wire in the semiconductor substrate, and is disposed in the dielectric layer 80 and connected to the $ 80. The 82B connection forms an electrical connection with the circuit of the semiconductor substrate: metal, layer 84A and a fourth metal line layer 84A are located at 〃. And the third, ~ ~ brother one and second gold
0503-6862TW ； TSMC2001-0671 ； peggy.ptd 第20頁0503-6862TW; TSMC2001-0671; peggy.ptd page 20
五、發明說明（17) 屬線層正上方 鑲嵌結構，且 及第二金屬線 在一較佳 需要建構多層 ~ 、第二、第 採用鋁金屬層 用鋼金屬、在呂 含甲基之矽氧 由於根據 屬雙鑲嵌結構 低金屬層間介 ，因此上述本 有效的避免金 雖然本發 定本發明，任 和範圍内，當 圍當視後附之 丄與第一與第二插塞δΐ A與81B間形成金屬雙 第三與第四金屬線層間之平行距離，盥第一 層間距離相同。 貝施例中，上述交錯式金屬雙鑲嵌結構可依 一、’成多重金屬層内連線結構。而上述第 三與第四金屬線層82A、82B、84A與84β，可 金屬層。而上述金屬插塞81A與81β可採 或鎢金屬。而介電層可採用低介電值之 =物，但本發明並非以此為限。 ;;5 : t设計之實驗結I，發現只要兩組金 = 於或等於3微米，即可有效的減 發明所提出之ΐ : Ϊ ^屬層間介電層的完整 屬層間介電声二ΐ孟屬層内連線結構，可以 明以較佳_ 受到兩金屬線層的破壞。 月以孕乂佳貫施例揭露 何熟悉此項技藝者，/^ 、然其並非用以限 可做些許更動t 不脫離本發明之精神 "專利；者：：本發明之保護範 0503-6862TWF ； TSMC2001-0671 ； peggy.ptd 第21頁V. Description of the invention (17) It belongs to the inlay structure directly above the wire layer, and the second metal wire needs to be constructed in multiple layers ~, the second and the first use aluminum metal layer with steel metal, and silicon-containing silicon oxide in Lu It is a low-metal interlayer with a dual mosaic structure, so the above is effective to avoid gold. Although the present invention was made, within the scope of the present invention, a metal is formed between 丄 and the first and second plugs δ ΐ A and 81B. The parallel distance between the double third and fourth metal wire layers is the same as the distance between the first layers. In the exemplary embodiment, the above-mentioned staggered metal dual damascene structure can be formed as a multiple metal layer interconnect structure. The third and fourth metal line layers 82A, 82B, 84A, and 84β may be metal layers. The metal plugs 81A and 81β may be made of tungsten or tungsten. The dielectric layer can be made of a low dielectric value, but the invention is not limited thereto. ; 5: Experimental design I of t design, found that as long as two sets of gold = 3 μm or less, the proposed invention can be effectively reduced ΐ: Ϊ ^ Complete interlayer dielectric layer 2 The structure of the interconnected layer in the Mon-Mongolian layer can be better damaged by the two metal wire layers. The following is an example of how to familiarize yourself with this technique, but it is not intended to limit some changes. Without departing from the spirit of the present invention "patent;6862TWF;TSMC2001-0671; peggy.ptd page 21
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6787803B1 (en) * | 2003-06-24 | 2004-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test patterns for measurement of low-k dielectric cracking thresholds |
| TWI574294B (en) * | 2013-12-25 | 2017-03-11 | A method of manufacturing a plasma processing chamber and an electrostatic chuck thereof | |
| TWI578365B (en) * | 2013-12-25 | 2017-04-11 | A method of manufacturing a plasma processing chamber and an electrostatic chuck thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6787803B1 (en) * | 2003-06-24 | 2004-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Test patterns for measurement of low-k dielectric cracking thresholds |
| TWI574294B (en) * | 2013-12-25 | 2017-03-11 | A method of manufacturing a plasma processing chamber and an electrostatic chuck thereof | |
| TWI578365B (en) * | 2013-12-25 | 2017-04-11 | A method of manufacturing a plasma processing chamber and an electrostatic chuck thereof |
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