TW522499B

TW522499B - Semiconductor apparatus and fabrication method of reducing the influence of package induced stress on IC parameter offset

Info

Publication number: TW522499B
Application number: TW091107267A
Authority: TW
Inventors: Shen-Ru Ni
Original assignee: Ru Yi Invest Co Ltd
Priority date: 2002-04-11
Filing date: 2002-04-11
Publication date: 2003-03-01

Abstract

This invention relates to a semiconductor apparatus and a fabrication method of reducing the influence of package induced stress on IC parameter offset. On a silicon chip, there is a first insulation layer formed. On the first insulation layer, there is a first metal wiring layer formed. On the first metal wiring layer, there is a first passivation layer formed. There is a second passivation layer formed on the first passivation layer. There are several through holes in the second passivation layer. There are air bubble voids with area larger than the though holes in the first metal wiring layer corresponding to the through holes of the second passivation layer, in which the through holes of the second passivation layer and the first metal wiring layer are separated by air. When the chip is packaged by a molding compound, the viscous force of the molding compound can be used to seal the openings of the through holes and thus the molding compound will not drip into the air bubble voids. Therefore, the molding compound separates from the first metal wiring layer through air of the air bubble voids, which reduces the piezoelectric effects caused by package material stress on the high precision or high sensitivity IC devices of the chip corresponding to the air bubble voids and thus achieves the goal of improving IC fabrication yield.

Description

522499 五、發明說明（1) 本發明係有關一種可降低因數偏移（〇 f f s e t)影響之半導體裝可減少因封裝材料應力於I C所高IC製造良率之半導體裝置及按’一般半導體I C在經過道程序即必須將晶粒（chip ) 一架上’並以金屬線連結晶粒上之導線架（lead frame)上之端子，以成為I C (請參閱第ία圖之封裝所產生應力對I C參置及製造方法，尤指一種產生之壓電效應，藉以提製造方法。各種製造步驟後，·最後一個個切割開來黏合於導線電極墊片（bond pads)與再以塑膠樹脂封住晶粒，一般I C封裝剖面結構圖但目前高精密在於當晶粒封裝後壓產生之原因，係壓電材料（piezoe 分子材料封住該晶 (stress)，而該應生相對應之微小電除的偏移電壓（請由於該偏移電 1 C的應用範圍，表面形成一可緩衝膠層（s i 1 i c〇ne ) PATENT 5, 026, 6 67 於封裝後可微調之度或南靈 I C内部因製作I 1 ectr i c 粒時，會力經由矽壓，此微參閱第1 壓之產生習式之改塑膠樹脂或聚酰亞 )等，或方式將偏敏度I C最不易所產生之偏移電 c所使用之石夕材material)，當對石夕晶粒表面產材料本身具有的小電壓使I C内 Β 1Γ —般I c剖係限制了高精密良作法，即在製造成之應力的材胺（polyimide 者於設計I C時移電壓調整至最解決的問題即壓，該偏移電料本身即為一塑膠樹生一應壓電特部產生面結構度及高作完成料，例 )(U. 5即預小數值脂等高力性會產不易消圖）。靈敏度之晶粒如石夕軟 S 留一些，但前 522499 五、發明說明（2) 者以增加緩衝序，而且該石夕 (例如：矽軟加但降低I C 調偏移電壓之接腳加入一般微調接腳訊號數值，此種作響，但由於必設計時勢必需後，必須針對人力，並不理層之方軟膠層膠層必· 參數偏方式，電路的驅動微法雖可須在I 增加線每顆I 想。式必須或聚酰須控制移的效則必須設計之調電路調整偏 c上附路所需 c均作在晶粒之亞胺層形在50-200 果卻不如在設計之中，使晶處理，以移電壓，加微調電之面積及測量、調製程中增加一道裎成時其厚度不易控帝j #m)，導致成本增預期。而後者預留；^ 初，即將微調電路及粒在封裝後，可利用調整偏移電壓至最+ 降低I C參數偏移影路及接腳，因此，在接腳數目，且在封裝整，相當麻煩又浪費匁趣善上述缺 I c參數護層形成或南靈敏透空孔下當以塑膠用該些空材料產生及砍晶粒路不致因以僅須調於上述缺點，本發明人特加以失’其係提供一種可降低因封偏移影響之半導體裝置及製造時，於該第二保護層上相對於度電路位置之預定處設有透空方之第一保護層可經由蝕刻而樹脂封裝時，塑膠樹脂與第一氣泡空洞以空氣作隔離，以阻之應力直接加諸於第一金屬導表面，使矽晶粒上之高精密度封裝材料之應力產生壓電效應整製程，但不須外加隔離材料研究與裝所產方法，碎晶粒孔，使成為空金屬導絕封裝線層、電路或而出現或增加生應力S 利用第二上高精爸第二保I 氣泡空# 線層間艮I 時塑膠相第一絕Η 高靈敏肩偏移電歷電路及接522499 V. Description of the invention (1) The present invention relates to a semiconductor device that can reduce the influence of a factor offset (〇ffset) on a semiconductor device that can reduce the stress on packaging materials due to the high IC manufacturing yield of the IC. After the procedure, the chip must be mounted on a frame, and the terminals on the lead frame on the chip must be connected with a metal wire to become an IC (see the stress generated by the package on the IC as shown in the figure). Participation and manufacturing method, especially a piezoelectric effect generated to improve the manufacturing method. After various manufacturing steps, the last one is cut to bond the wire electrode pads (bond pads) and the crystal is sealed with plastic resin. Grain, general IC package cross-section structure diagram, but the current high-precision is due to the pressure generated after the die is packaged, which is a piezoelectric material (piezoe molecular material seals the crystal (stress), and the corresponding micro-electrostatic Offset voltage (Because of the application range of the offset voltage 1 C, a bufferable adhesive layer (si 1 icone) is formed on the surface. PATENT 5, 026, 6 67 can be fine-tuned after packaging or In the spirit IC, because I 1 ectr ic particles are produced, they will pass through the silicon pressure. Refer to the first pressure to change the formula (plastic resin or polyimide), etc., or the method will make the least sensitive IC difficult to produce. The material used in the offset electric c), when the small voltage on the material produced on the surface of the stone Xi makes the B 1Γ in the IC-the general I c profile system limits high-precision good practices, that is, in the manufacture of The material stress of polyimide (polyimide is the most solved problem when designing the IC time-shift voltage. That is, the offset material itself is a plastic tree that generates surface structure and high-quality finished materials. Example) (U. 5 means that high-strength properties such as pre-fabricated lipids will not easily disappear.) Some grains of sensitivity such as Shi Xi soft S are left, but the first 522499 V. Description of the invention (2) To increase the buffer order, And the Shi Xi (for example: silicon soft plus but lower IC offset voltage is added to the general fine-tuning pin signal value, this kind of ringing, but because it must be designed when necessary, it must be directed to manpower, not to reason Square soft rubber layer The number bias method, although the driving micro method of the circuit must be added to each line of I. I must use the formula or the polyimide must control the effect of the shift, you must design a tuning circuit to adjust the bias c. The c required is attached to the crystal. The thickness of the grain of imine is 50-200, but it is not as good as in the design. The crystal is processed to shift the voltage, and the area of fine adjustment is added. The thickness of the measurement and modulation process is not easy to control. Emperor j #m ), Resulting in increased costs. The latter is reserved; ^ At the beginning, after the trimming circuit and the chip are packaged, the offset voltage can be adjusted to the maximum + to reduce the IC parameter offset shadow path and pins. Therefore, the number of pins and the entire package are quite equivalent. It is troublesome and wasteful. The above-mentioned lack of I c parameter protective layer formation or south sensitive through-holes should be generated and cut by the use of plastic with these empty materials. It is not necessary to adjust to the above-mentioned disadvantages. It is to provide a semiconductor device which can reduce the influence due to the sealing offset and manufacture. The first protective layer provided with a hollow side at a predetermined position on the second protective layer relative to the circuit position can be etched to resin. During packaging, the plastic resin is isolated from the first bubble cavity by air, and the stress of resistance is directly applied to the first metal conductive surface, so that the stress of the high-precision packaging material on the silicon die produces a piezoelectric effect. It is not necessary to add isolation material research and production methods to break the grain holes, so that it becomes an empty metal insulation package line layer, the circuit or the emergence or increase of stress. I bubble retention space between the plastic layer with a first line # must Η calendar sensitive electrical circuit when the offset shoulder Burgundy and then I

522499 五、發明說明（3) 之方式，即本發明應力對I C 要係於矽晶第一保護層上高精密度利用該些透孔與第一金以塑膠樹脂力，因此，孑L開口，而塑膠樹脂與氣作隔離，金屬導線層之·高精密度達到減少偏本發明應力對I C 項調整形成種，即可達為使瞭解，下列為方便為範例’但可達到提高I C製造良之主要目的係在提供_ 參數偏移影響之半導體粒上依序形成第一絕緣及第二保護層，該第二或同致敏度電路位置之空孔對第一保護層作蝕屬導線層間具有空氣泡封住晶粒時’由於該塑在流動至保護層透空孔不會向下滴落填充空氣第一金屬導線層間可藉塑膠樹脂所產生之材料及第一絕緣層上，而空或高靈敏電路即不會因移電壓，提高1C製造之另一目的係在提供一參數偏移影響之半導體第二保護層之製程及增到提高I C製造良率之貴審查委員對本發明案茲舉一較佳實施例並配說明起見，本示意圖係本發明並不限於應用於率之目的。種可降低因封裝所產生裝置及製造方法，其主 _ 層、第一金屬導線層、 · 保護層上相對於矽晶粒 ·522499 V. Method of description of invention (3), that is, the stress of the present invention should be tied to the first protective layer of silicon crystal with high precision to make use of these through holes and the first gold with plastic resin. Therefore, 孑 L opens, The plastic resin is isolated from the gas, and the high precision of the metal wire layer can be reduced. The stress of the present invention can be adjusted to form the IC item. For the sake of understanding, the following is an example for convenience. The purpose is to sequentially form a first insulation layer and a second protection layer on the semiconductor particles that provide the effect of the parameter shift. The holes in the second or the same sensitivity circuit position corrode the first protection layer. There is air between the layers of wires. When the bubble is sealed, because the plastic flows to the protective layer through-holes, it will not drip down and fill the air. The first metal wire layer can be made of plastic resin and the first insulating layer. Sensitive circuits will not be shifted by voltage. Another purpose of improving 1C manufacturing is to provide a process for the second protective layer of semiconductors affected by a parameter offset and to increase the cost of IC manufacturing yield. The investigating committee presents a preferred embodiment of the present invention and provides a description of the present invention. For the sake of explanation, this schematic diagram is not intended to limit the application of the present invention. A device and a manufacturing method capable of reducing the generation due to packaging. The main layer, the first metal wire layer, and the protective layer are opposite to the silicon die.

預定處設有透空孔，以刻，使第二保護層透空空洞以空氣作隔離，當膠樹脂本身具有一黏滯開口時，只會封住透空 I 泡空洞中，使成型後之、由該些空氣泡空洞以空應力即無法加諸於第一氣泡空洞下方矽晶粒上應力產生偏移電壓，以良率之目的。種可降低因封裝所產生裝置及製造方法，其僅加蝕刻第一保護層之製目的。 · ，有更進一步的認識與 θ圖示詳述如后： :般基本半導體製作， >、他以此為基礎而衍生 522499 五、發明說明（4) 之製作方式。請參，第2A圖，該内部已具有電路圖樣及離子極區 1 1之矽f粒1上係形成一第一絕緣層2，該第一絕緣層可為以矽晶粒表面經氧化後所產生之氡化矽層（Si〇2 )二氣相沉積方式所產生之氧化矽層（si〇2)或硼磷矽玻璃声 (BPSG)或參雜填之氧化矽層。凊參閱第2 B圖，該第一絕緣層2經曝光顯影及蝕刻後，在第一絕緣層2上形成裸露矽晶粒1表面之接觸窗口 2 1 ，該接觸窗口為位於離子極區1 1之上方。A through hole is provided at the predetermined place to engrav the second protective layer through the air to isolate the air. When the gum resin has a viscous opening, it will only seal the through hole I, so that after molding, The stress caused by these air bubble cavities cannot be applied to the silicon crystal grains under the first bubble cavities to generate an offset voltage for the purpose of yield. The invention can reduce the device and manufacturing method due to packaging, which only adds the purpose of etching the first protective layer. · There is further understanding and θ diagram detailed as follows:: Basic semiconductor production, > He derived from it 522499 V. Production method of invention description (4). Please refer to FIG. 2A. The silicon f particle 1 having a circuit pattern and an ion electrode region 1 1 inside has a first insulating layer 2 formed thereon. The first insulating layer may be formed by oxidizing the surface of the silicon crystal grains. The silicon oxide layer (Si0 2) produced by the two-phase vapor deposition method is a silicon oxide layer (SiO 2) or a borophosphosilicate glass acoustic (BPSG) or a mixed filled silicon oxide layer.凊 Referring to FIG. 2B, after the first insulating layer 2 is exposed, developed, and etched, a contact window 2 1 is formed on the surface of the exposed first silicon layer 1 on the first insulating layer 2, and the contact window is located in the ion electrode region 1 1 Above.

請參閱第2 C圖，該第一絕緣層2上係形成一第一金屬導線層3 ，並經曝光顯影及蝕刻後，以形成金屬配線，而該第一金屬導線層3形成電極3 i之部分則利用第一絕緣層2之接觸窗口 2 1與矽晶粒1上之離子極區^丄接觸，而該第一金屬導線層3可為鋁層（A1)、鋁銅合金層、銘矽銅合金層或銅金屬或鎢金屬。曰請參閱第2D圖，該第一金屬導鍊層3上係以電漿輔助氣相 /冗積法（Plasma Enhanced Chfemical Vapor Deposition，PECVD)形成一第一保護層4，該第一保護Referring to FIG. 2C, a first metal wire layer 3 is formed on the first insulating layer 2 and is exposed, developed, and etched to form metal wiring, and the first metal wire layer 3 forms an electrode 3 i. In part, the contact window 21 of the first insulating layer 2 is used to make contact with the ion electrode region ^ on the silicon die 1. The first metal wire layer 3 may be an aluminum layer (A1), an aluminum-copper alloy layer, or silicon. Copper alloy layer or copper metal or tungsten metal. Please refer to FIG. 2D. The first metal guide chain layer 3 is formed with a plasma-assisted vapor phase / redundancy method (PECVD) to form a first protective layer 4. The first protective layer 4

，4可為氧化石夕層（Si〇2 )或參雜磷之氧化其厚度約0.5 - 1ββ5 _。 μ多閱第2 Ε圖，在該第一保護層4上以積法形成-第二保護層5，該第二保護層曰Si3N4)或氮氧化矽層（si〇N)，厚度約為〇 $ 一 m，並對該第二保護層5進行曝光顯影及蝕刻，使第, 4 can be the oxide layer (SiO2) or the oxidation of impurity phosphorus, and its thickness is about 0.5-1ββ5 _. μ Read the second E diagram, and form a second protective layer 5 on the first protective layer 4 by a stack method. The second protective layer is called Si3N4) or a silicon oxynitride layer (siON), and the thickness is about 0. $ One m, and the second protective layer 5 is exposed, developed, and etched so that

第8頁五、發明說明（5) 護層5上可具有若干透空孔5 令置係為下方具有第一金屬 μ透二孔5 1之形成位孔5 1之形成位置為相對於矽：〒過之位f ’且該透空靈敏度電路之位置。 sa/、1上具有高精密度或高請參閱第2 F圖，以適八勒如氧| 如：氫氟酸BOE )經第二保；：^虱化矽之酸性溶液（例護層4進行蝕％，由於透空:曰卜透空孔5 1對第—保線層3通過，因此，在醆性物之F方係有第一金屬導線層3時即被阻擋，而當透=二;了拜刻至該第—金屬導已被向外擴散蝕刻至一預定=$ 1下方之第—保護層4 )時即停止蝕刻，使該第一 ^ j向外擴散蝕刻1 -5 # m 空洞4 1 ’且空氣泡空洞4二二：：:s’隔具有若干空氣泡大，此時，第二保護層5透==空孔51面積為間即可利用該些空氣泡空洞二、：-金屬導線層3 空洞4 1之形成位置亦相對於上：：,作隔離’而空氣泡高靈敏度電路之位置。、Ba粒1上具有面精密度或請參閱第3圖，封裝砗，# / _ ^ h π β& 時係以塑膠樹脂6封住該晶粒，在塑膠樹脂6流動至第-徂嗜旺r „ 封住該透空孔5 i之開空孔51時二滯性，因m透空孔5=於:亥塑膠樹脂6係具有；充於空氣泡空洞41内，工：塑;膠樹脂並不會滴，填向/、疋呈—滴狀封住該透空孔 5 1開口，二成型後之塑膠樹脂6與第一金屬導線廣3仍利用該t空軋泡空洞4 1而以空氣作隔離，因&，封裝完成後之塑勝樹脂6材料應力則可藉由該些空m洞4 iPage 8 V. Description of the invention (5) The protective layer 5 may have a plurality of through holes 5 so that the position is formed with the first metal μ through hole 5 1 below. The formation position of the hole 51 is relative to silicon: The passing position f 'and the position of the air-through sensitivity circuit. Sa /, 1 has high precision or high, please refer to Figure 2F, in order to adapt to Ba Le such as oxygen | such as: hydrofluoric acid BOE) through the second guarantee ;: ^ lice acid silicon solution (such as protective layer 4 Etching%, due to the air-through: said through-holes 51 pass through the first-wire protection layer 3, so when the first metal wire layer 3 in the F side of the nature is blocked, and when the penetration = two The etching is stopped until the first-metal guide has been outwardly diffused and etched to a predetermined first protective layer 4 below $ 1), and the etching is stopped, so that the first ^ j outwardly diffused and etched 1 -5 # m The cavity 4 1 ′ and the air bubble cavity 4 222 :: s' have a large number of air bubbles. At this time, the second protective layer 5 is transparent == the area of the hole 51 can be used for these air bubbles. :-The position of the metal wire layer 3 and the cavity 41 1 is also relative to the upper ::, for isolation 'and the position of the air bubble high-sensitivity circuit. 1. Ba particle 1 has surface precision or please refer to Figure 3, package 砗, # / _ ^ h π β & When the crystal is sealed with plastic resin 6, the plastic resin 6 flows to the first- r „The hysteresis of the open hole 51 which seals the through hole 5 i is 51, because m through hole 5 = in: Hai plastic resin 6 series; filled in the air bubble cavity 41, work: plastic; rubber resin It does not drip, and fills the opening of the through-hole 51 in a drop-shaped manner. The plastic resin 6 and the first metal wire 3 after the second molding are still using the t-rolled bubble cavity 41. The air is used for isolation. Because &

522499 ιβι_ιββ_ββι<βββ<_____1_«____·__ββ_«_<ιβββββιβιιβ<ιι^______ ^00^0001^^ 五、發明說明（6) 之隔離，而不直接加諸於第一金屬導線層3及第一絕緣層 2上，使矽晶粒1上相對於透空孔5 1及空氣泡空洞4 1 位置之高精密度或高靈敏度電路，產不會文到封裝材料應力之影響而使石夕晶粒產生壓電效應，以降低I c之偏移電壓，使1C之製造良率提高。 ’522499 ιβι_ιββ_ββι < βββ < _____ 1 _ «____ · __ββ _« _ < ιβββββιβιιβ < ιι ^ ______ ^ 00 ^ 0001 ^^ Isolation without adding directly to the first metal wire layer 3 and the first insulation On layer 2, the high-precision or high-sensitivity circuit on the position of silicon die 1 with respect to the through hole 5 1 and the air bubble hole 4 1 can produce the influence of the stress on the packaging material and cause the Shi Xi grain to be generated. The piezoelectric effect reduces the offset voltage of I c and improves the manufacturing yield of 1 C. ’

請參閱第4圖，該第二保護層5經曝光顯影姓刻出之透空孔5 1圖樣可依實際需求而作不同之安排。圖4 Α 一 4 D即為透空孔5 1為不同幾何圖形之實施例圖，其各透空孔5 1開孔之大小及與相鄰透空孔5 1間之間距應考慮當第一保護層4橫向蝕刻完成後，以空氣泡空洞形成網f 懸空時，該第二保護層5所能承受上方之壓力但不至於朋塌為基準。圖4 A — 4 D上之參數a為透空孔大小，即^ 孔邊長或圓形之半徑約為2 - 20 um，參數b為各相鄰遂空孔之間距，其係約2 - 20 um，參數c為最外側之透交孔外側至第二保護層5邊緣所須之距離，其數值約為參數 b 之 1 · 5 - 2 倍。Please refer to FIG. 4. The pattern of the through-holes 51 engraved by the second protective layer 5 after exposure and development can be differently arranged according to actual needs. Fig. 4A-4D are examples of the through holes 51 which are different geometrical figures. The size of the openings of each through hole 51 and the distance from the adjacent through hole 51 should be considered as the first. After the lateral etching of the protective layer 4 is completed, when the air bubble forming network f is suspended, the second protective layer 5 can withstand the pressure above but not collapse. The parameter a in Figure 4 A — 4 D is the size of the hole, that is, the length of the side of the hole or the radius of the circle is about 2-20 um, and the parameter b is the distance between adjacent adjacent holes, which is about 2- 20 um, parameter c is the distance from the outside of the outermost through hole to the edge of the second protective layer 5 and its value is about 1 · 5-2 times the parameter b.

請參閱第5圖，本發明亦可應用於雙金屬導線I C 其主要係於製造第一金屬導線層3及第一保護層4間加A 下列製程：請參閱第5A圖，其主要係於第一金屬導線層3之製程完成後，在該第一金屬導線層3上以氣相沉積方式成塗抹矽氧玻璃（SOG )方式形成一第二絕緣層7，該第二絕緣層可為氧化矽層（Si02)或硼磷矽玻璃層（BPSG) ° 請參閱第5 B圖，在該第二絕緣層7以化學研磨戒離Please refer to FIG. 5. The present invention can also be applied to a bimetallic wire IC. The main process is to add A between the first metal wire layer 3 and the first protective layer 4. The following process is shown in FIG. 5A, which is mainly based on After the manufacturing process of a metal wire layer 3 is completed, a second insulating layer 7 is formed on the first metal wire layer 3 by vapor deposition in a silicon-oxygen glass (SOG) coating method, and the second insulating layer may be silicon oxide. Layer (Si02) or borophosphosilicate glass layer (BPSG) ° Please refer to Fig. 5B. The second insulating layer 7 is chemically ground and detached.

第10頁 522499 五、發明說明（7) 子蝕刻方式進行刻，以形成一金請導線層 7 1與請蝕刻後在該第保護層若干透第二金性溶液 5 1對有第二參閱第5 8 ，使第第一金屬參閱第5 ，於該第一保護層 5進行曝空孔5 1 屬導線層 (例如：第一保護金屬導線該第二金屬導線第一保護層4已散蝕刻具有若空孔5 二金屬隔離，泡空洞第二絕矽晶粒 1 - 5 // m ) 干空氣泡 1面積為導線層8 使封裝後 4 1之隔緣層7、 1上南精平坦化屬接觸 C圖，二金屬導線層 D圖，二金屬 4上並光顯影，該透 8通過氫IL酸層4進層8通層8時被向外時即停空洞4 大，此間即可之塑膠離’而第一金密度或後，將第二絕緣層7曝光顯影及蝕窗口 7 1。於第二絕緣導線層8可 3接觸。該第二金屬導線層8經導線層8上形成一第一層7上形成一第二金屬利用該金屬接觸窗口形成一第二及蝕刻，使空孔5 1之之位置，再 BOE )經第行姓刻，由過，因此，即被阻擋，擴散蝕刻至止钱刻，使 1 ，且空氣時，第二保利用該些空樹脂6材料不直接加諸屬導線層3 高靈敏度電保諜層5 ，第二保護層形成位置係以適合蝕刻二保護層5 於透空孔5 在酸性溶液而當透空孔一預定寬度該第泡空護層氣泡應力於第及第路，一保護洞4 1 5透空空洞4 則可藉二金屬一絕緣並不會曝光顯影及保護層4，並對談第二 5上可具有為下方具有氧化矽之酸之透空孔 1之下方係向下蝕刻至 5 1下方之 (約向外擴層4間隔之面積較透孔5 1與第 1以空氣作由該些空氣導線層8、層2上，使受到封裝材Page 10 522499 V. Description of the invention (7) Sub-etching is performed to form a gold conductive wire layer 7 1 and a number of second gold solutions 5 are penetrated in the first protective layer after etching. 5 8, so that the first metal is referred to No. 5, and the first protective layer 5 is exposed to holes 5 1 is a wire layer (for example: the first protective metal wire, the second metal wire, the first protective layer 4 has been etched to have If the hole 5 is separated by two metals, the second hollow silicon die of the cavity 1-5 // m) The area of the dry air bubble 1 is the wire layer 8 so that the spacer layer 7 and 1 of the 1 after the package 4 are flattened. Contact picture C, picture of two metal wire layer D, and photo development on two metal 4, the transparent layer 8 passes through the hydrogen IL acid layer 4 into the layer 8 and the layer 8 is closed outward when the hole 4 is large. After the first gold density is removed, the second insulating layer 7 is exposed and developed and the window 71 is etched. The second insulated wire layer 8 may be in contact with each other. The second metal wire layer 8 is formed on the wire layer 8 by forming a first layer 7 on which a second metal is formed. The metal contact window is used to form a second and etch, so that the position of the hole 51 is formed. The name of the engraving is passed, so it is blocked, and the diffusion etching is stopped until the money is engraved, so that when the air is in the air, the second insurance uses these empty resins. 6 The material is not directly added to the wire layer. 3 High-sensitivity electrical security The layer 5 and the second protective layer are formed in a position suitable for etching the second protective layer 5 in the through hole 5 in the acid solution and when the through hole has a predetermined width, the bubble of the second protective layer is stressed on the first and second paths, and a protective hole 4 1 5 through-holes 4 can be insulated by two metals and will not expose the developing and protective layer 4, and the second 5 can have a through-hole 1 with a silicon oxide-containing acid below, which is downward. Etched below 5 1 (approximately the area of the outwardly expanding layer 4 interval is larger than the through-holes 5 1 and 1 with air as the air conductor layer 8 and layer 2 so that the receiving material is sealed.

第11頁 522499 五、發明說明（8) 料應力之影響移電壓，使I 請參閱第，亦可將第二層3之上方，第二絕緣層7 緣層7形成間之透空孔5 1 洞4 1隔離，空洞4 1與第綜上所述二保護層之製裝後之塑膠樹作隔離，以保靈敏電路不致因此，可以在達到降低封裝之壓電效應目匕特為提出申而使矽 C之製 6圖，保護層當酸性進行I虫隔之若與第一使封裝一金屬 ’由於程及增脂與第護第一受到封不須增材料應的，其請。晶粒產造良率本發明 5之透溶液由刻後，干空氣金屬導後之塑導線層本發明加餘刻一金屬絕緣層裝材料加材料力對高確較習生壓電效應提高。應用於具雙空孔5 1形透空孔5 1 即會於第一泡空洞4 1 線層3間則膠樹脂6亦 3以空氣作係利用調整 ’以降低I C之偏金屬導成於第對第一保護層，而第利用該可藉由隔離。 I C製第一保護層之製程導線層及第下方矽晶粒之應力影響或I C設計精密度或尚式具有實質一絕緣上之南而產生及接腳靈敏度上之效線之I C時一金屬導線保護層4及 4及第二絕一保護層5 些空氣泡空該些空氣泡作時形成第 ’即可使封層間以空氣精密度或高偏移電壓，之成本下，電路所產生益増進，因Page 11 522499 V. Description of the invention (8) The effect of material stress on the voltage shift, so that I can refer to the first, can also be above the second layer 3, the second insulating layer 7 edge layer 7 to form a through hole 5 1 The hole 41 is isolated, and the hole 41 is isolated from the plastic tree after the two protective layers are assembled in order to protect the sensitive circuit. Therefore, it is possible to reduce the piezoelectric effect of the package in order to make a claim. Make the silicon C system 6 map, when the protective layer is acidic, and if the first layer is sealed with a metal, it is not necessary to add materials due to the process and fattening and the first protection is not required, please. Grain production yield The 5th solution of the present invention is engraved with dry air and the plastic is conductive after the metal wire layer. The present invention adds a metal insulation layer. The material and material strength are higher than the conventional piezoelectric effect. Applied to the double-hole 5 1 shaped through-hole 5 1 that will be between the first bubble 4 1 and the wire layer 3, then the resin 6 and 3 will be adjusted using air as a system to reduce the partial metal of the IC. For the first protective layer, the first can be used by isolation. The process of the first protective layer of IC made of the conductive layer and the underlying silicon die stress or IC design precision or fashion has a substantially south of insulation and the effect of the sensitivity of the pin is a metal wire The protective layers 4 and 4 and the second absolute protective layer 5 Some air bubbles are formed when the air bubbles are formed, so that the precision of the air between the sealing layers or the high offset voltage can be used, and the cost of the circuit is improved. ,because

第12頁 522499 圖式簡單說明；第1 A _ 1 B圖：係為習式之I C封裝及組成剖面示意圖第2 第3 第4 第5 第6 (圖矽曰曰第一第一第一第二塑膠第二第二 A — 2 F圖：係為本發明之製造流程剖面示意圖。圖：係為本發明封裝時之示意圖。 A — 4 D圖：係為本發明第二保護層透空孔之各種實施例圖。 A — 5 D圖：係為本發明應用在具雙金屬導線I C之示意圖。圖··係為本發明應用在具雙金屬導線I C之另一實施例。號說明）粒1 絕緣層2 金屬導線層3 保護層4 保護層5 樹脂6 絕緣層7 金屬導線層8 離子極區1 1 接觸窗口 2 1 電極3 1 空氣泡空洞4 1 透空孔5 1 金屬接觸窗口 7Page 12 522499 Brief description of the drawings; Figure 1 A _ 1 B: It is a schematic diagram of the IC package and composition cross section of the custom 2nd 3rd 4th 5th 6th (Figure silicon is called first first first first Two plastic second second A-2 F: is a schematic cross-sectional view of the manufacturing process of the present invention. Figure: is a schematic diagram when the present invention is packaged. A-4 D: is the second protective layer through hole of the present invention. Figures of various embodiments. A-5D: This is a schematic diagram of the present invention applied to a IC with a bimetallic wire. Fig. · Is another embodiment of the present invention applied to a IC with a bimetallic wire. 1 Insulating layer 2 Metal wire layer 3 Protective layer 4 Protective layer 5 Resin 6 Insulating layer 7 Metal wire layer 8 Ion electrode area 1 1 Contact window 2 1 Electrode 3 1 Air bubble cavity 4 1 Through hole 5 1 Metal contact window 7

第13頁Page 13

Claims

^22499 六、申請專利範圍 1 · 一種可降半導體裝，該第一第一金屬上並具有空孔，而具有一面護層透空 2 ·如申請專力對I C 絕緣層係或參雜磷 3 ·如申請專力對I C 金屬導線銅金屬或 4 ·如申請專力對I C 保護層係 (PSG)。 5 ·如申請專力對I C 保護層可 6 ·如申請專低因封置，其絕緣層導線層 -第二該第一積較透孔與第利範圍參數偏為氧化之氧化利範圍參數偏層可為鎢金屬利範圍參數偏為氧化裝所產生應力對I 至少係於一矽晶粒上則具有一上具有一第保護層，該保護層與第空孔為大之一金屬導線第1項所述移影響之半矽層（Si02) 石夕層。第1項所述移影響之半銘層、銘銅〇第1項所述移影響之半矽層（Si02) 第一金一保護第二保二保護空氣泡層間以之可降導體裝或爛碟 C參數偏上具有第屬導線層層，該第護層則具層透空孔空洞，以空氟作隔低因封裝置，其中矽坡璃層移影響之一絕緣層，並於該一保護層有若干透相對處則使第二保離。所產生應，該第一 (BPSG ) 之可降低因封裝所產生應導體裝置’其中，該第一合金層、叙矽銅合金層或之可降低因封裝所產生應導體裝置’其中，該第一或參雜瑞之氧化石夕層 # 利範圍第1項所述之可降低因封裝所產生應參數偏移影響之半導體裝置，其中，該第二為気化矽層（Si3N4)或氮氧化矽層（Si0N)。利範圍第1項所述之可降低因封裝所產生應^ 22499 6. Scope of patent application 1 · A semiconductor package that can be lowered. The first first metal has holes in it and has a protective layer that penetrates through the surface 2 · If you apply for IC insulation layer or doped phosphorus 3 · If apply for IC metal conductor copper metal or 4 · If apply for IC protection layer system (PSG). 5 · If you apply for the IC protection layer, you can apply it. · If you apply for low-level encapsulation, the insulation layer wire layer-the second product, the first product, the through hole and the first range parameter, which are more oxidized, and the second range, which is oxidized. The layer may be tungsten metal. The parameter range is the stress generated by the oxidation. I is at least tied to a silicon die and has a first protective layer on the top. The protective layer and the first hole are one of the larger metal wires. The semi-silicon layer (Si02) Shi Xi layer affected by the above-mentioned shift. The semi-silicon layer and copper that are affected by the migration described in item 1. The semi-silicon layer (Si02) that is affected by the migration described in item 1. The first gold one protects the second and the second protects the air bubble layer, so that the conductor can be installed or rotten. The upper part of the parameter C of the disk has a first layer of the conductor layer, and the first protective layer has a layer of through-holes and hollow fluorine as a low-density sealing device. One of the insulating layers is affected by the silicon slope glass layer migration. The protective layer has a number of opposite sides to make the second detachment. The produced response, the first (BPSG) can reduce the stress conductor device produced by the package 'wherein the first alloy layer, the silicon copper alloy layer or the reduced conductor conductor device produced by the package' can be reduced, among which the first A semiconductor device that can reduce the influence of the parameter shift caused by the package as described in item 1 of the scope of the first or second mixed oxide, wherein the second is a silicon oxide layer (Si3N4) or silicon oxynitride Layer (Si0N). The benefits described in Item 1 can reduce the

第14頁Page 14

522499 六、申請專利範圍力對I c參數偏移影響之半導體裝置，其中，該第二保濩層透空孔及第一保護層空氣七空洞之形成位置係相對於矽晶粒上高精密度或高靈敏度之電路位置的上方。 7 ·如申請專利範圍第1項所述之可降低因封裝所產生應力對I C參數偏移影響之半導體裝置，其中，該第二保護層透空孔係可為多邊形之幾何形狀或圓形，其開孔邊長或半徑係為2 - 2 0 /z m，且相鄰之各孔間之間距約為2 - 20 um，而各最外側之透’空孔外側至第二保護層邊緣所須之距離係為各孔間之間距的丨· 5 _ 2俾 8 ·如申請專利範圍第1項所述之可降低因封裝所產生應力對I C參數偏移影響之半導體裝置，其中，該第一保護層之空氣泡空洞係較第二保護層透空孔週^向外大於1 -5 # m。 9 · 一種可降低因封裝所產生應力對I c參數偏移影響之522499 6. The semiconductor device with a patent scope effect on the I c parameter shift, in which the formation position of the second protective layer through hole and the first protective layer air seven holes are relative to the silicon chip with high precision Or above the position of the high-sensitivity circuit. 7 · The semiconductor device capable of reducing the influence of the stress generated by the package on the deviation of IC parameters as described in item 1 of the scope of the patent application, wherein the second protective layer through-hole may be a polygonal geometry or a circle, The length or radius of the side of the opening is 2-2 0 / zm, and the distance between adjacent holes is about 2-20 um, and the outermost through hole must be outside the hole to the edge of the second protective layer. The distance is the distance between the holes 丨 · 5 _ 2 俾 8 · The semiconductor device that can reduce the effect of the stress generated by the package on the deviation of IC parameters as described in the first item of the scope of patent application, wherein the first The air bubble cavity of the protective layer is larger than 1 -5 # m outward than the periphery of the second protective layer through hole. 9 · A method to reduce the influence of package stress on I c parameter shift

半導體裝置’其至少係於一石夕晶粒上具有第一絕緣層，該第一絕緣層上則具有一第一金屬導線層，且於二第一金屬導線層上具有一第二絕緣層，該第二絕緣層上並具有一第二金屬導線層，該第二金屬導^層係與第一金屬導線接觸，而該第二金屬導線層上則具有一第一保護層’該第一保護層上並具有一第二保護芦，該第二保護層則具有若干透空孔，而該第一保護^與第二保護層透空孔相對處則具有一面積較透空孔為大A semiconductor device has at least a first insulating layer on a stone chip. The first insulating layer has a first metal wire layer and a second insulating layer on two first metal wire layers. There is a second metal wire layer on the second insulation layer, the second metal wire layer is in contact with the first metal wire, and the second metal wire layer has a first protective layer 'the first protective layer There is a second protective reed on the top, the second protective layer has a plurality of through holes, and the first protective layer and the second protective layer have a larger area than the through holes.

522499 六、申請專利範圍屬導之空氣泡空洞，以使第二保護層透空孔與第線層間以空氣作隔離。〇 ·如申請專利範圍第9項所述之可降低因封装所產生應力對I C參數偏移影響之半導體裝置，^中，該第二保護層之透空孔可形成於下方具第一 ^屬導G 置’而透空孔與第一金屬導線層間則具有空虱泡空洞。 11 如申請專利範圍第9項所述之可降低因封裝所產生應力對I C參數偏移影響之半導體裝置，其中，兮第一絕緣層及第二絕緣層係為氧化矽層（Si02)或= 磷石夕玻璃層（BPSG)或參雜磷之氧化砂展 12 如申請專利範圍第9項所述之可；：因夕：裝所產生應力對I C參數偏移影響之半導體裝置，复第一金屬冑線層及第二金屬導層係、為紹/銘銅= 金層、鋁矽銅合金層或銅金屬或嫣金屬。一種可降低因封裝所產生應力對丨C參數偏之半導體製造方法’其至少包4下列步驟：’、’ 係於内部已具有電路圖樣及離子極 a 成一第一絕緣層；之ク日日拉上形該第一絕緣層經曝光顯影及蝕刻後，形晶粒表面之接觸窗口；於該第一絕緣層上形成一第一金屬導線層，並％曝光顯影及蝕刻後，形成配線，而該第一金屬導線層形成電極之部分則利用第一、絕緣層之接觸窗口盥石;522499 6. Scope of patent application The air bubble cavity is a guide, so as to isolate the second protective layer through hole from the air layer. 〇 · As described in item 9 of the scope of the patent application, a semiconductor device that can reduce the influence of the stress generated by the package on the deviation of IC parameters, in which the through-holes of the second protective layer can be formed below the first protective layer The guide hole is set, and there is an empty lice bubble cavity between the through hole and the first metal wire layer. 11 The semiconductor device capable of reducing the influence of the stress generated by the package on the deviation of IC parameters as described in item 9 of the scope of the patent application, wherein the first insulating layer and the second insulating layer are silicon oxide layers (Si02) or = Phosphate glass layer (BPSG) or oxidized sand with doped phosphorus 12 can be as described in item 9 of the scope of patent application; The metal hafnium wire layer and the second metal conductive layer are Shao / Ming copper = gold layer, aluminum-silicon-copper alloy layer or copper metal or Yan metal. A semiconductor manufacturing method capable of reducing the bias of the C parameter due to the stress generated by the package, which includes at least the following four steps: ',' is already provided with a circuit pattern and an ion electrode a to form a first insulating layer; After the first insulation layer is exposed, developed, and etched, the contact surface of the crystal grain surface is formed; a first metal wire layer is formed on the first insulation layer, and after exposure and development and etching, wiring is formed, and the The portion of the first metal wire layer forming the electrode uses the first, insulating layer to contact the window lava;

522499 六、申請專利範圍第一保護層已被蝕刻並向外擴展蝕刻至一預定寬度時停止蝕刻，使該第一保護層具有若干空氣泡空二，而第二保護層透空孔與該第二金屬導線層間則利用該些空氣泡空洞以空氣作隔離。 •一種可降低因封裝所產生應力對〗C參數偏移影響之半導體製造方法，其至少包括下列步驟·· 係於内部已具有電路圖樣及離子極區之矽晶粒上形成一第一絕緣層；遠第一絕緣層經曝光顯影及蝕刻後，形成出裸露矽晶粒表面之接觸窗口；於該第一絕緣層上形成一第一金屬導線層，並經曝光顯影及蝕刻後，形成配線，而該第一金屬導線層形成電極之部分則利用第一絕緣層之接觸窗口與石夕晶粒上之離子極區接觸；於該第一金屬導線層上形成一第二絕緣層；該第二絕緣層經曝光顯影及蝕刻後，形成裸露第一金屬導線層之金屬接觸窗口；於第二絕緣層上形成一第二金屬導線層，且將該第二金屬導線層曝光顯影及蝕刻；於該第二金屬導線層上形成一第一保護層；在該第一保護層上形成一第二保護層，該第二保j 層上經曝光顯影及蝕刻後具有若干透空孔’該透二孔形成位置之下方則具有第一金屬導線層；以酸性溶液經第二保護層之透空孔對第一保護層及522499 6. The scope of the patent application The first protective layer has been etched and etched out to a predetermined width to stop etching, so that the first protective layer has a number of air bubbles, and the second protective layer through-holes and the first protective layer The two metal wire layers use these air bubbles to isolate the air. A semiconductor manufacturing method capable of reducing the influence of the stress caused by the package on the C parameter shift, which includes at least the following steps: forming a first insulating layer on a silicon die that has a circuit pattern and an ion electrode region inside ; The first insulating layer is exposed, developed, and etched to form a contact window on the surface of the exposed silicon crystal grains; a first metal wire layer is formed on the first insulating layer, and exposed, developed, and etched to form wiring, The part of the first metal wire layer forming the electrode is in contact with the ionic electrode region on the stone grain using the contact window of the first insulating layer; a second insulating layer is formed on the first metal wire layer; the second After the insulating layer is exposed, developed, and etched, a metal contact window of the exposed first metal wire layer is formed; a second metal wire layer is formed on the second insulating layer, and the second metal wire layer is exposed, developed, and etched; A first protective layer is formed on the second metal wire layer; a second protective layer is formed on the first protective layer, and the second protective layer is formed by exposure, development, and etching. Dry void below 'the through hole formation positions of the two having a first metal wiring layer; a second hole through the protective layer of the acid solution through the first protective layer and

第20頁 522499 六、申請專利範圍第二絕緣層進行蝕刻，當蝕刻時間到達第二保護層透空孔下方之第一保護層及第二絕緣層已被蝕刻並向外擴展蝕刻至一預定寬度時停止蝕刻，使該第一保護層及第二絕緣層具有若干空氣泡空洞，而第二保護層透空孔與該第一金屬導線層間則利用該些空氣泡空洞以空氣作隔離。Page 20 522499 VI. Patent application scope The second insulating layer is etched. When the etching time reaches the first protective layer and the second insulating layer below the second protective layer through hole, the first protective layer and the second insulating layer have been etched and expanded to a predetermined width. At the same time, the etching is stopped, so that the first protective layer and the second insulating layer have a plurality of air bubble cavities, and the air holes are used for the air separation between the second protective layer through holes and the first metal wire layer.

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