TW522356B

TW522356B - Liquid crystal display device with built-in driving circuit corresponding to digital image signal input

Info

Publication number: TW522356B
Application number: TW88119625A
Authority: TW
Inventors: Hiroshi Kageyama; Hideo Sato; Yoshiaki Mikami; Tatsuya Okubo
Original assignee: Hitachi Ltd
Priority date: 1998-11-10
Filing date: 1999-11-10
Publication date: 2003-03-01
Also published as: JP2000148096A; KR20000035327A

Abstract

The purpose of the present invention is to provide a liquid crystal display device formed with a TFT by giving the circuit constitution that the threshold voltage of the TFT doesn't affect the voltage precision, thereby reducing the number of elements and reducing a circuit area. All circuit elements existing in current routes supplying an analog voltage from an analog voltage input part to a drain line in a drain driver are constituted of analog switches containing analog multiplexers. Furthermore, the drain driver is constituted of a first circuit controlled by the high-order bit of the image data and a second circuit controlled by the low-order bit of the image data, and the first circuit selects/outputs plural analog voltages supplied from the analog voltage input part, and the second circuit is provided with the circuit sampling the output voltage of the first circuit to the drain line at the prescribed timing.

Description

522356 A7 ______B7 五、發明説明（） 1 (本發明所屬之技術領域）本發明係有關於一種內藏有周邊電路之液晶顯示裝置 (請先閲讀背面之注意事項再填寫. 〇 (習知技術） -口以往的液晶顯示裝置，作多灰階顯示的技術有特開平 5 - 3 5 2 0 0號公報。而與本發明有直接關係的部分則表示在第2 1圖。4 1爲第1顯示電壓產生手段，4 2爲弟2顯不電壓產生手段》4 3爲線依序時序電路。線依序時序電路43係由電容器44、45與開關電路46，輸出緩衝器4 7所構成。藉由第1顯示電壓產生手段4 1與第2顯示電壓產生手段4 2來產生多灰階的電壓，而所產生的電壓則爲電容器4 4所保持，依據鎖存（latch )信號的時間，在電容器4 5實施取樣。而在電容器4 5被取樣的電壓，則在輸出緩衝器4 7中被放大而輸出。 (本發明想要解決的課題）經濟部智慧財產局員工消費合作社印製薄膜電晶體（以下簡稱爲TFT)的閾値電壓會因爲 TFT而各有不同，或是變化激烈。因此，用於放大利用 T F T而作成的電流放大電路或是電壓放大電路等之類比電壓的緩衝電路，則難以提升輸出的電壓精度。因此，當以T F T來構成緩衝器4 7時，則輸出電壓精度會變差，而會對顯示畫像帶來惡劣的影響。又’當省略輸出緩衝器 4 7時，爲了要輸出高精度的電壓’則必須要加大電容器本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） — -4- 522356 A7 B7 五、發明説明（） 2 44與45的電容，由於電容器44、 45成爲大面積， (請先閱讀背面之注意事項再填寫· 因此，驅動器的電路面積會變大。基於以上的理由’第 2 1圖的構成很難應用在以T F T所形成驅動電路。本發明之目的在於提供一種藉著具有T F T的閾値電壓的個體差或經時變化不會對電壓精度造成影響之電路構成，可以以T F T來製作’且能夠減少元件數目’而減低電路面積的液晶顯示裝置。 (解決課題的手段）、π 線經濟部智慧財產局員工消費合作社印製在本發明中，在汲極驅動器內，位在從類比電壓輸入部，將類比電壓供給到汲極線之電流路徑上的電路元件’ 全部是由包含類比多工器在內之類比開關所構成。更者，汲極驅動器係由被畫像資料之上位位元所控制的第1電路，以及被畫像資料之下位位元所控制的第2電路所構成，第1電路乃將從類比電壓輸入部所供給的多個的類比電壓予以選擇輸出，而第2電路，則具備有針對上述第1電路的輸出，依據一定的時點，在汲極線取樣（s a m p 1 i n g )電壓的電路。更者，在本發明中，上述多工器係由與上述類比多工器相同的電路構成所形成。更者，畫像資料的上位j位元與畫像資料之下位k位元，當畫像資料的位元數m爲偶數時，則分成j = k的相同的位元數，而當畫像位元數m爲奇數時，則分成具有j = k + l或+1之關係的位元數。本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） " -5- 522356 經濟部智慧財產局員工消費合作社印製 A7 __B7__五、發明説明（） 3 (發明之實施形態）第1圖係表本發明之實施例。在絕緣基板1的表面具有由呈矩陣狀被配置之汲極線D L、閘極線G L、以及被配置在汲極線D L與閘極線G L之各交點的畫素T F T 5 、顯示電極D X所構成之顯示領域2，利用T F T所構成之汲極驅動器3、閘極驅動器4、記憶體7。在第1圖中，爲了要易於了解液晶顯示裝置之構成，雖然汲極線D L 與閘極線G L的數目各只舉出2條，但是實際上卻是有多條，例如對於橫6 4 Ο X縱4 8 Ο X R G B的V G A尺寸的液晶顯示裝置而言，閘極線G L有4 8 0條、汲極線 D L 有 1 9 2 0 條。汲極驅動器係由：由類比信號匯流排V R 〇〜V R 3 、類比信號輸入部8、多個的類比多工器Μ P 1所構成的第1電路C C 1、以及由脈衝信號匯流排ΤΡ 〇〜ΤΡ 3 與脈衝信號輸入部9、多個的多工器ΜΡ2、多個的類比開關A SW所構成之第2電路C C 2而構成。類比多工器 Μ P 1、多工器Μ P 2、類比開關A S W，則針對1條汲極線D L各有1個元件。將被記憶在記憶體7之m位元的畫像資料分成上位j 位兀、下位k位兀，根據上位j位元的資料來選擇類比多工器ΜΡ 1 ，而根據下位k位元來選擇多工器Mp 2。m 、j、k 的關係則爲 m^j+k，j^l j、k雖然是只要是自然數皆可，但是在實施例中，係一本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ' -6- (請先閲讀背面之注意事項再填寫〕522356 A7 ______B7 V. Description of the invention () 1 (Technical field to which the present invention belongs) The present invention relates to a liquid crystal display device with a built-in peripheral circuit (please read the precautions on the back first and then fill in. 〇 (Learning Technology) -Conventional liquid crystal display device, multi-gray level display technology is disclosed in Japanese Patent Laid-Open No. 5-3 5 2 0 0. The parts directly related to the present invention are shown in Fig. 21. 4 1 is the first The display voltage generation means, 42 is the second display voltage generation means. "4 3 is a line sequential circuit. The line sequential circuit 43 is composed of capacitors 44, 45, a switch circuit 46, and an output buffer 47. The first display voltage generating means 41 and the second display voltage generating means 42 are used to generate a multi-gray-scale voltage, and the generated voltage is held by the capacitor 44, according to the time of the latch signal, Sampling is performed in the capacitor 45. The voltage sampled in the capacitor 45 is amplified and output in the output buffer 47. (Problems to be Solved by the Invention) The Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumer Cooperative Printed Film Transistor (Hereinafter referred to as TFT) the threshold voltage can be different depending on the TFT, or it can change drastically. Therefore, it is difficult to increase the buffer voltage of the analog voltage buffer circuit, such as a current amplifier circuit or a voltage amplifier circuit, which is created using the TFT. Output voltage accuracy. Therefore, when the buffer 47 is constituted by a TFT, the output voltage accuracy will be deteriorated, which will adversely affect the displayed image. Also, when the output buffer 47 is omitted, To output a high-precision voltage, you must increase the capacitor. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) — -4- 522356 A7 B7 V. Description of the invention () 2 44 and 45 capacitors, The capacitors 44 and 45 have a large area. (Please read the precautions on the back before filling in. Therefore, the circuit area of the driver will increase. For the above reasons, the structure of Figure 21 is difficult to apply to the driving circuit formed by TFT. The object of the present invention is to provide a circuit configuration that does not affect the voltage accuracy by the individual difference of the threshold voltage of the TFT or the change with time. A liquid crystal display device made of TFTs that can reduce the number of components and reduce the circuit area. (Means for solving problems) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs in the present invention, in the drain driver The circuit elements located in the current path that supplies the analog voltage to the drain line from the analog voltage input section are all composed of analog switches including an analog multiplexer. Furthermore, the drain driver is composed of The first circuit controlled by the upper bit of the image data and the second circuit controlled by the lower bit of the image data. The first circuit is selected from a plurality of analog voltages supplied from the analog voltage input unit. The second circuit is provided with a circuit that samples the voltage at the drain line according to a certain point in time with respect to the output of the first circuit. Furthermore, in the present invention, the multiplexer is formed by the same circuit configuration as the analog multiplexer. Furthermore, the upper j bits of the portrait data and the lower k bits of the portrait data. When the number of bit m of the portrait data is even, it is divided into the same number of bits of j = k, and when the number of portrait bits m When the number is odd, it is divided into the number of bits with the relationship of j = k + l or +1. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) " -5- 522356 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 __B7__ V. Description of the invention () 3 (Implementation form of the invention) Section Figure 1 shows an embodiment of the present invention. On the surface of the insulating substrate 1, there are drain lines DL, gate lines GL arranged in a matrix, pixel TFTs 5 and display electrodes DX arranged at the intersections of the drain lines DL and GL. The display area 2 is composed of a drain driver 3, a gate driver 4, and a memory 7 composed of TFTs. In FIG. 1, in order to easily understand the structure of the liquid crystal display device, although the number of the drain lines DL and the gate lines GL is only two each, there are actually many. In the case of a liquid crystal display device of VGA size of X vertical 4 8 0 XRGB, there are 480 gate lines GL and 192 drain lines DL. The drain driver is composed of a first circuit CC 1 composed of analog signal buses VR 0 to VR 3, an analog signal input section 8, a plurality of analog multiplexers MP1, and a pulse signal bus TP 〇 ~ TP 3 is constituted by a second circuit CC 2 constituted by a pulse signal input unit 9, a plurality of multiplexers MP2, and a plurality of analog switches ASW. Analog multiplexer MP 1, multiplexer MP 2, and analog switch A SW have one element for each drain line D L. The m-bit image data stored in the memory 7 is divided into upper j-bit and lower k-bit, and the analog multiplexer MP 1 is selected according to the data of the upper j-bit.工器 Mp 2. The relationship between m, j, and k is m ^ j + k. Although j ^ lj and k are all natural numbers, in the embodiment, the paper size applies the Chinese National Standard (CNS) A4 specification ( 210X297 mm) '-6- (Please read the precautions on the back before filling in]

、11 線 522356 A7 _B7____ 五、發明説明（） 4 分成影像資料的位元數m爲4位元，上位位元數〗爲2位元，下位位元數k爲2位元的例子。構成第一電路之類比多工器Μ P 1全部連接到類比信號匯流排V R 0〜V R 3，而根據記億體7所記憶之影像資料的上位j = 2位元來作選擇動作。類比信號匯流排 V R 〇〜V R 3有2 △ j條，在實施例中，由於」·二2 ’因此有4條。又，構成第2電路之多工器Μ P 2全部連接到脈衝信號匯流排，而根據記憶體7所記憶的影像資料的下位k = 2位元來作選擇動作。脈衝信號匯流排有2 Λ k條’在實施例中，由於k = 2，因此有4條。類比多工器Μ P 1的輸出，則經由類比開關A S W ’ 而連接到汲極線D L。類比開關A S W的〇N /〇F F係根據多工器MP 2的輸出電壓位準而被控制。在實施例中，當多工器Μ P 2的輸出爲高位準（Η )，類比開關 ASW爲ON，而當低位準（L)時，則成爲OFF。在汲極線D L具有作爲汲極線D L本身所擁有之靜電電容的汲極線電容CD，當類比開關ASW爲OF F時，則具有保持汲極線D L之電壓的作用。第2圖係表由丁FT所形成之類比多工器MP1與使用在多工器MP 2的2位元的類比多工器的電路圖。在實施例中，多工器MP 2使用類比工器，係一完全與類比多工器Μ P 1相同的構告。第2圖的類比多工器係由4個將使汲極-源極彼此連本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） (請先閲讀背面之注意事項再填寫本頁) 、1Τ 線經濟部智慧財產局員工消費合作社印製 522356 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（） 5 接般而2個呈串聯連接的η通道型TFT，與同樣地2個呈串聯連接之P通道型T F T設成一對之轉送閘1 〇所構成，連接4個轉送聞1 0之其中一端而設成輸出端子 A 〇 u t ’而將各自之另一觸設成A 〇〜A 3的輸入端子〇藉著使選擇信號B〇，B1 ，對應於二位元碼，交互地連接到構成4個轉送閘之T F T的閘極，而如第3圖所示，可以根據2位元的數位選擇信號來選擇A 〇〜A 3的信號。在B 0、B 1的記號畫上上線的記號，則是表示b 〇、B1的反轉信號。雖然在驅動第2圖的多工器時，選擇信號B 0、B 1會在記憶體7的輸出也準備好反轉信號，但是當不能夠準備時，則可以藉著在記憶體7的輸出附設第4圖所示的電路，來產生反轉信號。又，第2圖雖然是2位元的例子，但是當構成η位元的類比多工器時，則將η個構成轉送閘1 〇的τ F Τ加以串聯連接’而將2 η個的轉送閘設成1組而構成。第5圖係表類比開關A SW的電路圖。類比開關 ASW是由用來製作構成轉送閘11的n通道型 TFT12、 ρ通道型TFT13，以及ρ通道TFT之驅動信號的反相器1 4所構成。第5圖之類比開關電路，當控制輸入（G )爲高位準 (Η )時，則類比開關兩端A — Y間成爲連接狀態〇N，而當控制輸入G爲低位準（L )時，則類比開關兩端A — 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公董) " -8 - (請先閱讀背面之注意事項再填寫一11, line 522356 A7 _B7____ 5. Description of the invention (4) The number of bits m divided into image data is 4 bits, the number of upper bits is 2 bits, and the number of lower bits k is 2 bits. The analog multiplexers MP1 constituting the first circuit are all connected to the analog signal buses V R 0 to V R 3, and the selection operation is performed based on the upper j = 2 bits of the image data memorized by the recorder 7. There are 2 Δj analog signal buses V R 0 to V R 3. In the embodiment, there are 4 since "· 2 2 '". Moreover, all the multiplexers MP2 constituting the second circuit are connected to the pulse signal bus, and the selection operation is performed based on the lower k = 2 bits of the image data stored in the memory 7. The pulse signal bus has 2 Λ k bars. In the embodiment, since k = 2, there are 4 bars. The output of the analog multiplexer MP1 is connected to the drain line DL via the analog switch ASW '. The ON / OFF F system of the analog switch A SW is controlled according to the output voltage level of the multiplexer MP 2. In the embodiment, when the output of the multiplexer MP 2 is at a high level (Η), the analog switch ASW is ON, and when it is at a low level (L), it becomes OFF. The drain line D L has a drain line capacitance CD which is an electrostatic capacitance possessed by the drain line D L itself. When the analog switch ASW is OF F, it has the function of maintaining the voltage of the drain line D L. Fig. 2 is a circuit diagram showing an analog multiplexer MP1 formed by D-FT and a 2-bit analog multiplexer used in the multiplexer MP2. In the embodiment, the multiplexer MP 2 uses an analog multiplexer, which is exactly the same as the analog multiplexer MP 1. The analog multiplexer in Figure 2 consists of 4 drain-source connections. The paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) (Please read the precautions on the back before filling this page. ) 、 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the 1T line 522356 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () 5 Two n-channel TFTs connected in series are the same The two grounded P-channel TFTs connected in series are set as a pair of transfer gates 10, and one of the four transfer channels 10 is connected to one end and set as an output terminal A 0ut '. The input terminals 〇 to A 〇 ~ A 3 are alternately connected to the gates of the TFTs constituting the four transfer gates by making the selection signals B0, B1 corresponding to the two-digit code, and as shown in FIG. 3, The signals of A 0 to A 3 can be selected based on a 2-bit digital selection signal. Marking the lines B 0 and B 1 with an on-line mark indicates the inverted signals of b 0 and B1. Although the selection signals B 0 and B 1 are also ready to be inverted at the output of the memory 7 when the multiplexer of FIG. 2 is driven, when it cannot be prepared, the output of the memory 7 can be used. The circuit shown in Figure 4 is attached to generate an inverted signal. In addition, although FIG. 2 is an example of two bits, when η-bit analog multiplexers are configured, η τ F τ constituting transfer gates 10 is connected in series to transfer 2 η The gates are configured in one group. Figure 5 is a circuit diagram of the analog switch A SW. The analog switch ASW is composed of an n-channel TFT 12, a p-channel TFT 13, and an inverter 14 for driving signals for the p-channel TFT. In the analog switch circuit of FIG. 5, when the control input (G) is at a high level (Η), the two ends of the analog switch A to Y become connected ON, and when the control input G is at a low level (L), Then the ends of the analog switch A — This paper size applies to China National Standard (CNS) A4 specifications (210X297 public director) " -8-(Please read the precautions on the back before filling in one

訂線 522356 經濟部智慧財產局員工消費合作社印製 A7 B7 _五、發明説明（） 6 Y間成爲開放狀態〇F F。當讓控制輸入G之H / L狀態與類比開關之〇N / 〇F F之對應關係反轉時，則可以讓T F Τ 1 2與 TFT13的η型、ρ型反轉。液晶顯示裝置，針對畫像資料，藉著將相對於中心電壓V c呈對稱之+以及-方向的電壓交互地施加在顯示電極上，可以得到明暗對應於電壓振幅的影像。在第1圖的實施例中，由於m二4位元’必須要顯示具有2 Λ m = 1 6 灰階之明暗的顯示，因此必須要供給1 6階段的電壓。更者，爲了要從中心電壓V c呈對稱地產生交流，因此要供給成倍的3 2階段的電壓。第7圖係表輸入到第1圖之實施例之類比信號匯流排 VRO〜VR3，以及脈衝信號匯流排ΤΡ〇〜TP3的波形。而呈週期性地將（A )以及（B )的波形反覆地輸入到類比信號匯流排V R 〇〜V R 3。被輸入到類比信號匯流排C R 〇〜C R 3的信號，則是一使在1 6個階段的電壓中鄰接的4個階段的電壓隨著時間變化的波形。在類比信號匯流排V R 〇〜V R 3的波形中，4個階段的電壓變化的時點，即是在1行期間內之從T 〇到T 4之間的Τ 1、T 2、T 3。在脈衝信號匯流排Τ P 〇〜Τ P 3，則被輸入有具有局位準（H)與低位準（L )的2個狀態，且具有不同脈寬的脈衝波形。脈衝信號匯流排Τ P 0〜丁 P 3的脈衝波形。雖然上升的時間係在1行期間之始端T 〇附近，但是本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -- (請先閱讀背面之注意事項再填寫·Order line 522356 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 _V. Description of the invention (6) Room Y becomes open. When the corresponding relationship between the H / L state of the control input G and the ON / OFF of the analog switch is reversed, the TF and η types of T F T 1 2 and TFT 13 can be reversed. The liquid crystal display device, by applying a voltage symmetrical to the + and-directions with respect to the center voltage V c to the display electrodes with respect to the image data, can obtain a light and dark image corresponding to the voltage amplitude. In the embodiment of FIG. 1, since m = 4 bits' must display a display with 2 Λ m = 16 gray levels, it is necessary to supply a voltage of 16 stages. In addition, in order to generate alternating current symmetrically from the center voltage V c, a voltage of 32 times is supplied in multiples. Fig. 7 shows the waveforms of the analog signal buses VRO ~ VR3 and the pulse signal buses TPO ~ TP3 input to the embodiment of Fig. 1. The waveforms of (A) and (B) are repeatedly input to the analog signal buses V R 0 to V R 3 periodically. The signal input to the analog signal buses C R 0 to C R 3 is a waveform in which the voltages of the four phases adjacent to the sixteen phases of voltages change with time. In the waveforms of the analog signal buses V R 0 to V R 3, the time point of the voltage change in the four stages is T 1, T 2, T 3 from T 0 to T 4 during a period of one line. On the pulse signal buses T P 0 to T P 3, two states having a local level (H) and a low level (L) are input, and pulse waveforms with different pulse widths are input. Pulse waveforms of the pulse signal buses T P 0 to D 3. Although the rise time is near T 〇 at the beginning of the 1-line period, this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)-(Please read the precautions on the back before filling in ·

、1T 線 -9- 522356 A7 B7 五、發明説明（） 7 (請先閲讀背面之注意事項再填寫. 下降的時間，則分別爲T a、T b、T c、T d。但是具有 T〇<Ta<Tl，Tl<Tb<T2，T2<Tc< T3，T3<Td<T4 的關係。、 1T line-9- 522356 A7 B7 V. Description of the invention () 7 (Please read the precautions on the back before filling in. The falling time is T a, T b, T c, T d. But it has T. < Ta < Tl, Tl < Tb < T2, T2 < Tc < T3, T3 < Td < T4.

、1T 線經濟部智慧財產局員工消費合作社印製接著則說明在顯示電極p X施加電壓之具體的動作。第8圖係表當類比信號匯流排V R 0〜V R 3的波形爲（ A )，而被記憶在記憶體7內之畫像資料爲「9」時之各部分之電壓變化的說明圖。此時，應該被輸出到D L的電壓，則是與畫像資料「9」呈對應的電壓V c + V 9。由於將「9」二値化成二元碼時，則成爲（1〇〇1)，而影像信號的上位2位元（1 〇 ) =「2」、下位2位元（ 01) =「1」，因此，類比工器MP1選擇類比信號匯流排V R 2，而類比多工器M p 2選擇脈衝信號匯流排 TP1〇VR2的電壓，則在T1〜T3的時點，從Vc + V1 1變化到V c+V8的電壓値。TP 1的電壓，到丁 c之前爲高位準’而從T c開始成爲低位準（L )。從 T0附近到T c爲止’由於VR 1爲高位準’類比開關爲〇N，因此，汲極線D L的電壓會追蹤VR 1電壓波形。在T c ，由於VR 1成爲低位準’而類比開關A sw成爲 OFF，因此，汲極線DL會與VR1分離。在Tc的時點，汲極線D L的電壓V c + V 9由於在汲極線D L具有汲極線本身所擁有的靜電電容C D ’因此’從Τ c到Τ 4 ，可以維持在T c時的電壓V c +V 9。以上所說明的動作’雖然是指被記憶在記憶體7內的畫像資料爲「9」的情形，但是畫像資料從「〇」到「本紙張尺度適用中國國家標準（CNS ) A4規格（210x297公董） -10- 522356 A7 B7 五、發明説明（ 8 1 5」的時候也是極線D L產生與畫 V 5的電壓。又，當爲第7 針對畫像資料^ 0 線D L可以產生與 V 1 5的電壓。第9圖係表在電壓波形。在1個 G L，則根據從閘，而在各自對應的準。在1行期間內相同。最遲，在T d的時點，可以在汲像資料呈對應之從v c + V 〇到V c + 圖（B )時，根據以上所說明的動作，」到「1 5」，在T d的時點，在汲極Line 1T Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, the specific operation of applying a voltage to the display electrode p X will be described. FIG. 8 is an explanatory diagram showing changes in voltage of each part when the waveform of the analog signal buses V R 0 to V R 3 is (A), and the image data stored in the memory 7 is “9”. At this time, the voltage to be output to D L is a voltage V c + V 9 corresponding to the image data “9”. When "9" is converted into a binary code, it becomes (1001), and the upper 2 bits of the video signal (1 0) = "2" and the lower 2 bits (01) = "1" Therefore, the analog multiplexer MP1 selects the analog signal bus VR 2 and the analog multiplexer M p 2 selects the voltage of the pulse signal bus TP1〇VR2, and then changes from Vc + V1 1 to V at the time point of T1 ~ T3. c + V8 voltage 値. The voltage of TP 1 is at a high level before Tc, and it becomes a low level (L) from Tc. From T0 to Tc, since VR 1 is at a high level, the analog switch is ON. Therefore, the voltage of drain line D L will track the voltage waveform of VR 1. At T c, since VR 1 goes low and the analog switch A sw goes OFF, the drain line DL is separated from VR1. At the time of Tc, the voltage V c + V 9 of the drain line DL has the electrostatic capacitance CD 'thereby' possessed by the drain line itself at the drain line DL, so that it can be maintained at T c from T c to T 4. Voltage V c + V 9. Although the action described above refers to the case where the image data stored in the memory 7 is "9", the image data ranges from "0" to "this paper size applies the Chinese National Standard (CNS) A4 specification (210x297) Dong) -10- 522356 A7 B7 V. Description of the invention (8 1 5 "is also the voltage generated by the polar line DL and draws V 5. When it is the seventh for the portrait data ^ 0 The line DL can be generated with V 1 5 Figure 9 shows the voltage waveforms. At 1 GL, the corresponding voltages are based on the slave gates. It is the same during 1 row. At the latest, at the time of T d, the data can be acquired. In the corresponding graph (B) from vc + V 〇 to V c +, according to the actions described above, "" to "1 5", at the time of T d, at the drain

畫像資料呈對應的VCorresponding V for portrait data

V 0到V 1個圖場期間之閘極線G L與各部分之圖場期間有多個的1行期間。爲個閘線驅動器4所輸出之信號GL 1〜GLn 1行期間# 1〜# η，成爲1次的高位，閘極線G L之脈衝的上升最遲要在與已經成爲高位準的閘極線G L連接的請先閱讀背之注意事項再經濟部智慧財產局員工消費合作社印製 T d之前完成，而橫一列的畫素TFT5成爲ON ’更者’連接的橫一列的顯示電極P X與各汲極線D L ’則成爲連接狀態。當閘極線G L爲高位準（Η )的期間，顯示電極P X的電壓會追蹤汲極線D L的電壓。藉由位在閘極線G L之脈衝之T d 後的下降，橫一列的畫素TFT5成爲OFF，更者’連接之橫-列的顯示電極P X畫素成爲浮動狀態。閘極線 G L的脈衝在下降時的汲極線D L的電壓’則爲顯示電極 P X所擁有的顯示電極電容C P所保持’且被保持到直到連接的閘極線G L再度成爲高位準爲止。當1個圖場期間結束時，則將一定的電供給到全部的顯示電極P X，而可本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -11 - 522356 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（） 9 以顯示任意的畫像。第1 0圖係表第7圖之類比信號波形（A )以及（B )的出現型態例。藉著讓（A )以及（B )的類比信號’ 依據第1 0圖所示之型態來出現’可以進行顯示電極p X 的交流化。根據第1 〇圖（a )可進行各圖框反轉驅動’ 而根據第1 〇圖（b )可進行各行反轉驅動。第1 1圖係表在設置2個系統的類比信號匯.流排的實施例中，汲極驅動器之部分的說明圖。汲極驅動器以外的部分則與第1圖的實施例相同。類比信號匯流排V R 0 〇〜V R 3 〇，則連接到與第奇數個的汲極線呈對應的類比多工器MP 1 〇，而類比信號匯流排VR〇 e〜VR3 e ，則連接到與第偶數個的汲極線呈對應的類比多工器 Μ P 1 e。在第11圖中，雖然VROo〜VR30以及 VROe〜VR3e ，係供給與第7圖之（A)以及（B )的VR0〜VR3相同的波形，但是也可以當VR〇〇〜VR3〇爲（A)時，則 VROe 〜VR3e 爲（B) ，相反地，當VROo〜VR3〇爲（B)時，貝[J VROe 〜VR3e 爲（A)。第1 2圖係表第7圖之類比信號波形（A )以及（B )的出現型態例。藉著讓（A )以及（B )的類比信號’ 依據第1 2圖所示的型態而出現，來進行顯示電極電壓 P X的交流化。根據第1 2圖（a )可進行各列反轉驅動，而根據第1 2圖（a )可進行各點反轉驅動。本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫·There are a plurality of one-line periods between the gate line G L in one field period from V 0 to V and the field period of each part. The signals GL 1 to GLn output by the gate line driver 4 during the 1-line period # 1 to # η become the high level once. The rise of the pulse of the gate line GL must be at the latest with the gate line that has already reached the high level. Please read the precautions for the GL connection before completing the printing of T d by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the pixel TFT5 in the horizontal row becomes ON. The epipolar line DL 'is connected. While the gate line G L is at a high level (Η), the voltage of the display electrode P X will track the voltage of the drain line D L. By falling after T d of the pulse of the gate line G L, the pixel TFT5 of the horizontal column becomes OFF, and the display electrode P X of the horizontal column is connected to a floating state. The voltage of the drain line D L when the pulse of the gate line G L falls is held by the display electrode capacitance C P possessed by the display electrode P X and is held until the connected gate line G L again reaches a high level. When one field period ends, a certain amount of electricity is supplied to all display electrodes PX, but this paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -11-522356 Intellectual Property Bureau of the Ministry of Economic Affairs Employee Consumer Cooperatives printed A7 B7 V. Invention Description (9) to display arbitrary portraits. Fig. 10 is an example of appearance patterns of analog signal waveforms (A) and (B) in Fig. 7 of the table. By allowing the analog signals of (A) and (B) to appear according to the pattern shown in FIG. 10, the display electrodes pX can be exchanged. The frame inversion driving can be performed according to FIG. 10 (a) and the line inversion driving can be performed according to FIG. 10 (b). Fig. 11 is an explanatory diagram of a portion of a drain driver in an embodiment in which analog signal buses and busbars of two systems are provided. The parts other than the drain driver are the same as those in the first embodiment. The analog signal buses VR 0 ～ VR 3 〇 are connected to the analog multiplexer MP 1 〇 corresponding to the odd number of drain lines, and the analog signal buses VR 0e ~ VR3 e are connected to the The even-numbered drain lines are corresponding analog multiplexers MP1e. In Fig. 11, although VROo ~ VR30 and VROe ~ VR3e provide the same waveforms as VR0 ~ VR3 of Fig. 7 (A) and (B), they can also be used when VR〇～ VR3〇 is (A ), Then VROe ~ VR3e is (B). Conversely, when VROo ~ VR3o is (B), [J VROe ~ VR3e is (A). Fig. 12 is an example of appearance patterns of analog signal waveforms (A) and (B) in Fig. 7 of the table. By making the analog signals ′ of (A) and (B) appear according to the pattern shown in FIG. 12, the display electrode voltage P X is exchanged. According to FIG. 12 (a), each column can be inverted for driving, and according to FIG. 12 (a), each point can be inverted for driving. This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling in.

、1T -線 -12- 522356 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（） 10 用來驅動第1圖以及第11圖之實施例之第7圖所示的類比信號匯流排與脈衝信號匯流排的信號波形’則至少其中一者可以在汲極驅動器3的內部製作。第1 3圖係表將類比信號產生電路A S G設在汲極驅動器3內的實施例，係表汲極驅動器3之部分。汲極驅動器以外的部分，則與第1圖的實施例相同。類比信號產生電路A S G係設在類比信號輸入部2 0與類比信號匯流排 V R 0〜V R 3之間。第1 4圖係表類比信號產生電路A S G的電路圖。類比信號產生電路ASG ’係由具有8個電路之j = 2位元選擇的類比多工器2 1 ，與具有4個電路之1位元選擇的類比多工器2 2所構成。類比多工器2 1使用第2圖的電路，而類比多工器 2 2，則使用第1 5圖所示的電路。類比信號輸入部2 0具有3 2個端子，從外部供給從基準電壓Vc+V15到Vc+V〇，以及從Vc — VI 5到Vc — V〇之32個階段的固定電壓。SA0、 SA1爲用來表現多重化之時刻ΤΟ、 ΤΙ、 T2、 T3 、T 4的二位元信號，而根據第1 6圖所示的時點來供給信號。 I V爲A / B的切換信號輸入，根據I V的狀態來決定要產生A以及B之那一個波形。藉著將以上之從VC+V15到Vc+VO、以及從 Vc— V15 到 Vc— V〇、SA〇、SA1、 IV 的信請先閱讀背面之注意事項再填、 1T -line-12- 522356 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of invention () 10 Used to drive the analog signal bus shown in Figure 7 of the embodiment of Figure 1 and Figure 11 At least one of the signal waveforms of the bus and the pulse signal bus can be produced inside the drain driver 3. FIG. 13 shows an embodiment in which the analog signal generating circuit A S G is provided in the drain driver 3, and is a part of the drain driver 3. The parts other than the drain driver are the same as the embodiment shown in FIG. The analog signal generating circuit A S G is provided between the analog signal input section 20 and the analog signal buses V R 0 to V R 3. Figure 14 is a circuit diagram of the analog signal generating circuit A S G. The analog signal generating circuit ASG 'is composed of an analog multiplexer 2 1 having 8 circuits selected by j = 2 bits, and an analog multiplexer 2 2 having 1 circuits selected by 4 circuits. The analog multiplexer 21 uses the circuit of FIG. 2, and the analog multiplexer 22 uses the circuit of FIG. 15. The analog signal input section 20 has 32 terminals, and externally supplies a fixed voltage of 32 stages from a reference voltage Vc + V15 to Vc + V0 and from Vc-VI 5 to Vc-V0. SA0 and SA1 are two-bit signals used to represent multiple times T0, T1, T2, T3, and T4, and the signals are supplied according to the time points shown in FIG. I V is the switching signal input of A / B. According to the state of I V, it is decided which waveform of A and B is to be generated. By writing the above letters from VC + V15 to Vc + VO, and from Vc- V15 to Vc- V0, SA〇, SA1, IV, please read the notes on the back side first and then fill in

訂線本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 13- 522356 A7 B7 經濟部智慧財產局員工消費合作社印製五、發明説明 () 1 11 1 I 號供給到類比信號產生電路A S G ，可以使類比信號匯流 1 1 排 V R 0 到 VR3產生如第7圖之類比信號匯流排 V R 0 1 V R 3 的波形。請 1 先 1 第 1 7 圖係表將脈衝信號產生電路P S G 設在汲極驅閱讀 1 背 1 動器3 內的實施例，係表示汲極驅動器3的部分〇而汲極面之 1 I 驅動器 3 以外的部分，則與第1圖的實施例相同〇脈衝信 /土意事 rS 1 1 1 Prfe Wu 產生電路 p s G則連接到脈衝信號匯流排T F 丨0 工貝再填 1 1 T Ρ 3 〇寫 t丨第 1 8 圖係表脈衝信號產生電路P S G的電路圖〇脈 1 | 衝信號產生電路PSG，係由4個的 N A N D 閘 2 6 與 3 1 I 個的反相器 2 5所構成。S B 0、 S B 1爲用來表現 T a 1 1 信號，而根第訂 T b T c、T d時刻的二位元據 1 9 圖 1 所示的時點來供給信號。 1 1 藉著將 SB〇、SB1的信號供給到脈衝信號產生電 1 | 路，可以產生如第7圖所示之脈衝信號匯流排T ' P 0 1 線 Τ P 3 的脈衝信號。根據k = 2位元的位址信號來產生 4 ( 個具有不同脈寬之脈衝。脈衝產生電路也可以當作外部電 1 路，而不包含在液晶顯示裝置內。 1 1 此外 j 以上說明之反相器係根據第2 2圖 ( a ) 而 1 I Ν AN D 閘，則根據第2 2圖（b〕 >所示的電路，利 1用 1 1 I Τ FT 來構成。 1 1 I 第 2 0 圖（a )係表從供給第 1圖之實施例之類比電 1 1 壓的汲極驅動器3到汲極線爲止的路徑，與位在路徑之 1 1 Τ FT 元件之連接關係的說明圖。 1 1 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -14 - 522356 A7 B7 五、發明説明（ 12 經濟部智慧財產局員工消費合作社印製被輸入到類比信號輸入部8的信號，則通過類比信號匯流排VRO〜VR 3之其中任一者，類比多工器MP 1 ，以及經由類比開關A S W的路徑3 0，而被供給到汲極線D L。又，當內藏有類比信號產生電路A S G時，則位於第 2 0圖（b )所示的路徑，而被輸入到類比信號輸入部 2 0的信號，則通過類比信號產生電路A S G，.類比信號匯流排VRO〜VR3之其中任一者，類比多工器MP 1 ，以及經由類比開關A S W的路徑3 1 ，而被供給到汲極線 D L。類比信號，由於是通過將T F T之汲極-源極間呈串聯連接的多個類比開關而被供給，因此，畫素電極之電壓精度，雖然會因爲T F T之ON電阻與在汲極驅動器內的配線電阻，以及顯示電極電容C D所造成的信號延遲而受到影響，但是藉著設成不與TFT的閾値電壓有關，而最適當地設計信號延遲時間，可以實現一高精度地作安定動作的電路。因爲T F T的0 N電阻，在汲極驅動器內的配線電阻，以及顯示電極電容CD，使得汲極線DL的電壓，在 ΤΙ、 T2、 T3的電壓變化點會發生信號延遲。電壓變化愈大，則愈會影響到汲極線的電壓精度。藉著依序供如第7圖之類比信號匯流排VR0〜VR3般鄰接的電壓’ 可以減少電壓精度因爲在ΤΙ、 T2、 T3的電壓變化點請先閱讀背面之注意事項再The paper size of the booklet is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) 13- 522356 A7 B7 Printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy The circuit ASG can make the analog signal buses 11 1 VR0 to VR3 generate the waveform of the analog signal bus VR 0 1 VR 3 as shown in FIG. 7. Please refer to the first embodiment. Figure 1 shows the example where the pulse signal generating circuit PSG is set in the drain driver. 1 The back 1 driver 3 shows the part of the drain driver 3 and the 1 on the drain side. The parts other than 3 are the same as in the embodiment of FIG. 0. The pulse signal / earthly matter rS 1 1 1 Prfe Wu The generating circuit ps G is connected to the pulse signal bus TF 丨 0 The work case is filled again 1 1 T Ρ 3 〇 Writing t 丨 Figure 18 is a circuit diagram of the pulse signal generating circuit PSG. Pulse 1 | The pulse signal generating circuit PSG is composed of 4 NAND gates 2 6 and 3 1 I inverters 2 5. S B 0 and S B 1 are used to represent the T a 1 1 signal, and the two bits at time T b T c and T d are supplied according to the time points shown in FIG. 1. 1 1 By supplying the signals of SB0 and SB1 to the pulse signal to generate electricity 1 |, it is possible to generate the pulse signal of the pulse signal bus T 'P 0 1 line T P 3 as shown in FIG. 7. According to the address signal of k = 2 bits, 4 (pulses with different pulse widths are generated. The pulse generating circuit can also be regarded as an external circuit and not included in the liquid crystal display device. 1 1 In addition to the above description, The inverter is according to Fig. 22 (a) and the 1 I Ν AN D gate, and according to the circuit shown in Fig. 22 (b) >, 1 is constituted by 1 1 I TT FT. 1 1 I Fig. 20 (a) is a table showing the relationship between the path from the drain driver 3 to the drain line supplied with the analog voltage 1 1 of the embodiment of Fig. 1 and the 1 1 TT FT element located at the path. Illustrative figure: 1 1 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) -14-522356 A7 B7 V. Description of invention (12 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs and input into analog signal input The signal of the part 8 is supplied to the drain line DL through any one of the analog signal buses VRO to VR 3, the analog multiplexer MP 1, and the path 30 through the analog switch ASW. Inside When there is an analog signal generating circuit ASG, it is located on the path shown in Figure 20 (b), and the signal input to the analog signal input section 20 is passed through the analog signal generating circuit ASG. The analog signal bus VRO ~ Any one of VR3, the analog multiplexer MP 1 and the analog switch ASW path 3 1 is supplied to the drain line DL. The analog signal is formed by connecting the drain-source of the TFT in series. The connected analog switches are supplied. Therefore, the voltage accuracy of the pixel electrode is affected by the signal delay caused by the ON resistance of the TFT, the wiring resistance in the drain driver, and the display electrode capacitance CD. However, by not setting the threshold voltage of the TFT and designing the signal delay time most appropriately, a stable operation circuit can be realized with high accuracy. Because the 0 N resistance of the TFT, the wiring resistance in the drain driver, and The display electrode capacitance CD causes the voltage of the drain line DL to have a signal delay at the voltage change points of T1, T2, and T3. The larger the voltage change, the more it will affect The voltage accuracy of the polar line. By sequentially supplying the adjacent voltages of the analog signal buses VR0 ~ VR3 as shown in Figure 7 ', the voltage accuracy can be reduced because the voltage change points at Τ, T2, and T3 must be read on the back again

訂線本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 15- 522356 A7 B7__ 五、發明説明（） 13 所發生的信號延遲所受到的影響° 由於多工器MP 2使用類比多工器MP 1，而不需要像第2圖所示，在多工器MP 2的電路實施電源配線’因此，電路會變得簡單，而可以減少汲極驅動器的電路規模〇Dimensions of this paper are in accordance with Chinese National Standard (CNS) A4 specification (210X297 mm) 15-522356 A7 B7__ V. Description of the invention () 13 The impact of the signal delay occurred ° Because the multiplexer MP 2 uses more analogies The MP 1 does not need to implement power wiring in the circuit of the multiplexer MP 2 as shown in FIG. 2. Therefore, the circuit can be simplified and the circuit size of the drain driver can be reduced.

構成汲極驅動器之T F T的個數愈少’則愈可以減小汲極驅動器的電路規模。在第1圖的實施例以及其他的實施例中，當表示m位元的影像信號’而分成上位j位元與下位k位元時，則構成MP 1與MP 2的TFT數目分別爲 2A(j+l)、 2 A ( k + 1 )，合計 TFT 的個數 S =2A(j+l)+2A(k+l)，可知當時，藉由相加相乘平均可取得最小値。但是m、 j、k爲整數，當m爲偶數時，藉著設成j =k=m/2，S會成爲最小。而當m爲奇數時，藉著設成j = k + 1、或k = j + 1 ，S會成爲最小。 (發明的效果）根據本發明，藉著具有T F T的閾値電壓不會影響到電壓精度的電路構成，因此可以提供具有數位介面的液晶顯示裝置。更者，可以提供一能夠減少汲極驅動器元件的數目，且減低電路面積的液晶顯示裝置。圖面之簡單說明：第1圖係表本發明之液晶顯示裝置之實施例（以下簡本紙張尺度適用中國國家標準（CNS ) A4規格（21〇X297公釐） (請先閱讀背面之注意事項再填寫本頁) -訂線經濟部智慧財產局員工消費合作社印製 -16- 522356 A7 __B7 五、發明説明（） 14 稱爲本實施例）的說明圖。 (請先閲讀背面之注意事項再填寫本頁) 第2圖係表作爲本實施例之構成要素之類比多工器以及多工器的電路圖。第3圖係表作爲本實施例之構成要素之類比多工器以及多工器之動作表。第4圖係表反轉信號產生電路例。第5圖係表作爲本實施例之構成要素之類比開關的電路圖。第6圖係表作爲本實施例之構成要素之類比開關的動作表。第7圖係表輸入到作爲本實施例之構成要素的類比信號匯流排與脈衝信號匯流排之波形的說明圖。第8圖係表本實施例之各部分之動作波形之具體例的說明圖。第9圖係表本實施例之1個圖場期間之閘線與各部之電壓波形的說明圖。經濟部智慧財產局員工消費合作社印製第1 0圖係表本實施例之第7圖之類比信號波形（A )以及（：6)之出現圖案例的說明圖。第1 1圖係表在本實施例當設置2系統之類比信號匯流排時之汲極驅動器之部分的說明圖。第1 2圖係表在本實施例當設置2系統之類比信號匯流排時之實施例之第7圖的類比信號波形（A )以及（B )之出現型態例的說明圖。第1 3圖係表在本實施例，當將類比信號產生電路設本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐) -17- 522356 經濟部智慧財產局員工消費合作社印製 A7 B7五、發明説明（） 15 在汲極驅動器內時之汲極驅動器之部分的說明圖。第1 4圖係表在本實施例，當將類比信號產生電路設在汲極驅動器內時之類比信號產生電路A S G的電路圖。第1 5圖係表在本實施例之類比信號產生電路中所使用之1位元選擇之類比多工器的電路圖。第1 6圖係表在本實施例之類比信號產生電路中所使用之時序信號的說明圖。第1 7圖係表在本實施例，當將脈衝信號產生電路設在汲極驅動器內時之汲極驅動器之部分的說明圖。第1 8圖係表在本實施例，當將脈衝信號產生電路設在汲極驅動器內時之脈衝信號產生電路P S G的電路圖。第1 9圖係表在本實施例之脈衝信號產生電路中所使用之時序（timing)信號的說明圖。第2 0圖係表從本實施例之供給類比電壓的類比信號輸入部到汲極線爲止的路徑，與位在路徑上之T F T元件之連接關係的說明圖。第2 1圖係表有關本發明之習知之液晶顯示裝置之要點的說明圖。第2 2圖係表在本實施例中所使用之反相器與 N A N D閘之構成例的說明圖。符號的說明： D L…汲極線，G L…閘極線，P X…顯示電極， C D…汲極線電容，C P…顯示電極電容，C C 1… 請先閲讀背之注意事項再The smaller the number of T F T constituting the drain driver ', the more the circuit scale of the drain driver can be reduced. In the embodiment of FIG. 1 and other embodiments, when the m-bit video signal is expressed and divided into upper j-bits and lower k-bits, the number of TFTs constituting MP 1 and MP 2 is 2A ( j + l), 2 A (k + 1), and the total number of TFTs S = 2A (j + l) + 2A (k + l). It can be seen that the minimum 値 can be obtained by adding and multiplying the average. But m, j, and k are integers. When m is even, by setting j = k = m / 2, S will be the smallest. When m is an odd number, by setting j = k + 1, or k = j + 1, S becomes the smallest. (Effects of the Invention) According to the present invention, a circuit configuration in which the threshold voltage of T F T does not affect voltage accuracy can provide a liquid crystal display device having a digital interface. Furthermore, a liquid crystal display device capable of reducing the number of drain driver elements and reducing the circuit area can be provided. Brief description of the drawings: Figure 1 shows an embodiment of the liquid crystal display device of the present invention (the following simplified paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm)) (Please read the precautions on the back first (Fill in this page again)-Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-16- 522356 A7 __B7 V. Description of Invention () 14 This is called this embodiment). (Please read the precautions on the back before filling out this page.) Figure 2 shows the analog multiplexer and the circuit diagram of the multiplexer as the constituent elements of this embodiment. Fig. 3 is a table of the analog multiplexer and the operation table of the multiplexer as the constituent elements of this embodiment. Fig. 4 shows an example of an inverted signal generating circuit. Fig. 5 is a circuit diagram of an analog switch as a constituent element of this embodiment. Fig. 6 is a table showing the operation of an analog switch as a constituent element of this embodiment. Fig. 7 is an explanatory diagram showing the waveforms of the analog signal bus and the pulse signal bus inputted as the constituent elements of this embodiment. Fig. 8 is an explanatory diagram showing a specific example of operation waveforms of each part of this embodiment. Fig. 9 is an explanatory diagram showing a gate line and voltage waveforms of various parts during a field in this embodiment. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 10 is an explanatory diagram showing examples of the analog signal waveforms (A) and (: 6) in Figure 7 of this embodiment. FIG. 11 is an explanatory diagram of a part of a drain driver when an analog signal bus of 2 systems is provided in this embodiment. Fig. 12 is an explanatory diagram showing examples of appearance patterns of the analog signal waveforms (A) and (B) of Fig. 7 of the embodiment when an analog signal bus of 2 systems is provided in this embodiment. Figure 13 is a table in this example. When the analog signal generating circuit is set to the paper size, the Chinese National Standard (CNS) A4 specification (210X297 mm) is applied. -17- 522356 The Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperative, printed A7. B7 V. Invention Description (15) An explanatory diagram of the part of the drain driver when it is inside the drain driver. FIG. 14 is a circuit diagram of the analog signal generating circuit A S G when the analog signal generating circuit is provided in the drain driver in this embodiment. Fig. 15 is a circuit diagram showing a 1-bit selection analog multiplexer used in the analog signal generating circuit of this embodiment. Fig. 16 is an explanatory diagram of a timing signal used in the analog signal generating circuit of this embodiment. Fig. 17 is an explanatory diagram showing a part of the drain driver when the pulse signal generating circuit is provided in the drain driver in this embodiment. Fig. 18 is a circuit diagram of the pulse signal generating circuit PSG when the pulse signal generating circuit is provided in the drain driver in this embodiment. Fig. 19 is an explanatory diagram showing a timing signal used in the pulse signal generating circuit of this embodiment. FIG. 20 is an explanatory diagram showing a connection relationship between a path from an analog signal input section to which an analog voltage is supplied to a drain line and a T F T element located on the path. Fig. 21 is an explanatory diagram showing the main points of the conventional liquid crystal display device of the present invention. FIG. 22 is an explanatory diagram showing a configuration example of an inverter and a N A N D gate used in this embodiment. Explanation of symbols: D L… Drain line, G L… Gate line, P X… Display electrode, C D… Drain line capacitance, C P… Display electrode capacitance, C C 1… Please read the notes at the back first

訂線本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） -18- 522356 A7 _ B7 五、發明説明（） 16 第1電路，CC2…第2電路，MP1、MP10、 Μ P 1 e、 2 1、 2 2…類比多工器，Μ P 2…多工器，A S W…類比開關，V R 〇〜V R 3、 V R 0 〇〜V R 3 ο、V R 0 e〜V R 3 e…類比信號匯流排，T P 〇〜T P 3…脈衝信號匯流排，A S G…類比信號產生電路，P S G…脈衝信號產生電路，1…絕緣基板，2…顯示領域，3…汲極驅動器，.4…閘驅動器，5…畫素T F T，7…記憶體，8、2 0…類比信號輸入部，9…脈衝信號輸入部，1 〇、 1 1… 轉送閘，1 2…η通道型丁 F T，1 3…P通道型 T F Τ，1 4、2 5…反相器，2 6…N A N D閘， 3 0、3 1…電流路徑，4 1…第1顯示電壓產生手段，4 2…第2顯示電壓產生手段，4 3…線依序時序電路，4 4、4 5…電容器，4 6…開關電路， 4 7…輸出緩衝器。經濟部智慧財產局員工消費合作社印製本纸張尺度適用中國國家標準（CNS)A4規格（210x297公釐） •19-Dimensions of this paper are in accordance with Chinese National Standard (CNS) A4 specifications (210 × 297 mm) -18- 522356 A7 _ B7 V. Description of the invention () 16 First circuit, CC2 ... Second circuit, MP1, MP10, MP P 1 e, 2 1, 2, 2 ... analog multiplexer, MP 2 ... multiplexer, ASW ... analog switch, VR 〇 ~ VR 3, VR 0 〇 ~ VR 3 ο, VR 0 e ~ VR 3 e ... analog signal Bus, TP 〇 ~ TP 3 ... Pulse signal bus, ASG ... Analog signal generating circuit, PSG ... Pulse signal generating circuit, 1 ... Insulation substrate, 2 ... Display area, 3 ... Drain driver, 4 ... Gate driver, 5 ... pixel TFT, 7 ... memory, 8, 2 ... analog signal input section, 9 ... pulse signal input section, 10, 1 1 ... transfer gate, 1 2 ... n channel type D FT, 1 3 ... P Channel-type TF T, 1 4, 2 5 ... inverter, 2 6 ... NAND gate, 3 0, 3 1 ... current path, 4 1 ... first display voltage generating means, 4 2 ... second display voltage generating means, 4 3 ... line sequential circuit, 4 4, 4 5 ... capacitor, 4 6 ... switch circuit, 4 7 ... output buffer. Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized for China National Standard (CNS) A4 (210x297 mm) • 19-

Claims

522356 |f/·年办抑胗止丨 g88 [.補充i .......... " ，一 v‘j，.一·一一一 …..ί 六、申請專利範圍第88 1 19625號專利申請案中文申請專利範圍修正本民國9 1年5月修正 1 . 一種液晶顯示裝置，其主要針對一具有至少其中一個爲透明之一對的基板’以及爲上述基板所挾持的液晶層，而在上述一·對基板之其中一者具有顯示領域，與用來驅動該顯示領域的周邊電路，在上述顯示領域則成呈矩陣狀被配置的多個汲極線與閘極線，以及薄膜電晶體，且在上述驅動電路領域形成由多個的薄膜電晶體所構成之汲極驅動器與閘極:麗:動器，而可輸入數位的畫像資料之可多灰階顯示之液晶顯示裝置，其特徵在於：上述汲極驅動器係由被上述畫像資料之上位位元所控制的第1電路，與被上述畫像資料之下位位元所控制的第 2電路所構成’上述第1電路是一選擇輸出從類比電壓輸入部所供給之多個類比電壓的電壓選擇手段，而上述第2 電路是一將上述第1電路的輸出，在一定的時點，針對上述汲極線取樣電壓的電壓供給手段，位在上述第1電路以及上述第2電路內，且位在從上述類比電壓輸入部，將類比電壓供到上述汲極線之電流路徑上的電路元件，全部是由包含類比多工器在內之類比開關所構成。 2 .如申請專利範圍第1項之液晶顯示裝置，具備有汲極驅動器，其係由將上述畫像資料分割成上位j位元與下位k位元，而與外部連接之至少有2 ' j條的第1配線群本Μ•張尺度適用中關家檩準（CNS ) A4^· ( 21GX 297公董) " ~ ----------.Aw! (請先閱讀背面之注意事項再填寫本頁) 訂 w 經濟部智慧財產局員工消費合作社印製 2356 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍，連接到上述第1配線群，根據上述畫像資料的上位j位元，選擇輸出上述第一配線群之電壓的類比多工器，與外部連接之至少有2 Λ k條的第2配線群，連接到上述第2配線群’而根據上述畫像資料的下位k位元，選擇輸出上述第一配線群之電壓的多工器，以及連接上述類比多工器的選擇輸出與上述汲極配線，而根據上述多工器的輸出値來控制其開閉情形的類比開關所構成。 3 ·如申請專利範圍第丨項之液晶顯示裝置，具備有汲極驅動器，其係由將上述畫像資料分割成上位j位元與下位k位元，而由類比多工器所構成之類比信號產生電路，連接到上述類比信號產生電路之至少有2 Λ j條的第1配線群，連接到上述第1配線群，而根據上述畫像資料之上位j位元來選擇上述第1配線群之類比電壓的類比多工器，產生不同之脈寬之脈衝的脈衝信號產生電路，連接到上述脈衝信號產生電路之至少有2 Λ k條的第2配線群，連接到上述第2配線群，而根據上述晝像資料之下位k位元來選擇上述第2配線群之脈衝信號的多工器，以及連接上述類比多工器的選擇輸出與上述汲極配線，而根據上述多工器的輸出値控制其開閉情形的類比開關所構成。 4 .如申請專利範圍第1項之液晶顯示裝置，具備有汲極驅動器，其係由將上述畫像資料分割成上位j位元與下位k位元，而由類比多工器所構成之類比信號產生電路，連接到上述類比信號產生電路之至少有2 Λ j條的第1配線群，連接到上述第1配線群，而根據上述晝像資料之上本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------------訂------·—^ (請先閱讀背面之注意事項再填寫本頁) ▼22356 A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製六、申請專利範圍位j位元來選擇上述第1配線群之類比電壓的類比多工器，與外部連接之至少有2 Λ k條的第2配線群’連接到上述第2配線群，而根據上述晝像資料之下位k位元來選擇上述第2配線群之脈衝信號的多工器，以及連接上述類比多工器的選擇輸出與上述汲極配線，而根據上述多工器的輸出値控制其開閉情形的類比開關所構成。 5 .如申請專利範圍第1項之液晶顯示裝置，具備有汲極驅動器，其係由將上述畫像資料分割成上位j位元與下位k位元，而與外部連接之至少有2 Λ j條的第1配線群，連接到上述第1配線群，根據上述畫像資料的上位.j位元，選擇輸出上述第一配線群之電壓的類比多工器，產生不同脈寬之脈衝的脈衝信號產生電路，與上述脈衝信號產生電路連接之至少有2 Λ k條的第2配線群，連接到上述第 2配線群，而根據上述畫像資料的下位k位元，選擇輸出上述第二配線群之電壓的多工器，以及連接上述類比多工器的選擇輸出與上述汲極配線，而根據上述多工器的輸出値來控制其開閉情形的類比開關所構成。 6 .如申請專利範圍第3項或第4項之液晶顯示裝置，上述類比電壓產生電路係由類比多工器所構成，係一將具有多階段的類比電壓，依據鄰接之電壓値的順序實施多重化而供給到上述第1配線群的電路。 7 ·如申請專利範圍第2項、第3項、第4項、第5 項或第6項之液晶顯示裝置，上述多工器係由與上述類比多工器相同的電路構成所形成。本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------------訂------Aw~ (請先閱讀背面之注意事項再填寫本頁) -3- 2356 A8 B8 C8 D8 六、申請專利範圍 8 .如申請專利範圍第7項之液晶顯示裝置，上述畫像資料的上位j位元與上述畫像資料的下位k位元，當上述畫像資料的位元數m爲偶數時，則被分成j = k的相同位元數，或當上述畫像位元數m爲奇數時，則被分成具有 j = k+l或k = j +1之關係的位元數。 (請先閱讀背面之注意事項再填寫本頁) -----訂------~ 經濟部智慧財產局員工消費合作社印製本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）522356 | f / · year office suppression 丨 g88 [.Supplement i .......... ", one v'j ,. one · one one one… .. 6 88 1 19625 Patent Application Chinese Application Patent Range Amendment May 1st, 2011 Amendment 1. A liquid crystal display device, which is mainly directed to a substrate having at least one of the transparent pairs, and a substrate held by the substrate The liquid crystal layer has a display area in one of the above-mentioned pair of substrates, and peripheral circuits for driving the display area. In the display area, a plurality of drain lines and gate lines are arranged in a matrix. And thin-film transistors, and in the above-mentioned driving circuit field, a drain driver and a gate composed of a plurality of thin-film transistors are formed. The liquid crystal can be displayed in multiple gray scales, and digital image data can be input. The display device is characterized in that: the drain driver is composed of a first circuit controlled by the upper bit of the image data, and a second circuit controlled by the lower bit of the image data. Is a choice to lose A voltage selection means for a plurality of analog voltages supplied from an analog voltage input section is provided, and the second circuit is a voltage supply means for sampling the output voltage of the drain line at a certain point in time from the output of the first circuit, The circuit elements located in the first circuit and the second circuit and located in the current path for supplying the analog voltage to the drain line from the analog voltage input section are all including an analog multiplexer. Analog switch. 2. For example, the liquid crystal display device of the first patent application scope is provided with a drain driver, which divides the above image data into upper j bits and lower k bits, and there are at least 2 'j pieces connected to the outside. The first wiring group book M · Zhang scale applies to Zhongguan Jiazheng Standard (CNS) A4 ^ (21GX 297 public director) " ~ ----------.Aw! (Please read the back Note: Please fill in this page again.) Order w Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2356 Printed by the Employee Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 The upper j bit of the image data selects the analog multiplexer that outputs the voltage of the first wiring group, and the second wiring group with at least 2 Λ k externally connected to the second wiring group is connected to the second wiring group according to the above. The lower k bits of the image data select the multiplexer that outputs the voltage of the first wiring group, and connect the selection output of the analog multiplexer with the drain wiring, and control the multiplexer according to the output of the multiplexer Analogy of opening and closing situations Off the constitution. 3. If the liquid crystal display device according to item 丨 of the patent application is equipped with a drain driver, it is an analog signal composed of an analog multiplexer that divides the image data into upper j bits and lower k bits. The generating circuit is connected to the first wiring group having at least 2 Λ j pieces of the analog signal generating circuit, and is connected to the first wiring group. The analogy of the first wiring group is selected based on the upper j bits of the image data. An analog multiplexer of voltage, a pulse signal generating circuit that generates pulses with different pulse widths, is connected to the second wiring group of at least 2 Λ k wires of the pulse signal generating circuit, and is connected to the second wiring group. The multiplexer that selects the pulse signal of the second wiring group by k bits below the day image data, and connects the selection output of the analog multiplexer and the drain wiring, and is controlled based on the output of the multiplexer. It is composed of an analog switch of the opening and closing situation. 4. For example, the liquid crystal display device of the first patent application scope is provided with a drain driver, which is an analog signal composed of an analog multiplexer by dividing the image data into upper j bits and lower k bits. The generating circuit is connected to the first wiring group having at least 2 Λ j pieces of the above analog signal generating circuit, and is connected to the first wiring group. According to the above-mentioned day image data, this paper standard applies Chinese National Standard (CNS) A4 Specifications (210X297 mm) --------------- Order ------ · — ^ (Please read the precautions on the back before filling this page) ▼ 22356 A8 B8 C8 D8 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 6. The scope of application for patents is in bit j. The analog voltage multiplexer with the analog voltage of the first wiring group is selected. The second wiring group with at least 2 Λ k lines connected to the outside. 'Connect to the second wiring group, and select the multiplexer of the pulse signal of the second wiring group based on the k bits below the day image data, and connect the selection output of the analog multiplexer and the drain wiring. And according to the output of the above multiplexer 値Opening and closing system analog switch constituted situation. 5. For example, the liquid crystal display device of the first patent application scope has a drain driver, which divides the above image data into upper j bits and lower k bits, and at least 2 Λ j lines connected to the outside The first wiring group is connected to the first wiring group, and selects an analog multiplexer that outputs the voltage of the first wiring group according to the upper .j bit of the image data, and generates pulse signals of pulses with different pulse widths. Circuit, the second wiring group having at least 2 Λ k pieces connected to the pulse signal generating circuit is connected to the second wiring group, and the voltage of the second wiring group is selected and output according to the lower k bits of the image data And an analog switch that connects the selected output of the analog multiplexer and the drain wiring, and controls the opening and closing of the multiplexer according to the output of the multiplexer. 6. If the liquid crystal display device of the third or fourth item of the scope of patent application, the above analog voltage generating circuit is composed of an analog multiplexer, and the analog voltage will be implemented in multiple stages according to the order of adjacent voltages 値Multiple circuits are supplied to the first wiring group. 7 · If the liquid crystal display device of the second, third, fourth, fifth or sixth item of the scope of patent application, the multiplexer is formed by the same circuit configuration as the analog multiplexer. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) --------------- Order ------ Aw ~ (Please read the precautions on the back before (Fill in this page) -3- 2356 A8 B8 C8 D8 6. Application for Patent Scope 8. For the liquid crystal display device under the scope of patent application item 7, the upper j bit of the above-mentioned image data and the lower k bit of the above image data, when When the number of bits m of the portrait data is even, it is divided into the same number of bits of j = k, or when the number of bits m of the portrait data is odd, it is divided into j = k + l or k = j + The number of bits in the relationship of 1. (Please read the precautions on the back before filling out this page) ----- Order ------ ~ Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (210X297) Mm)