TW519749B - Gateless diode device of ESD protection circuit and its manufacturing method - Google Patents

Gateless diode device of ESD protection circuit and its manufacturing method Download PDF

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Publication number
TW519749B
TW519749B TW091101026A TW91101026A TW519749B TW 519749 B TW519749 B TW 519749B TW 091101026 A TW091101026 A TW 091101026A TW 91101026 A TW91101026 A TW 91101026A TW 519749 B TW519749 B TW 519749B
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Taiwan
Prior art keywords
diode
gateless
patent application
voltage supply
scope
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TW091101026A
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Chinese (zh)
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Ming-Dau Ke
Gen-Gang Hung
Tian-Hau Tang
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United Microelectronics Corp
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Priority to TW091101026A priority Critical patent/TW519749B/en
Priority to US10/060,743 priority patent/US6933573B2/en
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Publication of TW519749B publication Critical patent/TW519749B/en
Priority to US10/702,372 priority patent/US7141484B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Abstract

A kind of silicon on insulator (SOI) gateless diode structure includes the followings: an SOI substrate, which is provided with a substrate, an insulation layer and a silicon layer stacked sequentially; the pair of isolation structures, which is located in the silicon layer so as to have a well region between the paired isolation structures and the silicon layer; and the ion implantation region of the first type and ion implantation region of the second type, which are located in the well region and are respectively adjacent to each of the isolation structures. The invented gateless diode structure can be used in ESD protection circuit to increase the ESD protection capability of integrated circuit products. In addition, the present invention also proposes a manufacturing method of the gateless diode structure.

Description

經濟部智慧財產局員工消費合作社印製 519749 五、發明說明（/ ) 本發明是有關於一種靜電放電防護電路及其製造方 法’且特別是有關於一種無閘極二極體元件之靜電放電防 護電路及其製造方法’且更特別是關於一種利用絕緣層上 有矽（silicon on insulator，SOI)製程之無閘極二極體元件 之靜電放電防護電路及其製造方法。 絕緣層上有矽（SOI)製程技術在目前低電壓與高速應 用上是具有潛力的主要競爭技術，因爲相較於一般基體 (bulk)CMOS製程而言，SOI製程技術具有高隔離（is〇iati〇n) 程度 '免於閂鎖(latch-up)效應以及較低的接面電容等等。 目目U ’對於SOI製程而言，靜電放電防護（electrostatic discharge，ESD)是一個極需發展的技術。 ESD防護電路所能夠提供的保護等級係取決於當ESD 電路將電壓箝制到較小電壓時，ESD電路所能夠帶走的電 流量。在ESD脈衝進入期間內，熱量失控(thermal runaway) 與接續的劇烈破壞會對內部電路元件造成嚴重破壞。在SOI 元件中，SOI的埋入式氧化層（buried oxide)之熱傳率 (thermal conductivity)僅爲矽的百分之一左右；這導致元件 更易因ESD而過熱，而使得熱量失控加速增加。 第1圖繪示SOI閘極二極體（gated diode)的剖面圖， 其爲一種SOI上有CMOS之ESD保護電路。此結構係由 S· Voldman等人發表於期刊“Proc· 办'1996, pp. 291-301。如第1圖所示，SOI閘極二極體係形成於一 SOI基底上，其包括基底10、埋入式氧化層12與矽層。 在砂層中形成淺溝渠隔離（shallow trench isolation，STI)結 3 -----------41^ ·—I----訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙尺度適用中0國家標準（CNS)A丨規格（21〇χ 297公釐） 519749 H7 7 8 9 7 t w f · d 〇 c / Ο Ο 9 五、發明說明（> ) (請先閱讀背面之注意事項再填寫本頁) 構14。在STI隔離結構之間具有一 Ρ型擴散區（diffusion region) (P+)20與N型擴散區（N+)16。P型擴散區20與N 型擴散區16中間則爲N型井或P型井區域18。若該井區 18爲植入N型離子（N-)，則P型擴散區（P+)20與N井（N-)18 形成SOI二極體；反之，若該井區18爲植入P型離子（P-)， 則N型擴散區20(N+)與P井(P〇18形成SOI二極體。在 井區18上更具有一閘極結構，其包括P+區24與N+區22(兩 者做爲閘極）、間隙壁26與閘氧化層28等。 P型擴散區(P+)20與N型擴散區(N+)16分別連接到電 壓VI、V2，各自做爲SOI二極體之兩個電壓施力口端點。 以P型擴散區（P+)20與N井(N_)18所形成SOI二極體爲 例，假如電壓VI相對於電壓V2爲正，則此SOI二極體 爲順向偏壓；反之，假如電壓V2相對於電壓VI爲正， 則此SOI二極體爲逆向偏壓。 經濟部智慧財產局員工消費合作社印裂 若ESD電壓在P型擴散區(P+)20/N型井(N_)18間的 接面所產生的熱很小的話，SOI二極體可以承受較高的ESD 電壓。熱是產生在PN接面的局部區域。大部分在PN接 面上的熱爲焦耳熱(joule heating)。二次崩潰係發生在當SOI 二極體中之最大溫度到達它的本徵溫度（intrinsic temperature)Tintrinsti。時。因此，爲了要得到較佳的ESD防 護等級，便必須降低功率密度與焦耳熱量。 因此本發明之目的係提出一種無閘極二極體元件之靜 電放電防護電路及其製造方法，此無閘極二極體具有低功 率密度。 4 本紙張又度適用中1¾國家標準（CNSM.丨規格（210 X 297公釐) " " 經濟部智慧財產局員工消費合作社印製 519749 五、發明說明（}) 本發明之另一目的係提出一種無閘極二極體元件之靜 電放電防護電路及其製造方法，此無閘極二極體可以應用 到SOI電路的靜電防護電路，並可以提高它的ESD耐壓 度。 本發明之另一目的係提出一種無閘極二極體元件之靜 電放電防護電路及其製造方法，此無閘極二極體可以適用 SOI製程或基體CMOS製程。 爲達到上述與其他目的，本發明提出提出一種無閘極 二極體元件結構，應用此無閘極二極體元件之靜電放電防 護電路及無閘極二極體元件製造方法，其簡述如下： 本發明提供一種絕緣層上有矽之無閘極二極體結構， 包括：一絕緣層上有矽基底，其具有基底、絕緣層與矽層 依序堆疊；對隔離結構，位於矽層中，使在對隔離結構之 間與矽層中具有一井區；第一型離子植入區與一第二型離 子植入區，位於井區中並且分別緊鄰各隔離結構。 本發明更提出另一種絕緣層上有矽之無閘極二極體結 構，包括：絕緣層上有矽基底，其具有基底、絕緣層與矽 層依序堆疊；對隔離結構，位於矽層中，使在對隔離結構 之間與矽層中具有第一井區與第二井區，其中第一井區與 第二井區相鄰；第一型離子植入區與第二型離子植入區， 分別位於第一與第二井區中，並且分別緊鄰各隔離結構， 藉以使絕緣層上有矽之無閘極二極體元件之接面爲第一與 第二井區之接面。 本發明更提供一種無閘極二極體元件之靜電放電防護 5 本紙張&度適用中阀國家標準（CNS)A.丨規格（21〇χ 297公堃) ---— —— — — —--— — — — — — — ^ ·1111111 ' (請先閱讀背面之注意事項再填寫本頁) 519749 五、發明說明（4 ) (請先閱讀背面之注意事項再填寫本頁) 電路，其耦接於輸入焊墊與內部電路之間。此防護電路包 括以下元件。高電壓供應線與低電壓供應線；第一二極體， 其具有陽極耦接至高電壓供應線與陰極耦接至一節點；第 二二極體，其具有陰極耦接至低電壓供應線與陽極耦接至 節點；第一二極體串，由複數個二極體串聯所構成，其中 具有陽極耦接至高電壓供應線與陰極耦接至節點；第二二 極體串，由複數個二極體串聯所構成，具有陰極耦接至低 電壓供應線與陽極耦接至節點；以及電阻，其第一端耦接 至節點與第二端耦接至內部電路。 經濟部智慧財產局員工消費合作社印製 當相對於高電壓供應線之正電壓施加於輸入焊墊時， 無閘極二極體元件之靜電放電防護電路提供一條經由第一 二極體到高電壓供應線的放電路線。當相對於低電壓供應 線之負電壓施加於輸入焊墊時，無閘極二極體元件之靜電 放電防護電路提供一條經由第二二極體到低電壓供應線的 放電路線。當相對於高電壓供應線之負電壓施加於輸入焊 墊時，無閘極二極體元件之靜電放電防護電路提供一條經 由第二二極體、第二二極體串與第一二極體串到高電壓供 應線的放電路線。當相對於低電壓供應線之高電壓施加於 輸入焊墊時，無閘極二極體元件之靜電放電防護電路提供 一條經由第一二極體、第一二極體串與第二二極體串到低 電壓供應線的放電路線。 本發明更提供一種無閘極二極體元件之靜電放電防護 電路，其耦接於輸出焊墊與預驅動器之間。此防護電路包 括以下元件。高電壓供應線與一低電壓供應線，分別耦接 6 本紙張尺度適用中阀國家標準（CNS)A丨規格（210 x 297公釐） 經濟部智慧財產局員工消費合作社印製 519749 五、發明說明（f) 到預驅動器；第一二極體，其具有陽極耦接至高電壓供應 線與陰極耦接至一節點；第二二極體，其陰極耦接至低電 壓供應線與陽極耦接至節點；第一二極體串，由複數個二 極體串聯所構成，其中具有陽極親接至高電壓供應線與陰 極耦接至節點；第二二極體串，由複數個二極體串聯所構 成，具有陰極耦接至低電壓供應線與陽極耦接至節點；第 一型MOS電晶體，其源極耦接到高電壓供應線，汲極耦 接到節點，閘極耦接到預驅動器；以及第二型MOS電晶 體，其源極耦接到低電壓供應線，汲極耦接到節點，閘極 耦接到第一型MOS電晶體該閘極。 其中當相對於高電壓供應線之正電壓施加於輸出焊墊 時，無閘極二極體元件之靜電放電防護電路提供一條經由 第一二極體到高電壓供應線的放電路線。當相對於低電壓 供應線之負電壓施加於輸出焊墊時，無閘極二極體元件之 靜電放電防護電路提供一條經由第二二極體到低電壓供應 線的放電路線。當相對於高電壓供應線之一負電壓施加於 輸出焊墊時，無閘極二極體元件之靜電放電防護電路提供 一條經由第二二極體、第二二極體串與第一二極體串到高 電壓供應線的放電路線。當相對於低電壓供應線之高電壓 施加於輸出焊墊時，無閘極二極體元件之靜電放電防護電 路提供一條經由第一二極體、第一二極體串與第二二極體 串到低電壓供應線的放電路線。 本發明更提出一種無閘極二極體元件之靜電放電防護 電路，其耦接於輸入焊墊與內部電路之間。此防護電路包 7 本紙張尺度適用中1¾國家標準（CNS)/U規格（2ΐ〇χ 297公楚） -------I I I I · 11丨！訂·-----丨-線 (請先閱讀背面之注意事項再填寫本頁) B7 519749 7 8 9 7 twf . doc/Ο Ο 9 五、發明說明（L ) 括以下構件。高電壓供應線與低電壓供應線，均耦接至內 部電路；第一二極體與一第二二極體係串聯一起，其中第 一二極體之陽極耦接至一節點，而第二二極體之陰極耦接 至高電壓供應線；第三二極體與第四二極體係串聯一起， 其中第三二極體之陽極耦接至低電壓供應線，而第四二極 體之陰極耦接至節點；電阻具有第一端耦接至節點與第二 端稱接至內部電路；MOS電晶體之閘極與源極一起親接至 低電壓供應線，而汲極耦接至電阻之第二端；以及靜電放 電箝制電路，耦接於高電壓供應線與低電壓供應線之間。 其中上述之電放電箝制電路係由複數個二極體串聯而 成，其具有陽極耦接到高電壓供應線與陰極耦接到低電壓 供應線。 本發明更提出一種形成絕緣層上有矽之無閘極二極體 的方法。首先，提供一絕緣層上有砂基底，其係依序堆疊 基底、絕緣層與矽層。形成一對隔離結構於矽層中，使在 對隔離結構之間與矽層中具有一井區。形成第一型離子植 入區與第二型離子植入區於井區中，並且分別緊鄰各隔離 結構。 本發明更提出一種形成絕緣層上有矽之無閘極二極體 的方法。首先，提供一絕緣層上有矽基底，其係依序堆疊 基底、絕緣層與矽層依序堆疊。形成一對隔離結構於該矽 層中。形成第一井區與第二井區在對隔離結構之間與矽層 中’其中第一井區與第二井區相鄰。形成第一型離子植入 區與第一型離子植入區，分別位於第一與該第二井區中， 8 本纸張尺度適用中Η國家標準（CNS)A.丨规格x 297公釐）---- ------------i — — — — — — ^« — — — — — 1 — ^we (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 519749 7 8 9 7 twf :/009 Λ7 H7 五、發明說明（η ) 並且分別緊鄰各該隔離結構，藉以使絕緣層上有矽之無閘 極二極體元件之接面爲第一與第二井區之接面。 (請先閱讀背面之注意事項再填寫本頁) 本發明更提供一^種基體COMS無聞極一極體結構’包 括：具有一井之基底；一對隔離結構，位於基底中；第一 型離子植入區係位於上述之井中；一對第二型離子植入 區，位於井中並且分別緊鄰各該隔離結構，其中該對第二 型離子植入區分別以該井與該第一型離子植入區分離。 本發明更提供一種形成基體COMS無閘極二極體的方 法，包括：提供一基底，該基底中形成一井；形成一對隔 離結構於該基底；形成一第一型離子植入區與該井中，且 位於該對隔離結構之間；形成一對第二型離子植入區於該 井區中，並且分別緊鄰各該隔離結構，各該第二型離子植 入區分別以該井與該第一型離子植入區分離。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下： 圖式之簡單說明： 第1圖繪示SOI之有閘極二極體(gated diode)的剖面 圖，其爲一種SOI上有CMOS之ESD保護電路； 經濟部智慧財產局員工消費合作社印製 第2圖係依據本發明之一實施例所述之具有以STI區 隔結構（STI-blocking structure)之無閘極二極體（non-gated diode)的剖面示意圖； 第3A圖與第3B圖分別繪示出STI隔離結構與STI 區隔結構的上視圖；Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 519749 V. Description of the Invention (/) The present invention relates to an electrostatic discharge protection circuit and a manufacturing method thereof, and in particular to an electrostatic discharge protection of a gateless diode element The circuit and its manufacturing method ', and more particularly, it relates to an electrostatic discharge protection circuit using a gateless diode element with a silicon on insulator (SOI) process and a manufacturing method thereof. The silicon-on-insulator (SOI) process technology is the main competitive technology with potential for low-voltage and high-speed applications at present, compared to the general bulk CMOS process, the SOI process technology has high isolation (is〇iati 〇n) degree 'free from latch-up effects and lower junction capacitance and so on. For the SOI process, electrostatic discharge (ESD) is a technology that needs to be developed. The level of protection provided by an ESD protection circuit depends on the amount of electricity that the ESD circuit can take away when the ESD circuit clamps the voltage to a lower voltage. During the ESD pulse entry period, thermal runaway and subsequent severe damage will cause serious damage to the internal circuit components. In SOI devices, the thermal conductivity of the buried oxide of SOI is only about one percent of that of silicon; this makes the device more susceptible to overheating due to ESD, which accelerates the increase in thermal runaway. FIG. 1 is a cross-sectional view of a gated diode of an SOI, which is an ESD protection circuit with CMOS on the SOI. This structure was published by S. Voldman et al. In the journal "Proc. Office" 1996, pp. 291-301. As shown in Fig. 1, the SOI gate diode system is formed on a SOI substrate, which includes the substrate 10, Buried oxide layer 12 and silicon layer. A shallow trench isolation (STI) junction 3 is formed in the sand layer ----------- 41 ^ · -I ---- order --- ------ Line (Please read the precautions on the back before filling in this page) The paper size is applicable to 0 National Standards (CNS) A 丨 Specifications (21〇χ 297 mm) 519749 H7 7 8 9 7 twf · d 〇c / Ο Ο 9 V. Description of the invention (&); (Please read the precautions on the back before filling out this page) Structure 14. There is a P-type diffusion region (P +) 20 between the STI isolation structures And N-type diffusion region (N +) 16. The middle of P-type diffusion region 20 and N-type diffusion region 16 is N-type well or P-type well region 18. If the well region 18 is implanted with N-type ions (N-), Then the P-type diffusion region (P +) 20 and N-well (N-) 18 form an SOI diode; otherwise, if the well region 18 is implanted with P-type ions (P-), then the N-type diffusion region 20 (N +) It forms a SOI diode with P well (P018. There is also a gate junction on well area 18. Structure, which includes P + region 24 and N + region 22 (both as gates), spacer 26 and gate oxide layer 28, etc. P-type diffusion region (P +) 20 and N-type diffusion region (N +) 16 are connected to The voltages VI and V2 are respectively the ends of two voltage application ports of the SOI diode. Take the SOI diode formed by the P-type diffusion region (P +) 20 and N-well (N_) 18 as an example. If the voltage V2 is positive, the SOI diode is forward biased; otherwise, if the voltage V2 is positive with respect to the voltage VI, the SOI diode is reverse biased. Employee Consumer Cooperatives, Bureau of Intellectual Property, Ministry of Economic Affairs If the heat generated by the ESD voltage at the junction between the P-type diffusion region (P +) 20 / N-type well (N_) 18 is small, the SOI diode can withstand a higher ESD voltage. The heat is generated in Local area of the PN junction. Most of the heat on the PN junction is joule heating. The secondary collapse occurs when the maximum temperature in the SOI diode reaches its intrinsic temperature, Tintrinsti Therefore, in order to obtain a better ESD protection level, it is necessary to reduce the power density and the Joule heat. Therefore, the object of the present invention is to provide An electrostatic discharge protection circuit and a manufacturing method for the non-diode element are provided. The non-diode has low power density. 4 This paper is also suitable for 1¾ national standard (CNSM. 丨 Specification (210 X 297) (Mm) " " Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519749 V. Description of the invention (}) Another object of the present invention is to propose an electrostatic discharge protection circuit without gate diode element and its manufacturing method This non-gate diode can be applied to the electrostatic protection circuit of the SOI circuit and can improve its ESD withstand voltage. Another object of the present invention is to provide an electrostatic discharge protection circuit for a gateless diode element and a manufacturing method thereof. The gateless diode can be applied to a SOI process or a base CMOS process. In order to achieve the above and other objectives, the present invention proposes a non-diode element structure, an electrostatic discharge protection circuit using the non-diode element, and a method for manufacturing the non-diode element, which are briefly described below. The invention provides a gateless diode structure with silicon on an insulating layer, comprising: a silicon substrate on an insulating layer, which has the substrate, the insulating layer and the silicon layer sequentially stacked; and an isolation structure located in the silicon layer So that there is a well region between the pair of isolation structures and the silicon layer; the first type ion implantation region and a second type ion implantation region are located in the well region and are adjacent to each isolation structure respectively. The invention further proposes another gateless diode structure with silicon on the insulating layer, including: a silicon substrate on the insulating layer, which has the substrate, the insulating layer and the silicon layer sequentially stacked; and the isolation structure is located in the silicon layer So that there are a first well region and a second well region between the isolation structure and the silicon layer, wherein the first well region is adjacent to the second well region; the first type ion implantation region and the second type ion implantation The regions are respectively located in the first and second well regions and are adjacent to the isolation structures, respectively, so that the interface of the gateless diode element with silicon on the insulating layer is the interface of the first and second well regions. The invention further provides a gate-less diode element for electrostatic discharge protection. 5 sheets of paper & degree are applicable to the National Standard for Valves (CNS) A. 丨 Specification (21〇χ 297 公 堃) -------- ———— — — — — — — ^ · 1111111 '(Please read the notes on the back before filling this page) 519749 V. Description of the invention (4) (Please read the notes on the back before filling this page) Circuit, It is coupled between the input pad and the internal circuit. This protective circuit includes the following components. A high voltage supply line and a low voltage supply line; a first diode having an anode coupled to the high voltage supply line and a cathode coupled to a node; a second diode having a cathode coupled to the low voltage supply line and The anode is coupled to the node; the first diode string is composed of a plurality of diodes connected in series, wherein the anode is coupled to the high voltage supply line and the cathode is coupled to the node; the second diode string is composed of a plurality of two The electrode body is formed in series, and has a cathode coupled to a low voltage supply line and an anode coupled to a node; and a resistor having a first terminal coupled to the node and a second terminal coupled to an internal circuit. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. When a positive voltage relative to the high voltage supply line is applied to the input pad, the electrostatic discharge protection circuit of the gateless diode element provides a high voltage through the first diode. Discharge route of the supply line. When a negative voltage relative to the low voltage supply line is applied to the input pad, the ESD protection circuit of the gateless diode element provides a discharge path through the second diode to the low voltage supply line. When a negative voltage relative to the high voltage supply line is applied to the input pad, the ESD protection circuit of the gateless diode element provides a second diode, a second diode string, and the first diode. Discharge route to high voltage supply line. When a high voltage relative to the low voltage supply line is applied to the input pad, the ESD protection circuit of the gateless diode element provides a path through the first diode, the first diode string, and the second diode. Discharge route to low voltage supply line. The invention further provides an electrostatic discharge protection circuit of a gateless diode element, which is coupled between the output pad and the pre-driver. This protective circuit includes the following components. A high-voltage supply line and a low-voltage supply line are respectively connected to 6 paper sizes. Applicable to the National Standard for Valves (CNS) A 丨 specifications (210 x 297 mm). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 519749 V. Invention Note (f) to the pre-driver; first diode with anode coupled to high voltage supply line and cathode coupled to one node; second diode with cathode coupled to low voltage supply line and anode coupled To the node; the first diode string is composed of a plurality of diodes connected in series, wherein the anode is connected to the high voltage supply line and the cathode is coupled to the node; the second diode string is connected to a plurality of diodes in series It has a cathode coupled to a low voltage supply line and an anode coupled to a node. The first type MOS transistor has a source coupled to a high voltage supply line, a drain coupled to a node, and a gate coupled to a A driver; and a second type MOS transistor, the source of which is coupled to the low voltage supply line, the drain coupled to the node, and the gate coupled to the gate of the first MOS transistor. When a positive voltage relative to the high-voltage supply line is applied to the output pad, the ESD protection circuit of the gateless diode element provides a discharge path through the first diode to the high-voltage supply line. When a negative voltage relative to the low voltage supply line is applied to the output pad, the ESD protection circuit of the gateless diode element provides a discharge path through the second diode to the low voltage supply line. When a negative voltage is applied to the output pad relative to one of the high voltage supply lines, the ESD protection circuit of the gateless diode element provides a second diode, a second diode string, and the first diode. Discharge route from body string to high voltage supply line. When a high voltage relative to the low voltage supply line is applied to the output pad, the ESD protection circuit of the gateless diode element provides a path through the first diode, the first diode string, and the second diode. Discharge route to low voltage supply line. The invention further provides an electrostatic discharge protection circuit of a gateless diode element, which is coupled between the input pad and the internal circuit. This protective circuit package 7 This paper size applies to 1¾ national standard (CNS) / U specifications (2ΐ〇χ 297 公 楚) ------- I I I I · 11 丨! Order ------- 丨 -line (Please read the precautions on the back before filling in this page) B7 519749 7 8 9 7 twf .doc / Ο Ο 9 V. Description of the invention (L) includes the following components. The high-voltage supply line and the low-voltage supply line are both coupled to the internal circuit; the first diode is connected in series with a second diode system, in which the anode of the first diode is coupled to a node, and the second diode The cathode of the pole is coupled to the high voltage supply line; the third diode is connected in series with the fourth diode system, where the anode of the third diode is coupled to the low voltage supply line and the cathode of the fourth diode is coupled Connected to the node; the resistor has a first terminal coupled to the node and a second terminal connected to the internal circuit; the gate and source of the MOS transistor are connected to the low voltage supply line together, and the drain is coupled to the first Two ends; and an electrostatic discharge clamping circuit, which is coupled between the high-voltage supply line and the low-voltage supply line. The above-mentioned electric discharge clamping circuit is formed by connecting a plurality of diodes in series, which has an anode coupled to a high-voltage supply line and a cathode coupled to a low-voltage supply line. The invention further provides a method for forming a gateless diode with silicon on the insulating layer. First, a sand substrate is provided on an insulating layer, which sequentially stacks the substrate, the insulating layer, and the silicon layer. A pair of isolation structures are formed in the silicon layer so that there is a well region between the pair of isolation structures and in the silicon layer. A first-type ion implantation region and a second-type ion implantation region are formed in the well region, and are adjacent to the isolation structures, respectively. The invention further provides a method for forming a gateless diode with silicon on the insulating layer. First, a silicon substrate is provided on an insulating layer. The substrate is sequentially stacked, and the insulating layer and the silicon layer are sequentially stacked. A pair of isolation structures are formed in the silicon layer. A first well region and a second well region are formed in the silicon layer between the pair of isolation structures, wherein the first well region is adjacent to the second well region. Form the first type ion implantation area and the first type ion implantation area, which are located in the first and the second well areas, respectively. 8 paper sizes are applicable to the China National Standard (CNS) A. 丨 size x 297 mm ) ---- ------------ i — — — — — — ^ «— — — — 1 — ^ we (Please read the notes on the back before filling this page) Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 519749 7 8 9 7 twf: / 009 Λ7 H7 V. Description of the invention (η) and next to each of the isolation structures respectively, so that there is a silicon-free gate diode element on the insulation layer. The interface is the interface between the first and second well areas. (Please read the precautions on the back before filling this page) The present invention also provides a ^ substrate COMS singular pole-polar structure 'includes: a substrate with a well; a pair of isolation structures in the substrate; the first type The ion implantation zone is located in the above-mentioned well; a pair of second-type ion implantation zones are located in the well and are adjacent to each of the isolation structures respectively, wherein the pair of second-type ion implantation zones respectively use the well and the first-type ion The implanted area is separated. The invention further provides a method for forming a substrate COMS gateless diode, comprising: providing a substrate, a well formed in the substrate; forming a pair of isolation structures on the substrate; forming a first-type ion implantation region and the In the well, and between the pair of isolation structures; a pair of second-type ion implantation regions are formed in the well region, and are adjacent to each of the isolation structures, respectively, and each of the second-type ion implantation regions is the well and the The first type of ion implantation zone is separated. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, the following exemplifies preferred embodiments and the accompanying drawings to make detailed descriptions as follows: Brief description of the drawings: FIG. 1 illustrates SOI A cross-sectional view of a gated diode, which is an ESD protection circuit with CMOS on SOI. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 2 is based on an embodiment of the present invention. A schematic cross-sectional view of a non-gated diode with an STI-blocking structure; Figures 3A and 3B respectively show the STI isolation structure and the STI isolation structure. Top view

第4A至第4G圖係繪示以SOI製程來製作出具有STI 9 本紙張尺度適用中1¾ 0家標準（CNS)A·丨規格（210 X 297公t ) 519749 五、發明說明（<g ) 隔離結構， (請先閱讀背面之注意事項再填寫本頁) 第5A圖至第5G圖係繪示以SOI製程來製作出不具 有ST1隔離結構； 第6A圖至第6G圖係繪示以基體CMOS製程來製作 出具有STI隔離結構； 第7A圖至第7G圖係繪示以基體CMOS製程來製作 出不具有STI隔離結構； 第8圖繪示有閘極與無閘極SOI二極體之邊長與ESD 電壓之間的比較關係圖； 第9圖係依據本發明之另一實施例所述之具有以STI 區隔結構之無閘極二極體的剖面示意圖； 第10圖係繪示應用本發明之無閘極二極體元件在輸 入端靜電放電防護電路上之應用； 第11圖係繪示應用本發明之無閘極二極體元件在輸 出端靜電放電防護電路上之應用； 第12圖係繪示應用本發明之無閘極二極體元件在輸 入端靜電放電防護電路上之另一種應用；以及 經濟部智慧財產局員工消費合作社印製 第13圖係繪示利用本發明之無閘極二極體元件來實 現第12圖的ESD箝制電路。 標號說明： 12絕緣層 16 N+擴散區 20 P+擴散區 24 P+區（鬧極） 10基底 14 STI結構 18 N-(或 P-)井 22 N+區（閘極） 本紙張尺度適用中國國家標準（CNS)A丨規格（21〇χ 297公坌） 519749 A7 7897twf.doc/〇〇9 B7 五、發明說明) 經濟部智慧財產局員工消費合作社印製 26間隙壁 40基底 42絕緣層 44 STI結構 46N+擴散區 48 N-(或 P-)井 50 P+擴散區 60、70 STI 結構 62、72絕緣層 64、66、68離子植入區 74、76、78離子植入區 100a/b基底 102a/b絕緣層 104a/b矽層 106a/b氮化砂層 108a/b光阻 110a/b STI 結構 112a/b光阻 114a/b井區 116a/b光阻 118a/b離子植入區 120井區 200a/b基底 202a/b井區 204a/b氮化砂層 206a/b光阻 208a/b STI 結構 210a/b光阻 212a/b離子植入區 214a/b光阻 216a/b離子植入區 218井區 300輸入焊塾 302第一二極體串 304第二二極體串 306內部電路 310輸出焊墊 312第一二極體串 314第二二極體串 316預驅動電路 320輸入焊墊 322內部電路 324 ESD箝制電路 (請先閱讀背面之注意事項再填寫本頁) 11 本紙張尺度適用中0國家標準（CNS)A丨規格（210 χ 297公Μ ) 519749 Λ7 H7 7897twf.doc/〇〇9 五、發明說明（\〇 ) 330輸入焊墊 332內部電路 334二極體串 奮施例 第2圖係依據本發明之一實施例所述之不具有STI隔 離結構（STI-blocking structure)之無閘極二極體（non-gated diode)的剖面示意圖。如第2圖所示，SOI閘極二極體係 形成於一 SOI基底上，其包括基底40、絕緣層42與矽層。 基底40可以爲P-型或N-型基底，而絕緣層42則可以如 埋入式氧化層。具有STI區隔結構之SOI二極體則形成於 矽層之中。在矽層中，SOI二極體係形成於兩個STI結構 44之間，亦即構成SOI二極體之離子植入區均被兩個STI 結構所隔離。在絕緣層42上與兩個STI結構之間則形成 濃度較淡的P型或N型離子（P-井或N-井）之井區50。此 外，在P-或N-井50之角落且鄰接兩個STI結構44則分 別形成濃度較高的P型擴散區（P+)48與N型擴散區 (N+)46 〇 接著要說明在SOI製程中形成STI結構有兩種：STI 隔離結構（STI-isolating structure)與不具有STI隔離結構 (STI-blocking structure)。第3A圖與第3B圖分別繪示出 此兩種結構的上視圖。以下的說明將指出STI隔離結構 (STI-isolating structure)無法形成SOI二極體，因爲每個離 子植入區均被STI結構隔離開。如第3A圖所示，在絕緣 層(埋入式氧化層)62上之矽層中形成數個STI結構60，而 離子植入區64(N+)、66(P+)與68(N+)則個別形成於STI結 12 本紙張尺度適用中國國家標準（CNS)A丨規格（210x 297公堃） ------------in----訂------丨丨-線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 519749 7897twf·doc/〇〇9 五、發明說明（\\) 構60之間，兩兩彼此不連接，因此無法形成二極體之P-N接面。其次，如第3B圖所示，在絕緣層(埋入式氧化層)72 上之矽層中形成兩個ST1結構7〇，而離子植入區74(N+)、 76(P+)與78(N+)則均形成於兩個STI結構70之間，因此 可以形成二極體之P-N接面 第4A圖至第4G圖係繪示以SOI製程來製作出具有 STI隔離結構，而第5A圖至第5G圖係繪示以SOI製程來 製作出不具有STI隔離結構。由結果可以看出具有STI隔 離結構之製程中的離子植入區係兩兩彼此不連接，因此無 法形成二極體之P-N接面。 請參考第4A圖與第5A圖，首先提供一基底l〇〇a、 100b。接著，在基底100a、l〇〇b上分別形成絕緣層l〇2a、 102b。之後，在絕緣層102a ' l〇2b上形成一砂層。絕緣 層102a、102b可以是埋入式氧化層。此外，在矽層植入P 型離子，以形成P型井區l〇4a、104b。至此，兩種製程的 步驟仍相同。 接著，參考第4B圖與第4C圖，繼續形成一墊氧化層 (pad oxide)106b與光阻108b，並暴露出要形成STI結構的 區域。接著，以墊氧化層l〇6b與光阻.108b爲罩幕，將P 型井（矽層）l〇4b蝕刻出溝渠後，再移除墊氧化層106b與 光阻108b。之後，再以絕緣材料塡入溝渠，並進行平坦化 以形成STI結構。參考第4D圖，接著形成光阻112b於部 分P型井104b與部分STI結構ll〇b上，並暴露出其中之 一被STI結構所圍出的P型井區104b。接著，進行離子植 13 本 張&度適用中國國家標準（CNSM丨規格（210x297公餐） (請先閱讀背面之注意事項再填寫本頁) .i——— —訂·---丨-線. 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 519749 7897twf.d〇c/〇〇9 五、發明說明（VV) 入步驟，將P型離子植入暴露出來的P型井區104b，以 形成P+型區域114b。最後，如第4E圖所示，將光阻112b 移除。接著，如第4F圖所示，形成光阻116b於P+區域 114b，並進行離子植入步驟。將N型離子植入於暴露出的 P型井區中，以形成N+區域118b。最後，移除光阻116b， 如第4 G圖所示。 接著，參考第5B圖與第5C圖，繼續形成一墊氧化層 106a與光阻l〇8a，並暴露出要形成STI結構的區域。接 著，以墊氧化層106a與光阻108a爲罩幕，將P型井(矽 層）l〇4a蝕刻出溝渠後，再移除墊氧化層i〇6a與光阻l〇8a。 之後，再以絕緣材料塡入溝渠，並進行平坦化以形成STI 結構。參考第5D圖，接著形成光阻112a於部分P型并l〇4a 與部分STI結構110a上，並暴露出部分p型井區104a。 接著，進行離子植入步驟，將P型離子植入暴露出來的P 型并區l(Ma，以形成P+型區域U4a。最後，如第5E圖 所示，將光阻112a移除。接著，如第5F圖所示，形成光 阻116a於P+區域114a，並進行離子植入步驟。光阻116a 之寬度略大於底下覆蓋的P+區域114a。接著，將N型離 子植入於暴露出的P型井區104a中，以形成N+區域ll8a。 最後，移除光阻116a，如第5G圖所示。因爲光阻〗16a 之見度略大於底下覆室的P+區域114a，所以在N+區域118a 與P+區域1 l4a之間會存在P-井區120，具有寬度SP。 如上所述，比較第4G圖與第5g圖可以得知，只有 不具有STI隔離結構（STI-blocking structure)的製程可以形 (請先閱讀背面之注意事項再填寫本頁) · ϋ I ϋ I n I ϋ ( n 1 n ϋ I ϋ ϋ I ϋ i ·1 ϋ ϋ ϋ ϋ ϋ ϋ I ϋ ϋ I .1 H ϋ ϋ — — — — — — 本紙張汶度適用中國國家標準（CNS)A1規格（21〇x 297公坌） 519749 Λ7 7897twf.d〇c/009 五、發明說明（〇 ) 成SOI二極體。 (請先閱讀背面之注意事項再填寫本頁) 影響應用於ESD防護電路之SOI CMOS製程之無閘 極STI區隔結構之二極體的主要參數爲二極體尺寸、井區 離子植入濃度以及二極體之陰極節點與陽極節點間的間隔 (spacing，SP)。其中間隔SP之參數不僅僅影響在二極體 順向偏壓下’ ESD放電之導通電阻(〇n-resistance)，他也影 響二極體之逆向崩潰電壓。因此，藉由適當地控制間隔SP 値，可以製作出在ESD保護電路中任何適合的逆向崩潰 電壓値。 第6A圖至第6G圖係繪示以基體CMOS製程來製作 出具有STI隔離結構，而第7A圖至第7G圖係繪示以基 體CMOS製程來製作出不具有STI隔離結構之二極體元 件。 請參考第6A圖與第7A圖，首先提供一基底200a、 200b。接著，在基底200a、200b上分別形成P型井區202a、 202b。至此，兩種製程的步驟仍相同。 經濟部智慧財產局員工消費合作社印製 接著，參考第6B圖與第6C圖，繼續形成一墊氧化層 (pad oxide)204b與光阻206b，並暴露出要形成STI結構的 區域。接著，以墊氧化層204b與光阻206b爲罩幕，將p 型井202b蝕刻出溝渠後，再移除墊氧化層204b與光阻 206b。之後，再以絕緣材料塡入溝渠，並進行平坦化以形 成STI結構。參考第6D圖，接著形成光阻2l〇b於部分P 型井202b與部分STI結構208b上，並暴露出其中之一被 STI結構所圍出的P型井區202b。接著，進行離子植入步 15 本紙張尺度適用中阀國家標準（CNSM丨規格（210 x 297公釐） 519749 7 8 9 7 twf · :/009 Λ7 H7 五、發明說明（γ/V ) (請先閱讀背面之注意事項再填寫本頁> 驟’將Ρ型離子植入暴露出來的Ρ型井區202b，以形成Ρ+ 型擴散區域212b。最後，如第6E圖所示，將光阻210b 移除。接著，如第6F圖所示，形成光阻214b於P+擴散 區域212b，並進行離子植入步驟。將n型離子植入於暴 露出的P型井區202b中，以形成N+擴散區域216b。最後， 移除光阻214b，如第6G圖所示。 經濟部智慧財產局員工消費合作社印製 接著，參考第7B圖與第7C圖，繼續形成一墊氧化層 204a與光阻206a，並暴露出要形成STI結構的區域。接 著，以墊氧化層204a與光阻206a爲罩幕，將ρ型井202a 蝕刻出溝渠後，再移除墊氧化層204a與光阻206a。之後， 再以絕緣材料塡入溝渠，並進行平坦化以形成STI結構 208a。參考第7D圖，接著形成光阻210a於部分P型井202a 與部分STI結構208a上，並暴露出部分ρ型井區202a。 接著，進行離子植入步驟，將P型離子植入暴露出來的P 型井區202a，以形成P+型區域212a。最後，如第7E圖 所示，將光阻210a移除。接著，如第7F圖所示，形成光 阻214a於P+區域212a，並進行離子植入步驟。光阻214a 之寬度略大於底下覆蓋的P+區域212a。接著，將N型離 子植入於暴露出的P型井區202a中，以形成N+區域216a。 最後，移除光阻212a，如第7G圖所示。因爲光阻214a 之寬度略大於底下覆蓋的P+區域212a，所以在N+區域216a 與P+區域212a之間會存在P-井區218，具有寬度SP。 如上所述，比較第6G圖與第7G圖可以得知，只有 不具有STI隔離結構（STI-blocking structure)的製程可以形 16 本紙張尺度適用中國國家標準（CNSM丨规格（21〇x 297公釐） 經濟部智慧財產局員工消費合作社印製 519749 五、發明說明（\< ) 成相臨的二極體結構。 影響應用於ESD防護電路之基體CMOS製程之無閘 極STI區隔結構之二極體的主要參數爲二極體尺寸、井區 離子植入濃度以及二極體之陰極節點與陽極節點間的間隔 (spacing ’ SP)。其中間隔SP之參數不僅僅影響在二極體 順向偏壓下，ESD放電之導通電阻(〇n-resistance)，他也影 響二極體之逆向崩潰電壓。因此，藉由適當地控制間隔SP 値，可以製作出在ESD保護電路中任何適合的逆向崩潰 電壓値。 第8圖繪示有閘極與無閘極SOI二極體之邊長與ESD 電壓之間的比較關係圖。由圖可以看出幾點結論。第一： 二極體的邊長越長的話’元件所能夠承受的ESD放電電 壓越大，也越能保護內部電路。第二：很明顯地’無閘極 SOI二極體所能承受的ESD電壓大於有閘極S01二極體 (SOI lubistor diode)。由於 ESD 耐壓度（ESD robustness)與 二極體邊長間的關係爲線性關係。因此’可以很輕易地利 用本發明之SOI無閘極二極體來預估與設計靜電放電保護 電路之ESD等級。 第9圖係依據本發明之另一^實施例所述之不具有STI 隔離結構之無閛極二極體的剖面示意圖。如第9圖所示’ Sf〇i ^極二極體係形成於一 S01基底上，其包括基底90' 絕緣層92與矽餍。基底90可以爲p-型或N_型基底’而 絕緣層92則可以如埋入式氧化層。不具有STI隔離結構 之s〇I二極體則形成於矽層之中。在矽層中，SOI二極體 17 1本紙張义度適用中阀國家標(~;1()χ29/ Λg} --1 — — — — — — — — - — ——HI— ^ ·1111111« · (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 519749 五、發明說明（屮） 係形成於兩個STI結構94之間，亦即構成SOI二極體之 離子植入區均被兩個STI結構所隔離。在絕緣層92上與 兩個STI結構之間則形成兩個相鄰的濃度較淡之p型與n 型離子（P-井或N-井）之井區。此外，在？_與N—井區98b、 98a外側與STI結構94則分別形成濃度較高的p型擴散區 (P+)96b與N型擴散區(N+)96a。此實施例與第2圖之實施 例的差別在於，第9圖所示之SOI無閘極二極體之PN接 面係在於整個結構的中間，而第2圖所示之PN接面則位 於一側。 接著以數個例子來說明應用本發明之SOI無閘極二極 體之ESD防護電路。 第10圖係繪示應用本發明之第2圖或第9圖的SOI 無閘極二極體之ESD防護電路。如第1〇圖所示，ESD防 護電路包括一輸入焊墊(input pad)300，第一二極體D1與 第二二極體D2，第一二極體串302、第二二極體串304， 輸入電阻R，以及高電壓供應線（Vdd voltage supply rail) Vdd與低電壓供應線（Vss voltage supply rail) Vss。內部電 路306係連接到高電壓供應線Vdd與低電壓供應線Vss以 及輸入電阻R之間。第一二極體D1之陰極連接到Vdd， 而陽極連接到焊墊300;第二二極體D2之陽極連接到Vss， 而陰極連接到焊墊300。第一二極體串302係由複數個二 極體Dul，Du2，...，Dun以陽極陰極方式彼此串聯起來，其 中二極體Dul之陽極連接到Vdd，二極體Dun之陰極連接 到焊墊300。第二二極體串304係由複數個二極體 18 I I II — — — — — — — · I I I I I I I ^ ·1111111 ^__w— — — — — — — — — — — — — I I — I II (請先閱讀背面之注意事項再填寫本頁) _ 本紙張尺度適用中國國家標準（CNSM丨規格（210x297公坌) " 519749 五、發明說明） (請先閱讀背面之注意事項再填寫本頁)Figures 4A to 4G show the use of the SOI process to produce STI 9 paper standards. 1¾ 0 standard (CNS) A · 丨 specifications (210 X 297 g t) 519749 5. Description of the invention (&g; g ) Isolation structure, (Please read the precautions on the back before filling out this page) Figures 5A to 5G are shown using SOI process to make the structure without ST1; Figures 6A to 6G are shown with The base CMOS process is used to fabricate the structure with STI; Figures 7A to 7G show the use of the base CMOS process to produce the structure without STI; Figure 8 shows the gate and non-gate SOI diodes Figure 9 shows the comparison relationship between the side length and the ESD voltage. Figure 9 is a schematic cross-sectional view of a gateless diode with an STI separation structure according to another embodiment of the present invention. Figure 10 is a drawing Fig. 11 shows the application of the gateless diode element of the present invention to the electrostatic discharge protection circuit at the input end; Fig. 11 shows the application of the gateless diode element of the present invention to the electrostatic discharge protection circuit at the output end Figure 12 shows the application of the gateless diode element Another application on the input electrostatic discharge protection circuit; and printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 13 shows the use of the gateless diode element of the present invention to implement the ESD clamping circuit of Figure 12. Explanation of symbols: 12 insulating layer 16 N + diffusion region 20 P + diffusion region 24 P + region (alarm) 10 substrate 14 STI structure 18 N- (or P-) well 22 N + region (gate) This paper is applicable to Chinese national standards ( CNS) A 丨 Specifications (21〇χ297297) 519749 A7 7897twf.doc / 〇〇9 B7 V. Description of the invention) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, the Consumer Cooperatives 26, the spacer 40, the substrate 42, the insulation layer 44 and the STI structure 46N + Diffusion region 48 N- (or P-) well 50 P + diffusion region 60, 70 STI structure 62, 72 Insulation layer 64, 66, 68 Ion implantation region 74, 76, 78 Ion implantation region 100a / b Substrate 102a / b Insulating layer 104a / b Silicon layer 106a / b Nitrided sand layer 108a / b Photoresistor 110a / b STI structure 112a / b Photoresistor 114a / b Well area 116a / b Photoresistance 118a / b Ion implantation area 120 Well area 200a / b substrate 202a / b well area 204a / b nitrided sand layer 206a / b photoresist 208a / b STI structure 210a / b photoresist 212a / b ion implantation area 214a / b photoresist 216a / b ion implantation area 218 well area 300 input welding pad 302 first diode string 304 second diode string 306 internal circuit 310 output pad 312 first diode string 314 second diode string 316 pre-drive Circuit 320 Input pad 322 Internal circuit 324 ESD clamping circuit (please read the precautions on the back before filling this page) 11 This paper is applicable to 0 National Standards (CNS) A 丨 Specifications (210 χ 297mm) 519749 Λ7 H7 7897twf.doc / 〇〇9 V. Description of the invention (\ 〇) 330 input pad 332 internal circuit 334 diode string embodiment Example 2 is based on an embodiment of the present invention without STI isolation structure ( A schematic cross-sectional view of a non-gated diode (STI-blocking structure). As shown in FIG. 2, the SOI gate-diode system is formed on an SOI substrate, which includes a substrate 40, an insulating layer 42, and a silicon layer. The substrate 40 may be a P-type or N-type substrate, and the insulating layer 42 may be, for example, a buried oxide layer. An SOI diode with an STI barrier structure is formed in the silicon layer. In the silicon layer, the SOI diode system is formed between the two STI structures 44, that is, the ion implantation regions constituting the SOI diode are isolated by the two STI structures. A well region 50 of P-type or N-type ions (P-well or N-well) having a relatively low concentration is formed on the insulating layer 42 and between the two STI structures. In addition, at the corner of the P- or N-well 50 and adjacent to the two STI structures 44 are formed a high-concentration P-type diffusion region (P +) 48 and N-type diffusion region (N +) 46 respectively. Next, the SOI process will be explained. There are two types of STI structures: STI-isolating structure and STI-blocking structure. Figures 3A and 3B show top views of these two structures, respectively. The following description will point out that STI-isolating structures cannot form SOI diodes because each ion implantation region is isolated by the STI structure. As shown in FIG. 3A, several STI structures 60 are formed in the silicon layer on the insulating layer (buried oxide layer) 62, and the ion implantation regions 64 (N +), 66 (P +), and 68 (N +) are Individually formed at STI junction 12 This paper size applies to China National Standard (CNS) A 丨 Specifications (210x 297 cm) ------------ in ---- Order ------ 丨丨 -line (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519749 7897twf · doc / 〇〇9 V. Description of the invention (\\) Between structures 60 No connection, so the PN junction of the diode cannot be formed. Secondly, as shown in FIG. 3B, two ST1 structures 70 are formed in the silicon layer on the insulating layer (buried oxide layer) 72, and the ion implantation regions 74 (N +), 76 (P +), and 78 ( N +) are both formed between the two STI structures 70, so the PN junctions of the diodes can be formed. Figures 4A to 4G show the SOI process to produce the STI isolation structure, and Figures 5A to Figure 5G illustrates the use of the SOI process to fabricate a structure without STI isolation. It can be seen from the results that the ion implantation regions in the process having the STI isolation structure are not connected to each other, so the P-N junction of the diode cannot be formed. Please refer to FIG. 4A and FIG. 5A. First, a substrate 100a, 100b is provided. Next, insulating layers 102a and 102b are formed on the substrates 100a and 100b, respectively. After that, a sand layer is formed on the insulating layer 102a'102b. The insulating layers 102a and 102b may be buried oxide layers. In addition, P-type ions are implanted in the silicon layer to form P-type well regions 104a and 104b. So far, the steps of the two processes are still the same. Next, referring to FIG. 4B and FIG. 4C, a pad oxide layer 106b and a photoresist 108b are continuously formed, and the area where the STI structure is to be formed is exposed. Next, the pad oxide layer 106b and the photoresist 108b are used as a mask, the P-type well (silicon layer) 104b is etched out of the trench, and then the pad oxide layer 106b and the photoresist 108b are removed. After that, the trench is penetrated with an insulating material and planarized to form an STI structure. Referring to FIG. 4D, a photoresist 112b is then formed on part of the P-type well 104b and part of the STI structure 110b, and one of the P-type well regions 104b surrounded by the STI structure is exposed. Next, carry out ion implantation of 13 sheets & degrees to Chinese national standards (CNSM 丨 specifications (210x297 meals) (please read the precautions on the back before filling in this page). I ———— Order · --- 丨- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by 519749 7897twf.d〇c / 〇〇9 V. Description of Invention (VV) Steps to expose the P-type ion implantation P-type well region 104b to form a P + -type region 114b. Finally, as shown in FIG. 4E, the photoresist 112b is removed. Then, as shown in FIG. 4F, a photoresist 116b is formed in the P + region 114b, and is performed. Ion implantation step. N-type ions are implanted into the exposed P-type well area to form N + region 118b. Finally, photoresist 116b is removed, as shown in Figure 4G. Next, refer to Figure 5B and In FIG. 5C, a pad oxide layer 106a and a photoresist 108a are continuously formed, and the area where the STI structure is to be formed is exposed. Next, the pad oxide layer 106a and the photoresist 108a are used as a mask, and a P-type well (silicon layer) is formed. ) After the trench is etched by 104a, the pad oxide layer 106 and photoresist 108a are removed. After that, The edge material penetrates into the trench and is planarized to form an STI structure. Referring to FIG. 5D, a photoresist 112a is formed on part of the P-type and 104a and part of the STI structure 110a, and a part of the p-type well region 104a is exposed. Next, an ion implantation step is performed to implant the exposed P-type parallel region l (Ma to form a P + -type region U4a. Finally, as shown in FIG. 5E, the photoresist 112a is removed. Next, As shown in FIG. 5F, a photoresist 116a is formed in the P + region 114a, and an ion implantation step is performed. The width of the photoresist 116a is slightly larger than the P + region 114a covered below. Next, an N-type ion is implanted into the exposed P In the well region 104a, an N + region 118a is formed. Finally, the photoresist 116a is removed, as shown in FIG. 5G. Because the visibility of the photoresist 16a is slightly greater than the P + region 114a of the bottom cover, it is in the N + region 118a There will be a P-well region 120 with a width SP between the P + region 11 and 4a. As mentioned above, comparing Figure 4G and Figure 5g shows that only processes without STI-blocking structure can be used. Shape (please read the precautions on the back before filling this page) · ϋ I ϋ I n I (n 1 n ϋ I ϋ ϋ I ϋ i · 1 ϋ ϋ ϋ ϋ ϋ ϋ I ϋ ϋ I .1 H ϋ ϋ — — — — — — This paper is compliant with China National Standard (CNS) A1 specifications (21〇 x 297 males) 519749 Λ7 7897twf.doc / 009 V. Description of the invention (0) It becomes an SOI diode. (Please read the precautions on the back before filling this page) The main parameters of the diode that affect the gateless STI segmentation structure of the SOI CMOS process applied to ESD protection circuits are the diode size and ion implantation concentration in the well area And the spacing (SP) between the cathode and anode nodes of the diode. The parameter of the interval SP not only affects the on-resistance of the ESD discharge under forward bias of the diode, it also affects the reverse breakdown voltage of the diode. Therefore, by properly controlling the interval SP 値, any suitable reverse breakdown voltage 値 in an ESD protection circuit can be produced. Figures 6A to 6G show the use of a base CMOS process to fabricate a diode device with STI isolation, and Figures 7A to 7G show the use of a base CMOS process to fabricate a diode element without an STI isolation structure . Please refer to FIG. 6A and FIG. 7A. First, a substrate 200a, 200b is provided. Next, P-type well regions 202a and 202b are formed on the substrates 200a and 200b, respectively. So far, the steps of the two processes are still the same. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, referring to Figures 6B and 6C, a pad oxide layer 204b and a photoresist 206b are continuously formed, and the area where the STI structure is to be formed is exposed. Then, the pad oxide layer 204b and the photoresist 206b are used as masks, and the p-type well 202b is etched out of the trench, and then the pad oxide layer 204b and the photoresist 206b are removed. After that, the trench is penetrated with an insulating material and planarized to form an STI structure. Referring to FIG. 6D, a photoresist 21b is then formed on part of the P-type well 202b and part of the STI structure 208b, and one of the P-type well regions 202b surrounded by the STI structure is exposed. Next, proceed to the ion implantation step 15. This paper size is applicable to the Chinese valve national standard (CNSM 丨 specifications (210 x 297 mm) 519749 7 8 9 7 twf ·: / 009 Λ7 H7 V. Description of the invention (γ / V) (Please Read the precautions on the back before filling in this page. Step 'Implant P-type ions into the exposed P-type well region 202b to form a P + -type diffusion region 212b. Finally, as shown in Figure 6E, the photoresist 210b is removed. Then, as shown in FIG. 6F, a photoresist 214b is formed in the P + diffusion region 212b, and an ion implantation step is performed. An n-type ion is implanted into the exposed P-type well region 202b to form N + Diffusion area 216b. Finally, remove the photoresist 214b, as shown in Figure 6G. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Next, referring to Figures 7B and 7C, continue to form a pad oxide layer 204a and photoresist 206a, and the area where the STI structure is to be formed is exposed. Next, using the pad oxide layer 204a and the photoresist 206a as a mask, the p-well 202a is etched out of the trench, and then the pad oxide layer 204a and the photoresist 206a are removed. , And then pierce the trench with an insulating material and planarize to form an STI structure 208a. Referring to FIG. 7D, a photoresist 210a is then formed on part of the P-type well 202a and part of the STI structure 208a, and a part of the p-type well region 202a is exposed. Next, an ion implantation step is performed to expose the P-type ion implantation to expose The resulting P-type well region 202a forms a P + -type region 212a. Finally, as shown in FIG. 7E, the photoresist 210a is removed. Then, as shown in FIG. 7F, a photoresist 214a is formed in the P + region 212a, and The ion implantation step is performed. The width of the photoresist 214a is slightly larger than the P + region 212a covered below. Next, N-type ions are implanted into the exposed P-type well region 202a to form the N + region 216a. Finally, the light is removed Resistor 212a, as shown in Figure 7G. Because the width of the photoresist 214a is slightly larger than the P + region 212a covered underneath, there will be a P-well region 218 between the N + region 216a and the P + region 212a, with a width SP. As shown above As can be seen from the comparison between Fig. 6G and Fig. 7G, only processes without STI-blocking structure can form 16 paper standards that are applicable to Chinese national standards (CNSM 丨 specifications (21 × 297 mm)) Printed by Consumers Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 519749 V. Description of the invention (<) Diode structures adjacent to each other. The main parameters affecting the diodes of the gateless STI segmentation structure used in the base CMOS process of ESD protection circuits are the diode size, The ion implantation concentration in the well area and the spacing between the cathode and anode nodes of the diode (spacing 'SP). Among them, the parameter of the interval SP not only affects the on-resistance of the ESD discharge under forward bias of the diode, it also affects the reverse breakdown voltage of the diode. Therefore, by properly controlling the interval SP 値, any suitable reverse breakdown voltage 値 in an ESD protection circuit can be produced. Figure 8 shows the comparison between the edge length of the gated and non-gated SOI diodes and the ESD voltage. Several conclusions can be seen from the figure. First: The longer the side of the diode, the greater the ESD discharge voltage that the component can withstand, and the more it can protect the internal circuit. Second: Obviously, the ESD voltage that a gateless SOI diode can withstand is greater than a gated S01 diode (SOI lubistor diode). Because the relationship between ESD robustness and the side length of the diode is linear. Therefore, the SOI gateless diode of the present invention can be used to easily estimate and design the ESD level of the electrostatic discharge protection circuit. FIG. 9 is a schematic cross-sectional view of an electrodeless diode without an STI isolation structure according to another embodiment of the present invention. As shown in FIG. 9, the 'Sf0i' diode system is formed on a S01 substrate, which includes a substrate 90 ', an insulating layer 92, and a silicon wafer. The substrate 90 may be a p-type or N-type substrate 'and the insulating layer 92 may be, for example, a buried oxide layer. SoI diodes without the STI isolation structure are formed in the silicon layer. In the silicon layer, the SOI diode 17 1 paper is applicable to the national standard of the valve (~; 1 () χ29 / Λg} --1 — — — — — — — — — — — — 1111111 «· (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519749 5. Description of the Invention (屮) It is formed between two STI structures 94, which constitutes the SOI dipole The bulk ion implantation area is isolated by two STI structures. Two adjacent p-type and n-type ions (P-well or N-type) are formed on the insulating layer 92 and between the two STI structures. -Well). In addition, the p-type diffusion region (P +) 96b and N-type diffusion region (N +) 96a with higher concentrations are formed on the outside of the? _ And N-well regions 98b and 98a and the STI structure 94, respectively. The difference between this embodiment and the embodiment of FIG. 2 is that the PN junction of the SOI gateless diode shown in FIG. 9 is located in the middle of the entire structure, and the PN junction shown in FIG. 2 is located at Next, several examples will be used to explain the ESD protection circuit of the SOI gateless diode to which the present invention is applied. Fig. 10 shows the second or ninth diagram to which the present invention is applied. SOI ESD protection circuit without gate diode. As shown in Figure 10, the ESD protection circuit includes an input pad 300, a first diode D1 and a second diode D2. A diode string 302, a second diode string 304, an input resistor R, and a high voltage supply line (Vdd voltage supply rail) Vdd and a low voltage supply line (Vss voltage supply rail) Vss. The internal circuit 306 is connected to The high voltage supply line Vdd and the low voltage supply line Vss and the input resistance R. The cathode of the first diode D1 is connected to Vdd and the anode is connected to the bonding pad 300; the anode of the second diode D2 is connected to Vss, The cathode is connected to the bonding pad 300. The first diode string 302 is connected in series with each other by a plurality of diodes Dul, Du2, ..., Dun, in which the anode of the diode Dul is connected to Vdd, The cathode of the diode Dun is connected to the bonding pad 300. The second diode string 304 is composed of a plurality of diodes 18 II II — — — — — — — IIIIIII ^ · 1111111 ^ __ w — — — — — — — — — — — — — II — I II (Please read the notes on the back before filling This page) _ This paper scales applicable Chinese National Standards (CNSM Shu size (210x297 public dust) " 519749 V. invention will be described) (Please read the back of the precautions to fill out this page)

Ddl，Dd2,...，Ddn以陽極陰極方式彼此串聯起來，其中二極 體Ddl之陽極連接到焊墊300，二極體Ddn之陰極連接到 焊墊Vss。上述之第一二極體D1、第二二極體D2、第一 與第二二極體串302/304中的各個二極體均可以是前述第 2圖或第9圖所示之SOI無閘極二極體。此外，輸入電阻 R也可以連接到內部電路306中的一輸入緩衝器（未繪示出） 上 接著說明第1〇圖之ESD防護電路的運作方式。當相 對於高電壓供應線Vdd爲正電壓的ESD事件輸入到輸入 焊墊300時，第一二極體D1爲順向偏壓；並且因爲低電 壓供應線Vss爲浮置，所以第二二極體D2沒有作用。因 此，此ESD事件(電壓)會經由第一二極體D1放電到高電 壓供應線Vdd。同理，當相對於低電壓供應線Vss爲負電 壓的ESD事件輸入到輸入焊墊300時，第二二極體D2爲 順向偏壓；並且因爲高電壓供應線Vdd爲浮置，所以第一 二極體D1沒有作用。因此，此ESD事件(電壓)會經由第 二二極體D2放電到低電壓供應線Vss。 經濟部智慧財產局員工消費合作社印製 當相對於高電壓供應線Vdd爲負電壓的ESD事件輸 入到輸入焊墊300時，第一二極體D1爲逆向偏壓。因爲 低電壓供應線Vss爲浮置，所以在Vss上的電壓會跟上施 加於輸入焊墊300的負電壓。由於第二二極體D2之順向 導通電壓與順向導通電阻，在Vss與輸入焊墊300會有些 微的電壓差存在。此時，第一二極體串302(Dul，Du2，...，Dun) 爲順向偏壓，所以ESD放電電流會經由第一二極體串 19 本紙張又度適用中P3國家標準（CNS)A l x 297公餐)" " 519749 五、發明說明（v$ ) 302(Dul，Du2，...，Dim)放電到 Vdd。 (請先閱讀背面之注意事項再填寫本頁) 當相對於低電壓供應線Vss爲正電壓的ESD事件輸 入到輸入焊墊300時，第二二極體D2爲逆向偏壓。因爲 高電壓供應線Vdd爲浮置，所以在Vdd上的電壓會跟上 施加於輸入焊墊300的正電壓。由於第一二極體D1之順 向導通電壓與順向導通電阻，在Vdd與輸入焊墊300會有 些微的電壓差存在。此時，因爲第二二極體串 304(Ddl，Dd2,…，Ddn)爲順向偏壓，所以ESD放電電流會 經由第二二極體串 304(0(11，0(12，...，0(111)放電到¥33。 經濟部智慧財產局員工消費合作社印製 第11圖係繪示應用本發明之第2圖或第9圖的SOI 無閘極二極體之ESD防護電路。如第11圖所示，ESD防 護電路包括一輸出焊墊（output pad)310，第一二極體D1與 第二二極體D2，第一二極體串312、第二二極體串314， PM0S電晶體Mp，NMOS電晶體Μη，以及高電壓供應線 (Vdd voltage supply rail) Vdd 與低電壓供應線（Vss voltage supply rail) Vss。預驅動電路316係連接到高電壓供應線 Vdd與低電壓供應線Vss以及PM0S電晶體Mp與NM0S 電晶體Μη的閘極之間。第一二極體D1之陰極連接到 Vdd，而陽極連接到焊墊310 ;第二二極體D2之陽極連接 到Vss，而陰極連接到焊墊310。第一二極體串312係由 複數個二極體Dul，Du2，...，Dim以陽極陰極方式彼此串聯 起來，其中二極體Dul之陽極連接到Vdd，二極體Dim之 陰極連接到焊墊310。第二二極體串314係由複數個二極 體Ddl，Dd2，...，Ddn以陽極陰極方式彼此串聯起來，其中 20 本紙張尺度適用中國國家標準（CNSM丨規格（210 x 297公釐） 519749 Λ7 H7 7897twf.doc/009 五、發明說明（θ ) 二極體Ddl之陽極連接到焊墊310，二極體Ddri之陰極連 接到焊墊Vss。PMOS電晶體Mp之源極連接到Vdd，而 NMOS電晶體Μη之源極連接到Vss。PMOS電晶體Mp之 汲極與NMOS電晶體Μη之汲極連接在一起至焊墊310。 上述之第一二極體D1、第二二極體D2、第一與第二二極 體串302/304中的各個二極體均可以是前述第2圖或第9 圖所示之SOI無閘極二極體。 接著說明第11圖之ESD防護電路的運作方式。當相 對於高電壓供應線Vdd爲正電壓的ESD事件輸入到輸出 焊墊310時，第一二極體D1爲順向偏壓；並且因爲低電 壓供應線Vss爲浮置，所以第二二極體D2沒有作用。因 此，此ESD事件(電壓)會經由第一二極體D1放電到高電 壓供應線Vdd。同理，當相對於低電壓供應線Vss爲負電 壓的ESD事件輸入到輸入焊墊310時，第二二極體D2爲 順向偏壓；並且因爲高電壓供應線Vdd爲浮置，所以第一 二極體D1沒有作用。因此，此ESD事件(電壓)會經由第 二二極體D2放電到低電壓供應線Vss。 當相對於高電壓供應線Vdd爲負電壓的ESD事件輸 入到輸出焊墊310時，第一二極體D1爲逆向偏壓。因爲 低電壓供應線Vss爲浮置，所以在Vss上的電壓會跟上施 加於輸出焊墊310的負電壓。此時，因爲第一二極體串 312(Dul，Du2，...，Dun)爲順向偏壓，所以ESD放電電流會 經由第一二極體串312(Dul，Du2，...，Dun)放電到Vdd。 當相對於低電壓供應線Vss爲正電壓的ESD事件輸 21 本紙張尺度適用中阀國家標準（CNS)A丨規格（21〇χ 297公g ) --------------------訂--------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 519749 五、發明說明（>〇 ) 入到輸出焊墊310時，第二二極體D2爲逆向偏壓。因爲 高電壓供應線Vdd爲浮置，所以在Vdd上的電壓會跟上 施加於輸出焊墊310的正電壓。此時，因爲第二二極體串 314(Ddl，Dd2，...，Ddn)爲順向偏壓，所以ESD放電電流會 經由第二二極體串314(Ddl，Dd2，...，Ddn)放電到Vss。 第12圖係繪示應用本發明之第2圖或第9圖的SOI 無閘極二極體之ESD防護電路。如第12圖所示，ESD防 護電路包括一輸入焊墊（input pad)320，第一二極體D1、 第二二極體D2，第三二極體D3 '第四二極體D4，輸入電 阻 R，高電壓供應線（Vdd voltage supply rail) Vdd、低電 壓供應線(Vss voltage supply rail)Vss、NMOS 電晶體 Μη 以及ESD箝制電路（ESD damp ciixuit)324。內部電路322 係連接到高電壓供應線Vdd與低電壓供應線Vss、輸入電 阻R與NMOS電晶體Μη的汲極之間。第一二極體D1與 第二二極體D2串聯在一起，其中第一二極體Di之陽極 連接到輸入焊塾330 ’而桌—^ ^極體D2之陰極連接到 Vdd。第三二極體D3與第四二極體D4串聯在—起，其中 第三二極體D3之陽極連接到Vss，而第四二極體d4之陰 極連接到輸入焊墊320。輸入電阻R的一端連接到焊塾32〇 而另一端連接到NMOS電晶體Μη的汲極與內部電路322。 NMOS電晶體Μη的閘極與源極則一起連接到vss。 之二極體Dl、D2、D3與D4均可以是前述第2圖或第9 圖所示之SOI無閘極二極體。 第12圖之電路操作基本上與前面第10圖或第u ^ {請先閱讀背面之注意事項再填寫本頁) ▼裝 ------ 訂---— II--—線一 22 本紙張尺度適用中國國家標準(CNSM丨規格（210 χ 297 519749 7 8 9 7 twf :/009 Λ7 H7 經濟部智慧財產局員工消費合作社印製 五、發明說明（>') 相同，在此便不在多做敘述。如第12圖所示，第一與第 二二極體Dl、D2是用來代替第10圖或第11圖中的二極 體D1，而第三與第四二極體D3、D4是用來代替第1〇圖 或第11圖中的二極體D2。假設二極體D1之寄生接面電 容爲C1，二極體D2之寄生接面電容爲C2，二極體D3之 寄生接面電容爲C3，二極體D4之寄生接面電容爲C4 ° 則第10圖之輸入電容Cin爲C1+C2，而在本實施例(第12 圖）之輸入電容 Cin’爲[C1C2/(C1+C2)] + [C3C4/(C3+C4)] ° 假如二極體Dl、D2、D3與D4均相同，則代表 C1=C2=C3=C4=0 於是可以得到 Cin=2C，而 Cin，=C。因 此，第12圖之例子的輸入電容便減少，也造成RC時間常 數變小。藉由降低輸入延遲，此ESD防護電路便可以應 用到高頻(high frequency，HF)電路。 第13圖係繪示第12圖的一變化例。一二極體串334 形成於Vdd與Vss之間，二極體串334係做爲ESD箝制 電路之用。二極體串334包括串聯連接的二極體Dpi、 Dp2、…、Dpn，均可以是前述第2圖或第9圖所示之SOI 無閘極二極體。 因此，本發明的優點如下： 1. 本發明之無閘極二極體係完全與製程相容。亦即， 無論是SOI CMOS製程(如第5A圖到第5G圖所示）或基體 CMOS製程（如第7A圖到第7G圖所示）均適用。 2. 由於比閘極二極體有更多的PN接面區域，本發明 所提供之SOI無閘極二極體具有更低的功率密度。 23 ---------—·丨丨丨丨丨丨丨訂·--------線 t請先間讀背面之注意事項再填寫本頁> 本紙張尺ΐϊ適用中國國家標準（CNSM丨規格（210x 297公堃) ' 519749 Λ7 H7 7897twf·doc/009 五、發明說明（Vl/) 3·由於比閘極二極體有更多的PN接面區域，本發明 所提供之SOI無閘極二極體具有更高的耐ESD程度。 4.本發明所提供之SOI無閘極二極體可以應用在混合 電壓與類比/數位應用上。此外，本發明所提供之SOI無 閘極二極體更可以作爲輸出入ESD防護電路，以及在順 向偏壓的情形下做爲Vdd與Vss間的保護電路。 綜上所述，雖然本發明已以較佳實施例揭露如上，然 其並非用以限定本發明，任何熟習此技藝者，在不脫離本 發明之精神和範圍內，當可作各種之更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者爲準。 ---I-----I — ·1111111 ----I I I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 24 本紙張尺度適用中阈國家標準（CNSM丨規格（210 X 297公釐）Ddl, Dd2, ..., Ddn are connected in series with each other in an anode-cathode manner, in which the anode of the diode Ddl is connected to the pad 300, and the cathode of the diode Ddn is connected to the pad Vss. Each of the diodes in the first diode D1, the second diode D2, the first and second diode strings 302/304 may be the SOI elements shown in FIG. 2 or FIG. 9 described above. Gate diode. In addition, the input resistor R can also be connected to an input buffer (not shown) in the internal circuit 306. Next, the operation of the ESD protection circuit in FIG. 10 will be described. When an ESD event with a positive voltage relative to the high voltage supply line Vdd is input to the input pad 300, the first diode D1 is forward biased; and because the low voltage supply line Vss is floating, the second diode Body D2 has no effect. Therefore, this ESD event (voltage) is discharged to the high voltage supply line Vdd via the first diode D1. Similarly, when an ESD event with a negative voltage relative to the low voltage supply line Vss is input to the input pad 300, the second diode D2 is forward biased; and because the high voltage supply line Vdd is floating, the first One diode D1 has no effect. Therefore, this ESD event (voltage) is discharged to the low voltage supply line Vss via the second diode D2. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. When an ESD event with a negative voltage relative to the high voltage supply line Vdd is input to the input pad 300, the first diode D1 is reverse biased. Because the low-voltage supply line Vss is floating, the voltage on Vss will keep up with the negative voltage applied to the input pad 300. Due to the forward conduction voltage and forward conduction resistance of the second diode D2, there is a slight voltage difference between Vss and the input pad 300. At this time, the first diode string 302 (Dul, Du2, ..., Dun) is forward biased, so the ESD discharge current will pass through the first diode string. CNS) A lx 297 public meal) " " 519749 V. Description of the invention (v $) 302 (Dul, Du2, ..., Dim) discharged to Vdd. (Please read the precautions on the back before filling this page.) When an ESD event with a positive voltage relative to the low voltage supply line Vss is input to the input pad 300, the second diode D2 is reverse biased. Because the high-voltage supply line Vdd is floating, the voltage on Vdd will keep up with the positive voltage applied to the input pad 300. Due to the forward conduction voltage and forward conduction resistance of the first diode D1, there is a slight voltage difference between Vdd and the input pad 300. At this time, because the second diode string 304 (Ddl, Dd2, ..., Ddn) is forward biased, the ESD discharge current will pass through the second diode string 304 (0 (11,0 (12, ... ., 0 (111) discharge to ¥ 33. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 11 shows the ESD protection circuit of the SOI gateless diode using Figure 2 or Figure 9 of the invention. As shown in Figure 11, the ESD protection circuit includes an output pad 310, a first diode D1 and a second diode D2, a first diode string 312, and a second diode string. 314, PM0S transistor Mp, NMOS transistor Mn, and high voltage supply line (Vdd voltage supply rail) Vdd and low voltage supply line (Vss voltage supply rail) Vss. The pre-drive circuit 316 is connected to the high voltage supply line Vdd and The low-voltage supply line Vss and the gate of the PM0S transistor Mp and the NM0S transistor Mη. The cathode of the first diode D1 is connected to Vdd and the anode is connected to the pad 310; the anode of the second diode D2 is connected To Vss, and the cathode is connected to the pad 310. The first diode string 312 is composed of a plurality of diodes Dul, Du2, ..., Dim with an anode cathode The anodes of the diode Dul are connected to Vdd, and the cathode of the diode Dim is connected to the pad 310. The second diode string 314 is composed of a plurality of diodes Ddl, Dd2, ..., Ddns are connected in series with each other in the form of anode and cathode, of which 20 paper sizes are applicable to Chinese national standards (CNSM 丨 specifications (210 x 297 mm) 519749 Λ7 H7 7897twf.doc / 009 5. Description of the invention (θ) anode of the diode Ddl Connected to the pad 310, the cathode of the diode Ddri is connected to the pad Vss. The source of the PMOS transistor Mp is connected to Vdd, and the source of the NMOS transistor Mη is connected to Vss. The drain of the PMOS transistor Mp and NMOS The drains of the transistor Mη are connected together to the bonding pad 310. Each of the first diode D1, the second diode D2, the first and second diode strings 302/304 may be It is the SOI gateless diode shown in the aforementioned Figure 2 or Figure 9. Next, the operation of the ESD protection circuit in Figure 11 is explained. When an ESD event with a positive voltage to the high-voltage supply line Vdd is input to the output When bonding pad 310, the first diode D1 is forward biased; and because of the low voltage supply The line Vss is floating, so the second diode D2 has no effect. Therefore, this ESD event (voltage) will be discharged to the high voltage supply line Vdd via the first diode D1. Similarly, when compared to the low voltage supply line When an ESD event with Vss being a negative voltage is input to the input pad 310, the second diode D2 is forward biased; and because the high voltage supply line Vdd is floating, the first diode D1 has no effect. Therefore, this ESD event (voltage) is discharged to the low voltage supply line Vss via the second diode D2. When an ESD event having a negative voltage with respect to the high voltage supply line Vdd is input to the output pad 310, the first diode D1 is reverse biased. Because the low voltage supply line Vss is floating, the voltage on Vss will keep up with the negative voltage applied to the output pad 310. At this time, because the first diode string 312 (Dul, Du2, ..., Dun) is forward biased, the ESD discharge current will pass through the first diode string 312 (Dul, Du2, ..., Dun) to Vdd. When an ESD event with a positive voltage Vss relative to the low-voltage supply line is lost, this paper size is applicable to the National Standard for Valves (CNS) A 丨 specifications (21〇χ 297 g) ------------ -------- Order -------- line (please read the notes on the back before filling this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 519749 V. Description of the invention (>) When the input pad 310 is input, the second diode D2 is reverse biased. Because the high-voltage supply line Vdd is floating, the voltage on Vdd will keep up with the positive voltage applied to the output pad 310. At this time, because the second diode string 314 (Ddl, Dd2, ..., Ddn) is forward biased, the ESD discharge current will pass through the second diode string 314 (Ddl, Dd2, ..., Ddn) discharge to Vss. FIG. 12 shows the ESD protection circuit of the SOI gateless diode using the second or the ninth figure of the present invention. As shown in FIG. 12, the ESD protection circuit includes an input pad 320, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. Resistor R, high voltage supply line (Vdd voltage supply rail) Vdd, low voltage supply line (Vss voltage supply rail) Vss, NMOS transistor Mn, and ESD damping circuit (ESD damp ciixuit) 324. The internal circuit 322 is connected between the high-voltage supply line Vdd and the low-voltage supply line Vss, the input resistance R, and the drain of the NMOS transistor Mn. The first diode D1 and the second diode D2 are connected in series, in which the anode of the first diode Di is connected to the input electrode 330 ′ and the cathode of the table ^ ^ pole D2 is connected to Vdd. The third diode D3 is connected in series with the fourth diode D4. The anode of the third diode D3 is connected to Vss, and the cathode of the fourth diode d4 is connected to the input pad 320. One end of the input resistance R is connected to the solder pad 32 and the other end is connected to the drain of the NMOS transistor Mn and the internal circuit 322. The gate and source of the NMOS transistor Mn are connected to vss together. The diodes D1, D2, D3, and D4 may all be SOI gateless diodes shown in the foregoing FIG. 2 or FIG. 9. The operation of the circuit in Figure 12 is basically the same as that in Figure 10 or u ^ {Please read the precautions on the back before filling in this page) ▼ Install ------ Order ----II --- Line 1 22 This paper size applies to Chinese national standards (CNSM 丨 specifications (210 χ 297 519 749 7 8 9 7 twf: / 009 Λ7 H7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs) 5. The invention description (>) is the same, here it is Do not go into more details. As shown in Figure 12, the first and second diodes D1, D2 are used to replace the diode D1 in Figure 10 or 11, and the third and fourth diodes D3 and D4 are used to replace diode D2 in Figure 10 or Figure 11. Assume that the parasitic junction capacitance of diode D1 is C1, and the parasitic junction capacitance of diode D2 is C2, diode. The parasitic junction capacitance of D3 is C3, and the parasitic junction capacitance of diode D4 is C4 °, then the input capacitance Cin of Fig. 10 is C1 + C2, and the input capacitance Cin 'of this embodiment (Fig. 12) is [C1C2 / (C1 + C2)] + [C3C4 / (C3 + C4)] ° If the diodes D1, D2, D3 and D4 are all the same, it means C1 = C2 = C3 = C4 = 0 and then Cin = 2C, and Cin, = C. Therefore, in Figure 12 The input capacitance of the element is reduced, which also causes the RC time constant to become smaller. By reducing the input delay, this ESD protection circuit can be applied to high frequency (HF) circuits. Fig. 13 is a drawing of Fig. 12 Variation. A diode string 334 is formed between Vdd and Vss. The diode string 334 is used as an ESD clamping circuit. The diode string 334 includes diodes Dpi, Dp2, ..., Dpn connected in series. Both can be SOI gateless diodes shown in Figure 2 or Figure 9. Therefore, the advantages of the present invention are as follows: 1. The gateless diode system of the present invention is completely compatible with the manufacturing process. That is, Both the SOI CMOS process (as shown in Figures 5A to 5G) or the base CMOS process (as shown in Figures 7A to 7G) are applicable. 2. Because there are more than gate diodes In the PN junction area, the SOI gateless diode provided by the present invention has a lower power density. 23 ----------- · 丨 丨 丨 丨 丨 丨 Order · ----- --- Please read the precautions on the back of the line before filling in this page> This paper size is applicable to the Chinese National Standard (CNSM 丨 Specification (210x 297 cm)) 519749 Λ7 H7 7897twf · doc / 009 V. Description of the invention (Vl /) 3. Since there is more PN junction area than the gate diode, the SOI non-gate diode provided by the present invention has higher ESD resistance degree. 4. The SOI gateless diode provided by the present invention can be applied to mixed voltage and analog / digital applications. In addition, the SOI gateless diode provided by the present invention can be used as an input / output ESD protection circuit, and as a protection circuit between Vdd and Vss in the case of forward bias. In summary, although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. --- I ----- I — · 1111111 ---- III (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 24 This paper applies the middle threshold national standard (CNSM 丨 Specifications (210 X 297 mm)

Claims (1)

519749519749 六、申請專利範圍 1. 一種無閘極二極體元件之靜電放電防護電路，耦接 於一輸入焊墊與一內部電路之間，包括： 一高電壓供應線與一低電壓供應線； (請先閲讀背面之注意事項再填寫本頁) 一第一二極體，具有一陽極耦接至該高電壓供應線與 一陰極耦接至一節點； 一第二二極體，具有一陰極耦接至該低電壓供應線與 一陽極耦接至該節點； 一第一二極體串，由複數個二極體串聯所構成，其中 具有一陽極耦接至該高電壓供應線與一陰極耦接至該節 點；以及 一第二二極體串，由複數個二極體串聯所構成，具有 一陰極耦接至該低電壓供應線與一陽極耦接至該節點。 2. 如申請專利範圍第1項所述之無閘極二極體元件之 靜電放電防護電路，其中當相對於該高電壓供應線之一正 電壓施加於該輸入焊墊時，該無閘極二極體元件之靜電放 電防護電路提供一條經由該第一二極體到該高電壓供應線 的放電路線。 經濟部中央標隼局員工消費合作社印裝 3. 如申請專利範圍第1項所述之無閘極二極體元件之 靜電放電防護電路，其中當相對於該低電壓供應線之一負 電壓施加於該輸入焊墊時，該無閘極二極體元件之靜電放 電防護電路提供一條經由該第二二極體到該低電壓供應線 的放電路線。 4. 如申請專利範圍第1項所述之無閘極二極體元件之 靜電放電防護電路，其中當相對於該高電壓供應線之一負 25 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X ：297公釐） 519749 7897twf.doc/009 Co D8 六、申請專利範圍 電壓施加於該輸入焊墊時，該無閘極二極體元件之靜電放 電防護電路提供一條經由該第二二極體、該第二二極體串 與該第一二極體串到該高電壓供應線的放電路線。 (請先閲讀背面之注意事項再填寫本頁) 5. 如申請專利範圍第1項所述之無閘極二極體元件之 靜電放電防護電路，其中當相對於該低電壓供應線之一高 電壓施加於該輸入焊墊時，該無閘極二極體元件之靜電放 電防護電路提供一條經由該第一二極體、該第一二極體串 .與該第二二極體串到該低電壓供應線的放電路線。 6. 如申請專利範圍第1項所述之無閘極二極體元件之 靜電放電防護電路，其中該第一與該第二二極體與該第一 與該第二二極體串中的各該些二極體均爲無閘極二極體， 且係利用絕緣層上有矽（SOI)之製程製作。 7. 如申請專利範圍第1項所述之無閘極二極體元件之 靜電放電防護電路，其中該第一與該第二二極體與該第一 與該第二二極體串中的各該些二極體均爲無閘極二極體， 且係利用基體金屬氧化物半導體（bulk CMOS)之製程製 作。 經濟部中央標準局員工消費合作社印袈 8. 如申請專利範圍第1項所述之無閘極二極體元件之 靜電放電防護電路，其中該第一與該第二二極體的尺寸相 同，均具有相等的接面電容。 9. 如申請專利範圍第1項所述之無閘極二極體元件之 靜電放電防護電路，其中該第一與該第二二極體的尺寸不 相同，其接面電容均不相同。 10. —種無閘極二極體元件之靜電放電防護電路，耦接 26 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 519749 A8 7897twf.doc/009 B8 C8 D8 六、申請專利範圍 於一輸出焊墊與一預驅動器之間，包括： 一高電壓供應線與一低電壓供應線，分別耦接到該預 驅動器； (請先閲讀背面之注意事項再填寫本頁) 一第一二極體，具有一陽極耦接至該高電壓供應線與 一陰極耦接至一節點； 一第二二極體，具有一陰極耦接至該低電壓供應線與 一陽極耦接至該節點； 一第一二極體串，由複數個二極體串聯所構成，其中 具有一陽極耦接至該高電壓供應線與一陰極耦接至該節 點； 一第二二極體串，由複數個二極體串聯所構成，具有 一陰極耦接至該低電壓供應線與一陽極耦接至該節點； 一第一型MOS電晶體，具有一源極耦接到該高電壓 供應線，一汲極耦接到該節點，一閘極耦接到該預驅動器； 以及 一第二型MOS電晶體，具有一源極耦接到該低電壓 供應線，一汲極耦接到該節點，一閘極耦接到該第一型MOS 電晶體該閘極。 11. 如申請專利範圍第10項所述之無閘極二極體元件 之靜電放電防護電路，其中當相對於該高電壓供應線之一 正電壓施加於該輸出焊墊時，該無閘極二極體元件之靜電 放電防護電路提供一條經由該第一二極體到該高電壓供應 線的放電路線。 12. 如申請專利範圍第10項所述之無閘極二極體元件 27 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I 519749 7897twf.doc/009 Co D8 六、申請專利範圍 (請先閲讀背面之注意事項再填寫本頁) 之靜電放電防護電路，其中當相對於該低電壓供應線之一 負電壓施加於該輸出焊墊時，該無閘極二極體元件之靜電 放電防護電路提供一條經由該第二二極體到該低電壓供應 線的放電路線。 13. 如申請專利範圍第10項所述之無閘極二極體元件 之靜電放電防護電路，其中當相對於該高電壓供應線之一 負電壓施加於該輸出焊墊時，該無閘極二極體元件之靜電 .放電防護電路提供一條經由該第二二極體、該第二二極體 串與該第一二極體串到該高電壓供應線的放電路線。 14. 如申請專利範圍第10項所述之無閘極二極體元件 之靜電放電防護電路，其中當相對於該低電壓供應線之一 高電壓施加於該輸出焊墊時，該無閘極二極體元件之靜電 放電防護電路提供一條經由該第一二極體、該第一二極體 串與該第二二極體串到該低電壓供應線的放電路線。 15. 如申請專利範圍第10項所述之無閘極二極體元件 之靜電放電防護電路，其中該第一與該第二二極體與該第 一與該第二二極體串中的各該些二極體均爲無閘極二極 體，且係利用絕緣層上有矽（SOI)之製程製作。 經濟部中央標準局員工消費合作社印製 16. 如申請專利範圍第10項所述之無閘極二極體元件 之靜電放電防護電路，其中該第一與該第二二極體與該第 一與該第二二極體串中的各該些二極體均爲無閘極二極 體，且係利用基體金屬氧化物半導體（bulk CMOS)之製程 製作。 17. 如申請專利範圍第10項所述之無閘極二極體元件 28 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 519749 7897twf.doc/009 Co D8 六、申請專利範圍 之靜電放電防護電路，其中該第一與該第二二極體的尺寸 相同，均具有相等的接面電容。 (請先閲讀背面之注意事項再填寫本頁) 18. 如申請專利範圍第10項所述之無閘極二極體元件 之靜電放電防護電路，其中該第一與該第二二極體的尺寸 不相同，其接面電容均不相同。 19. 如申請專利範圍第10項所述之無閘極二極體元件 之靜電放電防護電路，其中該第一型MOS電晶體係PMOS .電晶體，而該第二型MOS電晶體係NMOS電晶體。 20. —種無閘極二極體元件之靜電放電防護電路，耦接 於一輸入焊墊與一內部電路之間，包括： 一高電壓供應線與一低電壓供應線，均耦接至該內部 電路； 一第一二極體與一第二二極體，係串聯一起，其中該 第一二極體之陽極耦接至一節點，而該第二二極體之陰極 耦接至該高電壓供應線； 一第三二極體與一第四二極體，係串聯一起，其中該 第三二極體之陽極耦接至該低電壓供應線，而該第四二極 體之陰極耦接至該節點；以及 經濟部中央標準局員工消費合作社印製 一靜電放電箝制電路，耦接於該高電壓供應線與該低 電壓供應線之間。 21. 如申請專利範圍第20項所述之無閘極二極體元件 之靜電放電防護電路，其中該靜電放電箝制電路係由複數 個二極體串聯而成，具有陽極耦接到該高電壓供應線與陰 極耦接到該低電壓供應線。 29 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 519749 六、申請專利範圍 (請先閲讀背面之注意事項再填寫本頁) 22. 如申請專利範圍第20項所述之無閘極二極體元件 之靜電放電防護電路，其中該第一、該第二、該第三與該 第四二極體以及該靜電放電箝制電路中的各該些二極體均 爲無閘極二極體，且係利用絕緣層上有矽（SOI)之製程製 作。 23. 如申請專利範圍第20項所述之無閘極二極體元件 之靜電放電防護電路，其中該第一、該第二、該第三與該 .第四二極體均爲無閘極二極體，且係利用基體金屬氧化物 半導體(bulk CMOS)之製程製作。 24. 如申請專利範圍第21項所述之無閘極二極體元件 之靜電放電防護電路，其中該靜電放電箝制電路中的各該 些二極體均爲無閘極二極體，且係利用絕緣層上有矽（SOI) 之製程製作。 25. 如申請專利範圍第20項所述之無閘極二極體元件 之靜電放電防護電路，其中該靜電放電箝制電路中的各該 些二極體均爲無閘極二極體，且係利用基體金屬氧化物半 導體(bulk CMOS)之製程製作。 經濟部中央標準局員工消費合作社印製 26. 如申請專利範圍第20項所述之無閘極二極體元件 之靜電放電防護電路，其中該第一、該第二、該第三與該 第四二極體的尺寸相同，均具有相等的接面電容。 27. 如申請專利範圍第20項所述之無閘極二極體元件 之靜電放電防護電路，其中該第一、該第二、該第三與該 第四二極體的尺寸不相同，其接面電容均不相同。 28. —種絕緣層上有矽之無閘極二極體結構，包括： 30 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 519749 7897twf.doc/009 g D8 六、申請專利範圍 一絕緣層上有矽基底，包括一基底、一絕緣層與一矽 層依序堆疊； (請先閲讀背面之注意事項再填寫本頁) 一對隔離結構，位於該矽層中，使在該對隔離結構之 間與該矽層中具有一井區； 一第一型離子植入區與一第二型離子植入區，位於該 井區中並且分別緊鄰各該隔離結構。 29. 如申請專利範圍第28項所述之絕緣層上有矽之無 .閘極二極體元件，其中該第一型離子植入區與該第二型離 子植入區分別植入P型與N型離子。 30. 如申請專利範圍第28項所述之絕緣層上有矽之無 閘極二極體元件，其中該井區係植入淺濃度的P型離子。 31. 如申請專利範圍第28項所述之絕緣層上有矽之無 閘極二極體元件，其中該井區矽植入淺濃度的N型離子。 32. 如申請專利範圍第28項所述之絕緣層上有矽之無 閘極二極體元件，其中該絕緣層矽埋入式氧化層。 33. 如申請專利範圍第28項所述之絕緣層上有矽之無 閘極二極體元件，其中該對隔離結構爲淺溝渠隔離結構。 經濟部中央標準局員工消費合作社印製 34. —種絕緣層上有矽之無閘極二極體結構，包括： 一絕緣層上有矽基底，包括一基底、一絕緣層與一矽 層依序堆疊； 一對隔離結構，位於該矽層中，使在該對隔離結構之 間與該矽層中具有一第一井區與一第二井區，其中該第一 井區與該第二井區相鄰； 一第一型離子植入區與一第二型離子植入區，分別位 519749 A8 B8 C8 D8 7897twf.doc/009 六、申請專利範圍 (請先閲讀背面之注意事項再填寫本頁) 於該第一與該第二幷區中，並且分別緊鄰各該隔離結構， 藉以使該絕緣層上有矽之無閘極二極體元件之接面爲該第 一與該第二井區之接面。 35.如申請專利範圍第34項所述之絕緣層上有矽之無 聞極二極體元件’其中該第一型離子植入區與該第二型離 子植入區分別植入P型與N型離子。 36·如申請專利範圍第35項所述之絕緣層上有矽之無 .閘極二極體元件，其中該第一與該第二井區係分別植入淺 濃度的P型與N型離子。 37·如申請專利範圍第34項所述之絕緣層上有矽之無 閘極二極體元件’其中該絕緣層矽埋入式氧化層。 38·如申請專利範圍第34項所述之絕緣層上有矽之無 聞極二極體元件’其中該對隔離結構爲淺溝渠隔離結構。 39·一種形成絕緣層上有矽之無閘極二極體的方法，包 括： 提供一絕緣層上有矽基底，包括一基底、一絕緣層與 一矽層依序堆疊； 經濟部中央標準局員工消費合作社印製 形成一對隔離結構於該矽層中，使在該對隔離結構之 間與該矽層中具有〜幷胃； 形成一第一型離子植入區與一第二型離子植入區於該 井區中’並且分別緊鄰各該隔離結構。 40.如申請專利範園第39項所述之形成絕緣層上有砂 之無閘極二極體的方法，其中該第一型離子植入區與該第 二型離子植入區分別植入P型與N型離子。 32 本紙張尺度適用中國國家標準（CNS ) A4規格（X 297公董） 519749 A8 7897twf.doc/009 g D8 六、申請專利範圍 41. 如申請專利範圍第39項所述之形成絕緣層上有矽 之無閘極二極體的方法，其中該井區係植入淺濃度的P型 離子。 (請先閲讀背面之注意事項再填寫本頁) 42. 如申請專利範圍第39項所述之形成絕緣層上有矽 之無閘極二極體的方法，其中該井區矽植入淺濃度的N型 離子。 43. —種基體COMS無閘極二極體結構，包括： 一基底，該基底具有一井； 一對隔離結構，位於該基底中； 一第一型離子植入區，位於該井中，且位於該對隔離 結構之間；以及 一對第二型離子植入區，位於井中並且分別緊鄰各該 隔離結構，其中該對第二型離子植入區分別以該井與該第 一型離子植入區分離。 44. 如申請專利範圍第43項所述之基體COMS無閘極 二極體，其中該第一型離子植入區與該第二型離子植入區 分別植入P型與N型離子。 經濟部中央標準局員工消费合作社印袈 45. 如申請專利範圍第43項所述之基體COMS無閘極 二極體，其中該井區係植入淺濃度的P型離子。 46. —種形成基體COMS無閘極二極體的方法，包括： 提供一基底，該基底中形成一井； 形成一對隔離結構於該基底； 形成一第一型離子植入區與該井中，且位於該對隔離 結構之間；以及 33 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 519749 A8 7897twf.doc/009 ?营 D8 六、申請專利範圍 形成一對第二型離子植入區於該井區中，並且分別緊 鄰各該隔離結構，各該第二型離子植入區分別以該井與該 第一型離子植入區分離。 47. 如申請專利範圍第46項所述之形成基體COMS無 閘極二極體的方法，其中該第一型離子植入區與該第二型 離子植入區分別植入P型與N型離子。 48. 如申請專利範圍第46項所述之形成基體COMS無 .閘極二極體的方法，其中該井區係植入淺濃度的P型離子。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印袈 34 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）6. Scope of patent application 1. An electrostatic discharge protection circuit of a gateless diode element is coupled between an input pad and an internal circuit, and includes: a high-voltage supply line and a low-voltage supply line; ( Please read the precautions on the back before filling this page) A first diode with an anode coupled to the high voltage supply line and a cathode coupled to a node; a second diode with a cathode coupled Connected to the low voltage supply line and an anode coupled to the node; a first diode string composed of a plurality of diodes connected in series, with an anode coupled to the high voltage supply line and a cathode coupled Connected to the node; and a second diode string composed of a plurality of diodes connected in series, having a cathode coupled to the low voltage supply line and an anode coupled to the node. 2. The electrostatic discharge protection circuit for a gateless diode element as described in item 1 of the scope of patent application, wherein when a positive voltage is applied to the input pad relative to one of the high voltage supply lines, the gateless The electrostatic discharge protection circuit of the diode element provides a discharge path through the first diode to the high voltage supply line. Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 3. The electrostatic discharge protection circuit of the gateless diode element as described in item 1 of the scope of patent application, wherein when a negative voltage is applied relative to one of the low voltage supply lines At the input pad, the ESD protection circuit of the gateless diode element provides a discharge path through the second diode to the low voltage supply line. 4. The electrostatic discharge protection circuit of the gateless diode element as described in item 1 of the scope of the patent application, wherein when it is minus 25 relative to one of the high-voltage supply lines, the paper size applies to the Chinese National Standard (CNS) A4 specification (210 X: 297 mm) 519749 7897twf.doc / 009 Co D8 6. When the patent application range voltage is applied to the input pad, the ESD protection circuit of the gateless diode element provides a line through the second two A discharge path of the polar body, the second diode string, and the first diode string to the high-voltage supply line. (Please read the precautions on the back before filling this page) 5. As described in item 1 of the scope of patent application, the ESD protection circuit of the gateless diode element is higher than one of the low voltage supply lines When a voltage is applied to the input pad, the ESD protection circuit of the gateless diode element provides a path through the first diode, the first diode string, and the second diode string to the Discharge route of low voltage supply line. 6. The electrostatic discharge protection circuit for a gateless diode element as described in item 1 of the scope of the patent application, wherein the first and the second diodes and the first and the second diode strings in the Each of these diodes is a gateless diode, and is manufactured by a process in which silicon (SOI) is on an insulating layer. 7. The electrostatic discharge protection circuit of the gateless diode element according to item 1 in the scope of the patent application, wherein the first and the second diodes and the first and the second diode strings in the Each of these diodes is a gateless diode, and is manufactured by using a bulk metal oxide semiconductor (bulk CMOS) process. Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China 8. As described in item 1 of the patent application scope, the electrostatic discharge protection circuit of the non-gate diode element, wherein the first and second diodes have the same size, All have equal junction capacitance. 9. The ESD protection circuit for a gateless diode element as described in item 1 of the scope of the patent application, wherein the first and second diodes are different in size, and their junction capacitances are different. 10. —A kind of electrostatic discharge protection circuit without gate diode element, coupled to 26 paper sizes applicable to Chinese National Standard (CNS) A4 specification (210 X 297 mm) 519749 A8 7897twf.doc / 009 B8 C8 D8 6 The scope of patent application is between an output pad and a pre-driver, including: a high-voltage supply line and a low-voltage supply line, respectively coupled to the pre-driver; (Please read the precautions on the back before filling this page ) A first diode with an anode coupled to the high voltage supply line and a cathode coupled to a node; a second diode with a cathode coupled to the low voltage supply line and an anode Connected to the node; a first diode string composed of a plurality of diodes connected in series, with an anode coupled to the high voltage supply line and a cathode coupled to the node; a second diode A string is composed of a plurality of diodes connected in series, having a cathode coupled to the low voltage supply line and an anode coupled to the node; a first type MOS transistor having a source coupled to the high voltage Supply line, one sink coupled Connected to the node, a gate is coupled to the pre-driver; and a second type MOS transistor having a source coupled to the low voltage supply line, a drain coupled to the node, and a gate coupled Connected to the gate of the first MOS transistor. 11. The electrostatic discharge protection circuit for a gateless diode device as described in item 10 of the scope of patent application, wherein when a positive voltage is applied to the output pad relative to one of the high voltage supply lines, the gateless The electrostatic discharge protection circuit of the diode element provides a discharge path through the first diode to the high voltage supply line. 12. The gateless diode element described in item 10 of the scope of patent application 27 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) I 519749 7897twf.doc / 009 Co D8 6. Apply for a patent Range (please read the precautions on the back before filling out this page) of the ESD protection circuit. When a negative voltage is applied to the output pad relative to one of the low voltage supply lines, the The ESD protection circuit provides a discharge path through the second diode to the low voltage supply line. 13. The electrostatic discharge protection circuit for a gateless diode element as described in item 10 of the scope of patent application, wherein when a negative voltage is applied to the output pad relative to one of the high voltage supply lines, the gateless The electrostatic discharge protection circuit of the diode element provides a discharge path through the second diode, the second diode string and the first diode string to the high voltage supply line. 14. The electrostatic discharge protection circuit for a gateless diode device as described in item 10 of the scope of patent application, wherein when a high voltage is applied to the output pad relative to one of the low voltage supply lines, the gateless The electrostatic discharge protection circuit of the diode element provides a discharge path through the first diode, the first diode string, and the second diode string to the low-voltage supply line. 15. The electrostatic discharge protection circuit for a gateless diode element as described in item 10 of the scope of patent application, wherein the first and the second diodes and the first and the second diode strings in the Each of these diodes is a gateless diode, and is manufactured by a process in which silicon (SOI) is on an insulating layer. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 16. The electrostatic discharge protection circuit of the gateless diode element as described in item 10 of the scope of patent application, wherein the first and second diodes and the first Each of the diodes in the second diode string is a gateless diode, and is manufactured by using a bulk metal oxide semiconductor (bulk CMOS) process. 17. The gateless diode element described in item 10 of the scope of patent application 28 This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 519749 7897twf.doc / 009 Co D8 6. Application The patented electrostatic discharge protection circuit, wherein the first and the second diodes have the same size, and both have the same interface capacitance. (Please read the precautions on the back before filling out this page) 18. As described in item 10 of the scope of patent application, the electrostatic discharge protection circuit of the gateless diode element, wherein the first and second diodes are The dimensions are different, and their junction capacitances are different. 19. The electrostatic discharge protection circuit for a gateless diode device as described in item 10 of the scope of patent application, wherein the first type MOS transistor system is a PMOS. Transistor, and the second type MOS transistor system is a NMOS transistor. Crystal. 20. —An electrostatic discharge protection circuit without a gate diode element, coupled between an input pad and an internal circuit, includes: a high voltage supply line and a low voltage supply line, both are coupled to the Internal circuit; a first diode and a second diode are connected in series, wherein the anode of the first diode is coupled to a node, and the cathode of the second diode is coupled to the high voltage A voltage supply line; a third diode and a fourth diode are connected in series, wherein the anode of the third diode is coupled to the low voltage supply line and the cathode of the fourth diode is coupled Connected to the node; and the consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs printed an electrostatic discharge clamping circuit coupled between the high-voltage supply line and the low-voltage supply line. 21. The electrostatic discharge protection circuit for a gateless diode element as described in item 20 of the scope of patent application, wherein the electrostatic discharge clamping circuit is formed by a plurality of diodes connected in series, and has an anode coupled to the high voltage. A supply line and a cathode are coupled to the low-voltage supply line. 29 This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 519749 6. Scope of patent application (please read the precautions on the back before filling this page) 22. If none of the scope of patent application is mentioned in item 20 Electrostatic discharge protection circuit of a gate diode element, wherein the first, the second, the third, and the fourth diodes and each of the diodes in the electrostatic discharge clamping circuit are all non-gate Diodes are manufactured using a silicon-on-insulator (SOI) process. 23. The electrostatic discharge protection circuit of the gateless diode element as described in the scope of the patent application, wherein the first, the second, the third, and the fourth diode are all gateless. Diodes are manufactured using a bulk CMOS process. 24. The electrostatic discharge protection circuit for a gateless diode element as described in item 21 of the scope of the patent application, wherein each of the diodes in the electrostatic discharge clamping circuit is a gateless diode, and is Fabricated using a process in which silicon is on the insulation (SOI). 25. The electrostatic discharge protection circuit for a gateless diode element as described in item 20 of the scope of the patent application, wherein each of the diodes in the electrostatic discharge clamping circuit is a gateless diode, and It is manufactured by using a bulk metal oxide semiconductor (bulk CMOS) process. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 26. The electrostatic discharge protection circuit of the gateless diode element as described in item 20 of the scope of patent application, wherein the first, the second, the third and the first The quadrupoles have the same size and all have the same junction capacitance. 27. The electrostatic discharge protection circuit for a gateless diode element as described in item 20 of the scope of the patent application, wherein the sizes of the first, the second, the third, and the fourth diodes are different, and The junction capacitances are all different. 28. — A gateless diode structure with silicon on the insulation layer, including: 30 paper sizes are applicable to China National Standard (CNS) A4 specifications (210X297 mm) 519749 7897twf.doc / 009 g D8 6. Apply for a patent A silicon substrate is on an insulating layer, including a substrate, an insulating layer, and a silicon layer stacked in sequence; (Please read the precautions on the back before filling this page). A pair of isolation structures are located in the silicon layer. There is a well region between the pair of isolation structures and the silicon layer; a first-type ion implantation region and a second-type ion implantation region are located in the well region and are adjacent to the isolation structures respectively. 29. As described in item 28 of the scope of the patent application, there is no silicon on the insulating layer. The gate diode element, wherein the first type ion implantation region and the second type ion implantation region are implanted with a P type, respectively. With N-ion. 30. The gateless diode element with silicon on the insulating layer as described in item 28 of the scope of the patent application, wherein the well region is implanted with a shallow concentration of P-type ions. 31. The gateless diode device with silicon on the insulation layer as described in item 28 of the scope of the patent application, wherein silicon in the well region is implanted with a shallow concentration of N-type ions. 32. The gateless diode device with silicon on the insulating layer as described in item 28 of the scope of the patent application, wherein the insulating layer is a silicon buried oxide layer. 33. The gateless diode device with silicon on the insulating layer as described in item 28 of the scope of the patent application, wherein the pair of isolation structures is a shallow trench isolation structure. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 34. A gateless diode structure with silicon on the insulation layer, including: a silicon substrate on the insulation layer, including a substrate, an insulation layer and a silicon layer. Sequential stacking; a pair of isolation structures located in the silicon layer such that there is a first well region and a second well region between the pair of isolation structures and the silicon layer, wherein the first well region and the second well region The well area is adjacent; a first type ion implantation area and a second type ion implantation area, respectively 519749 A8 B8 C8 D8 7897twf.doc / 009 6. Scope of patent application (please read the notes on the back before filling in (This page) in the first and the second puppet regions, and next to the isolation structures, respectively, so that the junction of the gateless diode device with silicon on the insulating layer is the first and the second The interface of the well area. 35. The obscure diode element with silicon on the insulating layer as described in item 34 of the scope of the patent application, wherein the first type ion implantation region and the second type ion implantation region are implanted with P-type and N-type ion. 36. The absence of silicon on the insulating layer according to item 35 of the scope of the patent application. Gate diode elements, wherein the first and the second well regions are implanted with shallow concentrations of P-type and N-type ions, respectively. . 37. The gateless diode element with silicon on the insulating layer as described in item 34 of the scope of the patent application, wherein the insulating layer is a silicon buried oxide layer. 38. The diodeless element with silicon on the insulating layer as described in item 34 of the scope of the patent application, wherein the pair of isolation structures is a shallow trench isolation structure. 39. A method of forming a gateless diode with silicon on an insulating layer, comprising: providing a silicon substrate on an insulating layer, including a substrate, an insulating layer, and a silicon layer sequentially stacked; the Central Standards Bureau of the Ministry of Economic Affairs The employee consumer cooperative prints a pair of isolation structures in the silicon layer, so that there is a stomach between the pair of isolation structures and the silicon layer; forming a first type ion implantation area and a second type ion implantation The access area is in the well area and is adjacent to each of the isolation structures. 40. The method for forming a gateless diode with sand on an insulating layer according to item 39 of the patent application park, wherein the first type ion implantation region and the second type ion implantation region are implanted separately P-type and N-type ions. 32 This paper size is applicable to Chinese National Standard (CNS) A4 specification (X 297 public director) 519749 A8 7897twf.doc / 009 g D8 VI. Application scope of patent 41. The insulation layer formed as described in item 39 of the scope of patent application has A gateless diode method of silicon, in which the well region is implanted with a shallow concentration of P-type ions. (Please read the precautions on the back before filling this page) 42. The method for forming a gateless diode with silicon on the insulating layer as described in item 39 of the scope of patent application, where silicon is implanted at a shallow concentration in the well area N-type ion. 43. — A substrate COMS gateless diode structure, comprising: a substrate having a well; a pair of isolation structures located in the substrate; a first type ion implantation region located in the well and located in the well Between the pair of isolation structures; and a pair of second-type ion implantation regions, located in the well and adjacent to the isolation structures, respectively, wherein the pair of second-type ion implantation regions are implanted with the well and the first-type ion, respectively Zone separation. 44. The substrate COMS gateless diode according to item 43 of the scope of the patent application, wherein the first-type ion implantation region and the second-type ion implantation region are implanted with P-type and N-type ions, respectively. Employees' Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs of the People's Republic of China 45. The substrate COMS non-gate diode as described in item 43 of the scope of the patent application, where the well area is implanted with shallow P-type ions. 46. A method for forming a substrate COMS gateless diode, comprising: providing a substrate, a well formed in the substrate; forming a pair of isolation structures on the substrate; forming a first-type ion implantation region and the well; , And is located between the pair of isolation structures; and 33 paper standards are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 519749 A8 7897twf.doc / 009? D8 6. The scope of patent application forms a pair of first A type-II ion implantation region is located in the well region and is adjacent to each of the isolation structures, and each of the second-type ion implantation region is separated from the first-type ion implantation region by the well. 47. The method for forming a matrix COMS gateless diode as described in item 46 of the scope of patent application, wherein the first type ion implantation region and the second type ion implantation region are implanted with P-type and N-type, respectively. ion. 48. The method for forming a matrix COMS gateless diode as described in item 46 of the scope of patent application, wherein the well region is implanted with a shallow concentration of P-type ions. (Please read the precautions on the back before filling out this page) Seal of the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 34 This paper size applies to China National Standard (CNS) A4 (210X297 mm)
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US10/060,743 US6933573B2 (en) 2002-01-23 2002-01-30 Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof
US10/702,372 US7141484B2 (en) 2002-01-23 2003-11-05 Electrostatic discharge protection circuit of non-gated diode and fabrication method thereof

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