JPH02308548A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH02308548A
JPH02308548A JP1128641A JP12864189A JPH02308548A JP H02308548 A JPH02308548 A JP H02308548A JP 1128641 A JP1128641 A JP 1128641A JP 12864189 A JP12864189 A JP 12864189A JP H02308548 A JPH02308548 A JP H02308548A
Authority
JP
Japan
Prior art keywords
region
regions
island
type
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1128641A
Other languages
Japanese (ja)
Other versions
JP2567472B2 (en
Inventor
Teruyoshi Mihara
輝儀 三原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP1128641A priority Critical patent/JP2567472B2/en
Priority to DE19904016695 priority patent/DE4016695C2/en
Publication of JPH02308548A publication Critical patent/JPH02308548A/en
Priority to US07/762,264 priority patent/US5212109A/en
Application granted granted Critical
Publication of JP2567472B2 publication Critical patent/JP2567472B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To facilitate formation of island regions for element isolation without using an epitaxial growth method by a method wherein the island regions are formed separately from a semiconductor substrate by etching and the island regions are surrounded by buried regions made of polycrystalline or amorphous semiconductor material. CONSTITUTION:Parts of the main surface side of an n-type Si substrate 1 are completely separated from the substrate 1 to form a plurality of island regions, i.e., a p-type island region 2 and n-type island regions 3 and 4. Polycrystalline Si or amorphous Si is buried between the substrate 1 and the respective regions 2-4 to form buried regions 5 and 6. The conductivity type of the regions 5 and 6 is p-type and the regions 5 and 6 are connected to a low potential point. The regions 3 and 4 are elastically isolated from the regions 5 and 6 by a reverse bias applied to a p-n junction. As the region 2 and the regions 5 and 6 have a substrate potential (low potential) in common, no isolation is provided between the region 2 and the region 5 and 6 by a p-n junction. With this constitution, the respective regions 2-4 can be formed without using an epitaxial growth method. Further, as the regions 5 and 6 are made of polycrystalline Si or amorphous Si, latchup can be avoided.

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） この発明は、新規なアイソレーション法を施した半導体
装置に関する。Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device using a novel isolation method.

（従来の技術） ＩＣでは集積された各素子が、その素子同士の間で相互
干渉をもたないように、電気的に分離される。(Prior Art) In an IC, each integrated element is electrically isolated so that there is no mutual interference between the elements.

第８図は、このようなアイソレーション法の施された第
１の従来例を示しており、自己分離法が用いられたＣＭ
Ｏ５の例を示している。同図中、１０１はｎ形基板であ
り、その主面には、ｐ＋ソース領域１０２、ｐ＋　ドレ
イン領域１０３、ゲート酸化膜１０４及びゲート電極１
０５等によりｐチャネルＭＯ３ＦＥＴ　（以下、ｐＭＯ
３のように云う）１０６が形成され、また、ｐウェル１
０７内にはｎ１ソース領域１０８、ｎ“　ドレイン領域
１０９、ゲート酸化１１１１１０及びゲート電極１１１
等によりｎＭＯ３１１２が形成され、この９ＭＯｓ１０
６及びｎＭＯｓ１１２によりＣＭＯ８が構成されている
。１１３はフィールド酸化膜、１１４は絶縁膜である。Figure 8 shows a first conventional example in which such an isolation method is applied, and shows a CM using the self-isolation method.
An example of O5 is shown. In the figure, 101 is an n-type substrate, and its main surface includes a p+ source region 102, a p+ drain region 103, a gate oxide film 104, and a gate electrode 1.
p-channel MO3FET (hereinafter referred to as pMO
3) 106 is formed, and p-well 1
07 includes an n1 source region 108, an n" drain region 109, a gate oxide 111110 and a gate electrode 111.
etc., nMO3112 is formed, and this 9MOs10
6 and nMOs 112 constitute CMO8. 113 is a field oxide film, and 114 is an insulating film.

そして、ｎ形基板１０１が電源ＶＤＤ　　（＞０）に接
続され、ｐウェル１０７が低電位点に接続されてｐＭＯ
５１０６及びｎＭＯ８１１２は、それぞれ電気的に独立
して動作するようになっている。Then, the n-type substrate 101 is connected to the power supply VDD (>0), the p-well 107 is connected to the low potential point, and the pMO
5106 and nMO8112 are designed to operate electrically independently.

しかしながら、このようなＣＭＯ３構造では、基板内に
ｐ”　　（１０２）−ｎ　（１０１）−Ｅ）（１０７）
−ｎ”　　（１０８）からなる寄生サイリスタが形成さ
れてラッチアップが起き易い。However, in such a CMO3 structure, p” (102)-n (101)-E)(107)
A parasitic thyristor consisting of -n'' (108) is formed and latch-up is likely to occur.

第９図は、第２の従来例を示しており、ｐｎ接合による
接合分離法が用いられたバイポーラＩＣの例を示してい
る。同図（Ａ）に示すように、まずｐ形基板２０１の上
にｎ形エピタキシャル層２０２が形成され、そのｎ形エ
ピタキシャル層２０２にｐ形基板２０１に達するように
ｐ＋分離拡散領域２０３が施されてｎ形の島領域２０４
が形成されている。同図（Ｂ）に示すように、ｎ形の島
領域２０４には、そのｎ形の島領域２０４をコレクタ領
域としてｐ形ベース領域及びｎ＋エミッタ領域によりｎ
ｐｎ　）ランジスタ２０５が形成され、また他の島領域
２０４には、そのｎ形の島領域２０４をベース領域とし
てｐ＋エミッタ領域及びｐ＋コレクタ領域によりｐｎｐ
）ランジスタ２０６が形成されている。２０７は、ｐ形
基板２０１に予め拡散形成されるｎ＋埋込層である。FIG. 9 shows a second conventional example, and shows an example of a bipolar IC in which a junction separation method using a pn junction is used. As shown in FIG. 2A, first, an n-type epitaxial layer 202 is formed on a p-type substrate 201, and a p+ isolation diffusion region 203 is formed on the n-type epitaxial layer 202 so as to reach the p-type substrate 201. n-shaped island area 204
is formed. As shown in the figure (B), the n-type island region 204 has an n-type base region and an n+ emitter region, with the n-type island region 204 as a collector region.
A pn transistor 205 is formed, and a pnp transistor 205 is formed in the other island region 204, with the n-type island region 204 as a base region and a p+ emitter region and a p+ collector region.
) A transistor 206 is formed. 207 is an n+ buried layer which is diffused and formed in the p-type substrate 201 in advance.

そして、ｐ形基板２０１が低電位点に接続されることに
より、各島領域２０４が電気的に分離され、ｎｐｎトラ
ンジスタ２０５及びｐｎｐ　ｔ−ランジスタ２０６が、
それぞれ独立して動作するようになっている。Then, by connecting the p-type substrate 201 to a low potential point, each island region 204 is electrically isolated, and the npn transistor 205 and pnp t-transistor 206 are
Each one operates independently.

しかしながら、このような接合分離法では、エピタキシ
ャル成長法を必須とするため、プロセスコストが高くな
ってチップコストの上昇を招いていた。However, since such a junction isolation method requires an epitaxial growth method, the process cost becomes high, leading to an increase in chip cost.

第１Ｏ図は、第３の従来例を示しており、絶縁膜による
誘電体分離法が用いられたものを示している。同図中、
３０１は多結晶Ｓｉ等からなる支持基板であり、支持基
板３０１上には、５ｉ０２膜からなる絶縁膜３０２によ
り、それぞれ誘電体分離されたｎ形の島領域３０３が形
成されている。FIG. 1O shows a third conventional example, in which a dielectric isolation method using an insulating film is used. In the same figure,
Reference numeral 301 denotes a supporting substrate made of polycrystalline Si or the like, and on the supporting substrate 301, n-type island regions 303 are formed which are dielectrically isolated from each other by an insulating film 302 made of a 5i02 film.

ｎ形の島領域３０３には、そのｎ形の島領域３０３をコ
レクタ領域として、ｐ形ベース領域及びｎ＋エミッタ領
域等によりｎｐｎ）ランジスタ３０４が形成されている
。An npn transistor 304 is formed in the n-type island region 303 by using the n-type island region 303 as a collector region, a p-type base region, an n+ emitter region, and the like.

しかしながら、このような誘電体分離法では、各島領域
３０３が絶縁膜３０２を用いて分離されているので放熱
性が悪く、サージ電圧や静電気による破壊耐量が低い。However, in such a dielectric isolation method, since each island region 303 is separated using the insulating film 302, heat dissipation is poor and breakdown resistance due to surge voltage and static electricity is low.

（発明が解決しようとする課題） 自己分離法が用いられた第１の従来例では、基板内にｐ
”−ｎ−ｐ−ｎ“の寄生サイリスタが形成されてラッチ
アップが起き易いという問題があった。(Problems to be Solved by the Invention) In the first conventional example in which the self-separation method was used, p
There is a problem in that a "-n-p-n" parasitic thyristor is formed and latch-up is likely to occur.

接合分離法が用いられた第２の従来例では、エピタキシ
ャル成長法を必須とするため、プロセスコストが高くな
り、ひいてはチップコストが高くなるという問題があっ
た。In the second conventional example in which the junction separation method is used, since the epitaxial growth method is essential, there is a problem that the process cost becomes high, and the chip cost becomes high.

また、誘電体分離法が用いられた第３の従来例では、各
島領域が絶縁膜を用いて分離されているため、放熱性が
悪く、サージ電圧や静電気による破壊耐量が低いという
問題があった。In addition, in the third conventional example in which the dielectric separation method is used, each island region is separated using an insulating film, which causes problems such as poor heat dissipation and low breakdown resistance due to surge voltage and static electricity. Ta.

そこで、この発明は、エピタキシャル成長法を用いずに
素子分離用の島領域を形成することができてチップコス
トを低減することができ、また島領域内の素子と半導体
基体上の素子或いは他の島領域内の素子との間のラッチ
アップ等の寄生動作を抑えることダでき、さらには放熱
性がよく、サージ電圧や静電気による破壊耐量を高める
ことのできる半導体装置を提供することを目的とする。Therefore, the present invention makes it possible to form an island region for element isolation without using epitaxial growth, thereby reducing chip cost, and to connect the elements in the island region to the elements on the semiconductor substrate or other islands. It is an object of the present invention to provide a semiconductor device that can suppress parasitic operations such as latch-up with elements within a region, has good heat dissipation, and can increase breakdown resistance due to surge voltage and static electricity.

［発明の構成］ （課題を解決するための手段） 上記課題を解決するために、第１の発明は、半導体基体
の主面にエツチングにより当該半導体基体から切離して
形成された島領域と、該島領域と前記半導体基体領域と
の間に埋込まれた多結晶又は非晶質の半導体からなる埋
込領域とを有することを要旨とする。また、前記埋込領
域は、前記島領域又は半導体基体とは逆の導電形である
ことも第１の発明の要旨として包含する。[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, a first invention provides an island region formed on the main surface of a semiconductor substrate by being separated from the semiconductor substrate by etching; The gist thereof is to have a buried region made of a polycrystalline or amorphous semiconductor buried between the island region and the semiconductor base region. The gist of the first invention also includes that the buried region has a conductivity type opposite to that of the island region or the semiconductor substrate.

さらに、第２の発明は、第１導電形の半導体基体の主面
に形成された第２導電チャネルのＭＩＳＦＥＴと、前記
半導体基体の一部に形成された第２導電形ウェルの表面
部に形成された第１導電チャネルのＭＩＳＦＥＴとから
なる相補形ＭＩＳＦＥＴにおいて、前記第２導電チャネ
ルのＭＩ　５ＦＥＴの形成部又は前記第２導電形ウェル
の少なくとも一方は前記半導体基体からエツチングによ
り切離して島領域とし、該島領域と前記半導体基体領域
との間には多結晶又は非晶質の半導体からなる埋込領域
を形成してなることを要旨とする。Furthermore, a second invention provides a MISFET having a second conductive channel formed on the main surface of the semiconductor substrate of the first conductivity type, and a MISFET formed on the surface portion of the well of the second conductivity type formed in a part of the semiconductor substrate. In a complementary MISFET comprising a first conductive channel MISFET, at least one of the second conductive channel MISFET formation portion or the second conductive type well is separated from the semiconductor substrate by etching to form an island region; The gist is that a buried region made of polycrystalline or amorphous semiconductor is formed between the island region and the semiconductor base region.

（作用） 第１の発明では、エピタキシャル成長法を用いずに接合
分離された島領域を形成することが可能となる。また、
埋込領域を形成している多結晶又は非晶質の半導体は多
量の再結合中心を含んでいるため、島領域内の素子と半
導体基体上の素子等との間の寄生動作が抑えられる。さ
らに多結晶又は非晶質の半導体は放熱性がよく、サージ
電圧や静電気による破壊耐量の向上が実現される。(Function) In the first invention, it is possible to form a junction-separated island region without using an epitaxial growth method. Also,
Since the polycrystalline or amorphous semiconductor forming the buried region contains a large number of recombination centers, parasitic operation between the elements in the island region and the elements on the semiconductor substrate is suppressed. Furthermore, polycrystalline or amorphous semiconductors have good heat dissipation properties, and can improve breakdown resistance due to surge voltage and static electricity.

また、第２の発明では、多量の再結合中心を含む多結晶
又は非晶質の半導体からなる埋込領域により、ＣＭＯ３
特有の寄生サイリスタによるラッチアップの発生が抑え
られる。In addition, in the second invention, CMO3
The occurrence of latch-up due to the peculiar parasitic thyristor can be suppressed.

（実施例） 以下、この発明の実施例を図面に基づいて説明する。(Example) Embodiments of the present invention will be described below based on the drawings.

第１図ないし第５図は、この発明の第１実施例を示す図
である。この実施例は、１チツプ上にＣＭＯ５とバイポ
ーラトランジスタとが集積されたＩＣを示している。1 to 5 are diagrams showing a first embodiment of the present invention. This embodiment shows an IC in which a CMO5 and a bipolar transistor are integrated on one chip.

まず、第１図ないし第４図を用いて半導体装置の構成を
説明すると、これらの図中、ｌは半導体基体としてのｎ
形（又はｐ形であってもよい）のＳｉ基板であり、その
主面側の一部が当該Ｓｉ基板１から完全に切離されて複
数個の島領域２．３．４が形成されている。島領域３．
４は、ｎ形のＳｉ基板１からそのまま切出されているの
で、ｎ形となっているが、他の島領域２は、予めｐ形の
拡散が施されてから切出されているので、ｐ形となって
いる。そしてＳｉ基板１と各島領域２．３．４との間に
は多結晶Ｓｔ又は非晶質Ｓｔが埋込まれて埋込領域５．
６が形成されている。埋込領域５．６は、多結晶Ｓｔ等
がｐ形にドープされてｐ形とな７ており、低電位点に接
続されている。First, the structure of the semiconductor device will be explained using FIGS. 1 to 4. In these figures, l represents n as a semiconductor substrate.
(or may be p-type), and a part of its main surface side is completely separated from the Si substrate 1 to form a plurality of island regions 2.3.4. There is. Island area 3.
4 is cut out as is from the n-type Si substrate 1, so it is n-type, but the other island regions 2 are cut out after being subjected to p-type diffusion in advance. It is p-type. Polycrystalline St or amorphous St is buried between the Si substrate 1 and each island region 2.3.4 in the buried region 5.
6 is formed. The buried region 5.6 is doped with polycrystalline St or the like to be p-type 7, and is connected to a low potential point.

ｐ形の島領域２には、ｎ＋ソース領域７、ｎ　４′ドレ
イン領域８及び多結晶Ｓｉのゲート電極９等によりｎＭ
Ｏ３１１が形成され、ｎ形の島領域３には、ｐ＋ソース
領域１２、ｐ＋　ドレイン領域１３及び多結晶ＳＬのゲ
ート電極１４等により９ＭＯ５１５が形成されている。In the p-type island region 2, an nM
In the n-type island region 3, a 9MO515 is formed by a p+ source region 12, a p+ drain region 13, a gate electrode 14 of polycrystalline SL, and the like.

このｎＭＯ３１１と９ＭＯ８１５とでＣＭＯ３が構成さ
れている。This nMO311 and 9MO815 constitute CMO3.

一方、ｎ形の島領域４には、そのｎ形の島領域４をコレ
クタ領域としてｐ形ベース領域１６及びｎ＋エミッタ領
域１７によりｎｐｎ）ランジスタ１８が形成されている
。On the other hand, in the n-type island region 4, an npn) transistor 18 is formed by a p-type base region 16 and an n+ emitter region 17, with the n-type island region 4 as a collector region.

ｎ形の島領域３．４とｐ形の埋込領域５．６との間は、
ｐｎ接合が逆バイアスされることにより電気的に分離さ
れている。ｐ形の島領域２と埋込領域５．６との間は、
基板電位（低電位）を共有しているので、あえてｐｎ接
合による分離はされてないが、島領域２を予めｐ形に拡
散するときの拡散窓の大きさを小さくして島嶺域２にお
ける埋込領域５．６との境界部にｎ形層が残るようにし
、そのｐｎ接合により電・気的な分離を施すことも可能
である。Between the n-type island region 3.4 and the p-type buried region 5.6,
The pn junction is electrically isolated by being reverse biased. Between the p-type island region 2 and the buried region 5.6,
Since they share the substrate potential (low potential), they are not intentionally separated by a p-n junction, but the size of the diffusion window when diffusing the island region 2 into p-type is made smaller in advance, so that the island region 2 It is also possible to leave an n-type layer at the boundary with the buried region 5.6 and provide electrical isolation through the pn junction.

この実施例の半導体装置は上述のように構成されている
ので、エピタキシャル成長法を用いずに各島領域２．３
．４を形成することが可能となる。Since the semiconductor device of this embodiment is constructed as described above, each island region 2.3 is grown without using epitaxial growth.
．． 4 can be formed.

また、埋込領域５．６を形成している多結晶Ｓｔ又は非
晶質Ｓｔは、単結晶Ｓｉと比べると多量の再結合中心を
含んでいるため、ＣＭＯ３の寄生サイリスクのゲイン和
が αＮＰＮ＋αＰＮＰ＜１ となり、ラッチアップの発生を完全に抑えることが可能
となる。さらに、多結晶Ｓｉ又は非晶質Ｓｉは熱伝導性
が良いので端子部等から過渡的なサージ電圧や静電気が
デバイスに印加されても、これに対する破壊耐量を高め
ることが可能となる。Furthermore, since the polycrystalline St or amorphous St forming the buried region 5.6 contains a large number of recombination centers compared to single crystal Si, the gain sum of parasitic silicon risks of CMO3 is αNPN+αPNP< 1, making it possible to completely suppress the occurrence of latch-up. Furthermore, since polycrystalline Si or amorphous Si has good thermal conductivity, even if a transient surge voltage or static electricity is applied to the device from a terminal portion or the like, it is possible to increase the breakdown resistance against this.

次に、第５図を用いて、この実施例に係る半導体装置の
製造方法の一例を説明する。なお、以下の説明において
、（ａ）〜（ｅ）の各項目記号は、第５図の（ａ）〜（
ｅ）のそれぞれに対応する。また、同図（ｂ）及び同図
（ｄ）には、それぞれ縮小平面図も併せ示しである。Next, an example of a method for manufacturing a semiconductor device according to this embodiment will be explained using FIG. In the following explanation, each item symbol of (a) to (e) is replaced by (a) to (e) in Fig. 5.
Corresponds to each of e). Further, FIGS. 3(b) and 4(d) also each show a reduced plan view.

（ａ）　　（１，ＯＯ）面のｎ形Ｓｔ基板１を使用し、
ｐ形の島領域を作る所に予めｐ形拡散を施してから、島
予定領域をＳ　ｉ０２−Ｓ　ｉ３　Ｎ４−Ｓ　ｉ。(a) Using an n-type St substrate 1 with a (1,OO) plane,
After performing p-type diffusion in advance where a p-type island region is to be created, the planned island region is Si02-S i3 N4-S i.

２の多層絶縁膜１９でマスクする。The multilayer insulating film 19 of No. 2 is used as a mask.

（ｂ）　　反応性イオンエツチングにより、垂直の溝２
１を掘る。(b) Vertical groove 2 created by reactive ion etching.
Dig 1.

（Ｃ）　　溝２１の側壁をヒドラジンやエチレンジアミ
ン等のアルカリ系異方性エツチング液を用いてエツチン
グし、各島領域となる部分を切出す。アルカリ系異方性
エツチング液でＳｉをエツチングすると（１１１）面で
著しくエッチレートか遅くなるので、（１１１）面が露
出したところでエツチングが止り、各島領域が適切に切
出される。(C) The side walls of the groove 21 are etched using an alkaline anisotropic etching solution such as hydrazine or ethylenediamine to cut out portions that will become each island region. When Si is etched with an alkaline anisotropic etching solution, the etching rate is significantly slower on the (111) plane, so the etching stops when the (111) plane is exposed, and each island region is properly cut out.

（ｄ）　　ｐ形のドープド多結晶Ｓｉで、エツチングに
より拡大された溝の部分を埋める。次いて前記の溝２１
と直角方向（Ｘ方向）に溝２２を掘り、これを再びｐ形
のドープド多結晶Ｓｔで埋込み、各島領域２．３．４を
Ｓｉ基板１から完全に分離し、またその分離した間隙部
に埋込領域５．６を形成する。(d) Fill the groove enlarged by etching with p-type doped polycrystalline Si. Next, the groove 21
A trench 22 is dug in the direction perpendicular to the direction (X direction), and this is filled again with p-type doped polycrystalline St, completely separating each island region 2.3.4 from the Si substrate 1, and also filling the separated gap. A buried region 5.6 is formed in the area.

（ｅ）　　埋込領域５．６部分の多結晶Ｓｉの表面を７
０００Ａ程度に厚く酸化して基板を完成する。(e) The surface of the polycrystalline Si in the buried region 5.6 is
The substrate is completed by oxidizing it to a thickness of about 000A.

この後、各島領域２．３．４に公知のプロセスにより、
ｎＭＯ３，ｐＭＯ３及びバイポーラトランジスタ等の所
望のデバイスを形成する。After this, by a process known to each island region 2.3.4,
Form desired devices such as nMO3, pMO3 and bipolar transistors.

このように、この実施例の半導体装置は、エピタキシャ
ル成長法を用いずに、ｐ形、ｎ形の各島領域２．３．４
が形成される。In this way, the semiconductor device of this embodiment can be constructed by forming the p-type and n-type island regions 2.3.4 without using the epitaxial growth method.
is formed.

次いで、第６図には、この発明の第２実施例を示す。同
図（ｂ）は同図（ａ）の１−１線断面図、同図（Ｃ）は
同図（ａ）の■−■線断面図である。Next, FIG. 6 shows a second embodiment of the present invention. 3B is a cross-sectional view taken along the line 1--1 in FIG. 3A, and FIG.

なお、第６図及び後述の第７図において、前記第１図な
いし第４図における部材及び部位等と同一ないし均等の
ものは、前記と同一符号を以って示し重複した説明を省
略する。In FIG. 6 and FIG. 7, which will be described later, the same or equivalent members and parts in FIGS. 1 to 4 are designated by the same reference numerals, and redundant explanation will be omitted.

この実施例では、各島領域２０が５角柱状に形成されて
いる。島領域２０をこのような形状に形成すると、深さ
方向の有効面積が増して、厚さの必要なデバイスの形成
に極めて好都合となる。勿論、前述のＣＭＯＳ及びバイ
ポーラトランジスタも、この島領域２０内に形成するこ
とができる。In this embodiment, each island region 20 is formed into a pentagonal column shape. When the island region 20 is formed in such a shape, the effective area in the depth direction increases, which is extremely convenient for forming a device that requires a large thickness. Of course, the aforementioned CMOS and bipolar transistors can also be formed within this island region 20.

製造法としては、前記第５図（ｂ）に示した溝の形成途
中で一旦溝壁面にＳｉ３Ｎ４等の耐エツチング膜を被着
してからさらに溝を所要深さまで掘下げる。次いで、溝
底部の露出した側壁をアルカリ系異方性エツチング液で
エツチングすることにより、５角柱状の各島領域２０が
形成される。As for the manufacturing method, during the formation of the groove shown in FIG. 5(b), an etching-resistant film such as Si3N4 is once applied to the groove wall surface, and then the groove is further dug to a required depth. Next, by etching the exposed side walls of the groove bottom with an alkaline anisotropic etching solution, each pentagonal columnar island region 20 is formed.

第７図には、この発明の第３実施例を示す。同図（ｂ）
は同図（ａ）の１−１線断面図、同図（Ｃ）は同図（ａ
）の■−■線断面図である。FIG. 7 shows a third embodiment of the invention. Same figure (b)
is a cross-sectional view taken along the line 1-1 of the same figure (a), and the same figure (C) is a cross-sectional view taken along the line 1-1 of the same figure (a).
) is a sectional view taken along the line ■-■.

この実施例は、バルクのＣＭＯＳ　（相補形Ｍ　ｌ５Ｆ
ＥＴ）に適用されている。This example is a bulk CMOS (complementary M I5F
ET).

そして、ｐチャネルのＭＩ　５ＦＥＴとしてのｐＭＯ３
１５の形成部がエツチングにより島領域２４として半導
体基板１から切出され、その島領域２４と半導体基板１
の領域との間にｎ形の埋込領域５．６が形成されている
。一方、ｎチャネルのＭＩＳＦＥＴとしてのｎＭＯ３１
１はｐウェル２５の表面部に形成されている。and pMO3 as p-channel MI 5FET
15 is cut out from the semiconductor substrate 1 as an island region 24 by etching, and the island region 24 and the semiconductor substrate 1 are
An n-type buried region 5.6 is formed between the region. On the other hand, nMO31 as an n-channel MISFET
1 is formed on the surface of the p-well 25.

この実施例のＣＭＯＳは上述のように構成されているの
で、多結晶Ｓｔ又は非晶質Ｓｔからなる埋込領域５．６
により、ｐＭＯｓ１５とｎ　Ｍ　ＯＳ１１との間にでき
るｐ＋　（１２）−ｎ　（２４）−ｎ（５）、（６）−
ｎ　（１）　　ｐ　（２５）−ｎ“（７）の経路からな
る寄生サイリスクのゲインが落されてラッチアップの発
生が防止される。Since the CMOS of this example is constructed as described above, the buried regions 5.6 made of polycrystalline St or amorphous St
Therefore, p+ (12)-n (24)-n(5), (6)- is created between pMOs15 and nMOS11.
The gain of the parasitic risk consisting of the path n (1) p (25) - n'' (7) is reduced to prevent latch-up from occurring.

上述のように、この実施例は、元来、自己分離形のＣＭ
ＯＳに適用したので、埋込領域５．６と島領域２４とは
同一導電形のｎ形でよい。また、ｐＭＯｓ１５の形成部
を島領域とすることに代えて、ｐウェル２５の部分を島
領域とし、その島領域と半導体基板１の領域との間にｐ
形の埋込領域を形成しても、上記と同様にラッチアップ
の発生を防止することができる。勿論、ｐＭＯ８１５の
形成部及びｐウェル２５の部分の両者を島領域とし、そ
の両島領域の周囲に埋込領域を形成してもよく、このと
きはラッチアップの発生を一層確実に防止することがで
きる。As mentioned above, this embodiment is originally a self-separated CM
Since this embodiment is applied to an OS, the buried region 5.6 and the island region 24 may be of the same conductivity type, n-type. Also, instead of forming the pMOs 15 as an island region, the p well 25 may be formed into an island region, and a p-well 25 may be formed between the island region and the semiconductor substrate 1 region.
Even if a shaped embedded region is formed, latch-up can be prevented from occurring in the same manner as described above. Of course, both the pMO 815 formation part and the p well 25 part may be made into island regions, and a buried region may be formed around both island regions.In this case, it is possible to more reliably prevent the occurrence of latch-up. I can do it.

なお、上述の各実施例において、Ｓｉ基板からの島領域
の切出しには異方性エツチングを用いたが、これに代え
て等方性エツチングを用いることもできる。In each of the above embodiments, anisotropic etching was used to cut out the island regions from the Si substrate, but isotropic etching may be used instead.

［発明の効果］ 以上説明したように、第１の発明によれば、半導体基体
からエツチングにより切離して形成した島領域を多結晶
又は非晶質の半導体からなる埋込領域で取囲む構成とし
たため、エピタキシャル成長法を用いずに素子分離用の
島領域を形成することがてきる。また埋込領域を形成し
ている多結晶又は非晶質の半導体は多量の再結合中心を
含んでいるので島領域内の素子と半導体基体上の素子等
との間の寄生動作を抑えることができる。さらに多結晶
又は非晶質の半導体は放熱性がよいのでサージ電圧や静
電気による破壊耐量を高めることができる。[Effects of the Invention] As explained above, according to the first invention, the island region formed by being separated from the semiconductor substrate by etching is surrounded by the buried region made of polycrystalline or amorphous semiconductor. , island regions for element isolation can be formed without using epitaxial growth. In addition, since the polycrystalline or amorphous semiconductor forming the buried region contains a large number of recombination centers, it is possible to suppress parasitic operation between the elements in the island region and the elements on the semiconductor substrate. can. Furthermore, since polycrystalline or amorphous semiconductors have good heat dissipation properties, they can enhance breakdown resistance due to surge voltage and static electricity.

また、第２の発明によれば、相補形ＭＩＳＦＥＴにおい
て、第２導電チャネルのＭＩＳＦＥＴの形成部又は第１
導電チャネルのＭＩＳＦＥＴの形成された第２導電形ウ
ェルの少なくとも一方を半導体基体からエツチングによ
り切離して島領域とし、その島領域を多結晶又は非晶質
の半導体からなる埋込領域で取囲む構成としたため、相
補形ＭＩＳＦＥＴに特有の寄生サイリスクによるラッチ
アップの発生を抑えることができる。Further, according to the second invention, in the complementary MISFET, the formation part of the MISFET of the second conductive channel or the first
At least one of the second conductivity type wells in which the conductive channel MISFET is formed is separated from the semiconductor substrate by etching to form an island region, and the island region is surrounded by a buried region made of a polycrystalline or amorphous semiconductor. Therefore, it is possible to suppress the occurrence of latch-up due to parasitic silage, which is specific to complementary MISFETs.

【図面の簡単な説明】[Brief explanation of drawings]

第１図ないし第５図はこの発明に係る半導体装置の第１
実施例を示すもので、第１図は平面図、第２図は第１図
のＩ−１線断面図、第３図は第１図の■−■線断面図、
第４図は第１図の■−■線断面図、第５図は製造方法の
一例を示す工程図、第６図はこの発明の第２実施例を示
す図、第７図はこの発明の第３実施例を示す図、第８図
は半導体装置の第１の従来例を示す縦断面図、第９図は
第２の従来例を示す縦断面図、第１０図は第３の従来例
を示す縦断面図である。 １：Ｓｉ基板（半導体基体）、 ２．３．４．２４：島領域、 ５．６：埋込領域、 １１　：　ｎＭＯ５（ＭＩＳＦＥＴ）、１５　：　ｐＭ
Ｏ３（ＭＩＳＦＥＴ）、２５：ｐウェル。 代理人　　弁理士　　三　好　　秀　和第１図 第２図 第３図 第４図 第５図（ａ） 第５図（ｂ） Ｍ５図（Ｃ） 第５図（ｄ　） 第５図（ｅ） 第７図（ａ） 第７図（ｂ） 第７図（Ｃ） 第８図 第９図（ａ） 第９図（ｂ）1 to 5 show a first diagram of a semiconductor device according to the present invention.
Fig. 1 is a plan view, Fig. 2 is a sectional view taken along line I-1 in Fig. 1, and Fig. 3 is a sectional view taken along line ■-■ in Fig. 1.
4 is a sectional view taken along the line ■-■ in FIG. 1, FIG. 5 is a process diagram showing an example of the manufacturing method, FIG. 6 is a diagram showing a second embodiment of the present invention, and FIG. 8 is a longitudinal sectional view showing the first conventional example of the semiconductor device, FIG. 9 is a longitudinal sectional view showing the second conventional example, and FIG. 10 is the third conventional example. FIG. 1: Si substrate (semiconductor base), 2.3.4.24: Island region, 5.6: Buried region, 11: nMO5 (MISFET), 15: pM
O3 (MISFET), 25:p well. Agent Hidekazu Miyoshi, Patent Attorney Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 (a) Figure 5 (b) Figure M5 (C) Figure 5 (d) Figure 5 (e) Figure 7 (a) Figure 7 (b) Figure 7 (C) Figure 8 Figure 9 (a) Figure 9 (b)

Claims (3)

【特許請求の範囲】[Claims] （１）半導体基体の主面にエッチングにより当該半導体
基体から切離して形成された島領域と該島領域と前記半
導体基体領域との間に埋込まれた多結晶又は非晶質の半
導体からなる埋込領域とを有することを特徴とする半導
体装置。(1) An island region formed on the principal surface of a semiconductor substrate by being separated from the semiconductor substrate by etching, and a buried region made of polycrystalline or amorphous semiconductor buried between the island region and the semiconductor substrate region. What is claimed is: 1. A semiconductor device comprising: a semiconductor device; （２）前記埋込領域は、前記島領域又は半導体基体とは
逆の導電形であることを特徴とする請求項１記載の半導
体装置。(2) The semiconductor device according to claim 1, wherein the buried region has a conductivity type opposite to that of the island region or the semiconductor substrate. （３）第１導電形の半導体基体の主面に形成された第２
導電チャネルのＭＩＳＦＥＴと、前記半導体基体の一部
に形成された第２導電形ウェルの表面部に形成された第
１導電チャネルのＭＩＳＦＥＴとからなる相補形ＭＩＳ
ＦＥＴにおいて、 前記第２導電チャネルのＭＩＳＦＥＴの形 成部又は前記第２導電形ウェルの少なくとも一方は前記
半導体基体からエッチングにより切離して島領域とし、
該島領域と前記半導体基体領域との間には多結晶又は非
晶質の半導体からなる埋込領域を形成してなることを特
徴とする半導体装置。(3) A second conductivity type formed on the main surface of the semiconductor substrate of the first conductivity type.
A complementary MIS comprising a conductive channel MISFET and a first conductive channel MISFET formed on the surface of a second conductivity type well formed in a part of the semiconductor substrate.
In the FET, at least one of the MISFET formation portion of the second conductive channel or the second conductivity type well is separated from the semiconductor substrate by etching to form an island region;
A semiconductor device characterized in that a buried region made of a polycrystalline or amorphous semiconductor is formed between the island region and the semiconductor base region.
JP1128641A 1989-05-24 1989-05-24 Semiconductor device Expired - Lifetime JP2567472B2 (en)

Priority Applications (3)

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JP1128641A JP2567472B2 (en) 1989-05-24 1989-05-24 Semiconductor device
DE19904016695 DE4016695C2 (en) 1989-05-24 1990-05-23 Method of forming buried areas in a semiconductor substrate
US07/762,264 US5212109A (en) 1989-05-24 1991-09-20 Method for forming PN junction isolation regions by forming buried regions of doped polycrystalline or amorphous semiconductor

Applications Claiming Priority (1)

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JP1128641A JP2567472B2 (en) 1989-05-24 1989-05-24 Semiconductor device

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JPH02308548A true JPH02308548A (en) 1990-12-21
JP2567472B2 JP2567472B2 (en) 1996-12-25

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US5405454A (en) * 1992-03-19 1995-04-11 Matsushita Electric Industrial Co., Ltd. Electrically insulated silicon structure and producing method therefor

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