TW517315B

TW517315B - Ag-pre-plated lead frame for semiconductor package

Info

Publication number: TW517315B
Application number: TW89126499A
Authority: TW
Inventors: Se-Chul Park; Nam-Seog Kim
Original assignee: Samsung Techwin Co Ltd; Samsung Electronics Co Ltd
Priority date: 2000-12-12
Filing date: 2000-12-12
Publication date: 2003-01-11

Abstract

A lead frame for a semiconductor package including a base metal layer made of copper (Cu), Cu alloy or iron-nickel (Fe-Ni) alloy, anderly-ing plating layer formed on at least one surface of the base metal layer and made of Ni or Ni alloy, an intermediate plating layer formed on the underlying plating layer to a thickness of 0.00025 to 0.1 μm (0.1 to 4 microinches) and made of palladium (Pd) or Pd alloy, and an outer plating layer formed in the intermediate plating layer to a thickness of 0.05 to 0.75 μm (2 to 30 microinches) and made of silver (Ag) or Ag alloy. Since an Ag plated layer is formed as the outer plating layer, excellent oxidation resistance and corrosion resistance can be exhibited even under a high-temperature thermal condition, thereby improving wire bondability, solderability and good adhesion with epoxy for use in the semiconductor package, and preventing heel crack at a wire bonding portion. In particular, since thin layers of the Pd plated layer and Ag plated layer are used, Ag migration can be prevented. Also, the amount of a noble metal such as Pd or Ag can be greatly reduced, thereby attaining thin-film, light-weigh semiconductor packages.

Description

517315 五、發明說明（1) 【發明有關之領域】本發明關於一種半導體封裝用之導線架，主要係於：，在高溫環境下，即使電鍍層很薄，該導線架亦可維持一極佳的封裝品質、可避免因為銀電鍍層的厚度降低，致使銀 ’ (A g )的游移（m i g r a t i ο η )，以及可降低生產成本者。【先前技術之敘述】517315 V. Description of the invention (1) [Fields related to the invention] The present invention relates to a lead frame for semiconductor packaging, which is mainly based on: In a high temperature environment, the lead frame can maintain an excellent performance even if the plating layer is thin. The package quality can avoid the migration of silver (A g) (migrati ο η) due to the decrease in the thickness of the silver plating layer, and can reduce the production cost. [Narration of prior art]

按，半導體導線架基本上包括有一組裝半導體記憶晶片的模塾器（die pad unit), 並將之予以固定，一藉由導線結合（w i r e b ο n d i n g )連接至晶片之内部導線，以及一連接至外部電路的外部導線。該導線結合晶片和導線結合内部導線是藉由模壓填料來完成半導體封裝。具有上述結 B 構之半導體導線架通常是藉由沖壓或浸蝕的方法來製成的〇在該半導體封裝用之導線架中，為了保持在内部導線内的良好導線結合性以及在模墊片和晶片之間良好的黏著性，在模墊片上和導線架的内部導線尖端上電鍍一層例如銀的金屬材質。另外，在樹脂鈍化膜成形（resin passiv -ation film molding)後，為了改善在組裝一連接至外部電路的外部導線時之可焊性，焊料電鍍，也就是說，錫-鉛（S η - P b )電鍍，是在該外部導線的預定處進行的。然而，由於電鍍在樹脂鈍化膜成形後通常是在潮濕的過程中進 _ 行，錫-鉛電鍍溶液會滲透入環氧樹脂和鉛之間的缺口，因而降低了成品的可靠度。為了解決該問題，於是有了預電鍍方法（預電鍍架）問世。在半導體封裝之前的預電鍍架The semiconductor lead frame basically includes a die pad unit for assembling a semiconductor memory chip, and fixes it, an internal wire connected to the chip by wire bonding, and a External wires for external circuits. The wire-bond chip and the wire-bond internal wire are formed by molding the filler to complete the semiconductor package. The semiconductor lead frame having the above-mentioned structure B structure is usually made by stamping or etching. In the lead frame for the semiconductor package, in order to maintain good wire bonding in the inner conductors, and in the die pad and With good adhesion between the wafers, a layer of metal material, such as silver, is plated on the die pads and the inner lead tips of the lead frame. In addition, after resin passiv-ation film molding, in order to improve solderability when assembling an external lead connected to an external circuit, solder plating, that is, tin-lead (S η-P b) Electroplating is performed at a predetermined position of the external lead. However, since electroplating is usually performed in a wet process after the resin passivation film is formed, the tin-lead plating solution will penetrate into the gap between the epoxy resin and the lead, thereby reducing the reliability of the finished product. To solve this problem, a pre-plating method (pre-plating frame) was introduced. Pre-plated rack before semiconductor packaging

第6頁 517315 五、發明說明（2) 中將一種濕性的金屬裝的過程中而簡4匕了半污染亦得以試想：線結合、環高的溫度下架時，外部所製造的導導線結合時性、與環氧溶度。此外外部電鍍層置長期的可因為外層電現象。滿足 I巴、金、銀性多為人們金和1〜5 /z m 進行高度整現象的纪，昧0 然而，具有良好的導線結合性、晶片黏接性和焊料吸電鍍在一金屬材質上，因此得以在半導體後封省略一鉛電鍍的步驟。由於預電鍍鉛架的使用導體後封裝過程，而且，由於鉛電鍍所造成的降低，因此，預電鍍架近來頗受重視。半導體組裝過程包括了半導體晶片的黏接、導氧樹脂模塑和焊接等等，通常是在2 0 0 °C或更進行，因此，在藉由預電鍍方法所製造的導線電鍍層是一極為重要的因素。藉由預電鍍方法線架之外部電鍍層的條件包括高溫抗氧化性、與結合線的良好結合性、與矽晶片的良好黏著樹脂的良好模塑性、以及在焊接時與鉛的良好，為了避免在導線結合時結合毛細管的磨損，應由具有適當展延性的金屬來製成。半導體裝靠度必需得以確保，在長期濕熱狀態下，不會鍍金屬游移至與其相接觸的物質上而產生短路上述條件的外部電錢層之材質為貴金屬，例如，特別是金和銀，由於其良好的導電性和展延所使用。在該例中，最好是電鑛0. 5〜2 // m厚的厚的銀。然而，半導體封裝早已進行微小化和合，因此，具有較稠密結構，且不會造成游移已漸獲得比會造成游移現象之金或銀較高的青在電鍍貴金屬時，為了維持電鍍層的平整性以Page 6 517315 V. Description of the invention (2) In the process of packing a wet metal, it is simple and contaminated. It can also be conceived: When the wire is combined and the ring is removed from the rack at a high temperature, the externally manufactured guide wire Combining time and solubility with epoxy. In addition, the external plating layer can be placed for a long time due to the outer layer electrical phenomenon. Satisfying the I, B, and Ag properties is mostly the age of gold and 1 ~ 5 / zm. However, it has good wire bonding, chip adhesion and solder plating on a metal material. Therefore, a lead plating step can be omitted after the semiconductor package. Due to the use of pre-plated leadframes for post-conductor packaging processes, and due to the reduction caused by lead plating, pre-plated frames have received much attention recently. The semiconductor assembly process includes the bonding of semiconductor wafers, oxygen-conductive resin molding, and soldering. Usually, it is performed at 200 ° C or higher. Therefore, the wire plating layer produced by the pre-plating method is extremely Important factor. The conditions of the external plating layer of the wire frame by the pre-plating method include high temperature oxidation resistance, good bonding with bonding wires, good moldability with a good adhesion resin to a silicon wafer, and good lead with soldering in order to To avoid abrasion of the bonded capillary during wire bonding, it should be made of a metal with appropriate ductility. The reliability of the semiconductor must be ensured. Under long-term humid and hot conditions, the material of the external electric money layer that does not migrate to the material in contact with it and cause a short circuit is the noble metal, such as gold and silver in particular. Its good electrical conductivity and extension are used. In this example, it is preferable that the power ore is 0.5 to 2 // m thick silver. However, semiconductor packages have long been miniaturized, so they have a denser structure and will not cause migration. Gradually higher cyan than gold or silver, which will cause migration, is used to maintain the flatness of the plating layer when plating precious metals. To

517315 五、發明說明（3) 及減少貴金屬的著力之金屬所製金屬電鍍到底部底部電鍍層的材第1圖至第體導線架的電鍍首先，第1 半導體導線架的底部電鍍層1 2形表面1 1上，而另外部層。該專利形成於一0.1〜1 I 部電鍍層的金（0 可避免。鈀具有著相此外，當外層由能會發生氧化的點也變得更高，管的磨損或破壞 ogen embrittle 時，它即與氫結第2圖係為導體導線架的橫中所出現問題的使用量，由與被電鍍材質具有良好電鍍黏成的底部電鍍層先予以完成，然後再將貴，電鑛層上。在該例中，鎳通常被用來作為質。 4圖係為以預電鐘方法為基礎之習知半導層結構示意圖。圖係為曰本專利1，5 0 1，7 2 3所揭示之習知橫剖圖，在塑膠封裝的導線架中，一鎳-成於晶片組裝區上和導線結合區的導線架一由鈀或鈀合金所製成的電鍍層13形成為之一實施例中，一0.1〜1/zm厚的鈀電鍍層 _ z m厚的鎳電鍍層上。依據該專利，作為外 • 5〜2 // m )或銀（1〜5 // m )，則游移的問題即當稠密的結構，並且是一高硬度的金屬。鈀製成時，在高溫半導體封裝過程中很可現象。因此，其電鍍層變得更硬，且其熔因而降低了可焊性以及造成導線結合毛細。再者，因為I巴是一具有氫脆化性（h y d r -ment)的金屬，因此，當其暴露於空氣中合，故導致電鑛層的脆化。曰本專利2，5 4 3，6 1 9所揭示之另一習知半剖圖，其中揭示了在日本專利1，5 0 1，7 2 3 解決方式。另，其亦提供了一在銅或銅合 517315 五、發明說明（4) 金層上具有 1 // m厚之錄於或等於0. 以及一 0 . 0 0 導線上的鈀然而，應用於需要問題。首先鍵層來作為之導線架來處易產生裂為在具有較不斷地受到面之間微弱者，由於疲上所述，由生，因而在導線結合部 (heel crac 性測試，其 (TC)時會產使用銀為外才會產生裂上述結構的複數金屬覆層半導體裝置的導線架，其中，一底部電鍍層2 2係設於銅或銅合金層2 1上、一小 3 //m厚的鈀或鈀合金層23完全地形成於其上、卜0 . 1 // m厚的金電鍍層2 4形成於導線架的外部或纪合金層上。於弟2圖所示之具有層豐結構之半導體導線架有長期可靠度之半導體封裝上時卻會發生下列，就導線結合部分的黏著性而言，具有一金電外部電鍍層的導線架是比具有一銀外部電鍍層得弱，因此在封裝半導體裝置後，在導線結合缝，因而造成了像是短路之產品瑕疵。這是因弱模塑黏著性（m ο 1 d i n g a d h e s i ο η )的導線架上熱衝擊，因而造成了模具部分和導線架結合表的起伏變化和造成疲乏（fatigue)的現象。再乏所產生的裂缝亦會造成短路現象的發生。如於持續的熱應力所導致的收縮和擴張的重覆發模具和導線架之間的介面上產生裂縫，或是在分產生了切口，這亦即所謂的「根部裂缝」 k)。具有上述結構的導線架進行了一項抗裂缝結果顯示，在小於或等於6 0 0 次溫度循環試驗生裂縫，如同於比較實例1中之說明，相較於部電鍍層（在超過1 0 0 0 次溫度循環試驗（TC)時缝）時，其具有極差的抗裂缝性。因此，具有半導體產品在長期的可靠度上是有問題的。517315 V. Description of the invention (3) Metals made of metals with reduced precious metal force plating to the bottom bottom plating layer Figure 1 to body lead frame plating First, the bottom plating layer of the first semiconductor lead frame 1 2 The surface 11 is on the other side. The patent is formed on a 0.1 ~ 1 I plating layer of gold (0 can be avoided. Palladium has a phase. In addition, when the outer layer becomes higher from the point where oxidation can occur, the tube wears or damages the source embrittle, it That is, the second picture with the hydrogen junction is the amount of problems in the horizontal direction of the conductor lead frame. The bottom plating layer with good plating adhesion to the material being plated is completed first, and then the expensive and electric ore layer is on In this example, nickel is usually used as a substance. Figure 4 is a schematic diagram of a conventional semiconducting layer based on the pre-electric clock method. The figure is disclosed in Japanese Patent No. 1,50 0,7 2 3 In a conventional cross-sectional view, in a plastic-encapsulated lead frame, a nickel-formed lead frame formed on a chip assembly area and a wire bonding area, and a plating layer 13 made of palladium or a palladium alloy is formed as an embodiment , A 0.1 ~ 1 / zm thick palladium plating layer _ zm thick nickel plating layer. According to the patent, as the outer • 5 ~ 2 // m) or silver (1 ~ 5 // m), the problem of migration That is, when the structure is dense, and it is a high hardness metal. When made of palladium, it is quite a phenomenon during high-temperature semiconductor packaging. As a result, its plating layer becomes harder, and its melting reduces solderability and causes wire bonding capillary. Furthermore, because Ibar is a metal with hydrogen embrittlement (hy d r -ment), when it is exposed to the air, it causes embrittlement of the power deposit. Another conventional half sectional view disclosed in Japanese Patent 2,5 4 3,6 1 9 discloses a solution in Japanese Patent 1,50 0 1,7 2 3. In addition, it also provides a copper or copper alloy 517315 V. Description of the invention (4) The gold layer has a thickness of 1 // m recorded at or equal to 0. and a palladium on a 0. 0 wire. However, it is applied to Need questions. Firstly, the bond layer is used as the lead frame, and it is easy to be cracked. It is weak between the continuous receiving surfaces. Because of the fatigue mentioned above, it is born. Therefore, it is at the wire junction (heel crac property test, which (TC) A lead frame for a plurality of metal-clad semiconductor devices with a cracked structure as described above will be produced when silver is used outside. Among them, a bottom plating layer 2 2 is provided on the copper or copper alloy layer 21 1 and a small 3 // m A thick palladium or palladium alloy layer 23 is completely formed thereon, and a 0.10 m thick gold plating layer 24 is formed on the outer or lead alloy layer of the lead frame. Yudi has a layer as shown in Fig. 2 The semiconductor lead frame with a rich structure has long-term reliability on a semiconductor package, but the following will occur. In terms of the adhesion of the wire bonding portion, a lead frame with a gold electrical outer plating layer is weaker than a silver outer plating layer. Therefore, after the semiconductor device is packaged, the seam of the wire is bonded, which causes a defect like a short circuit. This is due to the thermal shock on the lead frame with weak molding adhesion (m ο 1 dingadhesi ο η), which causes the mold Partial and The wire frame combines the fluctuations of the table and the phenomenon of fatigue. The cracks generated by the lack of it will also cause the occurrence of short circuits. Repeated molds and lead frames that contract and expand due to continuous thermal stress A crack is created in the interface between the two, or a cut is made in the branch, which is also called "root crack" k). A lead frame with the above structure was subjected to an anti-cracking result. It was found that cracks were generated at a temperature cycle test of less than or equal to 600, as explained in Comparative Example 1. Compared with the partial plating layer (in excess of 100), At the time of 0 temperature cycle test (TC), it has extremely poor crack resistance. Therefore, having a semiconductor product is problematic in terms of long-term reliability.

第9頁 517315 五、發明說明（5) 第3圖係為導線架之另一實請參閱第於由 (metal 製成厚層32上形成於缺或ίε合生裂缝 1 · Η 〜1 趨勢來得過大插腳裝換降低，銀游移會增加在層，例使用直層是藉，所以厚度為0. substra 度為0 . 0 1 。由銀或中間電鍍而，具有金所製成。此外， 0 /z m 〇就看，則每。因此，置時，下言之，在因為在半現象的產導線架的具有第1 如鎳電鍍流電的方由直流電在成形過美國專利4，5 2 9，6 6 7所揭示之習知預電鍍施例圖。圖，由鎳所製成之底部電鍍層32係為層疊 1〜5 //m之銅或銅合金所製成之金屬基片31 te)上。一由錫、纪、釕、錢或其合金所〜2 // m之中間電鍍層3 3係形成於底部電鍍銀合金所製成之卜3 //m之外部電鍍層34再層3 3上。上述層疊結構之導線架卻有著過厚、由鈀的中間電鍍層，因此，在導線彎折處易產形成於金屬基片上的諸電鍍層之總厚度為目前多插腳（mu 1 t i-p i η )和輕型導線架的一電鍍層的厚度和諸電鍍層的總厚度就顯當上述導線架應用於超過100根插腳的多-列的問題即會產生。銀電鍍層過厚的情況下，晶片可靠度即會導體封裝後，其於濕熱的電鍍環境下導致生。另，過度使用貴金屬，例如把或銀，生產成本。圖至第3圖所示之結構導線架中，其電鍍層、鈀電鍍層、銀電鍍層或金電鍍層，係法來進行電鍵。然而，若Ιε、銀或金電鍍方法來形成時，則電鍍層的展延性會變差程中很可能會產生裂缝。另外，厚度的變Page 9 517315 V. Description of the invention (5) The third picture is another reality of the lead frame. Please refer to the section on the thick layer 32 made of (metal) formed in the gap or εε joint crack 1 · Η ~ 1 The trend is too large The pin replacement is reduced, and the silver migration will increase in the layer. For example, using a straight layer is borrowed, so the thickness is 0. Substrat is 0. 0 1. It is made of silver or middle plating and has gold. In addition, 0 / zm 〇Look at it, so every time. So, in a timely manner, in the semi-phenomenon of the production of leadframes with the first galvanic current such as nickel plating, the direct current has been formed in the United States Patent 4,5 2 9,6 Figure 6 shows the conventional pre-plating example shown in the figure. The bottom plating layer 32 made of nickel is a metal substrate 31 te) made of copper or copper alloy laminated 1 ~ 5 // m . An intermediate plating layer 3 of 3 m made of tin, metal, ruthenium, money, or an alloy thereof is formed on the outer plating layer 34 of 3 m made of silver electroplated on the bottom layer 3 and 3 . The lead frame of the above-mentioned laminated structure has an excessively thick intermediate plating layer made of palladium. Therefore, the total thickness of the plating layers formed on the metal substrate easily at the bend of the wire is the current multi-pin (mu 1 t ip i η ) And the thickness of a plating layer and the total thickness of the plating layers of the light weight lead frame, the problem that the lead frame is applied to a multi-row with more than 100 pins will occur. When the silver plating layer is too thick, the reliability of the chip will be caused by the hot and cold plating environment after the conductor is packaged. In addition, the excessive use of precious metals, such as bar or silver, has production costs. In the structured lead frame shown in Figs. 3 to 3, the electroplating layer, palladium electroplating layer, silver electroplating layer, or gold electroplating layer are used to perform electric bonding. However, if Ιε, silver, or gold plating is used to form the plating, the ductility of the plated layer is deteriorated, and cracks are likely to occur during the process. In addition, the thickness changes

第10頁 517315 五、發明說明（6) 異也會因為電鍍厚度降低至1 // m 得嚴重，因此，是故，中間電鍍生氧化的現象，氧化，因而產生了避免這些問題化的後處理（P 0 S 成導線架的製造第4圖係為速度的不致 (4微吋）或更電鍍層無法發層或金屬基片或是金屬元素了彎折裂縫或，可以施以較 t-treatment) 示之另或鎳 β m 合金，其層4 3 的金少含施以厚度體封，由了導合金之金之其厚度的成屬基有鈀調變若具和元裝過於表線結成本。本創作習知導線架之所製成的鎳電屬基片41上。中一電鍍金屬為 0· 01 形方式片浸沒、金、電流。有上述件之保程時，面層處合性和〜1 · 5微如下：入一具銀以及申請人層疊結鍍層42 此外，之保護吋（約先將具有電鍍其合金層疊結構的導護層的導線架下列問題即會於高溫的狀態可焊性。在具而產生。因此，若電鍍層的少時，介面的不同質性會變揮其作為抗氧化層之功能。在高溫半導體封裝時亦會發會擴散至表面而於空氣中被降低了導線架的可焊性。為厚的電鍍層或是施以例如韋刃步驟，然而，這些步驟亦造之美國專利6，1 5 0，7 1 3所揭構圖。請參閱第4圖，由鎳形成於一厚度在0· 25〜0· 05 至少含有鈀、金、銀以及其層43係成形於鎳電鍵層42上 0.00025 〜0.05 /zm)。保護有成形於基片上之鎳電鍍層液的電鍍槽中，該電鍍液至其中之一，然後再對電鍍槽線架，也就是說，具有上述應用於1 5 0 t〜3 0 0 °C之半導產生：首先，在鈀保護層中下，因熱氧化的關係而降低有較弱的模塑黏著性之金保Page 10 517315 V. Explanation of the invention (6) The difference is also serious because the plating thickness is reduced to 1 // m. Therefore, it is because of the phenomenon of oxidation in the middle plating, which results in post-processing to avoid these problems. (The manufacturing of P 0 S lead frame is shown in Figure 4. The speed is not high (4 microinches) or the plating layer cannot be formed or the metal substrate or the metal element is bent or cracked, which can be applied for more t-treatment. ) As shown in the example or nickel β m alloy, the gold of layer 4 3 is thinly sealed with a thickness seal, and the thickness of the metal of the alloy is based on the palladium modulation. this. This work is known on a nickel substrate 41 made of a lead frame. S1 plated metal is in the form of 0 · 01, the sheet is immersed with gold, and current. With the guarantee of the above, the surface layer bonding and ~ 1.5 micrometers are as follows: Into a silver and the applicant's laminated junction plating layer 42 In addition, the protection (about first will have the guide protection of the alloy laminated structure of its plating) The following problems of the layered lead frame are solderability at high temperature. It occurs. Therefore, if the plating layer is small, the heterogeneity of the interface will change its function as an anti-oxidation layer. In high temperature semiconductor packaging It sometimes spreads to the surface and reduces the solderability of the lead frame in the air. For thick electroplated layers or applying steps such as weir blades, however, these steps also create US patent 6,150 The pattern is disclosed in 7 1 3. Please refer to Fig. 4. It is formed of nickel in a thickness of 0. 25 ~ 0. 05. It contains at least palladium, gold, silver, and its layer 43. It is formed on the nickel bond layer 42 0.00025 to 0.05. / zm). Protect the electroplating tank with the nickel plating solution formed on the substrate, the plating solution to one of them, and then the electroplating tank wire frame, that is, the above-mentioned application has been applied to 150 ° ~ 300 ° The semiconducting occurs: First, under the palladium protective layer, the gold guarantee of weak molding adhesion is reduced due to thermal oxidation.

第11頁 517315 五、發明說明（7) 護層中，當的封裝過程伏。因此，。另外，若部電鍍層上層和鎳電鍵低了導線的【發明為了解出一種半導 1 .以下列由一鎳上，接有良好然後由電鍍層 2. 可藉由焊性、 3. 可減少成形時 4. 大大也本發明線架的方法【解決其應用於時，模具在導線結在銀（Ag) 是不容易層之間的結合性。目的】決上述問體封裝用方式來改或錄合金著成形另物理性質 I巴或Ιε合和外部電降低諸電導線結合裂縫在諸的游移現降低生產之另一目〇方式】需要具有持黏著的不同合部分上產的保護層中的。即使銀黏著性仍是題，之導善不所製一由本創作線架，同電鍍成的底可作為或銀合製成之之間；的厚度環氧樹層上的以及續承受熱負荷之高可靠度部分之間會產生微弱的起生根部裂縫的可能性極高，要直接將銀電鍍在鎳底直接電鍍上去，則銀保護不佳，因而不可避免地降的主要目的，即在於創作其層的特徵，其方式如下：部電鍍層係形成於導線架預電鍍導線架材質、且具金所製成的外部電鍍層，中間電鍍層係成形於底部之銀金所鍵層鍵層性和電鍍象；成本。的在於提供一製造半導體封裝用之導來改善預電鍍導線架之可脂黏著性；生成和降低銀（Ag)於產品Page 11 517315 V. Description of the invention (7) In the protective layer, the encapsulation process of the current is volts. Therefore,. In addition, if the upper layer of the electroplating layer and the nickel bond have a lower conductive wire, [the invention is to understand a semiconductor 1. The following is made of a nickel, connected well and then the electroplated layer 2. Solderability, 3. Can reduce 4. When forming 4. The method of the wire frame of the present invention [solves its application when the wire is bonded to silver (Ag), which is not easy to bond between layers. Purpose] To determine the above-mentioned method for packaging the alloy to modify or record alloy physical properties and other physical properties I bar or Iε combined with external electricity to reduce the electrical wires in combination with the cracks in the various migration is to reduce the production of another way] Need to have sticking In the protective layer produced on different joints. Even though silver adhesion is still a problem, the guideline is not made by a wire frame made of this creation, and the bottom plated with silver can be used as silver or silver; the thickness of the epoxy tree layer and the continuous load of heat The possibility of weak root cracks between high-reliability parts is extremely high. If silver is directly plated on a nickel bottom, the silver is not well protected, so the main purpose is inevitably to fall, which is to create The characteristics of the layers are as follows: The partial plating layer is formed on the lead frame and the outer plating layer is made of pre-plated lead frame material. The intermediate plating layer is formed on the bottom of the silver-gold bond layer. And electroplating; cost. The purpose is to provide a semiconductor package manufacturing guide to improve the adhesion of pre-plated leadframes; generate and reduce silver (Ag) in the product

第12頁 517315 五、發明說明（8) 為了達到上述第一個目的，本創作提供了一半導體封裝用之導線架，其中包括了一由銅、銅合金或鐵-鎳合金 _ 所製成之底部金屬層、一形成於底部金屬層的至少一表面上和由鎳或鎳合金所製成的底部電鍍層、一形成底部電鍍 -層上，且由鈀或鈀合金製成之厚度為0.00025〜0.1 //m (0. 1〜4微吋）之中間電鍍層、以及一形成中間電鐘層内，且由銀或銀合金所製成之厚度為0 . 0 5〜0 · 7 5 // m ( 2〜3 0微吋）之外部電鍍層。依據本發明的其它特徵，半導體封裝用之導線架包括了一由銅、銅合金或鐵-鎳合金所製成之底部金屬層、一形成於底部金屬層的至少——表面上和由鎳或鎳合金所製成 ® 的底部電鍵層、一形成底部電鑛層上，且由ί巴或纪合金製成之厚度為0 · 0 0 0 2 5〜0 · 1 // m ( 0 · ：1〜4微吋）之中間電鍍層、以及一形成中間電鍍層内，且由銀或銀合金所製成之厚度為0.05〜0.75 /zm (2〜30微吋）之外部電鍍層。其中，中間電鍍層藉由針對電鍍槽施以調變電流來形成之。為了達到上述第二個目的，本發明之製作半導體封裝用之導線架的方法包括下列步驟： a) 提供一底部金屬層； b) 預處理底部金屬層； c )於該底部金屬層上形成一由鎳或鎳合金所製成的底部k 電鍍層； d)藉由將上述步驟3所得之結構浸沒入一含有把或le合金之電鍍槽内，並施以調變電流（頻帶為1 0 0 0〜2 0 0 0Page 12 517315 V. Description of the invention (8) In order to achieve the above first object, this work provides a lead frame for semiconductor packaging, which includes a copper, copper alloy or iron-nickel alloy_ A bottom metal layer, a bottom plating layer formed on at least one surface of the bottom metal layer and a bottom plating layer made of nickel or a nickel alloy, and a bottom plating layer formed on the bottom metal layer, and the thickness of the bottom metal layer is 0.00025 ~ 0.1 // m (0. 1 ~ 4 micro inches) intermediate plating layer, and a layer formed of silver or silver alloy inside the middle electric clock layer, and the thickness is 0. 0 5 ~ 0 · 7 5 // m (2 ~ 30 microinches) of external plating. According to other features of the present invention, a lead frame for a semiconductor package includes a bottom metal layer made of copper, a copper alloy or an iron-nickel alloy, and at least one surface formed on the bottom metal layer and made of nickel or Bottom key bond layer made of nickel alloy, one formed on the bottom electric ore layer, and made of 巴 bar or metal alloy with a thickness of 0 · 0 0 0 2 5 ~ 0 · 1 // m (0 ·: 1 ~ 4 microinches) of the intermediate plating layer, and an outer plating layer formed of silver or a silver alloy and having a thickness of 0.05 to 0.75 / zm (2 to 30 microinches) formed in the intermediate plating layer. The intermediate plating layer is formed by applying a modulation current to the plating bath. In order to achieve the above second object, the method for manufacturing a lead frame for semiconductor packaging according to the present invention includes the following steps: a) providing a bottom metal layer; b) pre-processing the bottom metal layer; c) forming a bottom metal layer on the bottom metal layer Bottom k plating layer made of nickel or nickel alloy; d) immersing the structure obtained in step 3 above into a plating bath containing alloy or le alloy, and applying a modulation current (frequency band 1 0 0 0 ~ 2 0 0 0

第13頁 517315 五、發明說明（9)Page 13 517315 V. Description of the invention (9)

Hz，負載係數duty cycle為5〜45%，對電鍍槽而言，平均電流密度為0 · 1〜3 A / d m 2 ); 以及 _ e )於中間電鍍層上形成一由銀或銀合金製成的外部電鍍層。 _ 為求進一步瞭解本發明之構造特徵、技術内容與功能，請參閱以下有關本發明之詳細說明與附圖，然而所附圖示乃供參考與說明用，並非用以對本發明施予限制者。【詳細内容】第5圖係為本發明導線架的層疊結構圖。請參閱第5圖，由鎳或鎳合金所製成之底部電鍍層5 2係形成於一底部金屬層51上。該底部電鍍層52的厚度最佳為0. _ 2 5〜2 · 5 // m。一由鈀或鈀合金所製成之中間電鍍層5 3係形成於底部電鍍層52上，其厚度為0.00025〜0.1 /zm (0.1〜4 微忖）。一由銀或銀合金所製成之厚度為0.05〜0.75 //m (2〜3 0微吋）之外部電鍍層5 4。於本發明中，底部電鍍層5 2係由鎳或鎳合金所製成。而鎳合金最好由80〜99.999 wt%的鎳和0.001〜20 wt%的鱗組成。底部電鍍層5 2的功能在於藉由在焊接時與焊接元件相熔合來支持一被焊結構，以及當上電鍍層和導線架底部金屬之間的黏著性增加的同時，亦可維持上電鍍層的均勻性。此外，底部電鍍層5 2亦可避免底部金屬層5 1的氧化，_ 以及避免因為底部金屬層51的金屬元素之擴散而造成氧化物的形成。底部電鑛層52的厚度最佳為0.25〜2.5 /zm。若底部電Hz, the duty cycle is 5 ~ 45%, and the average current density is 0 · 1 ~ 3 A / dm 2) for the plating bath; and _ e) is formed on the intermediate plating layer by silver or silver alloy Outer plating. _ In order to further understand the structural features, technical contents and functions of the present invention, please refer to the following detailed description and drawings of the present invention, but the attached drawings are for reference and explanation, and are not intended to limit the present invention. . [Details] FIG. 5 is a laminated structure diagram of a lead frame according to the present invention. Referring to FIG. 5, a bottom plating layer 52 made of nickel or a nickel alloy is formed on a bottom metal layer 51. The thickness of the bottom plating layer 52 is preferably 0. _ 2 5 to 2 · 5 // m. An intermediate plating layer 5 3 made of palladium or a palladium alloy is formed on the bottom plating layer 52 and has a thickness of 0.00025 to 0.1 / zm (0.1 to 4 micro4). An outer plating layer 54 made of silver or a silver alloy with a thickness of 0.05 to 0.75 // m (2 to 30 microinches). In the present invention, the bottom plating layer 52 is made of nickel or a nickel alloy. The nickel alloy is preferably composed of 80 to 99.999 wt% nickel and 0.001 to 20 wt% scales. The function of the bottom plating layer 52 is to support a structure to be welded by fusing with the welding component during welding, and to maintain the upper plating layer while the adhesion between the upper plating layer and the bottom metal of the lead frame is increased. Uniformity. In addition, the bottom plating layer 52 can also prevent the oxidation of the bottom metal layer 51 and the formation of oxides due to the diffusion of the metal elements of the bottom metal layer 51. The thickness of the bottom electrical ore layer 52 is preferably 0.25 to 2.5 / zm. If the bottom is charged

第14頁 517315 五、發明說明（ίο) 鍍層5 2的厚度小於0 . 2 5 // m時，則底部電鍍層5 2就很難作為一底部金屬層。若底部電鍍層52的厚度大於2.5 //m時，則在半導體組裝過程成形時易產生裂缝。當底部電鍍層5 2以鎳或鎳合金來成形時，則可藉由一般的直流電方法來進行電鍍。然而，為了形成一具有與底部金屬層5 1極佳黏著性和具有良好延展性的細薄底部電鍍層5 2，電鍍a寺最好是使用一調變式電流來進行。使用調變式電流可藉由間歇性的供電來增加電流的效率，因而可得到一平整的鍍層。若使用調變式電流來電鍍鎳或鎳合金時，調變式電流最好具有頻帶為1 0 0〜2 0 0 0 0 Hz，負載係數為 5〜8 0 %，而電流脈衝最好具有平均電流密度為1 5〜3 5 A / d m 2 中間電鍍鑛層5 2上。而金得由8 0〜9 9 . 釕、鎳和填至終產品的電鍍然而，把合金一固定的合金是無法大量生用。由纪或Is 鎳或鎳合金所銀或銀合金所層5 3係形成於由中間電鍍層5 3係 999 wt%的把和0 , 少其中之一來組品質會類似於使電鍍液比鈀電鍍比率，故而造成產之主因。因此合金所製成之中製成的底部電鍍製成的外部電鍍鎳合金所製或把合金所 -20 w t % 的若使用鈀合一纪金屬的鎳或由I巴 001 成。用單液來得昂貴，但一複雜的處理過，I巴比把合金較間電鍍層5 3係確層5 2，並且亦確層5 4。此外，中成的底部電製成。把合由金、銀、金時，則最電鑛品質。又必需維持程，而這正多為人所使實黏著於由實黏者於由間電鍍層5 3Page 14 517315 V. Description of the invention (ίο) When the thickness of the plating layer 5 2 is less than 0.2 5 // m, the bottom plating layer 5 2 is difficult to be used as a bottom metal layer. If the thickness of the bottom plating layer 52 is greater than 2.5 // m, cracks are likely to occur during the forming of the semiconductor assembly process. When the bottom plating layer 52 is formed of nickel or a nickel alloy, the plating can be performed by a general DC method. However, in order to form a thin bottom plated layer 5 2 having excellent adhesion to the bottom metal layer 51 and good ductility, the electroplating is preferably performed using a modulation current. The use of a modulating current can increase the efficiency of the current by intermittent power supply, so that a flat coating can be obtained. When modulating current is used to plate nickel or nickel alloy, the modulating current should preferably have a frequency band of 1 0 ~ 2 0 0 0 0 Hz, a load factor of 5 ~ 80%, and the current pulse should preferably have an average The current density is 1 5 ~ 3 5 A / dm 2 on the middle electroplated ore layer 5 2. However, gold has to be plated from 80 to 99. Ruthenium, nickel, and plating to fill the final product. However, a fixed alloy cannot be used in large quantities. Yuki or Is nickel or nickel alloy layer of silver or silver alloy 5 3 series is formed by intermediate plating layer 5 3 series of 999 wt% sum 0, less one of which is similar to making the plating solution better than palladium The plating ratio is the main cause of production. Therefore, the alloy is made of bottom plating, the outer plating is made of nickel alloy, or the alloy is -20 w t% of nickel, if made of palladium-grade metal, or made of 1 bar 001. It is expensive to use a single solution, but after a complex treatment, I Barbie compared the alloy to the electroplated layer 5 3 to ensure the layer 5 2 and also the layer 5 4. In addition, the bottom of the intermediate component is made electrically. When combined with gold, silver, and gold, it has the best ore quality. It is necessary to maintain the process, and this is mostly caused by people.

第15頁 517315 五、發明說明（11) 可避免底部金屬層51和底部電鍍層52的金屬元素擴散至表面而造成氧化現象，並協助外部電鍍層5 4即使在高溫狀態，下亦可維持其作為銀電鍍層之固有性質，俾使外部電鍍層 5 4更細薄。 ' 中間電鍍層5 3的最適厚度為0 . 0 0 0 2 5〜0 . 1 // m。若中間電鍍層5 3的厚度小於0 . 0 0 0 2 5 /z m時，則中間電鍍層5 3不足以完整覆蓋底部電鍍層5 2。因此，中間電鍍層5 3就難以發揮其中間電鍍層之功能。另一方面，若中間電鍍層5 3的的厚度大於0. 1 // m時，則因為厚度增加所帶來的品質改善效果是可以忽略的，但卻只增加產品的成本。再者，作為外部電鍍層5 4材質的銀之熔點過低，以致於銀易於熔化，然 _ 而，中間電鍍層5 3的鈀材質卻較不易熔化。若中間電鍍層 5 3變厚，而使得其厚度超過其範圍時，則只有外部電鍍層 5 4的銀電鑛層溶化，故而惡化了錯的焊料吸濕性。為了形成一稠密完全的中間電鍍層53，使其具有與底部電鍍層5 2和外部電鍍層5 4極佳黏著性和具有丧好延展性來看，把或ί巴合金最好使用調變式電流來進行電鍵，如此一來，電鍍層的品質即可藉由間歇式供電來調整鈀電鍍層的生成方向和成長速度而予以改善。可應用於形成由鈀或鈀合金所製成的中間電鍍層5 3之調變式電流的較佳實施例，包括一方形波脈衝電流，其中一定數目之脈衝波和逆轉 · 脈衝重覆如第6 Α圖所示、一方形波脈衝電流之極性在預定的時間間隔内做如第6 B圖所示之週期性逆轉、一方形波脈衝電流之極性做如第6 C圖所示之逆轉、一方形波脈P.15 517315 V. Description of the invention (11) It can prevent the metal elements of the bottom metal layer 51 and the bottom plating layer 52 from diffusing to the surface and cause oxidation, and assist the external plating layer 5 4 to maintain it even at high temperature. As an inherent property of the silver plating layer, the outer plating layer 54 is made thinner. 'The optimal thickness of the intermediate plating layer 53 is 0. 0 0 0 2 5 to 0. 1 // m. If the thickness of the intermediate plating layer 5 3 is less than 0.00 0 2 5 / z m, the intermediate plating layer 5 3 is insufficient to completely cover the bottom plating layer 52. Therefore, it is difficult for the intermediate plating layer 53 to function as the intermediate plating layer. On the other hand, if the thickness of the intermediate plating layer 5 3 is larger than 0.1 m, the quality improvement effect due to the increased thickness is negligible, but it only increases the cost of the product. Furthermore, the melting point of silver, which is the material of the outer plating layer 54, is too low, so that the silver is easy to melt, but the palladium material of the middle plating layer 53 is less likely to melt. If the intermediate plating layer 5 3 becomes thicker so that its thickness exceeds the range, only the silver electrooresis layer of the external plating layer 5 4 will be melted, thereby deteriorating the hygroscopicity of the wrong solder. In order to form a dense and complete middle plating layer 53 which has excellent adhesion to the bottom plating layer 5 2 and the outer plating layer 5 4 and has good ductility, it is best to use a modified alloy Electricity is used to perform electrical bonding. In this way, the quality of the plating layer can be improved by adjusting the generation direction and growth rate of the palladium plating layer by intermittent power supply. A preferred embodiment of a modulating current that can be applied to form an intermediate plating layer 5 3 made of palladium or a palladium alloy includes a square wave pulse current, in which a certain number of pulse waves and reversals. The pulse repeats as the first As shown in Fig. 6A, the polarity of a square wave pulse current is periodically reversed as shown in Fig. 6B within a predetermined time interval, and the polarity of a square wave pulse current is reversed as shown in Fig. 6C. A square wave

第16頁 517315 五、發明說明（12) 衝電流，如第6 D圖所示，其中一脈衝電流，在延遲一預定時間内不逆轉地進行重覆、以及一方形波脈衝電流，如第6 E圖所示，其中一脈衝持續一段時間進行重覆後，而其極性作週期性的逆轉。在形成中間電鍍層5 3時，施於含有鈀或鈀合金之電鍍槽内之調變式電流，其較佳狀態如下 : 頻帶為1 0 0 0〜2 Ο Ο Ο Η z，負載係數為5〜4 5 %，平均電流密度為0. 1〜3Α/dm2)頻帶為1 0 0 0〜2 0 0 0 Hz ，負載係數為5〜45%，該設定的目的在於將電流的間歇週期調整至一較高速度，以抑制氫的形成、控制電鍍層的生長方向、均勻形成電鍍層、以及避免結構性的瑕疵出現。因此，中間電鍍層5 3得以形成於一薄膜内，並達到極佳的產品品質。但是，若頻帶為1 0 0 0 Hz或更低，而負載係數為大過於45%時，則上述之效果就無法達成。若若頻帶大過於2 0 0 0 0 Hz或更低，而負載係數為小於5 %時，則現有的整流器就無法確保設備的穩定度，因而缺乏實用性。平均電流密度是影響電鍍速度的一個因素，最好是能夠保持在0 . 1〜3 A / dm 2之間。當電流密度較小時，電鍍分子的均勻度就增加。但是，若電流密度小於0. 1 A/dm2時，電鍍速度就較慢。如果電鑛密度大於3A/dm2時，則電鍍分子的成長速度就稍作增加，且均勻核子的成長可能性亦增高，故不足以形成一高品質、無瑕疵的鈀電鍍層來發揮中間電鍍層的功能。外部電鑛層5 4是由銀或銀合金所製成。銀合金係由80 〜9 9. 9 9 9 wt%的銀和0. 001〜20 wt% 的由鈀、銀、釕、鎳和Page 16 517315 V. Description of the invention (12) Impulse current, as shown in Fig. 6D, in which a pulse current is repeated without delay in reversal after a predetermined time delay, and a square wave pulse current, as shown in Fig. 6 As shown in Figure E, after one pulse is repeated for a period of time, its polarity is periodically reversed. When the intermediate plating layer 53 is formed, the modulation current applied to the plating bath containing palladium or a palladium alloy is preferably as follows: the frequency band is 1 0 0 0 ~ 2 Ο Ο Ο Η z, and the load factor is 5 ~ 45%, average current density is 0.1 ~ 3Α / dm2) frequency band is 1 0 0 0 ~ 2 0 0 0 Hz, load factor is 5 ~ 45%, the purpose of this setting is to adjust the intermittent period of the current to A higher speed to suppress the formation of hydrogen, control the growth direction of the plating layer, uniformly form the plating layer, and avoid the occurrence of structural defects. Therefore, the intermediate plating layer 53 can be formed in a thin film and achieves excellent product quality. However, if the frequency band is 100 Hz or lower and the load factor is larger than 45%, the above effects cannot be achieved. If the frequency band is larger than 2000 Hz or lower, and the load factor is less than 5%, the existing rectifier cannot ensure the stability of the equipment, and thus lacks practicality. The average current density is a factor that affects the plating speed, and it is best to keep it between 0.1 to 3 A / dm 2. When the current density is small, the uniformity of the plating molecules increases. However, if the current density is less than 0.1 A / dm2, the plating speed is slower. If the density of the electric ore is greater than 3A / dm2, the growth rate of the plating molecules will increase slightly, and the possibility of the growth of uniform nuclei will increase, so it is not enough to form a high-quality, flawless palladium plating layer to play the intermediate plating Functions. The outer electrical ore layer 54 is made of silver or a silver alloy. The silver alloy is composed of 80 to 9 9. 9 9 9 wt% of silver and 0.001 to 20 wt% of palladium, silver, ruthenium, nickel and

第17頁 517315 五、發明說明（13) 磷至少其中之一來組成。由銀或銀合金所製成之外部電鍍層5 4保護層疊於其下之諸電鍍層，俾以維持諸電鍍層之品 . 質。因此，由於銀本身的性質，即使在高溫的半導體組裝狀態下，具有0.05〜0.75//Π1薄膜厚度之外部電鍍層54可維 — 持適當的抗腐蝕性、極佳的導線結合性、模塑黏著性和可焊性。若由銀或銀合金所製成的外部電鍍層5 4之厚度小於 0. 0 5 // m時，則模塑黏著性會變得較弱，且避免底層效果的氧化亦可忽略。為了解決該問題，中間電鍍層5 3應變得較厚。如果外部電鍍層5 4的厚度大於0. 7 5 // m時、環氧樹脂黏著性、可焊性和導線結合性皆可改善。然而，在該例中，產生銀游務的可能性增高，因而導致半導體裝置長期豢可靠度的降低。另外，在考慮到由於厚度的增加而造成的成本上升，品質改善的有限效果是可以忽略的。外部電鍍層5 4如同中間電鍍層5 3可以藉由一調變式電流來形成。但是，若中間電鍍層5 3，也就是說，鈀電鍍層若稠密地成形時，具有適當厚度的銀電鍍層可相當程度地避免底部電鍍層的氧化。因此，如果只注意到厚度的條件，則外部電鍍層5 4也可以用一般的直流電的方式來形成。此處平均電流密度最佳為卜5A/dm2，此數據是考慮到底部金屬或中間金屬的電鑛速度和電鑛液的條件而得來的，因為底部、中間和外部的電鍍都是依據一般滾筒對滾筒電鍍 φ 方法（reel-to-reel plating method)在單一線路上進行的。如上所述，如果底部、中間和外部電鍍層的厚度以及Page 17 517315 V. Description of the invention (13) Phosphorus is composed of at least one of them. The outer plating layer 54 made of silver or a silver alloy protects the plating layers stacked thereunder, so as to maintain the quality of the plating layers. Therefore, due to the nature of silver, the external plating layer 54 having a film thickness of 0.05 to 0.75 // Π1 can be maintained even in a high-temperature semiconductor assembly state—maintaining appropriate corrosion resistance, excellent wire bonding, molding Adhesiveness and solderability. If the thickness of the outer plating layer 5 4 made of silver or a silver alloy is less than 0.005 // m, the mold adhesion will become weaker, and the oxidation of the underlying effect can be ignored. To solve this problem, the intermediate plating layer 53 should be made thicker. If the thickness of the outer plating layer 5 4 is greater than 0.7 5 // m, the epoxy resin adhesiveness, solderability and wire bonding properties can be improved. However, in this example, the possibility of silver travel is increased, which leads to a decrease in the long-term reliability of the semiconductor device. In addition, considering the cost increase due to the increase in thickness, the limited effect of quality improvement is negligible. The outer plating layer 5 4 can be formed by a modulation current as the middle plating layer 5 3. However, if the intermediate plating layer 5 3, that is, if the palladium plating layer is densely formed, a silver plating layer having an appropriate thickness can sufficiently prevent oxidation of the bottom plating layer. Therefore, if only the thickness condition is noticed, the outer plating layer 54 can also be formed by a general direct current method. Here the average current density is best 5A / dm2. This data is obtained by taking into account the electric ore speed of the bottom metal or intermediate metal and the conditions of the electric ore liquid, because the bottom, middle and external plating are based on general The reel-to-reel plating method is performed on a single line. As mentioned above, if the thickness of the bottom, middle, and

第18頁 517315 五、發明說明（14) 施於電鍍槽之調變式電流的頻帶、負載係數和平均電流密度超過上述提及之範圍時，則成品的製造效率即會降低、電鍍層結構的精細度和均勻度會變差，因此一半導體裝置所使用之預電鍍導線架的品質要求就無法達到。因此，本創作導線架之總厚度最佳為0 . 3 0 0 2 5〜3 . 6 // m 關過程，首所製成 reel m 式一對油、酸金屬浸，也就電流施形成一電鍍液 NiS04 且具有平均電若進行將液包括於製造一具有如第5圖所示之層疊結構的導線架之擬於下列詳述之。先，由銅、銅合金和鐵-錄合金，其中至少一金屬之導線架底部金屬係由滾筒對滾筒方法（r e e ：L - t 〇 -ethod)來持續供應。否則，底部金屬則以成批的方一地供應。然後，在供應的底部金屬上進行例如除潰或清洗等預處理工作。接著，經過預處理的底部沒入鎳電鍍液中，然後再施以直流電或調變式電流是說，具有波形之極端（ρ 〇 1 a r i t y )作週期性逆轉之於電鍍液中，因此，在底部金屬的至少一表面上可鎳或鎳合金的電鍵層。在此處，一習知鎳或鎳合金是用來作為鎳電鍍液。一典型的鎳電鍍液包含有。施於鎳電鍍液的電流係藉由一整流器來調變，並一 1 00〜2 0 0 0 0 Hz的頻帶以及5〜80 %的負載係數。而流密度為15〜35A/dm2。鎳電鍍層形成步驟完成後，中間電鍍層形成步驟則 I巴或把合金電鍍到鎳電鍍層上。使用的I巴或把合金了 Pb(NH3)4C12電鍍液、無氨電鍍液等等。Page 18 517315 V. Description of the invention (14) When the frequency band, load factor and average current density of the modulating current applied to the plating tank exceed the above-mentioned ranges, the manufacturing efficiency of the finished product will be reduced. The fineness and uniformity will deteriorate, so the quality requirements of a pre-plated lead frame used in a semiconductor device cannot be achieved. Therefore, the total thickness of the lead frame in this creation is best 0.30 0 2 5 ~ 3. 6 // m-off process, the first made reel m-type oil, acid metal immersion, which is also a current application. The plating solution NiS04 and having an average electric current are included in the manufacture of a lead frame having a laminated structure as shown in FIG. 5 which is described in detail below. First, copper, copper alloys, and iron-recording alloys, at least one of which is a metal, the bottom metal of the lead frame is continuously supplied by a roller-to-roller method (ree: L-t0-ethod). Otherwise, the bottom metal is supplied in batches. Then, a pretreatment such as decompression or cleaning is performed on the supplied bottom metal. Next, the pretreated bottom is immersed in the nickel plating solution, and then a direct current or a modulating current is applied. That is, the extreme (ρ 〇 arity) with the waveform is periodically reversed in the plating solution. Therefore, in the An electrical bond layer of nickel or a nickel alloy may be on at least one surface of the bottom metal. Here, it is known that nickel or a nickel alloy is used as a nickel plating solution. A typical nickel plating solution contains. The current applied to the nickel plating solution is modulated by a rectifier, a frequency band of 100 to 2000 Hz, and a load factor of 5 to 80%. The flow density is 15 ~ 35A / dm2. After the nickel plating layer forming step is completed, the intermediate plating layer forming step is performed by plating the alloy onto the nickel plating layer. The I bar used is alloyed with Pb (NH3) 4C12 plating solution, ammonia-free plating solution, etc.

第19頁 517315 五、發明說明（15) 此處所使用的電流為調變式電流，其頻帶為1 0 0 0〜2 0 0 0 Η z，負載係數d u t y c y c 1 e為5〜4 5 %，平均電流密度為 (K ：1 〜3A/dm2 ° 在中間電鍍層形成後，接著進行外部電鍍層的形成步驟，亦即將銀或銀合金電鍍到中間電鍍層上。所使用的銀或銀合金電鍍液包括一 KAg(CN)電鍍液、一無氰的電鍍液等等。此處所使用的電流可為調變式電流或直流電俾將銀電鍍層形成於鈀電鑛層上，而較佳的平均電流密度為1〜5 A /dm2 〇在形成外部電鍍層後，可接著進行例如酸潰或清洗的後處理步驟，因此，一導線架的預電鍍程序即告完成。施於鎳、鈀、銀電鍍槽内之調變式電流的較佳實施例包括了一方形波脈衝電流，其中一定數目之脈衝波和逆轉脈衝重覆如第6 A圖所示、一方形波脈衝電流之極性在預定的時間間隔内做如第6 B圖所示之週期性逆轉、一方形波脈衝電流之極性做如第6 C圖所示之逆轉、一方形波脈衝電流，如第6 D圖所示，其中一脈衝電流，在延遲一預定時間内不逆轉地進行重覆、以及一方形波脈衝電流，如第6 E圖所示，其中一脈衝持續一段時間進行重覆後，而其極性作週期性的逆轉。第7圖係為本發明導線架之平面圖。請參閱第7圖，半導體導線架包括複數條内部導線7 1、複數條分別連接至内部導線71之外部導線72以及一模墊器74(die pad unit )，俾以安裝一設於中間部位、由諸内部導線7 1環繞之半Page 19 517315 V. Description of the invention (15) The current used here is a modulating current, its frequency band is 1 0 0 0 ~ 2 0 0 0 Η z, the load factor dutycyc 1 e is 5 ~ 4 5%, average The current density is (K: 1 ~ 3A / dm2 °) After the intermediate plating layer is formed, the step of forming an external plating layer is performed, that is, silver or a silver alloy is plated on the intermediate plating layer. The silver or silver alloy plating solution used Including a KAg (CN) plating solution, a cyanide-free plating solution, etc. The current used here can be a modulating current or a direct current. The silver plating layer is formed on the palladium power deposit layer, and the average current is better. Density is 1 ~ 5 A / dm2 〇 After forming the external plating layer, post-processing steps such as pickling or cleaning can be performed, so a lead frame pre-plating process is completed. Applied to nickel, palladium, silver plating The preferred embodiment of the modulated current in the slot includes a square wave pulse current, in which a certain number of pulse waves and reverse pulses are repeated as shown in FIG. 6A. The polarity of a square wave pulse current is at a predetermined time. Do the week in the interval as shown in Figure 6B Periodic reversal, the polarity of a square wave pulse current is reversed as shown in Figure 6C, and a square wave pulse current is shown in Figure 6D. One of the pulse currents is not reversed within a predetermined time delay. Repeat and a square-wave pulse current, as shown in Figure 6E, after a pulse is repeated for a period of time, and its polarity is periodically reversed. Figure 7 is a plan view of the lead frame of the present invention Please refer to FIG. 7. The semiconductor lead frame includes a plurality of internal leads 71, a plurality of external leads 72 connected to the internal leads 71, and a die pad unit 74, respectively, so as to be installed at a middle position. Half surrounded by internal wires 7 1

第20頁 517315 五、發明說明（16) 導體晶片。此外，一作為底部電鍍層之錄或鎳合金電鑛層係形成於導線架的至少一表面上。再者，作為一中間電鍍 . 層之鈀或鈀合金電鍍層係形成於底部電鍍層上。然後，銀或銀合金電鍍層係形成為外部電鍍層。 _ 本發明參酌下列實例和比較實例再予以詳加說明，但卻不受此限。實例1 - 5 在電鍍鎳、鈀和銀時，其電流狀態如下：電鍍鎳時，頻帶、負載係數和平均電流密度分別設定為1 00 Hz、6 0%和20 A/dm2。電鍍鈀時，頻帶、負載係數和平均電流密度分別設定為2 0 0 0 Hz、20%和0. 5 A/dm2。 _ 電鍍銀時，可使用直流電，且平均電流密度設定為1 . 5A/ dm2o 依據上述電流狀態來實施電鍍，俾以得到具有如表一所示之電鍍層結構之諸導線架。關於上述導線架，例如導線結合性、可焊性、模塑黏著性、抗腐蝕性、抗裂縫性等等物理性質皆以下列方式來進行評估，並將結果顯示於表一當中。比較實例1 - 5 具有如表二中所示之電鍍層結構之半導體導線架係以習知方法進行製造。關於該導線架，例如導線結合性、可 _ 焊性、模塑黏著性、抗腐蝕性、抗裂縫性等等物理性質皆以下列方式來進行評估，並將結果顯示於表一當中評估物理性質的方法。在本發明的實例和比較實例中，係使用一Page 20 517315 V. Description of the invention (16) Conductor wafer. In addition, a bottom plating layer or a nickel alloy electro-deposit layer is formed on at least one surface of the lead frame. Furthermore, a palladium or palladium alloy plating layer as an intermediate plating layer is formed on the bottom plating layer. Then, a silver or silver alloy plating layer is formed as an outer plating layer. _ The present invention will be described in detail with reference to the following examples and comparative examples, but it is not limited thereto. Examples 1-5 When nickel, palladium, and silver are plated, the current states are as follows: When nickel is plated, the frequency band, load factor, and average current density are set to 100 Hz, 60%, and 20 A / dm2, respectively. When electroplating palladium, the frequency band, load factor, and average current density were set to 2000 Hz, 20%, and 0.5 A / dm2, respectively. _ When electroplating silver, direct current can be used, and the average current density is set to 1.5A / dm2o. Electroplating is performed according to the above current state, so as to obtain leadframes having a plating layer structure as shown in Table 1. Regarding the above lead frame, physical properties such as wire bonding, solderability, molding adhesion, corrosion resistance, crack resistance, etc. were evaluated in the following manner, and the results are shown in Table 1. Comparative Examples 1 to 5 Semiconductor lead frames having a plated layer structure as shown in Table 2 were manufactured by a conventional method. About this lead frame, physical properties such as wire bonding, solderability, mold adhesion, corrosion resistance, crack resistance, etc. are evaluated in the following manner, and the results are shown in Table 1 to evaluate the physical properties. Methods. In the examples and comparative examples of the present invention, a

第21頁 517315 五、發明說明（17) DRAM裝置、一STS0P2型封裝、丨· 2 “丨a型金導線、LME型環氧樹脂、一以銅為主的合金導線架、一熱塑性導線晶片 (LOC)帶。 ”、 (1 ) 導線結合性該項測試係用來評估結合線和導線之間的黏著力。用來測量該黏著力之裝置為由韓國三星技研株式會社所製造的S W B - 1 0 0 G。直到在導線結合後，結合又從一連結處分開所需的最小和平均力（gf)係藉讚80〜1〇〇的振動功率、80〜 100的壓迫力，15〜20的時間、具有7〇 _瓶頸的毛細管、一0· 8 mi 1金導線。此處所使用之一術語叩^的意思係為以應用於標準張力測δ式為基準，而具有完全分離導線結合部分之樣本數' (2 )可焊性電錢導線係浸沒入2 3 5 °C的雜液中2秒鐘後來測量在彎折導線部分之前或之後焊料受染污之程度。在大部分的導線架封裝之後，通常在一外部導線部分彎折後會產生裂缝。因此，在彎折後的測量會比在彎折前來得有意義些。在 2 7 5 °C加熱1小時後’即可進行95 °C、8小時的蒸氣老化測試。在可焊性的測試中，可焊性是用一 r -焊劑（r 一 f 1 u x )來測量的。 (3 )抗裂縫性本項測試是用來觀察裂縫在熱衝擊後的生成狀況。 PCTCpressure cooker test) ： 120 〇C/2 大氣壓/100% RH，TC(thermal cycle):在-65°C 和 150°C 低高溫來回變Page 21 517315 V. Description of the invention (17) DRAM device, an STS0P2 package, 2 "a type gold wire, LME type epoxy resin, a copper-based alloy lead frame, a thermoplastic wire chip ( (LOC) tape. ", (1) Wire bondability This test is used to evaluate the adhesion between the bond wire and the wire. The device for measuring the adhesion was SWB-100G manufactured by Samsung Technology Co., Ltd. of Korea. Until the wire is combined, the minimum and average force (gf) required for the combination to be separated from a joint is based on a vibration power of 80 ~ 100, a pressing force of 80 ~ 100, a time of 15 ~ 20, and a 7 〇_Capillary bottleneck, a 0.8 mi 1 gold wire. The term 叩 ^ used here refers to the number of samples with fully separated wire bonding parts based on the standard tension measurement δ formula. (2) Solderable electric money wire system is immersed in 2 3 5 ° The degree of contamination of the solder before or after bending the lead portion was measured 2 seconds later in the C liquid. After most leadframes are packaged, cracks usually occur when an external conductor portion is bent. Therefore, it is more meaningful to measure after bending than before bending. After heating at 2 7 5 ° C for 1 hour ', the steam aging test at 95 ° C and 8 hours can be performed. In the solderability test, solderability was measured using an r-flux (r-f 1 u x). (3) Crack resistance This test is used to observe the formation of cracks after thermal shock. PCTCpressure cooker test): 120 ℃ / 2 atmospheres / 100% RH, TC (thermal cycle): change back and forth between -65 ° C and 150 ° C at low and high temperatures

第22頁 517315 五、發明說明（18) 化超過1 0 0 0次的測試。 (4 )模塑黏著性一導線被拉至某一狀態，其中，導線架被模塑來測量負荷，藉用一設備（也就是UTM， Universal Test Machine )來測試模具和導線之間的黏著性。熱負荷狀態如下：儲存於175 °C/6小時，85 °C/85%RH，6小時，IR軟熔測試三次（預加熱溫度：2 2 0 °C，軟熔焊接溫度：2 4 0 °C ) (5 )抗腐蝕性評估方法：KSM 8012中性食鹽水喷灑方法；氯化納濃度： 40g/l; 壓力空氣的壓力：1.2kgf/cm2; 喷灑量：1. 51ml/80cni2/h; 蒸發器溫度：47 °C ;食鹽水塔溫度：3 5 °C ; 測試桶溫度:3 5 °C。在食鹽水狀態下腐蝕出現的程度是藉由中性食鹽水喷灑方法來進行，並以「無腐餘」、「輕微腐#」和「嚴重腐餘」來標示。 (下接表一、及表二）Page 22 517315 V. Description of the invention (18) Tests performed more than 100 times. (4) Molding Adhesiveness-A wire is pulled to a certain state, wherein the lead frame is molded to measure the load, and a device (that is, UTM, Universal Test Machine) is used to test the adhesion between the mold and the wire . The thermal load status is as follows: stored at 175 ° C / 6 hours, 85 ° C / 85% RH, 6 hours, IR reflow test three times (preheating temperature: 2 2 0 ° C, reflow soldering temperature: 2 4 0 ° C) (5) Evaluation method of corrosion resistance: spraying method of KSM 8012 neutral salt water; sodium chloride concentration: 40g / l; pressure of compressed air: 1.2kgf / cm2; spraying amount: 1. 51ml / 80cni2 / h; evaporator temperature: 47 ° C; saline tower temperature: 35 ° C; test barrel temperature: 35 ° C. The extent of corrosion in the saline solution was carried out by spraying with a neutral saline solution and marked with "no corrosion", "slightly rot #" and "severe rot". (Next to Tables 1 and 2)

第23頁 517315 五、發明說明（19) 抗裂縫性抗腐蝕性 EMC黏著性 9 I 導線結合性層疊結構 (微吋， ^m) 模塑時模塑後埒折前膂折後 M1N AVG OPEN 缺 S & μ m 72® wSl 翳趦馘藏 ¢1 函 600-1000 (TC cycles) i輕微腐蝕 36.1±0.7 32.6±2.9 50% 不濕(non-wet) 1.55 2.89 25/48 銀(1〆, 0.025//m) 钯(0.5//",0.0125//m) 鎳(25〆, 0.625//m) s m 超過 1000 (TC cycles) 無腐蝕 45.9±0.39 47.2±1.10 100% 97% 4.87 6.85 0/48 銀(3 Μ'0.075 "m) 1 SS(0.5unt 0.0125 μ m) 鎳(25//",0.625 em) 實例2 超過 1000 (TC cycles) 無腐蝕 50.9±0.39 48.1±0.31 100% 98% 5.28 7.12 0/48 Μ(8β'\ 0.2um) 裔2(0.5 私"，0.0125 从 m) 鎳(25 μ ",0.625 μ m) 實例3 超過 1000 (TC cycles) 無腐蝕 47.9 土 0.7 45.1±0.4 100% 98% 6.32 7.12 0/48 m(7u\ 0.175/zm) 鈀(0.3 A ",0.0075//m) 鎳(25//"，0.625//m) 實例4 超過 1000 (TC cycles) 無腐蝕 49.7±2.01 47.5+1.2 1 100% 98% 5.84 6.89 0/48 m m m "to 〇 OO y1 to ^ 一 - -= O S § K § I 實例5 所W斟線架底部金屬皆爲銅(Cu)Page 23 517315 V. Description of the invention (19) Crack resistance and corrosion resistance EMC adhesion 9 I Wire bonding laminated structure (micro-inch, ^ m) M1N AVG OPEN after folding before molding S & μ m 72® wSl ¢ 藏 ¢ 1 Letter 600-1000 (TC cycles) i Slight corrosion 36.1 ± 0.7 32.6 ± 2.9 50% non-wet 1.55 2.89 25/48 silver (1〆, 0.025 // m) Palladium (0.5 / ", 0.0125 // m) Nickel (25〆, 0.625 // m) sm Over 1000 (TC cycles) Non-corrosive 45.9 ± 0.39 47.2 ± 1.10 100% 97% 4.87 6.85 0 / 48 silver (3 μ'0.075 " m) 1 SS (0.5unt 0.0125 μm) nickel (25 // ", 0.625 em) Example 2 more than 1000 (TC cycles) no corrosion 50.9 ± 0.39 48.1 ± 0.31 100% 98% 5.28 7.12 0/48 M (8β '\ 0.2um) 2 (0.5 private ", 0.0125 from m) nickel (25 μ ", 0.625 μm) Example 3 more than 1000 (TC cycles) non-corrosive 47.9 soil 0.7 45.1 ± 0.4 100% 98% 6.32 7.12 0/48 m (7u \ 0.175 / zm) Palladium (0.3 A ", 0.0075 // m) Nickel (25 // ", 0.625 // m) Example 4 Over 1000 (TC cycles) no corrosion 49.7 ± 2.01 47.5 + 1.2 1 100% 98% 5.84 6.89 0/48 mmm " to 〇OO y1 to ^ I--= O S § K § I Example 5 The bottom of the W wire rack is copper (Cu)

第24頁 517315 五、發明說明（20) liii 抗裂縫性抗腐蝕性 EMC黏著性 5·^ 導線結合性一一......1. 1 層疊結構 (微吋， //m) 模塑時役塑後彎折前彎折後 _ AVG OPEN B铒铖 — to W _ _ 藏 r-J! r-Jti 6¾ pSJ m m m _ 藏〜600 (TC cycles) 輕微腐蝕 30.6±0.61 27.0±2.96 80% 〒®(non-wct) ! ! ! 鈀(4//",0.1 ;zm) 鎳(25〆，0.625/zm) 比較實例1 ~ 600 (TC cycles) 輕微腐蝕 I j 60% 不 M(non-wet) 14/48 S2(0.2/zn, 0.005 μ m) 鎳(25 #",0.625/zm) 比較實例2 ~ 600 (TC cycles) 嚴重腐蝕 f J 不濕(non-wet) OPEN 銀(5/Λ 0.125 _ 鎳(25〆）比較實例3 -600 (TC cycles) 輕微腐蝕 36.2±0.52 32.5±0.69 95-99% 60% 6.79 7.6 0/48 金(0.1 μ "，0.0025//m) 鈀(0.5〆，0.0125//m) 鎳(25#",〇.625/zm) 比較實例4 ~ 600 (TC cycles) 無腐蝕 28.2±0.36 15.510.31 99% 60% 1 6.89 7.25 0/48 金(0.4〆，0.01//m) 鈀(1.0〆，0.025//m) ί5ΐ(25μ"，α625/ζιη) 比較實例5 所饤妈線架底部金屬诗爲銅(Cu) muPage 24 517315 V. Description of the invention (20) liii Crack resistance Corrosion resistance EMC adhesion 5 · ^ Wire bonding properties one by one ... 1. 1 laminated structure (micro inch, // m) molding After the service, after plastic bending, before bending_ AVG OPEN B 铒铖 — to W _ _ Tibetan rJ! R-Jti 6¾ pSJ mmm _ Tibetan ~ 600 (TC cycles) Slightly corroded 30.6 ± 0.61 27.0 ± 2.96 80% 〒® (non-wct)!!! Palladium (4 // ",0.1; zm) Nickel (25〆, 0.625 / zm) Comparative Example 1 ~ 600 (TC cycles) Slightly corrosive I j 60% Not M (non-wet ) 14/48 S2 (0.2 / zn, 0.005 μm) Nickel (25 # ", 0.625 / zm) Comparative Example 2 ~ 600 (TC cycles) Severe corrosion f J non-wet OPEN silver (5 / Λ 0.125 _ Nickel (25〆) Comparative Example 3 -600 (TC cycles) Mild corrosion 36.2 ± 0.52 32.5 ± 0.69 95-99% 60% 6.79 7.6 0/48 Gold (0.1 μ ", 0.0025 // m) Palladium ( 0.5〆, 0.0125 // m) Nickel (25 # ", 〇.625 / zm) Comparative Example 4 ~ 600 (TC cycles) Non-corrosive 28.2 ± 0.36 15.510.31 99% 60% 1 6.89 7.25 0/48 Gold ( 0.4〆, 0.01 // m) Palladium (1.0〆, 0.025 // m) ΐ525 (25μ ", α625 / ζιη) Comparative Example 5 Metal poem at the bottom of the aunt wire rack For copper (Cu) mu

第25頁 517315 五、發明說明（21) 請參閱表一，當一由纪或纪合金細薄中間電鍍層形成於由鎳或鎳合金所製成的底部電鍍層和由銀或銀合金所製 _ 成的外部電鍍層之間時，鎳的氧化和擴散問題即可避免，因而得到較佳的結合性和可焊性。由於金屬本身可焊性的本質，即使在高溫的狀態下以及在焊接之後，外部電鍍層仍可表現出極佳的可焊性。請參閱表二，當一由把電鑛層形成於鎳電鍍層（比較實例1和2 )或當只有銀電鍍層細薄地形成為外部電鍍層（比較實例3 )時，底部電鍍層所受到的保護有限，因此容易受腐蝕。此外，鎳電鍍底層受到氧化或擴散入外部電鍍層因而在最外層形成一具耐火性的氧化物，而導致導線結合性 _ 和可焊性的惡化。在電鍍銀的實例中，卻是很難將銀電鍍在鎳電鍍層上。當鈀電鍍層和金電鍍層依序形成於鎳電鍍層上時（比較實例4和5 )，電鍍平面過於硬脆使得在彎折導線時，彎折部分的可焊性降低，但卻因為金外部電鍍層本身的性質而具有極佳的導線結合性。此外，因為環氧樹脂黏著性很弱，因此，在熱擴張和收縮的重覆進行下，導線結合部分卻產生了根部裂缝而影響了半導體產品長期可靠度。總而言之，由本創作實例1〜5所製成的導線架不會有被腐蝕的現象發生。那也就是說，該導線架具有極佳的抗 _ 腐蝕性。再者，本創作導線架的模塑黏著性極佳，幾乎等於無電鍍層的裸銅基片之模塑黏著性一般。而且，其抗裂缝性亦極佳。Page 25 517315 V. Description of the invention (21) Please refer to Table 1. When a thin intermediate plating layer of Yuki or Yuki alloy is formed on the bottom plating layer made of nickel or nickel alloy and made of silver or silver alloy When the external plating layer is formed, the problem of oxidation and diffusion of nickel can be avoided, so better bonding and solderability are obtained. Due to the nature of the solderability of the metal itself, the outer plating layer can exhibit excellent solderability even at high temperatures and after soldering. Please refer to Table 2. When the electroplating layer is formed on the nickel plating layer (Comparative Examples 1 and 2) or when only the silver plating layer is thinly formed as the outer plating layer (Comparative Example 3), the bottom plating layer is subjected to Limited protection and therefore susceptible to corrosion. In addition, the nickel plating bottom layer is oxidized or diffused into the outer plating layer, thereby forming a refractory oxide on the outermost layer, which leads to deterioration of wire bonding properties and solderability. In the case of silver plating, it is difficult to plate silver on a nickel plating layer. When the palladium plating layer and the gold plating layer were sequentially formed on the nickel plating layer (Comparative Examples 4 and 5), the plating plane was too hard and brittle, which caused the solderability of the bent portion to decrease when the wire was bent, but the The nature of the outer plating layer has excellent wire bonding properties. In addition, because epoxy resin has weak adhesion, under the repeated expansion and contraction of heat, root joint cracks occur in the wire bonding part, which affects the long-term reliability of semiconductor products. All in all, the leadframes made in this creative example 1 to 5 will not be corroded. That is to say, the lead frame is extremely resistant to corrosion. In addition, the lead adhesion of this creative lead frame is excellent, almost equal to that of bare copper substrate without electroplating layer. Moreover, its crack resistance is also excellent.

第26頁 517315 五、發明說明（22) 依據本發明的設計，貴金量可大幅地降低，因而可明顯於諸電鍍層的總厚度明顯變薄薄膜式的半導體封裝，因而可半導體封裝之目的。並且，由鍍層，因而可避免銀的游移現狀態下，亦可發揮極佳的抗氧銀電鍍層本身極佳的可焊性，善。而且，由於本創作極隹的因而可適用於具高可靠度的半惟以上所述者，僅為本發用來限定本發明實施之範圍。所作之均等變化與修飾，皆為，特先予以陳明。屬在預電鍍導線架上的使用地減少材料成本。再者，由，本創作之導線架可適用於達到多插腳的導線架和輕型於一銀電鍍層形成為外部電象發生，即使在高溫極熱的化和抗腐#性。此外，由於半導體封裝的可靠度得以改導線結合性和模塑黏著性，導體封裝上。明之較佳實施例而已，並非即凡依本發明申請專利範圍本發明申請專利範圍所含蓋Page 26 517315 V. Description of the invention (22) According to the design of the present invention, the amount of precious gold can be greatly reduced, so it can be clearly seen in the thin-film semiconductor package with the total thickness of the plating layers being significantly thinner, so that the purpose of semiconductor packaging can be achieved. . In addition, due to the plating layer, it is possible to avoid the migration of silver, and also to exert excellent anti-oxidation. The silver plating layer itself has excellent solderability, which is good. In addition, the present invention can be applied to semi-reliable devices with a high degree of reliability, but the above is only used to limit the scope of the present invention. All equal changes and modifications are made, and they are specifically acknowledged first. It is used on pre-plated leadframes to reduce material costs. Furthermore, from this, the lead frame of this creation can be applied to lead frames that achieve multiple pins and lightweight. A silver plating layer is formed for external image generation, even at high temperatures and extreme heat and corrosion resistance. In addition, the reliability of semiconductor packages has been improved due to wire bondability and mold adhesion, and conductor packages. This is only a preferred embodiment of the present invention, and is not meant to cover the scope of patent application according to the present invention.

第27頁 517315 圖式簡單說明 < 圖式之簡單說明 > 第 1 圖至第 4 圖係為習知半導體導線架的橫剖面圖第 5 圖係本發明半導體導線架之橫剖面圖〇第 6 A 圖至第 6 E 圖為本發明半導體導線架製作時用於電鍍過程中之調變電流的波形圖 0 第 7 圖係本發明導線架之平面圖〇 <圖式之元件對照說e |月〉 11 導線架底部 12 ... 底部電鍍層 13 底漆層 21 電鍍層 (銅合金層） 22 鎳底部電鍍層 23 鈀或鈀合金層 24 金電鍍層 31 金屬基片 32 底部電鍍層 33 中間電鍍層 3 4 外部電鍍層 41 金屬基片 42 鎳電鍍層 43 保護層 51 底部金屬層 52 底部電鍍層 53 中間電鍍層 54 外部電鍍層 71 内部導線 72 … 外部導線 74 模墊器Page 517315 Brief description of drawings < Simplified description of drawings > Figures 1 to 4 are cross-sectional views of a conventional semiconductor lead frame. Figure 5 is a cross-sectional view of a semiconductor lead frame of the present invention. 6A to 6E are waveform diagrams of the modulation current used in the electroplating process when the semiconductor lead frame of the present invention is manufactured. 0 FIG. 7 is a plan view of the lead frame of the present invention. Month> 11 bottom of lead frame 12 ... bottom plating layer 13 primer layer 21 plating layer (copper alloy layer) 22 nickel base plating layer 23 palladium or palladium alloy layer 24 gold plating layer 31 metal substrate 32 bottom plating layer 33 middle Plating layer 3 4 Outer plating layer 41 Metal substrate 42 Nickel plating layer 43 Protective layer 51 Bottom metal layer 52 Bottom plating layer 53 Intermediate plating layer 54 Outer electroplated layer 71 Inner conductor 72… Outer conductor 74 Die pad

第28頁Page 28

Claims

517315 六、申請專利範圍 1. 一種半導體封裝用之導線架，其中包括：一由銅、銅合金或鐵-鎳合金所製成之底部金屬層；一形成於底部金屬層的至少一表面上和由錄或錄合金所製成的底部電鍍層；一形成底部電鍍層上，且由鈀或鈀合金製成之厚度為 0 · 0 0 0 2 5〜0 · 1 // m ( 0 · 1〜4微吋）之中間電鍍層；以及，一形成中間電鍍層内，且由銀或銀合金所製成之厚度為 0 . 0 5〜0 . 7 5 // m ( 2〜3 0微吋）之外部電鍍層。 2. 如申請專利範圍第1項所述之導線架，其中鎳合金係由 80〜99.999 wt%的鎳和0.001〜20 wt%的石粦組成；I巴合金係由8 0〜9 9 . 9 9 9 w t %的鈀和0 . 0 0 1〜2 0 w t % 的由金、銀、釕、鎳和磷至少其中之一來組成；銀合金係由 8 0〜9 9 · 9 9 9 w t %的銀和0 · 0 0 1〜2 0 w t % 的由鈀、金、釕、鎳和鱗至少其中之一來組成。 3. —種半導體導線架，其中包括：一由銅、銅合金或鐵-錄合金所製成之底部金屬層；一形成於底部金屬層的至少一表面上和由鎳或鎳合金所製成的底部電鍍層；一形成底部電鍵層上，且由鈀或鈀合金製成之厚度為 0 · 0 0 0 2 5〜0 · 1 /z m ( 0 · 1〜4微吋）之中間電鑛層；以及，一形成中間電鍍層内，且由銀或銀合金所製成之厚度為 0 . 0 5〜0 . 7 5 // m ( 2〜3 0微吋）之外部電鍍層；其中，該中間電鍍層係由將調變式電流施於電鍍槽内而形成。517315 6. Scope of patent application 1. A lead frame for semiconductor packaging, comprising: a bottom metal layer made of copper, copper alloy or iron-nickel alloy; a formed on at least one surface of the bottom metal layer and A bottom plating layer made of a recording or recording alloy; one formed on the bottom plating layer and made of palladium or a palladium alloy with a thickness of 0 · 0 0 0 2 5 to 0 · 1 // m (0 · 1 to 4 microinches); and an intermediate electroplating layer formed in the intermediate electroplating layer and made of silver or a silver alloy with a thickness of 0.05 to 0.5 0.7 m (2 to 30 microinches) External plating. 2. The lead frame according to item 1 of the scope of patent application, wherein the nickel alloy is composed of 80 ~ 99.999 wt% of nickel and 0.001 ~ 20 wt% of stone gangue; the Iba alloy is composed of 80 ~ 99.9 9 9 wt% of palladium and 0.0 0 1 to 2 0 wt% are composed of at least one of gold, silver, ruthenium, nickel, and phosphorus; the silver alloy system consists of 80 to 9 9 · 9 9 9 wt% Of silver and 0. 0 0 1 to 2 0 wt% are composed of at least one of palladium, gold, ruthenium, nickel, and scale. 3. A semiconductor lead frame comprising: a bottom metal layer made of copper, a copper alloy or an iron-alloy; a formed on at least one surface of the bottom metal layer and made of nickel or a nickel alloy A bottom electroplating layer; an intermediate electrical ore layer formed on the bottom electric bond layer and made of palladium or a palladium alloy with a thickness of 0 · 0 0 0 2 5 to 0 · 1 / zm (0 · 1 to 4 microinches) And, an outer plating layer formed in the intermediate plating layer and made of silver or a silver alloy with a thickness of 0.05 to 0.75 // m (2 to 30 microinches); wherein, the The intermediate plating layer is formed by applying a modulation current to a plating bath.

第29頁 517315 六、申請專利範圍形成。 4. 如申請專利範圍第3項所述之導線架，其中，當底部電鍍層形成時，施於含有鎳或鎳合金的電鍍液中之調變式電流係具有頻帶1 00〜2 0 0 0 0 Hz，負載係數5〜80%，且平均電流密度為1 5〜3 5 A / d m 2 ; 當中間電鍍層形成時，施於含有鈀或鈀合金的電鍍液中之調變式電流係具有頻帶1 0 0〜 2 0 0 0 0 Hz，負載係數5〜45%，且平均電流密度為0. 1〜3A/ dm2 ; 當外部電鍍層形成時，施於含有銀或銀合金的電鍛液中之調變式電流係具有平均電流密度為1〜5 A / d m 2。 5. 如申請專利範圍第3項所述之導線架，其中鎳合金係由 80〜99.999 wt%的鎳和0.001〜20 wt%的填組成；纪合金係由80〜99. 999 wt%的I巴和0.001〜20 wt% 的由金、銀、釕、錄和填至少其中之一來組成；銀合金係由8 0〜 9 9. 9 9 9 wt%的銀和0. 0(Π〜20 wt% 的由鈀、金、釕、鎳和填至少其中之一來組成。 6. —種製造半導體封裝用的導線架之方法，其包括下列步驟： a) 提供一底部金屬層； b) 預處理底部金屬層； c) 於該底部金屬層上形成一由鎳或鎳合金所製成的底部電鍍層； d) 藉由將上述申請專利範圍第3項所得之結構浸沒入一含有鈀或鈀合金之電鍍槽内，並施以調變電流（頻帶為1000〜2000 Hz，負載係數duty cycle為5〜45%，對電Page 29 517315 6. The scope of patent application is formed. 4. The lead frame according to item 3 of the scope of patent application, wherein, when the bottom plating layer is formed, the modulating current applied to the plating solution containing nickel or a nickel alloy has a frequency band of 100 to 2000. 0 Hz, load factor 5 ~ 80%, and average current density of 15 ~ 3 5 A / dm 2; When the intermediate plating layer is formed, the modulating current applied to the plating solution containing palladium or palladium alloy has Band 1 0 ~ 2 0 0 0 0 Hz, load factor 5 ~ 45%, and average current density is 0.1 ~ 3A / dm2; when the external plating layer is formed, it is applied to an electro-forging solution containing silver or a silver alloy The modulating current has a mean current density of 1 to 5 A / dm 2. 999 wt% 的 I 5. Lead frame as described in the scope of application for patent No. 3, wherein the nickel alloy is composed of 80 ~ 99.999 wt% of nickel and 0.001 ~ 20 wt% of filler; Ji alloy is composed of 80 ~ 99. 999 wt% I 0 (Π〜20) Bar and 0.001 ~ 20 wt% are composed of at least one of gold, silver, ruthenium, recording and filling; silver alloy is composed of 8 0 ~ 9 9. 9 9 9 wt% silver and 0. 0 (Π ~ 20 wt% is composed of at least one of palladium, gold, ruthenium, nickel, and filler. 6. A method of manufacturing a lead frame for semiconductor packaging, including the following steps: a) providing a bottom metal layer; b) preliminarily Processing the bottom metal layer; c) forming a bottom plating layer made of nickel or a nickel alloy on the bottom metal layer; d) immersing the structure obtained in the above item 3 of the patent application by immersing a structure containing palladium or palladium In the alloy plating tank, a modulation current is applied (the frequency band is 1000 ~ 2000 Hz, the duty cycle is 5 ~ 45%.

第30頁 517315 六、申請專利範圍鍍槽而言，平均電流密度為0.1〜3A/dm2);以及， e)於中間電鍍層上形成一由銀或銀合金製成的外部電鍍，層。 7. 如申請專利範圍第6項所述之方法，其中，當進行底部 < 電鍍層形成的步驟時，施於含有鎳或鎳合金的電鍍液中之調變式電流係具有頻帶1 00〜2 0 0 0 0 Hz，負載係數5〜80% ，且平均電流密度為1 5〜3 5 A / d m 2 ; 當進行中間電鍍層形成之步驟時，施於含有鈀或鈀合金的電鍍液中之調變式電流係具有頻帶1 00〜2 0 0 0 0 Hz，負載係數5〜45%，且平均電流密度為(K 1〜3A/dm2 ;當進行外部電鍍層形成之步驟時，施於含有銀或銀合金的電鍍液中之調變式電流係具· 有平均電流密度為卜5A/dm2。 8. 如申請專利範圍第6項所述之方法，其中鎳合金係由8 0〜 99.999 wt%的錄和0.001〜20 wt%的填組成，並依上述申請專利範圍第6項中步驟（c) 於底部金屬層上形成一由鎳或鎳合金所製成的底部電鍍層；鈀合金係由80〜99. 999 w t %的鈀和0 . 0 0 1〜2 0 w t %的由金、銀、釕、鎳和磷至少其中之一組成，並依上述申請專利範圍第6項中步驟（d) 將導線架結構浸沒入一含有鈀或鈀合金之電鍍槽内，並’ 施以調變電流；又，前述銀合金係由8 0〜9 9 . 9 9 9 w t %的銀和0 . 0 0 1〜2 0 w t % 的由鈀、金、釕、鎳和磷至少其中之 _ 一組成，並依上述申請專利範圍第6項中步驟（e) 於中間電鍍層上形成一由銀或銀合金製成的外部電鍍層者。Page 30 517315 6. Scope of patent application For the plating bath, the average current density is 0.1 ~ 3A / dm2); and, e) forming an outer plating layer made of silver or silver alloy on the intermediate plating layer. 7. The method according to item 6 of the scope of patent application, wherein when the step of forming the bottom < electroplated layer is performed, the modulating current applied to a plating solution containing nickel or a nickel alloy has a frequency band of 100 to 2 0 0 0 0 Hz, load factor is 5 ~ 80%, and the average current density is 15 ~ 3 5 A / dm 2; when the step of forming an intermediate plating layer is performed, it is applied to a plating solution containing palladium or a palladium alloy The modulation current has a frequency band of 100 ~ 2 0 0 0 Hz, a load factor of 5 ~ 45%, and an average current density of (K 1 ~ 3A / dm2; when the step of forming an external plating layer is applied, Modulated current system in electroplating solution containing silver or silver alloy · The average current density is 5A / dm2. 8. The method described in item 6 of the scope of patent application, wherein the nickel alloy is from 80 to 99.999 wt% and 0.001 ~ 20 wt% of the filling composition, and according to step (c) in the above patent application range of step (c) on the bottom metal layer to form a bottom plating layer made of nickel or nickel alloy; palladium alloy It consists of 80 ~ 99.999 wt% of palladium and 0. 0 0 1 ~ 2 0 wt% of gold, silver, ruthenium, nickel and phosphorus at least It is composed of one of them, and the lead frame structure is immersed in an electroplating bath containing palladium or a palladium alloy according to step (d) in item 6 of the above-mentioned application patent scope, and a modulation current is applied; It is composed of 80 ~ 99.9% by weight of silver and 0.01 ~ 2 0% by weight of at least one of palladium, gold, ruthenium, nickel, and phosphorus. Step (e) of item 6 forms an outer plating layer made of silver or a silver alloy on the intermediate plating layer.

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