TW516182B

TW516182B - Manufacturing method of dual damascene structure

Info

Publication number: TW516182B
Application number: TW91101074A
Authority: TW
Inventors: Chao-Cheng Chen; Jen-Cheng Liu; Jyu-Horng Shieh
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2002-01-23
Filing date: 2002-01-23
Publication date: 2003-01-01

Abstract

A manufacturing method of dual damascene structure is provided. First, a first etch stop layer, a first dielectric layer, a second etch stop layer, a second dielectric layer and a hard mask layer are sequentially formed. Then, a contact hole is formed in the mask layer, second dielectric layer, second etch stop layer and first dielectric layer till exposing the first etch stop layer surface that corresponds to the conductive region. Second, a sacrificial protection layer is used to completely fill the contact hole. Then the etching recipe with etch selectivity between the mask layer and sacrificial protection layer smaller than one is chosen to selectively etch the mask layer and sacrificial protection layer till etching the sacrificial protection layer to a predetermined depth. Finally, the etching recipe with etch selectivity ratio between the mask layer and sacrificial protection layer larger than one is chosen to selectively etch the mask layer, second dielectric layer and sacrificial protection layer till exposing the second etch stop layer to form a trench. The sacrificial protection layer is removed to construct a dual damascene structure. An I-line photo resistor is used as the sacrificial layer, which can eliminate the conventional void issue, exactly prevent punch-through of the bottom etch stop layer and thus increase product yield.

Description

516182516182

本發明疋有關於半導體積體 · ICs) ^ Μ ^ ^ 守菔檟體電路（semiconductor )製耘技術，特別是有關於雙鑲嵌結構(dual damascene)的製作方沬，甘丁 y 層（b〇U〇m stop iaya)所造不/可料蝕穿底層蝕刻停止 « , - a _ . , y )所每成穿透（punch-through)問二接：形成犧牲保護層的過程中產生孔洞。夠的：積炎：=的積集度增力ϋ，使得晶片表面無法提供足 'y, ^ 乍所需的内連線，為了配合M0S元件尺寸縮 = 連線需*，兩層以上的金屬層設計，便逐 ίΪίί 積體電路所必須採用的方式，特別是一些功The present invention is related to semiconductor integrated circuits (ICs) ^ Μ ^ ^ manufacturing technology of semiconductor circuits, and in particular, it is related to the manufacturing method of dual damascene, Ganding y layer (b. U〇m stop iaya) can not be / can be etched through the underlying etch stop «,-a _., Y} The punch-through problem is connected: a hole is formed in the process of forming a sacrificial protective layer. Enough: Accumulation: The accumulation degree of = is increased, so that the chip surface cannot provide the required internal wiring. To meet the shrinkage of M0S component size = the wiring needs *, two or more layers of metal Layer design, which means that the integrated circuit must be used, especially some functions.

:Ϊ Ϊ的產’口，如微處理器，甚至需要四至五層的金屬二’ ί : ί Ϊ成微處理器内的各個元件間的連接。-般而二夕ί !内連線的製作，是在議的主體完成後才開口、此廷個製程，可被視為一個獨立的半導體製程。為了不讓第一&金屬Μ連線與第二層金屬㈣線直接 ί ^而發生短路’金屬内連線間必須以絕緣層也就是内金屬）丨電層（IMD)加以隔離。習知連接上、下兩層金屬内連線的方式主要是利用插塞，例如鎢插塞、鋁插塞等。: Ϊ Ϊ product's mouth, such as a microprocessor, even requires four to five layers of metal two 'ί: ί Ϊ to form the connection between the various components within the microprocessor. -Generally, the production of interconnects is opened after the main body of the discussion is completed. This process can be regarded as an independent semiconductor process. In order to prevent the short circuit between the first & metal M wire and the second metal wire directly, the metal inner wires must be separated by an insulating layer (ie, an inner metal) and an electrical layer (IMD). The conventional way to connect the upper and lower metal inner wires is to use plugs, such as tungsten plugs and aluminum plugs.

一，知的金屬内連線製程主要是先以微影程序以及蝕刻技術疋義出接觸通道，然後在接觸通道表面先形成一阻障層’以增加後續填入之金屬層與溝渠的内金屬介電層之間的附著力；之後，再以鎢回蝕刻法在溝渠内填入金屬鎢，然後，於上述所形成之結構表面沉積一隔離用的氮化鈦層’最後’再沉積一銘銅合金於其表面，然後再以反應性離子蝕刻法加以定義，完成由鎢插栓所構成，用來連接上First, the known metal interconnection process mainly uses the lithography process and etching technology to define the contact channel, and then forms a barrier layer on the surface of the contact channel to increase the metal layer and the inner metal of the trench. Adhesion between the dielectric layers; after that, tungsten is filled into the trench by tungsten etch-back, and then a titanium nitride layer for isolation is deposited on the surface of the structure formed above, and finally a deposit is made. The copper alloy is on its surface, and then it is defined by reactive ion etching. It is composed of tungsten plugs and is used for connection.

516182 五、發明說明（2) 办金屬内連線之雙溝渠連接通道。然而， c’習知的金屬内連線製程已無法適；缺點。：:=)線的寬出= 外在線宽尺寸低於〇· 25//ΙΠ的半導初， 2導電性較佳的銅作為金屬内連線的材料導，體以\= =為= = 尚必須提供-10…材料作= 低。日可將冋性此微電子凡件的RC-延遲效應降到最 2參照第1圖，其為習知技術形成之雙鑲嵌結構剖面該結構在填入銅金屬以及施以銅金屬平坦化之後成銅金屬内連線。 7 形成上述第1圖的步驟為，在形成有導電區域丨2(例如内連線）的半導體基底丨〇上依序形成一蝕刻停止層丨4、介電層16、蝕刻停止層18、介電層2〇、防反射遮蔽層22，然後利用傳統的微影技術以及選擇性蝕刻上述防反射遮蔽層22、介電層20、蝕刻停止層18、介電層16直到露出上述钱刻停止層14為止，以形成接觸孔24。接著，利用旋塗 (spin coating)的方式在上述接觸孔24填入例如伸芳香基醚類聚合物（p〇ly(arylene ether) p〇lymer)，具體例 $ Schumacher公司所製造的PAE — 2或是A1Ued Signal公司所製造的FLARE、H0SP、L0SP等有機聚合物材料，以當作後續蝕刻步驟的犧牲保護層26，來避免上述底層蝕刻停止層 14受損。第6頁 516182 五、發明說明（3) 然而’接觸孔24的尺寸已逐漸縮小至〇· 3 # m 以下，並且上述當作犧牲保護層26的傳統有機材^ ”黏度及填入均一度不佳的特性，所以容易產機生材如枓， ===的孔洞（void)30，此將使得犧牲保護層26在槽蚀刻的過程之保護效果大受影響。 h集有鑑於上述習知技術的問題，本發明的目516182 V. Description of the invention (2) Double-ditch connection channel for metal interconnection. However, the conventional metal interconnection process of c 'has been unsuitable; disadvantages. ：: =) the width of the line = the semiconducting element whose outer line width is less than 0.25 // IIΠ, 2 the copper with better conductivity is used as the material guide of the metal interconnect, and the body is ===== -10 ... Materials must be provided = low. Japan can reduce the RC-delay effect of this microelectronic component to the lowest. Refer to Figure 1, which is a cross-section of a dual damascene structure formed by conventional technology. This structure is filled with copper metal and flattened with copper metal. Into copper metal interconnects. 7 The step of forming the above-mentioned FIG. 1 is to sequentially form an etch stop layer on the semiconductor substrate formed with the conductive region, such as an interconnect, and the dielectric layer, the etch stop layer, and the dielectric layer. The electric layer 20 and the anti-reflection shielding layer 22, and then the conventional anti-reflection shielding layer 22, the dielectric layer 20, the etch stop layer 18, and the dielectric layer 16 are selectively etched by using conventional lithography technology until the above-mentioned money stop layer is exposed. 14 to form a contact hole 24. Next, the above-mentioned contact hole 24 is filled with a spin coating method, for example, a polymer such as poly (arylene ether) polymer. A specific example is PAE-2 manufactured by Schumacher. Or FLARE, HOSP, LOSP and other organic polymer materials manufactured by A1Ued Signal Company are used as the sacrificial protection layer 26 in the subsequent etching step to prevent the above-mentioned bottom etching stop layer 14 from being damaged. Page 6 516182 V. Description of the invention (3) However, the size of the contact hole 24 has gradually been reduced to below 0.3 m, and the above-mentioned conventional organic material used as the sacrificial protective layer 26 has a viscosity and a uniform filling degree. With good characteristics, it is easy to produce organic raw materials such as 枓, === voids 30, which will greatly affect the protection effect of the sacrificial protection layer 26 in the process of trench etching. Problem of the present invention

嵌；構的製作方法，採用卜1-光阻材料當S 孔二i，： ί其具有極佳的填溝能力，能夠消除習知的，確實防止底層㈣停止層錢穿，$而提高產根據上述目的，本發明提供一種雙鑲嵌結構的法，適用於具有導電區域的半導體基底，步驟包括在上述半導體基底上依序形成一第一蝕刻二 5層：第二崎止層、第二介電層以及一硬：罩二了；觸孔於上述硬遮罩層、第二介電層、第二蝕止層及第一介電層之中，直到露出第一蝕刻停止層. 1用=:上述接觸孔中填滿i_line光阻材料；接；來使二：上述硬遮罩層與上述i-be光阻材料钱刻選擇比光阻材料的選擇性蝕刻上述硬遮罩層及上述卜Hne 使用對上述第二介電層以及上述硬遮罩層與：二=光 m刻選擇比值大於一的方式，選擇性餘刻上述硬遮第I飩ΐ二介電層及上述卜1ine光阻材料，直到露出上述一划钕止層，以形成一溝槽，而構成雙鑲嵌結構。 0503-6497TW;TSMC20〇l-〇i55；dennis.ptd 第7頁五發明說明（4) 上述雙鑲嵌結構的製作方内卜line光阻材料的步驟。;二更包括去除上述接觸孔刻停止層為氮化矽或氮氧化矽層弟-蝕刻#止層及第二蝕一介電層為二氧化矽。㈢。且上述第一介電層及第再者，上述第二介電芦声為氮氧化石夕或有機底部防曰反射層上形成之硬遮罩層，例如以光=為二雙==製作方刻上述溝槽係層係同時進行。 *上途光阻層與去除上述犧牲保護Fabrication method, using Bu 1-Photoresistive material as S hole II: It has excellent trench filling ability, can eliminate the conventional, and indeed prevents the bottom layer from stopping the layer of money to pass through, increasing production. According to the above object, the present invention provides a method of a dual damascene structure, which is suitable for a semiconductor substrate having a conductive region. The steps include sequentially forming a first etched layer and a five-layered layer on the semiconductor substrate: a second etch stop layer, a second dielectric layer. Electrical layer and one hard: cover two; contact holes in the hard mask layer, the second dielectric layer, the second etch stop layer and the first dielectric layer until the first etch stop layer is exposed. 1 用 = : The above contact hole is filled with i_line photoresist material; then, to make the second: the hard mask layer and the i-be photoresist material are selectively etched into the hard mask layer and the substrate by selective etching than the photoresist material. Hne uses the above-mentioned second dielectric layer and the above-mentioned hard mask layer with: two = photo m engraving selection ratio is greater than one, selectively engraving the above-mentioned hard-shielding second dielectric layer and the above-mentioned photo resist Material until the above-mentioned scratched neodymium stop layer is exposed to form a trench, Constituting the dual damascene structure. 0503-6497TW; TSMC200-l-ii55; dennis.ptd page 7 5 Description of the invention (4) The steps of manufacturing the photoresistive material in the dual-mosaic structure. Secondly, it includes removing the contact hole, the etching stop layer is a silicon nitride or silicon oxynitride layer, an etching stop layer and a second etch, and a dielectric layer is silicon dioxide. Alas. In addition, the first dielectric layer and the second dielectric layer are a hard masking layer formed on an oxynitride stone or an organic bottom anti-reflection layer, for example, light = two pairs == production method The engraving of the trench-based layer is performed simultaneously. * Upward photoresist layer and removal of the aforementioned sacrificial protection

懂，ίΪ本發明之上述目㈤、特徵、和優點能更明顯易寺舉一較佳實施例，並配合所附圖式，作詳細說明如下·· 圖式簡單說明一第1圖為習知用以填入銅内連線之雙鑲嵌結構的剖面示意圖。第2 a〜第2 f圖為根據本發明實施例之雙銀嵌結構的製程剖面示意圖。第3a〜第3f圖為根據本發明另一實施例之雙鑲嵌結構的製程剖面示意圖。Understand that the above-mentioned objectives, features, and advantages of the present invention can be more obvious. Yi Si will give a preferred embodiment with the accompanying drawings, which will be described in detail as follows. The drawings are briefly explained. The first picture is conventional. A schematic cross-sectional view of a dual damascene structure used to fill copper interconnects. Figures 2a to 2f are schematic cross-sectional views of the manufacturing process of the dual-silver embedded structure according to the embodiment of the present invention. Figures 3a to 3f are schematic cross-sectional views of the manufacturing process of a dual mosaic structure according to another embodiment of the present invention.

[符號說明] 100〜半導體（矽）基底； 1 0 2〜導電區域； 1 0 4、1 0 8〜蝕刻停止層； 1 0 6、11 0〜金屬間介電層；[Symbol description] 100 ~ semiconductor (silicon) substrate; 102 ~ conducting area; 104, 108 ~ etch stop layer; 106, 110 ~ intermetal dielectric layer;

0503-6497TWF;TSMC2001-0155;dennis.ptd 第8頁 5161820503-6497TWF; TSMC2001-0155; dennis.ptd p. 8 516182

11 2〜防反射遮蔽層； 11 3〜接觸孔； 11 4、11 4 a〜犧牲保護層； 11 6〜溝槽餘刻用光阻圖案； 1 2 0〜溝槽。實施例以下利用第2 a〜第2 f圖所示之雙鑲嵌結構的製程圖’以更詳細地說明本發明之第一實施例。百先，請參照第2a圖，形成該剖面圖的步驟為，在 :有導電區域1〇2(例如銅内連線）的半導體基底1〇〇上依^ 形成第一蝕刻停止層1〇4、第一介電層1〇6、第二蝕刻停止層1 〇8、第二介電層丨丨〇、硬遮罩層丨丨2，然後利用傳統的微影技術以及選擇性蝕刻上述硬遮罩層112、第二介電層 110、第二蝕刻停止層108、第一介電層1〇6直到露出上述第一蝕刻停止層1 04為止，以形成接觸孔丨丨3。例如，首先於上述硬遮罩層112上塗佈一層正光阻，透過一光罩在^人I成接觸孔的位置對該正型光阻層進行曝光、顯影，以形成一光阻罩幕。接著’使用上述光阻罩幕當作遮蔽物，蝕刻上述硬遮罩，112、上述第二介電層11〇、第二蝕刻停止層108及第 =介電層106直到露出第一蝕刻停止層1〇4為止，以在上述導電區域相對位置上形成一接觸孔11 3。接著’利用旋塗（spin coating)的方式在上述接觸孔 113填入i-Une光阻材料114，接著以適當的溫度進行預烘11 2 ~ anti-reflection shielding layer; 11 3 ~ contact hole; 11 4, 11 4 a ~ sacrificial protection layer; 11 6 ~ photoresist pattern for trench remaining; 1 2 0 ~ trench. EXAMPLES The first embodiment of the present invention will be described in more detail using the process chart of the dual mosaic structure shown in Figs. 2a to 2f. Baixian, please refer to FIG. 2a. The step of forming the cross-sectional view is to form a first etch stop layer 104 on a semiconductor substrate 100 having a conductive region 102 (such as a copper interconnect). , The first dielectric layer 106, the second etch stop layer 108, the second dielectric layer 丨丨 0, the hard mask layer 丨丨 2, and then the conventional lithography technique and selective etching of the hard mask are used. The cap layer 112, the second dielectric layer 110, the second etch stop layer 108, and the first dielectric layer 106 are exposed until the first etch stop layer 104 is exposed to form a contact hole 3. For example, a positive photoresist is first coated on the hard mask layer 112, and the positive photoresist layer is exposed and developed through a photomask at the position of the contact hole to form a photoresist mask. Next, using the photoresist mask as a mask, the hard mask is etched, 112, the second dielectric layer 110, the second etch stop layer 108, and the third dielectric layer 106 until the first etch stop layer is exposed. Up to 104, a contact hole 113 is formed at the relative position of the conductive region. Next ’is filled with i-Une photoresist material 114 into the contact hole 113 by spin coating, and then pre-baked at an appropriate temperature.

五、發明說明（6) 烤，以當作後續蝕刻步驟的犧牲保護層，來避免上述第一钱刻停止層1 〇 4受損。 ^上述介電層106、11 〇例如為化學氣相沈積法形成之二氧化矽層或其他低介電常數材料層，第一、第二蝕刻停止層104、108及硬遮罩層112係由氮化矽或氮氧矽化物構成。由於i-line光阻材料之低黏度等材料特質，適用於尺寸極小（例如小於〇 · 3 # m)的接觸孔。 • •接著，請參照第2b圖，回蝕刻（etching back)上述 1 - 1/ ne光阻材料11 4，以在整個接觸孔丨丨3内留下當作犧牲保護層114a，上述回蝕刻的方式利用壓力1〇〇mt〇rr/功率 50 0W/氧氣流量2〇sccm/氮氣流量1 〇 sccm之操作條件以進然後，請參照第2c圖，利用微影技術進行塗佈深紫外線（deep UV)光阻材料、曝光、顯影、烘烤等步驟，以形成溝槽蝕刻用的光阻圖案1丨6。其次，請參照刻罩幕，接著，使阻材料11 4 a之餘刻 11 2的被敍刻率，，率，來選擇性蝕刻 114a，直到上述i 一後。接著，請參考以及上述第二介電刻選擇比大於一的第2d圖，利用上述光阻圖案116當作蝕用對上述硬遮罩層112與上述I —nne光選擇比小於一的方式，即上述硬遮罩層 I於上述丨―丨丨…光阻材料114a的被钱刻硬遮罩層112與上述i-line光阻材料 1 i n e光阻材料11 4 a被敍刻一既定深度第2e圖，再以使用對上述硬遮罩層丨12 層110與上述1-1 ine光阻材料η 4a之蝕方式，即上述光阻材料11 4a的被蝕刻 516182 五、發明說明（7) 率’比上述述硬遮罩層112以及上述第二介電層110的被蝕刻率大；擇選性钱刻上述硬遮罩層丨丨2、第二介電層丨丨〇及上述i-1 ine光阻材料114a，直到露出第二蝕刻停止層1〇8 ’形成溝槽1 2 0，其與接觸孔丨丨3構成雙鑲嵌結構。透過上述兩段式蝕刻選擇比不同之蝕刻，先以對 i-1 ine光阻114蝕刻性較強的蝕刻配方進行蝕刻，先蝕刻部份之i-line光阻114。接著，再使用對上述硬遮罩層112 以及第二介電層餘刻性較強的蝕刻配方進行蝕刻，直到露出第二钱刻停止層，藉此，不會於蝕刻過程中產生蝕刻不完全（突芽）的情況，而造成後續製程產生錯誤，因而導致 R-C開路的發生。緊接著，請參考第2f圖，以乾式及溼式清除方法同時去除上述光阻圖案116、硬遮罩層Η?及i-line光阻材料。後績還包括去除第一蝕刻停止層1〇4以露出導電區域1〇2表面’以及填入銅等金屬以形成内連線的步驟，在此不予明。以下利用第3a〜第3f圖所示之雙鑲嵌結構的製程剖面圖’以更詳細地說明本發明之第二實施例。首先’請參照第3a圖，形成該剖面圖的步驟為，在形成有導電區域2 02(例如銅内連線）的半導體基底1〇〇上依^ 形成一蝕刻停止層1〇4、一介電層2〇6、一硬遮罩層212，然後利用傳統的微影技術以及選擇性蝕刻上述硬遮罩層 212、介電層206直到露出上述蝕刻停止層2〇4為止，以曰形成接觸孔2 1 3。例如，首先，於上述硬遮罩層2丨2上塗佈二V. Description of the invention (6) Baking is used as a sacrificial protective layer for subsequent etching steps to avoid damage to the above-mentioned first etch stop layer 104. ^ The dielectric layers 106 and 11 are, for example, silicon dioxide layers or other low dielectric constant material layers formed by chemical vapor deposition. The first and second etch stop layers 104 and 108 and the hard mask layer 112 are formed by Composed of silicon nitride or oxynitride. Due to the low viscosity of i-line photoresist materials and other material characteristics, it is suitable for contact holes with extremely small size (for example, less than 0.3 m). • Next, please refer to Figure 2b, etching back the above 1-1 / ne photoresist material 11 4 to leave the entire contact hole 丨 3 as a sacrificial protective layer 114a. The method uses the operating conditions of pressure 100 mt rr / power 50 0 W / oxygen flow rate 20 sccm / nitrogen flow rate 10 sccm. Then, please refer to Figure 2c and apply lithography to apply deep UV (deep UV ) Photoresist material, exposure, development, baking and other steps to form a photoresist pattern 1 6 for trench etching. Secondly, please refer to the engraving mask, and then use the etched rate of the resist material 11 4 a and the etch rate of 11 2 to selectively etch 114 a until i is above. Next, please refer to the 2d diagram of the second dielectric etching selection ratio greater than one, and use the photoresist pattern 116 as an etching method to select the hard mask layer 112 and the I-nne light selection ratio less than one. That is, the hard mask layer I is engraved with the hard mask layer 112 of the photoresist material 114a and the i-line photoresist material 1 ine photoresist material 11 4 a. Figure 2e, and then use the above-mentioned hard mask layer 丨 12 layer 110 and the 1-1 ine photoresist material η 4a etching method, that is, the photoresist material 11 4a is etched 516182 5. Description of the invention (7) rate 'Large than the above-mentioned hard mask layer 112 and the second dielectric layer 110 are etched; the optional hard mask layer 丨丨 2, the second dielectric layer 丨丨 and the above i-1 ine photoresist material 114a until the second etch stop layer 108 is exposed to form a trench 1220, which forms a dual damascene structure with the contact hole 丨 3. Through the above-mentioned two-stage etching selection ratios, the i-1 ine photoresist 114 is etched with a strong etching formula, and the i-line photoresist 114 is etched first. Next, the hard mask layer 112 and the second dielectric layer are etched with a strong etch resistance until the second stop layer is exposed, thereby preventing incomplete etching during the etching process. (Burr), which causes errors in subsequent processes, which leads to RC open circuit. Next, please refer to FIG. 2f, and remove both the photoresist pattern 116, the hard mask layer Η, and the i-line photoresist material by dry and wet methods. The later results also include the steps of removing the first etch stop layer 104 to expose the surface 102 of the conductive region ', and filling metal such as copper to form interconnects, which are not described here. The second embodiment of the present invention will be described in more detail below using the process cross-sectional views of the dual mosaic structure shown in Figs. 3a to 3f. First, please refer to FIG. 3a. The step of forming the cross-sectional view is to form an etch stop layer 104 and a dielectric layer on the semiconductor substrate 100 on which a conductive region 202 (such as a copper interconnect) is formed. Electrical layer 206, a hard mask layer 212, and then using conventional lithography techniques and selective etching of the hard mask layer 212 and the dielectric layer 206 until the etching stop layer 204 is exposed to form a contact Hole 2 1 3. For example, first, apply two layers on the hard mask layer 2 丨 2.

516182 五、發明說明（8) -- 層正光阻’透過一光罩在欲形成接觸孔的位置對該正型光阻層進行曝光、顯影，以形成一光阻罩幕。接著’使用上述光阻罩幕當作遮蔽物，蝕刻上述硬遮罩層212、上述介電層206，直到露出上述餘刻停止層2〇4 為止’以在上述導電區域相對位置上形成一接觸孔2丨3。接著，利用旋塗（spirl coating)的方式在上述接觸孔 1 3填入i 1 i n e光阻材料2 1 4，接著以適當的溫度進行預烘烤，以當作後續蝕刻步驟的犧牲保護層，來避免上述蝕刻停止層2 0 4受損。上述介電層2 0 6例如為化學氣相沈積法形成之二氧化矽層或其他低介電常數材料層，上述蝕刻停止層2〇4及硬遮罩層2 1 2係由氮化矽或氮氧矽化物構成。由於丨—丨丨光阻材料之低黏度等材料特質，適用於尺寸極小（例如小於〇.3//m)的接觸孔。、接著，請參照第3b圖，回蝕刻（etching back)上述 i 1 i n e光阻材料2 1 4，以在整個接觸孔2 1 3内留下當作犧牲保護層214a，上述回蝕刻的方式利用壓力1〇〇mt〇rr/功率 50 0W/氧氣流i20sccm/氮氣流41〇sccm之操作條件以進行0 然後，請參照第3c圖，利用微影技術進行塗佈深紫外線（deep UV)光阻材料、曝光、顯影、烘烤等步驟，以形成溝槽蝕刻用的光阻圖案2 1 6。其次，請參照第3d圖，利用上述光阻圖案216當作蝕刻罩幕’接著，使用對上述硬遮罩層212與上述光516182 V. Description of the invention (8)-Layer positive photoresist 'Through a photomask, the positive photoresist layer is exposed and developed at the position where a contact hole is to be formed to form a photoresist mask. Then "use the photoresist mask as a shield, and etch the hard mask layer 212 and the dielectric layer 206 until the above-mentioned stop layer 204 is exposed" to form a contact at the relative position of the conductive region. Hole 2 丨 3. Then, the above-mentioned contact hole 1 3 is filled with i 1 ine photoresist material 2 1 4 by a spin coating method, and then pre-baked at an appropriate temperature to be used as a sacrificial protective layer in a subsequent etching step. In order to prevent the above-mentioned etch stop layer 2 0 4 from being damaged. The dielectric layer 206 is, for example, a silicon dioxide layer or other low dielectric constant material layer formed by a chemical vapor deposition method. The etch stop layer 204 and the hard mask layer 2 1 2 are made of silicon nitride or Nitroxide composition. Due to the low viscosity and other material characteristics of photoresist materials, it is suitable for contact holes with extremely small size (for example, less than 0.3 // m). Next, referring to FIG. 3b, the above i 1 ine photoresist material 2 1 4 is etched back to leave the entire contact hole 2 1 3 as a sacrificial protective layer 214a. The above etch back method is used Operating conditions for pressure 100m rr / power 50 0W / oxygen flow i20sccm / nitrogen flow 41 ° sccm to perform 0. Then, please refer to Figure 3c and apply lithography to apply deep UV photoresist Material, exposure, development, baking and other steps to form a photoresist pattern 2 1 6 for trench etching. Next, referring to FIG. 3d, the photoresist pattern 216 is used as an etch mask '. Then, the hard mask layer 212 and the light are used.

516182 五、發明說明（9) 阻材料2 1 4 a之蝕刻選擇比小於一的方式，即上述硬遮罩層 212的被蝕刻率，小於上述卜line光阻材料214&的被蝕刻率’來選擇性蝕刻硬遮罩層212與上述i-iine光阻材料 $ 1 4 a，直到上述i — 1 i n e光阻材料2 1 4 a被餘刻一既定深度後。接著，請參考第3e圖，再以使用對上述硬遮罩層212 以及上述介電層20 6與上述1-1 ine光阻材料2 14a之蝕刻選擇比大於一的方式，即上述光阻材料214a的被蝕刻率，比上述述硬遮罩層212以及上述介電層2〇6的被蝕刻率大；擇選性蝕刻上述硬遮罩層212、介電層2〇6及上述卜Hne光阻 ^料214a，直到露出上述蝕刻停止層2〇4，形成溝槽22〇，其與接觸孔213構成雙鑲嵌結構。緊接著’言青參考第3f圖，以乾式及溼式清除方法圖案216、硬遮罩層212及卜—光阻材料：後，還包括去除蝕刻停止層2〇4以露以及填入銅等金屬以形成内連線的步驟，…予，發明採用卜11116光阻材料當作犧牲保護層，佳的填溝能力，能夠消除習知的孔洞問㉚，確實;方發明犧牲保護層係可為任何；。另外，本材料，並不限定用倒比之其他有機雖然本發明已以較佳實施例揭露如上，鈇复限定本發明，任何熟習此技藝者， :、二w非用以和範圍内，當可作些許之更動本發明之精神範圍當視後附之申請專利ίΠ::者匕本發明之保護第13頁 0503.6497TWF;TSMC2001-0155;dennis.ptd516182 V. Description of the invention (9) The etching selection ratio of the resist material 2 1 4 a is less than one, that is, the etching rate of the hard mask layer 212 is lower than the etching rate of the photo resist material 214 & The hard mask layer 212 and the i-iine photoresist material $ 1 4 a are selectively etched until the i — 1ine photoresist material 2 1 4 a is etched to a predetermined depth. Next, please refer to FIG. 3e, and then use the etching selection ratio of the hard mask layer 212, the dielectric layer 20 6 and the 1-1 ine photoresist material 2 14a greater than one, that is, the photoresist material The etching rate of 214a is greater than the etching rate of the hard mask layer 212 and the dielectric layer 206; the hard mask layer 212, the dielectric layer 206, and the Hne light are selectively etched. The resist material 214a is exposed until the above-mentioned etch stop layer 204 is exposed, and a trench 22 is formed, which forms a dual damascene structure with the contact hole 213. Immediately after referring to Figure 3f, the dry and wet removal method pattern 216, the hard mask layer 212, and the photoresist material are used: after that, the etching stop layer 204 is removed to expose the copper and fill it with copper, etc. The step of forming a metal interconnect with ..., I, invented the use of Bu 11116 photoresist material as a sacrificial protective layer, good trench filling ability, can eliminate the conventional hole problem, indeed; the invention of sacrificial protective layer can be any;. In addition, this material is not limited to use of other organic organic materials. Although the present invention has been disclosed in the preferred embodiment as above, the present invention is again limited. Anyone who is familiar with this art, should not use it within the scope. Some changes can be made to the spirit of the present invention as the attached patent: Π :: protection of the invention page 13 0503.6497TWF; TSMC2001-0155; dennis.ptd

Claims

516182516182

適用於具有導電區域六、申請專利範圍種雙鑲嵌結構的製作方法 1 . 的半導體基底，包括下列步介電在上述半導體基底上依^， Μ . 成、命宏成很序形成一钱刻停止層層以及一硬遮罩層； θ 形成一接觸孔於上述硬遮罩層、出對應導電區域之上述蝕刻停止層表面；曰 f路在整個上述接觸孔中填滿犧牲保護層；使用對上述介電層以及上述硬遮罩層與上述犧牲保護層蝕刻選擇比值大於一的方式，選擇性蝕刻上述硬遮罩層、上述介電層及上述犧牲保護層，直到上述介電層被蝕刻一既定深度，以形成一溝槽，去除接觸孔中之犧牲保護層而構成雙鑲嵌結構。 s 使用對上述硬遮罩層述犧牲保護層㈣選擇比值於的方式，選擇性蝕刻上述硬遮罩層及上述犧牲保護層，直到上述犧牲保護層被蝕刻一既定深度；以及 2 ·如申請專利範圍第1項所述的雙鑲嵌結構的製作方法，其中於形成上述接觸孔的步驟包括：於上述硬遮罩層上塗佈一層光阻；透過一光罩在欲形成接觸孔的位置對該光阻層進行曝光、顯影，以形成一光阻罩幕；使用上述光阻罩幕當作遮蔽物，蝕刻上述硬遮罩層、上述介電層直到露出上述蝕刻停止層為止，以在上述導電區域相對位置上形成一接觸孔；以及去除上述光阻罩幕。Suitable for semiconductor substrates with conductive areas 6. Patent application range for manufacturing dual-damascene structure 1. The semiconductor substrate includes the following steps: Dielectrics are formed on the semiconductor substrate as described above. Layer and a hard mask layer; θ forms a contact hole on the surface of the above-mentioned etching stop layer of the hard mask layer and corresponding conductive area; said F-way fills the entire sacrificial protection layer in the contact hole; The electrical layer and the etching selection ratio of the hard mask layer and the sacrificial protection layer are greater than one, and the hard mask layer, the dielectric layer, and the sacrificial protection layer are selectively etched until the dielectric layer is etched to a predetermined depth. In order to form a trench, the sacrificial protection layer in the contact hole is removed to form a dual damascene structure. s Select a ratio of the sacrificial protection layer to the hard mask layer to selectively etch the hard mask layer and the sacrificial protection layer until the sacrificial protection layer is etched to a predetermined depth; and The method of manufacturing a dual damascene structure according to item 1 in the scope, wherein the step of forming the contact hole includes: coating a layer of photoresist on the hard mask layer; and passing a photomask to the position where the contact hole is to be formed. The photoresist layer is exposed and developed to form a photoresist mask. Using the photoresist mask as a shield, the hard mask layer and the dielectric layer are etched until the etching stop layer is exposed to conduct the conductive film. A contact hole is formed at a relative position of the area; and the photoresist mask is removed.

0503-6497TWF;TSMC2001-0155;denn i s.p t d0503-6497TWF; TSMC2001-0155; denn i s.p t d

六、申請專利範圍法Λ 項所述的雙鑲嵌結構的製作方步驟:、、 *接觸孔内填滿犧牲保護層’包括下列 •以：面性塗覆犧牲保護層於上述硬遮罩層上及接觸孔内回蝕刻上述犧牲伴罐s y ^ 阻材料。犧牲保邊層，以形成填滿上述接觸孔的光法 4甘t申請專利範圍第j項所述的雙鑲嵌結其中上述餘刻停止層為氮氧化石夕所構成。心作方法 5甘t t :t專利？圍第1項所述的雙鑲嵌結構的製作太，、中上述蝕刻停止層為氮化矽所構成。法 6.如申專利範圍第！項所述的雙其中上述介電層為二氧化石夕所構成。㈣1作方法 m ϊ專利範圍第1項所述的雙鑲嵌結構的製作* 其中去除上述犧牲保護層時， #方遮罩層。才3^仃云除上述硬 8. 如申請專利範圍第i項所述的雙镶嵌法，其中上述犧牲保護層，係為i_line光阻材料的製作方 9. 一種雙鑲故結構的製作方法，適用於具的半導體基底，包括下列步驟：守电（^域在上述半導體基底上依序形成一第一蝕刻停止層、 ;介電層、第二蝕刻停止層、第二介電層以及一硬‘罩弟形成一接觸孔於上述硬遮罩層、第二介電層、第-蝕 /、、申請專利範圍刻停止層及第— 1蝕刻停止層表面電a之中，直到露出對應導電區域之第 5 t述接觸孔中填滿犧牲保護層；小於一的方述^遮罩層與上述犧牲保護層姓刻選擇比值層’直到上i犧=上述硬遮罩層及上述犧牲保護使用對上刻一既定深度；以及保護層蝕刻選擇比#二=s以及上述硬遮罩層與上述犧牲罩層、第」式，選擇性姓刻上述硬遮蝕刻停止;I，以幵:点一犧牲保護層，直到露出上述第二而構成雙鑲嵌結;i。—》槽’去除接觸孔中之犧牲保護層 3 ·如申凊專利範圍第9項所述的雙鑲嵌&構# 法，其中於形成上述接觸孔的步驟包括鐶“構的製作方於上述硬遮罩層上塗佈一層光阻；透過一光罩在欲形成接觸孔光、顯影，以形成一光阻罩幕；對该先阻層進行曝使用上述光阻罩幕當作遮蔽上述第二介電層、上述第二蝕 :亥]亡述硬遮罩層、露出第-㈣停止層為止，以在：述以：介電層直到形成一接觸孔；以及戍相對位置上去除上述光阻罩幕。 Π.如申請專利範圍第9項所述的雙鑲 :驟其中於整個上述接觸孔内填滿犧牲保護層:以 0503-6497TWF;TSMC2001-0155;dennis.ptd 第16胃六、申請專利範圍全面性塗覆犧牲保護層 :以及上述硬遮罩層上及接觸孔内回蝕刻上述犧牲保護層，阻材料。 x形成填滿上述接觸孔的光 1 2 ·如申凊專利範圍第g項法’其中上述第一及第二蝕刻二J ，結構的製作方 13.如申請專利範圍第9項化石夕所構成。法，其中上述第一及第_勒|以的雙鑲敢結構的製作方 Η.如申請專利/圍一第停止層為氮化石夕所構成。法，其中上述第一介電/及1所述的雙鑲嵌結構的製作方成。呆以層及苐二介電層為二氧化矽所構法，1i.中如麥申/專利範圍第9項所述的雙鑲嵌結構的製作方 ;罩:中去除上述犧牲保護層時，係同時進行去除如申請專利範圍第9，所述的雙镶嵌法，其中上述犧牲保護層，係為卜iine光阻材料。i作方 17· 一種雙鑲嵌結構的製作太、奋田私目女、曾；域的半導體基I，包括下列步作驟方法’適用於具有導電區層形成一接觸孔於上述硬刻停止層及第一介電層之中一餘刻停止層表面；一入ii述ί導體基底上依序形成一第一蝕刻停止層、第 η “ a 、第一蝕刻停止層、第二介電層以及一硬遮罩罩層、第二介電層、第二蝕直到露出對應導電區域之第 0503-6497TWF;TSMC2001-0i55;dennis.ptd $ 17頁 5161826. The manufacturing steps of the dual mosaic structure described in Item Λ of the Patent Application Scope Method: ,, * The contact hole is filled with a sacrificial protective layer 'including the following • To: surface coating the sacrificial protective layer on the above hard mask layer And the contact hole is etched back to the sacrifice companion material. The edge-protection layer is sacrificed to form the photo-filling method for filling the contact hole. The double-mosaic junction described in item j of the patent application scope, wherein the above-mentioned stop layer is composed of oxynitride. Mind making method 5 Gan t t: t patent? The fabrication of the dual damascene structure described in item 1 above is made of silicon nitride. Law 6. The scope of patent application as claimed! The pair of items described above, wherein the above-mentioned dielectric layer is composed of a dioxide. ㈣1 operation method m 制作 Fabrication of the dual mosaic structure described in item 1 of the patent scope * Where the above-mentioned sacrificial protective layer is removed, the # square mask layer. Only 3 ^ cloud in addition to the above-mentioned 8. The dual-mosaic method described in item i of the scope of the patent application, wherein the sacrificial protective layer is a producer of i_line photoresist material 9. A method of manufacturing a dual-mosaic structure, The semiconductor substrate is suitable for a semiconductor substrate, and includes the following steps: a gate-protection region sequentially forms a first etch stop layer, a dielectric layer, a second etch stop layer, a second dielectric layer, and a hard layer on the semiconductor substrate; 'The masker forms a contact hole in the surface of the hard mask layer, the second dielectric layer, the first-etched /, the patent-application etch stop layer, and the first etch stop layer until the corresponding conductive area is exposed. The contact hole in the fifth t is filled with a sacrificial protection layer; a masking layer smaller than one ^ the masking layer and the above-mentioned sacrificial protection layer are selected by the ratio of the ratio 'up to i sacrificial = the hard mask layer and the sacrificial protection described above. A predetermined depth is engraved; and the protective layer etching selection ratio # 二 = s and the above-mentioned hard mask layer and the sacrificial mask layer, the formula "" is used to selectively engraving the above-mentioned hard mask etching stop; I, to 幵: point one sacrifice Protective layer until exposed above Secondly, a double damascene junction is formed; i. "" Slots "to remove the sacrificial protective layer in the contact hole 3. The double damascene & structure method as described in item 9 of the patent application scope, wherein the step of forming the above contact hole The fabricator including the "structure" coats a layer of photoresist on the hard mask layer; through a photomask, the light to be formed in the contact hole is developed and developed to form a photoresist mask; and the pre-resistance layer is exposed and used. The photoresist mask is used to shield the above-mentioned second dielectric layer, the above-mentioned second etch: Hai] the hard-shielding layer, and the first stop layer is exposed, so as to describe: the dielectric layer until a contact hole is formed And remove the photoresist mask at the relative position. Π. Double inlay as described in item 9 of the scope of patent application: in which the entire sacrificial protection layer is filled in the entire contact hole: 0503-6497TWF; TSMC2001-0155 dennis.ptd Sixteenth stomach Six, the scope of the patent application is comprehensive application of the sacrificial protective layer: and the above sacrificial protective layer is etched back on the hard mask layer and in the contact hole to block the material. x forms the light that fills the contact hole. 1 2 · If the patent application scope item g Method 'where the above-mentioned first and second etching second J, the structure of the production side 13. The composition of the scope of the application for the patent No. 9 is composed of fossils. Method, where the above first and first_ Fang Yi. If the patent application / the first stop layer is composed of nitride stone. Method, where the dual dielectric structure described in the first dielectric / and 1 above is made. Die layer and second dielectric layer It is a silicon dioxide construction method, 1i. The manufacturer of the dual mosaic structure as described in Maishen / Patent Scope Item 9; when the sacrificial protective layer is removed in the cover: the removal is performed at the same time as in the patent application scope No. 9, In the dual-damascene method, the sacrificial protection layer is a iine photoresist material. i Zuofang 17. · The production of a dual-mosaic structure, Tai Fen Tian Mu, Zeng; semiconductor semiconductor I of the field, including the following steps. 'Applicable to the formation of a contact hole with a conductive region layer in the hard-etched stop layer. And a first stop layer surface among the first dielectric layers; a first etch stop layer, an η "a, a first etch stop layer, a second dielectric layer, and A hard mask layer, a second dielectric layer, and a second etch until 0503-6497TWF; TSMC2001-0i55; dennis.ptd $ 17 page 516182 corresponding to the conductive area exposed

使用對上述第卜line光卩且# —介電層以及上述硬遮罩層與上述先F材料蝕刻選擇比值大於一的方式，# s 露出上诚裳"苐一；|電層及上述光阻材料，直之· —！·，4 一蝕刻停止層，以形成一溝槽，去除接觸？[ j 1 lne光阻材料而構成雙鑲嵌結構。、女申明專利範圍第1 7項所述的雙镶方法，其中於形成上述接觸孔的步驟包括鑲，、、·。構的製作於上述硬遮罩層上塗佈一層光阻；透過一光罩在欲形成接觸孔的位光、顯影，以形成一光阻罩幕；…先阻層進行曝上述ί用幕當作遮蔽物，㈣上述硬遮罩層、第=π為一介電層直到露出 -接觸孔；，乂 u在上*導電區域相對位置上形成去除上述光阻罩幕。如/請專利範圍第17項所述的雙鑲嵌結構的製# 括下列步驟：丨何料，包全面性塗覆i -1 i ne光阻材料於上述硬Using the above-mentioned method, the # —dielectric layer, the hard mask layer, and the first F material etching selection ratio are greater than one, # s exposes Cheng Chengshang " 苐一; | Electric layer and the above light Resistive materials, straight away! ·, 4 An etch stop layer to form a trench and remove the contact? [j 1 lne photoresist material to form a dual damascene structure. The female stated that the method of double inlaying described in item 17 of the patent scope, wherein the step of forming the contact hole includes inlaying, .... A photoresist is coated on the hard mask layer; a light mask is used to develop light at the position where a contact hole is to be formed to develop a photoresist mask; ... the resist layer is first exposed to the above-mentioned curtain. As a shield, the above-mentioned hard mask layer is used, and π is a dielectric layer until the exposure-contact hole is exposed; and 乂 u is formed at a position opposite to the upper conductive region to remove the photoresist mask. The manufacturing of the dual mosaic structure described in item 17 of the patent scope includes the following steps: 丨 What material, including comprehensive coating of i -1 i ne photoresist material on the above-mentioned hard

M6182 六、申請專利範圍孔内；以及回Μ刻上述i —! i I 的光阻材料。line^阻材枓，以形成填滿上述接觸孔方法2Qm專^範㈣17項所料雙鑲嵌結構的製作，:中上述第一蝕刻停止層及氣作矽或氮氧化矽層。 j丨τ止層為虱化方牛21盆如由申請專利範圍第17項所述的雙鑲缺結構的製作 2，λλ述广/電層及第二介電層為二氧二方法，其中去^17/所述的雙镶#結構的製作上述硬遮罩；iine光阻材料時，係同時進行去除 23. 一種雙鑲嵌結構的製作方法，適用於具有導 =半導體基底，且上述雙❹結構的製作方法包括下列在上述半導體基底上依序形成一第一蝕刻停止芦、電層、第二蝕刻停止層、第二介電層以及一硬遮罩層，、、於上述硬遮罩層上塗佈一層光阻；在欲形成接觸孔的位置對該光阻層進行曝光、与，以形成一光阻罩幕；〜使用上述光阻罩幕當作遮蔽物，蝕刻上述硬遮罩層、上述第二介電層、第二蝕刻停止層及第一介電層直到露出第一触刻停止層為止，以在上述導電區域相對位置上形一接觸孔； / 0503-6497TWF;TSMC2001-0155;denn i s.p t d 第19頁 516182 六、申請專利範圍去除上述光阻罩幕在整個上述接觸孔令使用對上述硬遮罩層光，；以及比值小：一的方式，選擇性飼：料韻刻選擇直到上述光阻材述使用對上述第二介電層以及』既疋深度； i-Hne光阻材料餘刻選擇比值大於—的=層與上述上述硬遮罩層、第2介電上 ’式’選擇性蝕霞屮什筮9紅电曰及上迷1 — 1 1 ne光阻材+ 蚀刻刻停止層，以形成-溝槽；以ΐ直到構。稱成雙鑲嵌結 0503-6497TWF;TSMC2001-0155;dennis.ptd 第20頁M6182 VI. In the scope of patent application hole; and the photoresist material of i —! I I engraved above. Line ^ resist material 枓 to fill the above contact hole Method 2Qm Special ㈣㈣㈣㈣ 17 expected double-damascene structure, the above-mentioned first etch stop layer and gas as silicon or silicon oxynitride layer. The j 丨 τ stop layer is made of the double-insertion structure of the lobsterized square cattle 21 pot as described in item 17 of the scope of patent application2. The lambda / radio layer and the second dielectric layer are dioxin methods, where The above-mentioned hard mask is made by the ^ 17 / mentioned double inlay # structure; iine photoresist material is removed at the same time. 23. A method of making a double inlay structure is suitable for a semiconductor substrate with a semiconductor substrate, and The manufacturing method of the structure includes the following steps: sequentially forming a first etch stopper, an electric layer, a second etch stopper layer, a second dielectric layer, and a hard mask layer on the semiconductor substrate, and forming the hard mask layer on the semiconductor substrate; A layer of photoresist is applied on top; the photoresist layer is exposed at the position where the contact hole is to be formed to form a photoresist mask; ~ the above photoresist mask is used as a shield to etch the hard mask layer The second dielectric layer, the second etch stop layer, and the first dielectric layer are formed until a first contact stop layer is exposed, so as to form a contact hole at the relative position of the conductive region; / 0503-6497TWF; TSMC2001-0155 ; denn i sp td p.19 516182 2. The scope of the application for the patent removes the above photoresist mask curtain and uses the light on the hard mask layer in the entire contact hole; and the ratio is small: one way, selective feeding: the material is selected until the above photoresist material is used. The second dielectric layer and the "deep" depth; i-Hne photoresist material selection ratio greater than-= layer and the above-mentioned hard mask layer, the second dielectric 'type' selective etching on the second dielectric. 9 Hongdian said the above 1 — 1 1 ne photoresistive material + etching stop layer to form-trench; Weigh into double mosaic knots 0503-6497TWF; TSMC2001-0155; dennis.ptd page 20