TW512502B - Method for forming a wafer level chip scale package, and package formed thereby - Google Patents

Abstract

A layer of gold (405) is disposed on upper surfaces (225) of copper pillars (210) on a bumped wafer (205). Coating material (410) is then applied to a level which is less than the height of the copper pillars (210), and etchant is disposed to remove coating material on the layer of gold (405) and to remove coating material (410) adhering to side surfaces of the copper pillars (210). Solder deposits are then disposed on the gold layer and reflowed to form balls (405) on the ends of the copper pillars (210), with the copper pillars (210) protruding into the solder balls (405).

Description

五、發明說明（1) 【發明領域】 本發明係有關形成晶圓等級晶片 更特殊的是形成晶圓等級晶片尺度封:封裝之方法，且 研磨· 展之方法可避免機械 【發明背景】 基於微小半導體封裝之需要，目 供半導體積體電路或晶粒的封裝，圓等級之製程 晶圓等、級晶片A度封裝，所·製得的封裝t” 尺度封裝（W L - C S P )。 、。月之晶圓等級晶片 參考圖示1及2A-E，現在以一種㊂n楚 ^ 裝之製程1 〇〇來敘ϋ，以孰悉此項技H級晶片尺J封 蔣久i i 拉触雨Μ … 文藝人士所了解的製程 程100由105ρ1 ^路、和襯墊製造在晶圓205上，封裝製 ί 广：提供110晶圓2°5以金屬粒柱210形成 圖2_示晶圓m以金屬粒柱_成在 =佛蘭，施卡•唐（Francisca Tung)於2〇〇〇年朝Μ 曰=吳2利序號為，5 64382，名稱為，，供半導體晶 片改^粒柱連接與製造方法"且部分連續自佛蘭西施卡· 唐2 2 0 0 0年4月26日向美國申請，序 晶片改善粒柱連接與製造方法，，且本專 Ι;Γ=指定…此教示其至少有-些粒柱二 構之成明，延些專利併入供本案參考。 一種塗佈材料215,如模鑄化合物、封裝的環 脂、例如底填塗佈材料、或光成像材料、例如笨並環丁烯V. Description of the invention (1) [Field of the invention] The present invention relates to the formation of wafer-level wafers. More specifically, the method of forming wafer-level wafer-scale seals: packaging methods, and grinding and spreading methods can avoid machinery. [Background of the Invention] The requirements for tiny semiconductor packages are for semiconductor integrated circuit or die packaging, round-level process wafers, A-level package packaging, etc. The resulting package is a t ”-scale package (WL-CSP). The wafer-level wafer of the month refers to Figures 1 and 2A-E. Now it is described in a manufacturing process of ㊂nchu ^. In order to understand this technology, the H-level wafer ruler J seal Jiang Jiii pulls the rain. … The process 100 understood by the literary artists is made from 105ρ1, and pads on the wafer 205, and packaged. Wide: Provide 110 wafers 2 ° 5 to form metal grain columns 210. Figure 2_ shows the wafer m to Metal particle pillars_Cheng Zai = Flanders, Francisca Tung in 2000, M = Wu 2 Li, serial number is 5 64382, and the name is for semiconductor wafers. Method of manufacture " and part continuous from Francesca Sch. Don 2 2 0 0 0 0 The United States filed a sequential wafer to improve the particle column connection and manufacturing method, and this book 1; Γ = specified ... This teaches that it has at least some particle columns of two structures, and some patents are incorporated for reference in this case. Material 215, such as molding compound, encapsulated cyclic grease, such as underfill coating material, or photo-imaging material, such as benzocyclobutene

第5頁 512502 五、發明說明（2) ~'' U BCB)或聚亞胺，被施加115在晶片2〇5上，金屬粒柱21〇 以塗佈材料21 5覆蓋’如圖2B所示，塗佈材料層215以旋轉 塗佈製程塗佈；典型地，兩層塗佈材料各約塗佈4〇 — 5〇微 丨米（um)的厚度使塗佈材料的厚度約為1〇〇um，在金分子 丨層210的塗佈材料厚度應不大於i〇u m的厚度，塗佈材料層 丨215隨而予與熟化。 V S / 热化之後’在銅金屬粒柱210上的過量塗佈材料利用 丨- 機械研磨機（由美國的Okamoto e股份有限公司或英國的 \Page 5 512502 V. Description of the invention (2) ~ `` U BCB) or polyimine, is applied 115 on the wafer 205, and the metal particle column 21 is covered with the coating material 21 5 'as shown in FIG. 2B The coating material layer 215 is applied in a spin coating process; typically, the two layers of coating material are each coated with a thickness of about 40-50 micrometers (um) so that the thickness of the coating material is about 100. um, the thickness of the coating material in the gold molecule layer 210 should not be greater than the thickness of i0um, and the coating material layer 215 is then aged. V S / After heating ’, the excess coating material on the copper metal particle column 210 is utilized 丨-mechanical grinder (by Okamoto e Co., Ltd. in the United States or

Kemet國際有限公司製造）上的研磨化合物並使用孔隙性 拋光墊予與研磨12 0去除，研磨12 0持續至過量的塗佈材料 ·· 被去除’且銅金屬粒柱210上表面22〇被裸露，已研磨的晶 圓如圖2 C所示。 在上表面2 2 0被形成1 2 5第二層的金分子2 2 5，例如， 可用電鑛法如圖2D所示，且焊球23 0被連接130至金分子層 225’没備製造商包括οκΐ、Casio、Fujitsu，這些皆是日 本製造可用予焊球連接，晶圓等級晶片封裝製程1 〇 〇隨而 結束1 3 5 ’在製程1 〇 〇之後，已有凸起的晶圓2 3 5再做晶圓 荨級日日片尺度封裝的切單（s i ngu 1 at e) 〇 在研磨階段1 2 〇期間，此晶圓2 0 5將承受極度的機械性 壓力’所以在晶圓上會造成微小裂痕；因此，以機械研磨 · 作晶圓等級晶片尺度封裝的製程將因微小裂痕而潛有不利 於可靠度之因素，機械研磨另一不利因素是研磨過慢，尚 ^ 有一不利因素是需要投資研磨設備，且伴隨著研磨耗材之 供應。 i(Made by Kemet International Co., Ltd.) and use a porous polishing pad to remove the abrasive 12 0. The polishing 12 0 continues until the excess coating material is removed ... and the upper surface 22 of the copper metal particle column 210 is exposed. The polished wafer is shown in Figure 2C. On the upper surface 2 2 0 is formed a 1 2 5 second layer of gold molecules 2 2 5. For example, an electric ore method can be used as shown in FIG. 2D, and the solder ball 23 0 is connected 130 to the gold molecular layer 225 ′. Vendors include οκΐ, Casio, Fujitsu, which are all made in Japan and can be used for solder ball connection. The wafer-level wafer packaging process 1 00 will then end 1 3 5 'After the process 1 100, there are already raised wafers 2 3 5 and then do wafer-level daily-to-day-scale package singulation (si ngu 1 at e) 〇 During the grinding phase 1 2 〇, this wafer 2 0 5 will be subjected to extreme mechanical pressure 'so the wafer It will cause micro-cracks; therefore, the process of mechanical grinding and wafer-level wafer-scale packaging will potentially have a negative impact on reliability due to micro-cracks. Another disadvantage of mechanical grinding is that the grinding is too slow. The factor is the need to invest in grinding equipment, which is accompanied by the supply of grinding consumables. i

第6頁 M2502 五、發明說明 ! 蝕刻 刻去除過 且具有相 丨去除，使 因為 丨以附著在 i片尺度封 丨分子表面 i | 旋轉 丨作以製得 ;%的塗佈 轉塗佈仍 【發明簡 本發 藉此而形 問題。 據此 級晶片尺 (a) 提供 個墊體具 (b) 在金 (c) 在半 緣材料層 表面，其 (3) Ί 是替代研磨的另一方法，其中蝕刻劑被施加以蝕 多的塗佈材料層2 1 5，然而蝕刻仍是緩慢製程， 2多量的塗佈材料層21 5必須進一步的以化合物 得餘刻過程更為困難。 ； 僅有金分子層的上表面暴露，所以焊錫球23 0可 I. 金分子層面積受到限制；因此，有關晶圓等級晶 卜 裝有關可靠度之另一不利因素是焊球可附著在金 · 積受到限制。 ， · 塗佈製程過於緩慢，除此，必須兩個旋轉塗佈操 所要厚度之塗層，另外，此旋轉塗佈製程約有Μ φ 材料之廢棄物附著在晶圓2 0 5上；因此，使用旋 有一不利因素是既昂責且緩慢。 略概要】 明尋求一種方法供晶圓等級晶片尺度之封裝， 成封裝，它能克服並至少能減少上述習知^蓺的 个| π定提供 從々仏，,六成 度的半導體之封裝，這方法包含的步驟為； 一種半導體晶圓具有複數層墊體的表面， 有一金屬導體延伸遠離自表面的第一預定每 =體的自由端形成—層導電性抗餘 離、 導體晶圓的表面佈放電性絕緣 立’， 具有-"導體晶圓表面至第二預定距：：性絕 中第一預定距離是小於第一預定距離*暴露 %性絕 今12502 五、發明說明（4) \ 緣材料部分被佈放在傳導性抗蝕刻材料層上，且在側邊表 面至少有某些金屬性導體； | 丨（d)佈放在傳導性抗蝕刻材料層與在側邊的某些金屬性導 i j 體上的所有電性絕緣材料部份予與蝕刻去除； 在另一觀念，本發明提供一種晶圓等級晶片尺度之封 . :裝，其包含； ‘ | 一種半導體晶粒其表面具有複數層的墊體； 金屬性導體其偶合且延伸第一預定距離自複數的墊體； 在金屬導體的自由端有一抗蝕刻層； 丨一絕緣層在表面，此絕緣層具有一與表面有預定距離的暴 f 丨露表面，其中第二預定距離小於第一預定距離；且 可迴流焊材料附著到抗蝕刻層且至少有部分的侧表面 1實質上是金屬性導電體。 【圖示簡要說明】 丨 本發明的具體實施例將參考圖式作具體充分說明； 丨第1圖顯示一依據習知技藝之形成晶圓等級晶片尺度的封 裝的詳細製程流程圖； 第2A-E圖顯示依據圖1的製程所形成晶圓等級晶片尺度封 裝之橫切面側視圖； · 丨第3圖顯示依據本發明所形成晶圓等級晶片尺度之封裝的 丨 詳細製程之流程圖； · 第4A-E圖顯示依據圖3的製程所形成晶圓等級晶片尺度之 - ! 封裝的橫切面側視圖； 第5-7圖顯示在圖4C-E的形成晶圓等級晶片尺度封裝的部Page 6 M2502 V. Description of the invention! The etching has been removed and has phase 丨 removed, so that 丨 is adhered to the i-sheet scale 丨 molecular surface i | rotation 丨 to make;% coating transfer coating is still [ The invention of this invention poses a problem. According to this grade wafer ruler (a) provides a pad body (b) on gold (c) on the surface of the half edge material layer, and (3) Ί is another method instead of grinding, in which an etchant is applied to etch more The coating material layer 2 1 5 is, however, the etching is still a slow process. 2 A large amount of the coating material layer 21 5 must be further compounded to obtain the remaining process, which is more difficult. ; Only the upper surface of the gold molecular layer is exposed, so the solder ball 230 can be I. The area of the gold molecular layer is limited; therefore, another disadvantage of the reliability of the wafer-level crystal packaging is that the solder ball can adhere to the gold · Product is limited. · The coating process is too slow. In addition, two coating layers with the thickness required by the spin coating operation are required. In addition, about φ material waste is attached to the wafer in this spin coating process; therefore, One disadvantage of using spins is both blame and slowness. Brief summary] Ming seeks a way to package wafer-level wafer-scale packages into packages, which can overcome and at least reduce the number of conventional methods mentioned above. Π provides a package of semiconductors of 60% degree, This method includes the steps of: a semiconductor wafer having a plurality of layers of pad body surface, a metal conductor extending away from the surface of the first predetermined free end of the body is formed-a layer of conductive anti-isolation, the surface of the conductor wafer Cloth discharge insulation stand, with-" Conductor wafer surface to the second predetermined distance :: the first predetermined distance in the sexual insulation is less than the first predetermined distance * exposure% existence 12502 V. Description of the invention (4) \ The edge material is placed on the conductive anti-etching material layer, and there are at least some metallic conductors on the side surface; | 丨 (d) placed on the conductive anti-etching material layer and some metals on the side All the electrically insulating material portions on the semiconductor body ij are etched away. In another concept, the present invention provides a wafer-level wafer-scale seal. The package includes: '| A semiconductor die whose surface has Several layers of mats; metal conductors that are coupled and extend a first predetermined distance from a plurality of mats; an anti-etching layer at the free end of the metal conductor; 丨 an insulating layer on the surface, the insulating layer has a predetermined distance from the surface The exposed surface of the distance f, wherein the second predetermined distance is smaller than the first predetermined distance; and the reflowable material is attached to the anti-etching layer and at least part of the side surface 1 is substantially a metallic conductive body. [Brief description of the diagram] 丨 The specific embodiments of the present invention will be described in detail with reference to the drawings; 丨 FIG. 1 shows a detailed process flow chart of forming a wafer-level wafer-scale package according to conventional techniques; Section 2A- Figure E shows a cross-sectional side view of a wafer-level wafer-scale package formed according to the process of FIG. 1; Figure 3 shows a detailed process flow chart of a wafer-level wafer-scale package formed according to the present invention; Figures 4A-E show the cross-sectional side view of the package at the wafer-level wafer scale formed in accordance with the process of Figure 3; Figures 5-7 show the portion of the wafer-level wafer-scale package formation shown in Figure 4C-E

第8頁 ^12502 丨五、發明說明（5) ~ 1 I 分橫切面侧視放大圖； 丨 I第8圖顯示可視同第3圖製程的促進部分之薄膜佈放在 | 體晶圓上的橫切面側視圖。 ' | 丨【圖式詳細說明】 | 在晶圓上一金分子層佈放在鋼粒柱的上表面，隨而塗 佈材料以銅粒柱之相對高度的較低位置利用擠壓製程將其 i塗佈在晶圓上，使銅粒柱凸穿塗佈材料的上表面，蝕刻^ μ i係用以去除金分子層上面部分的塗佈材料與附著在凸穿的 i銅粒柱側表面上的該部分塗佈材料；再將焊點佈放在銅粒I i柱上的金分子層，且這種組配係予迴焊；此焊點佈放在銅·· 粒柱上面的金分子層上形成球體，且銅粒柱凸穿入焊球 内；因此’焊錫球附著在金分子層上，除此，焊錫球亦能 很有利的附著銅粒柱的側表面上； 苓考第3圖和第4A-E圖，依據本發明形成晶圓等級晶 片尺度封裝的製程300，由30 5開始提供310—半導體晶圓 2 0 5 ’在晶圓2 0 5上以銅粒柱2 1 0伸展自晶粒塾2 1 2如圖4 A所 示’如前所述由佛蘭西施卡〇唐（Francisca Tung)於2000 年4月27曰申請美國專利序號為09/564382，名稱為，供半 導體晶片改善粒柱連接與製造方法，且部分連續自佛蘭西 鲁 施卡·唐於2 0 0 0年4月2 6日向美國申請，序號（迄未指定 )，名稱為’供半導體晶片改善粒柱連接與製造方法，， 「 且本專利申明亦為其共同指定人’在此教不其至少有一些 一 粒柱結構之說明，這些專利併入供本案參考。 i 一種金分子層40 5在銅粒柱210的上表面22 5上形成Page 8 ^ 12502 丨 V. Description of the invention (5) ~ 1 I enlarged cross-section side view; 丨 I Figure 8 shows that the film can be placed on the bulk wafer that can be seen as the promotion part of the process in Figure 3 Cross section side view. '| 丨 [Detailed description of the diagram] | On the wafer, a gold molecular layer is placed on the upper surface of the steel particle column, and the coating material is then pressed at a relatively low position of the copper particle column by an extrusion process. i is coated on the wafer so that the copper grain pillars protrude through the upper surface of the coating material and is etched ^ μ i is used to remove the coating material on the upper part of the gold molecular layer and the side surface of the copper grain pillars that are attached to the protrusion This part is coated with material; then the solder joint is placed on the gold molecular layer on the copper particle I i column, and this combination is reflowed; this solder joint is placed on the copper ... A sphere is formed on the molecular layer, and the copper particles pillars protrude into the solder balls; therefore, the 'solder balls are attached to the gold molecular layer, in addition, the solder balls can also be very favorably attached to the side surfaces of the copper particle pillars. 3 and 4A-E, a process 300 for forming a wafer-level wafer-scale package according to the present invention, starting from 30 5 to provide 310—semiconductor wafer 2 0 5 ′ on the wafer 2 0 5 with copper grain columns 2 1 0 Stretched from the grain 塾 2 1 2 As shown in Figure 4 A 'As mentioned before, Francisca Tung applied for a US patent on April 27, 2000. The serial number is 09/564382, and the name is for the semiconductor wafer to improve the particle column connection and manufacturing method, and part of it has been applied to the United States from April 26, 2000 by Franciscan Tang, serial number (so far (Unspecified), with the name 'for semiconductor wafers to improve the connection and manufacturing method of pellets, and "and this patent statement is also the co-designator of it" here to teach it at least some descriptions of the structure of a pellet, these patents are incorporated For reference in this case. I A gold molecular layer 40 5 is formed on the upper surface 22 5 of the copper particle column 210.

第9頁 512502 I五、發明說明（6) —- 315,且該金分子層在鎳分子層上形成，該鎳分子層可形 丨成種阻礙以防止金分子滲入銅分子中，在蝕刻過程中有 刀的金刀子層被去除和/或金分子擴散入銅粒柱21〇，剩 丨銅粒柱210被暴露。當使用鎳分子層，圖式中所參考的 丨405疋表不金分子與鎳分子兩層所組成的抗蝕刻導 丨層。 冷德：圖’在半導體晶圓205被施加320以流體狀 料=形成塗層410,其具有_相對於銅粒柱210高度 丨二淨德，所以造成具有金分子層405的銅粒柱210凸 匕塗！ 410;·理想上，塗佈材料層41〇小於 : um利用擠壓製程以形成塗佈材料層4 1 〇，可利如 德=達拉斯FAS技術的微電（Micr〇E)設備來達成； 佈材料有APS的;曰曰圓底塗（卿）之環氧樹脂，德 钮’ eXter S)底塗環氧樹脂或任何的光顯像塗佈材 2，使用Micr〇W壓塗佈設備和Aps的wcu環氧樹脂，此設 t設Λ包括P0H速率為115微升（ul)每秒，穿梭速度為2. ^ _)，塗佈厚度為125微米（um)，擠壓頭縫隙為 〇.2mm;使用擠壓塗佈製程有8〇_9〇%的塗佈材料被分配形 成塗佈層410 ’且一單一分配可製得符合所要厚度之塗佈 層410;除此，這擠壓塗佈製程可分配的塗 有符合跳需要之可容忍度，擠壓塗佈一般是應用 面 控制板顯示器上。 因此本發明如所述，其較旋轉塗佈可有利於半導體晶 圓上迅速形成一塗佈材料層且廢物較少，以單一施加即能Page 9 512502 I. Description of the invention (6) --- 315, and the gold molecular layer is formed on the nickel molecular layer, and the nickel molecular layer can form a kind of barrier to prevent the gold molecules from penetrating into the copper molecules, during the etching process The gold knife layer with the knife is removed and / or gold molecules diffuse into the copper particle column 21, and the remaining copper particle column 210 is exposed. When the nickel molecular layer is used, the reference 405 in the figure indicates the anti-etching conductive layer composed of two layers of gold molecules and nickel molecules. Leng De: Figure '320 is applied to the semiconductor wafer 205 to form a fluid material = to form a coating 410, which has a height of 210 ° relative to the copper particle pillars, and therefore has a copper particle pillar 210 with a gold molecular layer 405 Convex dagger! 410; · Ideally, the coating material layer 41〇 is smaller than: um using an extrusion process to form the coating material layer 4 1〇, which can be achieved by Microelectronics (MicrOE) equipment of FAS technology in Dallas; The material is APS; it is called epoxy resin with round bottom coating (Qing), E'Xter S) epoxy coating or any light imaging coating material 2, using Micr〇W pressure coating equipment and Aps Wcu epoxy, this setting t set Λ includes a POH rate of 115 microliters (ul) per second, a shuttle speed of 2. ^ _), a coating thickness of 125 microns (um), the gap of the extrusion head is 0. 2mm; 80 ~ 90% of the coating material is distributed to form a coating layer 410 ′ using an extrusion coating process, and a single distribution can produce a coating layer 410 that meets the desired thickness; in addition, this extrusion coating The cloth process can be distributed with a tolerance that meets the needs of the jump. Extrusion coating is generally applied on the control panel display. Therefore, as described in the present invention, compared with spin coating, it can facilitate the rapid formation of a coating material layer on a semiconductor wafer with less waste, which can be achieved by a single application.

第10頁 M2502 五、發明說明（7) 、 ~ - 形成所需之厚度。 塗佈層410亦可以使用習知的旋轉塗佈製程來製得， ，而，旋轉塗佈製程必須被控制以製得具有預定厚度之塗 丨佈層41 0;例如，塗佈材料分配在半導體晶圓2〇5上的量、 塗佈材料使用的種類v半導體晶圓2〇5在被旋轉期間的速 丨度、等皆可被選擇以製得具有所要厚度之塗佈材料層 410; —實施例是以美國SITE製造的旋轉塗佈機，它施加 BCB塗層或聚亞胺或環氧基塗佈材料，旋轉塗佈機設定 I參數包括150 0轉的第一塗佈速度3〇秒、；[8〇〇轉的第二塗佈 :速度2 0秒、塗佈的塗佈材料層厚度為3〇-4〇um。 另一形成佈層410的方法是使用與美國專利第5891384 號，Apic Yamada股份有限公司申請所教示類似之鐵氟龍 膜有關的模鑄製程，將它併入參考。 在施加塗佈材料層4 1 0之後，將半導體晶圓在氮氣 (N2)環境中加熱溫度設定在3 5 0°c中45至6〇分鐘加熱， 以熟化塗佈材料層4 1 0，通常是使用一具有可調控氮氣室 之爐具加以熟化。 第5圖顯示一具有金分子層4 0 5在已形成塗佈材料層 4 1 0之後的其中之一銅粒柱之放大截面透視圖，5 〇 5部分是 熟化的塗佈材料層410附著在金分子層40 5上之表面510， 且5 1 5部分是熟化的塗佈材料層4 1 0附著在銅粒柱2 1 0之側 表面5 2 0。 隨後，蝕刻劑被施加到半導體晶圓的2 0 5的塗佈面， 以蝕刻33 0去除熟化的塗佈材料層410附著在金分子層405Page 10 M2502 V. Description of the invention (7), ~-thickness required for formation. The coating layer 410 can also be made using a conventional spin coating process, and the spin coating process must be controlled to obtain a coating layer 41 0 having a predetermined thickness; for example, the coating material is distributed in a semiconductor The amount on wafer 205, the type of coating material used v the speed of semiconductor wafer 205 during rotation, etc. can be selected to produce a coating material layer 410 having a desired thickness;- The embodiment is a spin coater manufactured by SITE in the United States. It applies a BCB coating or a polyimide or epoxy coating material. The spin coater sets the I parameter to include a first coating speed of 30 seconds and 30 seconds. , [800 second rotation of the second coating: a speed of 20 seconds, the thickness of the coating material layer applied is 30-40 um. Another method of forming the cloth layer 410 is to use a die-casting process related to a Teflon film similar to that taught in US Patent No. 5,891,384, Apic Yamada Co., Ltd., which is incorporated herein by reference. After the coating material layer 4 10 is applied, the semiconductor wafer is heated in a nitrogen (N2) environment at a temperature of 350 ° C for 45 to 60 minutes to heat the coating material layer 4 1 0, usually A stove with a controllable nitrogen chamber is used for curing. FIG. 5 shows an enlarged cross-sectional perspective view of a copper particle column having a gold molecular layer 4 0 5 after a coating material layer 4 10 has been formed, and a portion 5 05 is a mature coating material layer 410 attached to The surface 510 on the gold molecular layer 40 5, and part 5 1 5 is a cured coating material layer 4 1 0 adhered to the side surface 5 2 0 of the copper particle column 2 1 0. Subsequently, an etchant is applied to the coating surface of the semiconductor wafer, which is etched to remove the cured coating material layer 410 attached to the gold molecular layer 405.

第11頁 512502 :五、發明說明（8) ' ] 上之表面5 1 0的5 0 5部分，與熟化的塗佈材料層4 1 〇附著在 :銅粒柱2 1 0之側表面5 2 0的5 1 5部分；第4D圖顯示蝕刻之後 丨的半導體晶圓，且第6圖顯示一具有金分子層之一銅粒柱 2 1 0之放大截面透視圖，去除熟化的塗佈材料層41 〇附著在 金分子層4 0 5上之表面的5 0 5部分與附著在銅粒柱2丨〇之側 表面的5 1 5部分。 、 使用電漿餘刻時，以含有5% CF4、90% 02、5% _· 丨電將钱刻劑氣體組成’電力設定在4〇 〇瓦1 5分鐘作餘刻。 本發明可有利的形成一具有相對小部分的塗佈材料之 去除面積，因此可使用蝕刻而避免直接使用機械研磨。 參考第4E圖，在蝕刻33 0之後，焊錫粒被佈放在銅粒 | 柱210之上，回流焊345,熔鎔焊錫形成連接335到銅粒柱 210之焊錫球415，這製程30 0隨而結束355。 第7圖顯不在回流焊之後其中之一的焊錫球&丨5附著在 鋼粒柱210的放大截面透視圖，具有金分子層4〇5的銅粒柱丨 2 10凸穿進入焊錫球41 5中；除此，焊錫球415附著在銅粒 柱21 0的側表面5 2 0。 本發明如所述’可有利的允許焊點附著在金分子層和 鋼粒柱的側表面，使具有更強的機械強度和可靠度的電性應 連接。 響 ^參考第8圖’為要促進蝕刻製程的效率，在蝕刻33 0之丨 月!|可使用一額外的清潔步驟；在半導體晶圓2〇5施加32〇塗卜 7材料410之後，於塗佈材料41〇熟化之前，將鐵氟龍膜 〇 5置放在半導體晶圓2丨〇上，向著半導體晶圓2丨〇對鐵氟Page 11 512502: V. Description of the invention (8) '] Part 5 5 of the surface 5 1 0 and the cured coating material layer 4 1 〇 attached to: the side surface of the copper particles 2 1 0 5 2 Part 5 1 5 of 0; Figure 4D shows the semiconductor wafer after etching, and Figure 6 shows an enlarged cross-sectional perspective view of a copper particle column 2 1 0 with one of the gold molecular layers, removing the cured coating material layer 504. A portion of 505 attached to the surface of the gold molecular layer 405 and a portion of 515 attached to the side surface of the copper particle column 205. When the plasma is used for the rest of the time, the electricity composition containing the 5% CF4, 90% 02, and 5% is used to set the electricity of the coin-cutting agent gas, and the power is set to 4,000 watts for 15 minutes for the rest of the time. The present invention can advantageously form a removal area with a relatively small portion of the coating material, so that etching can be used instead of directly using mechanical grinding. Referring to FIG. 4E, after etching 33 0, the solder particles are placed on the copper particles | pillar 210, reflow soldering 345, and the solder is melted to form a solder ball 415 connecting 335 to the copper particle pillar 210. And ended 355. Figure 7 shows an enlarged cross-sectional perspective view of one of the solder balls & 5 attached to the steel grain column 210 after reflow, a copper particle column with a gold molecular layer 4.05 and 2 10 protruding into the solder ball 41 5; In addition, the solder ball 415 is attached to the side surface 5 2 0 of the copper particle column 21 0. According to the invention, as described above, the solder joint can be advantageously allowed to be attached to the side surfaces of the gold molecular layer and the steel particle column, so that the electrical connection with stronger mechanical strength and reliability should be connected. ^ Refer to Figure 8 'To promote the efficiency of the etching process, an additional cleaning step can be used during the etching process. After the semiconductor wafer 205 is applied with a 32 ° gravel 7 material 410, Before the coating material 41 is matured, the Teflon film 05 is placed on the semiconductor wafer 2 and the Teflon is directed toward the semiconductor wafer 2

第12頁 512502 I五、發明說明（9) ~ i - i龍膜施加壓力，隨而移去鐵氟龍膜8〇5，取下塗佈曾材料 |之未熟化部份505，經此，留下較少的熟化部份5〇 5和 |515，這些塗佈材料必須以蝕刻製程33〇去除。 丨 鐵氟龍膜已是習知使用在模鑄之脫模膜，當模鑄時使 i |用一層塗佈的脫模膜，，此脫模膜可防止在模铸製程期間，丨 柄鑄化合物沾著在金分子層4〇5的表面510和銅粒柱21〇的 \-側表面5 2 0。 丨. i ! ! i " 可輔助塗佈材料未熟化部份的清潔之實施例係以使用 |美國3M脫模膜，此脫模膜可以手工施用。 | 可替代性地，可應用雷射清潔法將金分子層405上的 . |塗佈材料未熟化部份清除，雷射清潔法是熟悉此項技藝人 丨士所知，由新加坡自動化促進系統（ASA)股份有限公司 所製造的雷射清潔設備可使用再本實施例。 、 因此，本發明如所述，製造晶圓等級晶片尺度封裝不 需將半導體晶圓作機械研磨；除此，銅粒柱與焊球之 連接更可靠。 足疋藉由半導體晶圓的粒柱凸起（bumps)上形成一 f防蝕刻導電層而達成，這凸起是在沈積一層塗佈材料的 曰曰圓上延伸且凸穿自塗佈材料層的表面，隨後將凸起的頂 i部與侧面的塗佈材料層部份予以蝕刻去除，並將焊球芸 :在凸起的暴露部份。 ! 因此，本發明提供一種供形成晶圓等級晶片尺度封梦 !之方法及藉其所形成之封裝，它至少能克服或 ^ !知的問題。 述lPage 12 512502 I V. Description of the invention (9) ~ i-i Long film applies pressure, then removes the Teflon film 805, and removes the uncured portion 505 of the coating material | After that, Leaving less mature portions 505 and | 515, these coating materials must be removed by an etching process 33.丨 Teflon film is a mold release film that is commonly used in mold casting. When mold casting is used, i | use a layer of coating release film. This release film can prevent the shank casting during the mold casting process. The compound adheres to the surface 510 of the gold molecular layer 405 and the-side surface 5 2 0 of the copper particle column 210.丨. I!! I " The embodiment that can assist the cleaning of the uncured part of the coating material is to use the US 3M release film, which can be applied manually. Alternatively, the laser cleaning method can be applied to remove the gold molecular layer 405. | The uncured part of the coating material is removed. The laser cleaning method is known to those skilled in the art and is known by the Singapore Automation Promotion System The laser cleaning equipment manufactured by (ASA) Co., Ltd. can be used in this embodiment. Therefore, as described in the present invention, semiconductor wafers do not need to be mechanically polished for manufacturing wafer-level wafer-scale packages; in addition, the connection between copper pellets and solder balls is more reliable. The foot is achieved by forming an f-etch-resistant conductive layer on the bumps of the semiconductor wafer. The bumps extend on the circle where the coating material is deposited and penetrate through the coating material layer. Then, the top i portion of the protrusion and the portion of the coating material layer on the side are etched away, and the solder ball is placed on the exposed portion of the protrusion. Therefore, the present invention provides a method for forming a wafer-level wafer-scale dream seal and a package formed by the method, which can at least overcome the problems known or known. State l

第13頁 512502 i五、發明說明（ίο) I 值得讚賞的是本發明雖僅以一特殊實施例作詳細說 明，惟對於熟悉此項技藝人士仍能做各種修改與改善而不 偏離本發明精神。Page 13 512502 i V. Description of the Invention (I) It is commendable that although the present invention is only described in detail with a special embodiment, it can still make various modifications and improvements to those skilled in the art without departing from the spirit of the present invention .

Claims (1)

申請專利範圍Patent application scope 二ΐ用於形成晶圓等級晶片尺度封筆之方i—- 一 包括的步驟為： 展之方法’這方法 (b (c )提，-種半導體晶圓具有複數 個墊體具有一金屬導濟 墊體的表面，其中母 離。 - 退 自表面的第一預定距 f金屬導體的自由端形成一層導電性抗蝕刻材料。 在半導體晶圓的表面佈放電性 i ς 1 绫姑祖®目古 ^ 巴琢材村，其中電性絕 、，彖材枓層具有一自半導體晶圓 暴露表面，其中當-π — π她3 w芏罘一預疋距雔的 第一預疋距離是小於第一箱中w齡： 且電性絕緣材料部八姑佑淤卢捕、 員疋巨離’ 卩刀被佈放在傳導性抗蝕刻材料層 上且在側邊表面至少有某些金屬性導體。 餘刻材料層與在侧邊的某些金屬性導 體上的所有電性絕緣材料部份予與蝕刻去除。 如申印專利範圍第丨項所述之一種方法， 一 的步驟為： ％ ^匕3 )佈放可回流焊材料在自由端的金屬性導體上之 防蝕刻層上。 )回流焊此半導體晶圓，使回流焊材料附著在導電性防 餘刻層和金屬性導體之部分的側表面上。 如申請專利範圍第1項所述之方法，其中步驟（b )包含 沈積導電性防蝕刻材料在金屬性導體之自由端。 如申請專利範圍第3項所述之方法，其中步驟（b )包含 沈積金分子步驟。 如申請專利範圍第3項所述之方法，其中步驟（b )包含 )) (d ) 2. e (f 3. 4.The second method used to form a wafer-level wafer-scale seal is to include the following steps: Develop the method 'this method (b (c)),-a semiconductor wafer has a plurality of pads with a metal guide The surface of the mat body, in which the mother is separated.-The free end of the first predetermined distance f metal conductor receding from the surface forms a layer of conductive anti-etching material. The electrical discharge is distributed on the surface of the semiconductor wafer. ^ Ba Zhuocai Village, in which the electrical insulation layer has an exposed surface from the semiconductor wafer, where the first pre-distance from the pre-distance from -π to π3w is less than the first The w-age in a box: And the electrical insulation material department Bagu Youlu Lu Lu, Yuan Li's trowel is placed on the layer of conductive anti-etching material and there are at least some metallic conductors on the side surface. The remaining material layer and all the electrically insulating material portions on some metallic conductors on the side are etched away. As one method described in the first patent application scope, one step is:% ^ 3) Lay the reflowable material on the metal conductor at the free end. Etch layer. ) This semiconductor wafer is reflow-soldered so that the reflow material is adhered to the side surfaces of the conductive anti-etch-off layer and the portion of the metallic conductor. The method according to item 1 of the scope of patent application, wherein step (b) comprises depositing a conductive anti-etching material on the free end of the metallic conductor. The method as described in claim 3, wherein step (b) includes a step of depositing gold molecules. The method as described in item 3 of the scope of patent application, wherein step (b) includes)) (d) 2.e (f 3.4. 第16頁 512502 六、申請專利範圍 沈積鎳分子層，隨而將金分子層沈積在鎳分子層 上。 6 ·如申請專利範圍第1項所述之方法，其中步驟（b )包含 鍍敷防蝕刻材料在金屬性導體的自由端上。 7. 如申請專利範圍第1項所述之方法，其中步驟（c )包含 以擠壓塗佈製程佈放電性絕緣材料的步驟。 8. 如申請專利範圍第1項所述之方法，其中步驟（c )包含 一單一佈放步驟。 9. 如申請專利範圍第1項所述之方法，其中步驟（c )包含 旋轉塗佈電性絕緣材料層在半導體晶圓的表面之步驟。 I 0 ·如申請專利範圍第9項所述之方法，其中步驟（c )包 含選自底填塗佈材料與光易顯像材料所組成的組群中之 一種材料的旋轉塗佈步驟。 II ·如申請專利範圍第1項所述之方法，其中步驟（c )包 含在半導體晶圓的表面上以模鑄電性絕緣材料層的步驟 時使用脫模膜。 1 2.如申請專利範圍第1項所述之方法，其中步驟（d )包 含電漿蝕刻步驟。 1 3 ·如申請專利範圍第1項所述之方法其中步驟（e )包含 印刷沈積焊點的步驟。 1 4.如申請專利範圍第1項所述之方法，其進一步包含在步 驟（c )之後步驟（d )之前，熟化此電性絕緣材料步 驟。 1 5 ·如申請專利範圍第1 4項所述之方法，在步驟（c )之Page 16 512502 6. Scope of patent application Deposition of nickel molecular layer, and then deposit gold molecular layer on nickel molecular layer. 6. The method according to item 1 of the scope of patent application, wherein step (b) comprises plating an anti-etching material on the free end of the metallic conductor. 7. The method according to item 1 of the scope of patent application, wherein step (c) comprises a step of applying a discharge insulating process to the discharge insulating material. 8. The method as described in item 1 of the patent application scope, wherein step (c) includes a single deployment step. 9. The method according to item 1 of the scope of patent application, wherein step (c) includes a step of spin-coating an electrically insulating material layer on a surface of a semiconductor wafer. I 0. The method according to item 9 of the scope of patent application, wherein step (c) comprises a spin-coating step of one material selected from the group consisting of an underfill coating material and a photo-imaging developing material. II. The method according to item 1 of the scope of patent application, wherein step (c) includes a step of molding an electrically insulating material layer on the surface of the semiconductor wafer using a release film. 1 2. The method according to item 1 of the scope of patent application, wherein step (d) comprises a plasma etching step. 1 3 The method according to item 1 of the scope of the patent application, wherein step (e) includes a step of printing and depositing solder joints. 14. The method according to item 1 of the scope of patent application, further comprising the step of curing the electrical insulating material after step (c) and before step (d). 15 · The method as described in item 14 of the scope of patent application, in step (c) 512502 六、申清專利範圍 後和熟化：：性絕緣材料步狀前，清潔佈放在導電性 防#刻材料層上的部分導線性絕緣持料之牛驟 驟包括的步驟為. 施力:脫模膜上導電性防蝕刻材料層上；且去除脫模膜 17.如“專利乾圍第15項所述之方法，其中的清潔步 驟包括雷射清潔的步驟。 1 8 · —種晶圓等級晶片尺度之封裝，其包含·· 一種半導體晶粒表面具有複數墊體； 自複數塾體延伸一第一預定距離之金屬性導體； 在金屬性導體的自由端上有一防餘刻層； 表面上有一絕緣層，這絕緣層具有一暴露表面，距表 面有一第二預定距離，其中第二預定距離小於第一預 定距離；且回流焊材料附著在防蝕刻層和所有金屬性 導體之側表面之部分。 1 9 ·却申請專利範圍第丨8項之晶圓等級晶片尺度之封 裝’其中金屬性導體包含銅導體。 2 0 ·塹申請專利範圍第丨9項之晶圓等級晶片尺度之封 裝’其中銅導體包含複層的銅板層。 2 1 ·也申請專利範圍第〗8項之晶圓等級晶片尺度之封 裝’其中防蝕刻層包含金分子層。 2 2.塹申請專利範圍第18項之晶圓等級晶片尺度之封 裝’其中防蝕刻層包含一鎳分子層中含有金分子層。 23.埜申請專利範圍第22項之晶圓等級晶片尺度之封512502 VI. After applying for the patent scope and maturity: Before the step of insulating insulation material, the cleaning cloth is placed on the conductive anti-etching material layer of the part of the wire insulation holding material. The steps include: Applying force: On the release film on the conductive anti-etching material layer; and removing the release film 17. The method described in item 15 of the "patent dry enclosure", wherein the cleaning step includes a laser cleaning step. 1 8 · — wafer A chip-scale package, comprising: a semiconductor die surface having a plurality of pads; a metal conductor extending a first predetermined distance from the plurality of carcasses; an anti-etching layer on a free end of the metal conductor; a surface There is an insulating layer thereon, the insulating layer has an exposed surface and a second predetermined distance from the surface, wherein the second predetermined distance is less than the first predetermined distance; and the reflow soldering material is attached to the side surface of the anti-etching layer and all metallic conductors. 1 9 · While applying for a wafer-level wafer-scale package with a scope of patent No.8, where the metallic conductor contains a copper conductor. "Wafer-level package" where the copper conductor contains a laminated copper plate layer. 2 1 ・ Wafer-level wafer-level package with a patent scope of item 8 "where the anti-etch layer contains a molecular layer of gold. 2 2. 堑 Application Wafer-level wafer-scale package of item 18 of the patent scope, wherein the anti-etching layer includes a nickel molecular layer containing gold molecule layer. 23. No. 22 of the patent application scope of the wafer-level wafer-scale package 第18頁 512502 六、申請專利範圍 裝，其中金分子層的厚度是小於第一預定距離與第二 預定距離之間的值。 2 4.如申請專利範圍第1 8項之晶圓等級晶片尺度之封 裝，其中絕緣層包含一種選自模鑄化合物、膠囊環氧 樹脂、底填塗料和光易顯像性材料，如苯並環丁烯 (BCB )或聚亞胺所組成的材料中之一種。 2 5.塹申請專利範圍第1 8項之晶圓等級晶片尺度之封 裝，其中回流焊材料包含焊錫（s ο 1 d e r )。Page 18 512502 VI. Scope of patent application, in which the thickness of the gold molecular layer is smaller than the value between the first predetermined distance and the second predetermined distance. 2 4. The wafer-level wafer-scale package according to item 18 of the patent application scope, wherein the insulating layer comprises a material selected from the group consisting of a molding compound, a capsule epoxy resin, an underfill coating, and a photo-imaging material such as a benzo ring One of materials composed of butene (BCB) or polyimide. 2 5. 堑 The wafer-level wafer-scale package of item 18 in the scope of patent application, wherein the reflow soldering material contains solder (s ο 1 d e r). 2 6.楚申請專利範圍第2 5項之晶圓等級晶片尺度之封 裝，其中銲錫包含低共鎔性銲錫。2 6. The wafer-level wafer-scale package of the 25th item in the scope of Chu's patent application, in which the solder contains low common solder. 第19頁Page 19