507201 經濟部智慧財產局··!工消費合作社印製 A7 B7 五、發明說明（1 ) [發明背景] [發明領域] 本發明大體上係關於譬如快閃電子可拭除可程式唯讀 記憶體〔EEPROM〕記憶胞〔cell〕p車列之浮置閘極記憶 體裝置。詳言之，本發明係關於半導體積體電路記憶體裝 置’包括有子線追縱結構’用來匹配參考和區段核心字線 電壓，無關於區段位置而跨越整個晶片。 [相關技藝說明] 如於此技藝方面一般所知，存在有一種非依電性記憶 體裝置稱之為“快閃EEPROM”，此快閃EEPROM最近表現 為一種重要之記憶體裝置，結合了 EPR0M之密度和 EPROM之電子可拭除之優點。此種快閃EEpR〇M具有電 子可拭除性和小的記憶胞大小。於習知的快閃EEpR〇M記 憶體裝置’可以在半導體基板上形成複數個單一電晶體之 核心記憶胞，其中各記憶胞包含有P_型導電性基板、與此 1基板整體形成之N-型導電性源極區、和亦整體形成於基板 内之N-型導電性汲極區。浮置閘極藉由薄介電層而與基板 隔離。第二介電層將控制閘極與浮置閘極隔離。於基板上 之p-型通道區隔離源極和汲極·區。 使用為快閃記憶體之一種架構型式，一般稱之為nor 快閃記憶體架構，此種NOR快閃記憶體架構分成了複數個 區段之快閃EEPROM記憶胞〔浮置閘極〕陣列。再者，在 每一個區段内之記憶體記憶胞配置成字線之列和與該字線 之列相交又之位元線之行。在各區段内之各記憶胞電晶體 規格（21〇 X 297 公爱丁 反) 1 91649 I I III1IIII1I1 -Ills — — ! ^ *Ι11Ι!ΙΙ» (請先閱讀背面之注意事項再填寫本頁) 507201 A7 五、發明說明（2 ) 之源極區連結在共同節點。因此，能同時拭除在特定區段 内之所有記憶胞，且能根據一個區段接著—個區段之方式 施行拭除。記憶胞電晶體之控制閘極耦接到字線，而 極轉接到位元線。 在習知之操作中為了程式化快閃eepr〇m記憶胞，没 極區和控制閘極上升至高於施加至源極區電位之預定電 位。舉例而言，在汲極區施加了大約+5 · 5伏特之％電壓， 以控制閘極1具有大約+9伏特之施加電壓。這些電壓產 生“熱電子，，，會加速通過薄的介電層並到達浮置閘極。此 熱電子注入造成浮置閘極臨界值增加大約2至4伏特。 在習知之操作中為了拭除快閃EEPROM記憶胞，正電 位〔例如，+ 5伏特〕加至源極區。控制閘極施加以負電 位〔例如_ 8伏特〕，而允許汲極區浮置。在浮置閘極和源 極區之間產生強電場，而由佛勒-諾德漢〔Fowler-Nordheim〕穿遂方法將電子從浮置閘極吸引至源極區。 經濟部智慧財產局員工消費合作社印製 為了判定快閃EEPROM記憶胞是否已經適當地程式 化’則測量讀取電流之大小。一般而言，於源極區操作之 讀取模式保持在接地電位〔0伏特〕，而控制閘極保持在 大約+ 5伏特電位。源極區保持在大約+1至+2伏特之間電 位。在這些情況下，未程式化之記憶胞〔儲存邏輯“1，，〕將 傳導大約5 〇至10 0微安培位準之電流。而已程式化之記憶 胞〔儲存邏輯“〇’，〕將流過相當少之電流。 舉例而言，16百萬位元〔Mb〕快閃記憶體核心陣列 一般在單一晶片上製成NxM矩陣之型式，其中N等於列 本紙張尺度適用中國國家標準（CNS)A4規格（2iQ χ 297公爱） 91649 經濟部智慧財產局員工消費合作社印製 507201 五、發明說明（3 數而Μ等於行數。再者，記憶體核心陣列可以分成左半區 段陣列和右半區段陣列。左半區段陣列和右半區段陣列各 形成有許多的區段，譬如16個區段，各定義一個可選擇之 區塊〔BLOCK〕。各區段形成預定數目結合成群之列。對 於16百萬位元陣列分成在左半區段陣列之16個區段，和 在右半區段陣列之16個區段，各區段或區塊具有512列和 1 024行之大小。 如此顯示於第1圖中由左半區段陣列12和右半區段陣 列14組成之形成在單一晶片n上之一般16百萬位記憶體 核心陣列10。左半區段陣列12包括有16個區段，至 s 1 5。相似地，右半區段陣列i 4包括有J 6個區段，s〗6至 S31。各區段S0至S31儲存512 κ配置成512列和ι〇24 行之資料位元。如所示之，許多區段〔s〇至S31〕各別位 於跨越整個晶片11。因此，一個角落區段〔例如，區段s 24二和另一個角落區段〔例如，區段S23〕之間之距離是 非常長的。其結果，在記憶體核心陣列1〇中於不同的區段 之間的位置差異，在讀取操作模式期間將造成感測上的問 題。 詳言之，經常需要内部產生之電壓大於由外部或晶片 外供應至晶片之電源供應電位所產生之電壓。舉例而言， 已知快閃EEPROM操作於VCC趨近於+5伏特，需要等於 + 3.0伏特之高電廢產生用於記憶體記憶胞之操作讀取模 式。其結果，半導體記憶體一般亦包括内部升壓電路用來 產生提升至高於外部供應電壓之輸出信號。如此之升壓 本紙張尺度適用中_冢標準（CNS)A4規格—χ挪公爱） 91649 -ΙΙΙΙΙΙΙΙΙΙΙΙ — ·! I I I I I I «ΙΙΙΙΙ1Ι — (請先閲讀背面之注意事項再填寫本頁) 507201 A7 B7 五、發明說明（4 ) (請先閱讀背面之注意事項寫本頁) 路16如第1圖中所示，用來產生字線供應電壓VpxG於 節點N1，此字線供應電壓VPXG經由列解碼器18而傳送 至於記憶體核心陣列10中之不同之區段S〇至S3 1中之適 當之字線。 列解碼器1 8位於左半區段陣列12和右半區段陣列工4 之間中心位置。列解碼器1 8反應於用來致使字驅動器〔未 顯示〕供應從升壓電路16來之字線供應電壓vpxG至結 合之不同之區段適當之字線的位址信號。字線供應電壓 VPXG —般在+3.7伏特至+4·7伏特之範圍，此電壓範圍發 生高於一般+3.0伏特之輸入電源供應電位vcc。 若假設升壓電路16位於晶片u之下左側部，則區段 S23位於接近升壓電路16而區段S24位於很遠離升壓電路 16。因此，結合於區段S23之於節點N2之於字線的 字線電壓VPXG1，將實質相等於從升墨電路16來之提升 之電壓VPXG。此提升之電壓vpxG為目標電壓希望能維 持跨越整個晶片。然、而，結合區段S24之於節點N3之於 經濟部智慧財產局員工消費合作社印製 字線wlf的字線電壓VPXG2，在讀取模式操作期間，多 數之感測將實質小於目標電壓。 再者，假設參考區段或極小陣列20一般位於接近升 壓電路16。因此，結合於參考區段2〇之於節點n4之於字 線WLR时考字線電壓，，亦將實質相等於提升之電壓 VPXG。參考區段或陣列2()包括複數個配置成列和行〔例 如：2〇 X 20〕之參考記憶胞。電阻R1代表結合鄰接“近” 區段S23在節點N2和鄰接“遠，，區段S24在節點之間之 本紙張尺錢财 _ (210 X 297 ) 4 91649 507201 經濟部智慧財產局員工消費合作社印製 91649 A7 ____ B7 _ 五、發明說明（5 ) 導體線2 1之集總電阻負載。電容器&代表當連接到其結 合字線選擇之區段之電容負載。用於選擇之區段之電容負 載Cs代表具有相同之值，不管其在記憶體核心陣列1 〇中 之位置。電容器CR代表於參考區段或陣列2〇之輸入的電 容負載’和具有遠較電容器匕小之值。 對於高速讀取操作，於設定字線電壓之時間期間，在 他們到達直流〔DC〕穩定之前，必須讀取區段核心記憶 胞。因此，當於字線WLR和WLF電壓彼此接近隨耦時， 能獲得連續之最佳讀取。因此，當希望比較於參考或區段 陣列20之參考字線冒“上之電壓VPXG與結合之“遠，，區 段S24子線上之電壓VPXG2時，他們之間會獲得大的差 值。此是基於以下之事實，即保持在從升壓電路丨6至參考 區段20中之參考字線WLr，和至在“遠，，區段S24中之記 憶體核心字線WLF之行程路徑中之電阻和電容不匹配的 關係。其結果，使用於讀取期間，將引起於感測電路中〔圖 1中未顯示〕不良之邊緣感測，尤其是用於感測導通記憶體 核心記憶胞。 由此觀之，須設有一種字線追蹤結構，用來匹配跨越 整個晶片無關於區段位置之參考和區段核心字線電壓。本 發明藉由設有第二VPXG導體線操作連接於“遠，，區段和參 考記憶胞極小陣列之區段字線之間，而完成此設計。此第 二VPXG導體線較之I VPXG導體線操作連接於升壓電 路和“遠”區段之區段字線之輸出之間，具有實質較小之時 間常數。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公愛) -~ - — ιίι — IllilIII - i I f i ! I I «!!ϊι!ιιί (請先閱讀背面之注意事項再填寫本頁) 507201 A7 B7 _ 一― ~—------------------- - 五、發明說明（6 ) [發明概述] 因此，本發明之一般目的為提供一種字線追蹤結構， 用於配置成複數個區段之快閃EEPR0M記憶體記憶胞，此 複數個區段之結構相對較簡單，容易製造，且較之於先前 技藝δ己憶體裝置於讀取期間具有增進之正確性。 本發明之一個目的為提供一種字線追蹤結構，用於配 置成複數個區段之快閃EEPROM記憶體記憶胞，俾便於讀 取期間避免錯誤。 本發明之另一個目的為提供一種字線追蹤結構，用於 分割成複數個區段之快閃EEPROM記憶體記憶胞，俾便匹 配跨越整個晶片而無關於區段位置之參考和區段核心字線 電壓。 本發明之又一個目的為提供一種字線追蹤結構，用於 分割成複數個區段之快閃EEPR0M記憶體記憶胞，此複數 個區段包括第二VPXG導體線，操作連接於“遠，，區段和參 考記憶胞極小陣列之區段字線之間。 經濟部智慧財產局員工消費合作社印製 依照本發明之較佳實施例’設有一種字線追蹤結構， 用於半導體記憶裝置，此半導體記憶裝置具有分割成複數 個區4又之快閃EEPROM記憶體記憶胞陣列。字線追縱結構 用來匹配跨越整個晶片無關於區段位置之參考和區段核心 子線電壓。此字線追縱結構包括第二VPXG導體線，操作 連接於“遠’’區段和參考記憶胞極小陣列之區段字線之間。 第二VPXG導體線較之操作連接於升壓電路和“遠，，區段之 區段子線之輸出之間之第一 VPXG導體線具有實質較小之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 91649 507201 A7 B7 4 經濟部智慧財產局員工消費合作社印製 五、發明說明（7 ) 時間常數。 [圖式之簡單說明] 由下列之詳細說明，配合所附圖式，本發明之這些和 其他目的和優點將變得更為清楚，各圖中相同之參考號碼 係表示相對應之部分，其中： 第1圖為習知16百萬位元〔Mb〕EE PROM半導體積 體電路記憶體裝置之簡化方塊圖，該記憶體裝置具有分割 成複數個區段之記憶體記憶胞陣列，· 第2圖和第3圖顯示於第1圖之個別“近，，和“遠，，區段 各種信號之波形’可用於了解於讀取期間遭遇之問題； 第4圖為依照本發明原理構成，具有字線追蹤結構之 16百萬位元EEPROM半導體積體電路記憶體裝置之簡化 方塊圖； 第5圖和第6圖顯示於第4圖之個別“近，，和“遠，，區段 各種信说之波形’可用於了解如何解決讀取問題； 第7圖顯示分別於第1圖和第4圖中參考記憶胞字線 電壓和區段核心字線電壓對於“遠，，區段之波形；以及 第8圖為結合第4圖之第一和第二vpxG導體線之電 阻和寄生電容之電路圖 [符號說明] 10 記憶體核心陣列 11 曰H 99 r\ 12 左半區段陣列〔SO至S15〕 14 右半區段陣列〔S16至S31〕 16 升壓電路 18 列解碼器 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 91649 -IIIIIIIIIIII — · I I (請先閱讀背面之注意事項再填寫本頁) · 507201 五、發明說明（8 ) A7 -一___— B7 20 參考區段〔極小陣列〕 21 導體引線 S23 “近”區段 S24 “遠”區段 202、 204、206 曲線 302〜 304、306 曲線 400 半導體積體電路記憶體裝置 請 先 閱 讀 背 410 記憶體核心陣列 411 單一晶片 412 左半區段 414 右半區段 面 之 注 416 升壓電路 420 參考區段 意 事 項 421 第一 VPXG導體線 422 第二VPXG導體線 1 % 424 第一端 426 第二端 本 I S423 “近”區段 S424 “遠”區段 502、 504、506 曲線 602、 604、606 曲線 702、 704、706 曲線 [較佳實施例之詳細說明] 經濟部智慧財產局員工消費合作社印製 以下將說明用於快閃EEPROM記憶體記憶胞之字線 追蹤結構。於下列之說明中，為了能夠完全了解本發明， 而長：出許多詳細之說明，譬如特定之電路配置、組件等等。 然而’顯然對本技藝方面之一般技術人員而言，本發明為 實際可行而不需要這些特別之詳細說明。於其他的例子 中，已知之製程、電路、和控制線路，並不特別相關於本 發明之操作原理瞭解者，茲為了清楚之目的而將其省略。 現詳細參照圖式，第4圖所示為形成於單一晶片411 上之EEPROM半導體積體電路記憶體裝置4〇〇之簡化方塊 圖，此單一晶片411上包括有16百萬位元〔Mb〕記憶體 核心陣列4 1 0。記憶體核心陣列4 1 0由左半區段4 12和右 91649 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 507201 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（9 ) 半區段4 14所組成。左半區段陣列4 1 2由十六個區段S 4 0 0 至S41 5組成。同樣地，右半區段陣列4 14由十六個區段507201 Intellectual Property Bureau of the Ministry of Economic Affairs ·! Printed by the Industrial and Consumer Cooperatives A7 B7 V. Description of the Invention (1) [Background of the Invention] [Field of the Invention] The present invention relates generally to, for example, flash-electronic erasable and programmable read-only memory [EEPROM] memory cell [cell] floating gate memory device of the car. In detail, the present invention relates to a semiconductor integrated circuit memory device 'including a sub-line tracking structure' for matching the reference and segment core word line voltages, regardless of the segment position and spanning the entire chip. [Related technology description] As is generally known in this technology, there is a non-electric memory device called "flash EEPROM". This flash EEPROM has recently appeared as an important memory device, which combines EPR0M The density and advantages of EPROM's electronic erasability. This flash EEPROM has electron erasability and small memory cell size. The conventional flash ERepROM memory device 'can form a plurality of core cells of a single transistor on a semiconductor substrate, where each memory cell includes a P_-type conductive substrate, and N formed integrally with this 1 substrate. The -type conductive source region and the N-type conductive drain region also integrally formed in the substrate. The floating gate is isolated from the substrate by a thin dielectric layer. The second dielectric layer isolates the control gate from the floating gate. A p-type channel region on the substrate isolates the source and drain regions. A type of architecture used as a flash memory is generally called a nor flash memory architecture. This NOR flash memory architecture is divided into a plurality of sectors of an array of flash EEPROM memory cells (floating gates). Furthermore, the memory cells in each segment are arranged in a row of word lines and a row of bit lines that intersect with the row of the word lines. Specifications of each memory cell in each section (21〇X 297 male ED) 1 91649 II III1IIII1I1 -Ills — —! ^ * Ι11Ι! ΙΙ »(Please read the precautions on the back before filling this page) 507201 A7 V. The source region of the invention description (2) is connected to a common node. Therefore, all the memory cells in a specific section can be erased at the same time, and erasure can be performed according to one section after another. The control gate of the memory cell transistor is coupled to the word line, and the pole is switched to the bit line. In order to program the flash eeprom memory cells in the conventional operation, the electrode region and the control gate are raised to a predetermined potential higher than the potential applied to the source region. For example, a voltage of approximately + 5.5V is applied to the drain region to control the gate 1 to have an applied voltage of approximately + 9V. These voltages generate "hot electrons," which accelerate through the thin dielectric layer and reach the floating gate. This hot electron injection causes the floating gate threshold to increase by approximately 2 to 4 volts. In the conventional operation, this is done to erase Flash EEPROM memory cell, the positive potential (for example, + 5 volts) is added to the source region. The control gate is applied with a negative potential (for example, _ 8 volts), and the drain region is allowed to float. The floating gate and source A strong electric field is generated between the polar regions, and the Fowler-Nordheim tunneling method draws electrons from the floating gate to the source region. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Whether the flash EEPROM memory cell has been properly programmed 'measures the magnitude of the read current. Generally speaking, the read mode operating in the source region is maintained at ground potential [0 volts] and the control gate is maintained at approximately + 5 Volt potential. The source region remains at a potential between approximately +1 and +2 volts. In these cases, the unprogrammed memory cell [storage logic "1 ,,]" will conduct approximately 50 to 100 microamperes The current. The programmed memory cell [storage logic "0 '," will pass a relatively small amount of current. For example, a 16 million-bit [Mb] flash memory core array is generally made of a NxM matrix on a single chip. Type, where N is equal to the size of the paper. Applicable to China National Standard (CNS) A4 specification (2iQ χ 297 public love) 91649 Printed by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs 507201 V. Description of the invention (3 and M equal to the number of rows. Furthermore, the memory core array can be divided into a left half-segment array and a right half-segment array. The left half-segment array and the right half-segment array each form a number of segments, such as 16 segments, each of which defines one Selected block [BLOCK]. Each sector forms a predetermined number of clusters. For a 16 million bit array, it is divided into 16 sectors in the left half sector array and 16 in the right half sector array. Segments, each segment or block has a size of 512 columns and 1 024 rows. As shown in FIG. 1, it is generally composed of a left half segment array 12 and a right half segment array 14 formed on a single wafer n. 16 million-bit memory core array 10 The left half segment array 12 includes 16 segments to s 1 5. Similarly, the right half segment array i 4 includes J 6 segments, s 6 to S31. Each segment S0 to S31 stores 512 κ is configured as data bits of 512 rows and ι〇24 rows. As shown, many segments [s0 to S31] are located across the entire wafer 11. Therefore, one corner segment [for example, segment s 24] The distance between the second and another corner section (for example, section S23) is very long. As a result, the position difference between the different sections in the memory core array 10 is in the read operation mode This will cause sensing problems. In detail, it is often required that the internally generated voltage is greater than the voltage generated by the power supply potential supplied from the external or external chip to the chip. For example, it is known that flash EEPROM operates at VCC trend. Nearly +5 volts, a high power waste equal to + 3.0 volts is required to generate an operation read mode for the memory cells. As a result, semiconductor memory generally also includes an internal booster circuit for generating boosts above the external supply voltage Output signal. This boosts the paper Standards in use_CNS Standard A4 Specification-χ Norwegian public love) 91649-ΙΙΙΙΙΙΙΙΙΙΙΙΙ — ·! IIIIII «ΙΙΙΙΙ1ΙΙ — (Please read the precautions on the back before filling this page) 507201 A7 B7 V. Description of the invention (4) (Please read the note on the back to write this page first.) As shown in Figure 1, Road 16 is used to generate the word line supply voltage VpxG at node N1. This word line supply voltage VPXG is transmitted to the memory via column decoder 18. Appropriate zigzag lines in the different sectors S0 to S3 1 in the core array 10. The column decoder 18 is located at the center position between the left half sector array 12 and the right half sector array 4. The column decoder 18 is responsive to an address signal used to cause the word driver [not shown] to supply the word line supply voltage vpxG from the booster circuit 16 to the appropriate word line of the different sectors combined. Word line supply voltage VPXG-generally in the range of +3.7 volts to + 4 · 7 volts, this voltage range occurs higher than the normal +3.0 volt input power supply potential vcc. If it is assumed that the booster circuit 16 is located on the left side below the chip u, the section S23 is located close to the booster circuit 16 and the section S24 is located far away from the booster circuit 16. Therefore, the word line voltage VPXG1 from the node N2 to the word line combined with the segment S23 will be substantially equal to the boosted voltage VPXG from the ink raising circuit 16. This boosted voltage vpxG is the target voltage and it is hoped that it can be maintained across the entire wafer. However, combined with the segment line S24 to the node N3 to the word line voltage VPXG2 of the word line wlf printed by the employee consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, during the read mode operation, most of the sensing will be substantially smaller than the target voltage. Furthermore, it is assumed that the reference section or the extremely small array 20 is generally located close to the boost circuit 16. Therefore, considering the word line voltage when combining the reference section 20 with the node n4 and the word line WLR, it will also be substantially equal to the boosted voltage VPXG. The reference section or array 2 () includes a plurality of reference memory cells arranged in columns and rows [e.g. 20 × 20]. Resistor R1 represents the combination of the adjacent "near" segment S23 at node N2 and the adjacent "far," segment S24 between the nodes. (210 X 297) 4 91649 507201 Employees ’Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed 91649 A7 ____ B7 _ V. Description of the invention (5) Lumped resistance load of conductor line 21. Capacitor & represents the capacitive load when connected to the section selected by its combined word line. Used for the selected section The capacitive load Cs represents the same value regardless of its position in the memory core array 10. The capacitor CR represents the capacitive load at the input of the reference section or array 20 and has a value much smaller than that of the capacitor. For For high-speed read operations, during the time that the word line voltage is set, the core memory cells must be read before they reach the stabilization of the direct current [DC]. Therefore, when the word line WLR and WLF voltages are close to each other, they can Get the best continuous reading. Therefore, when comparing the reference word line of the reference or sector array 20 with the voltage “VPXG” and the “combined”, the voltage VPXG2 on the sub-line S24, they want There will be a large difference between them. This is based on the fact that the reference word line WLr held in the step-up circuit from the reference circuit 20 to the reference section 20, and the memory in the "far, section S24" The mismatch between the resistance and capacitance in the travel path of the core word line WLF. As a result, it is used during reading to cause bad edge sensing in the sensing circuit (not shown in Figure 1), especially for sensing the core memory cells of the conduction memory. In view of this, a word line tracking structure must be provided to match the reference of the segment position and the core word line voltage across the entire chip. The present invention completes this design by providing a second VPXG conductor line operatively connected between the "far," section and the section word line of the reference memory cell minimum array. This second VPXG conductor line is compared to the I VPXG conductor The line operation is connected between the boost circuit and the output of the word line in the "far" section, with a substantially smaller time constant. This paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) -~-— Ιίι — IllilIII-i I fi! II «!! ϊι! Ιιί (Please read the notes on the back before filling out this page) 507201 A7 B7 _ 一 ― ~ -------------- ----------V. Description of the Invention (6) [Summary of the Invention] Therefore, the general purpose of the present invention is to provide a word line tracking structure for flash EEPR0M memory configured into a plurality of sectors. The structure of the plurality of sections of the memory cell is relatively simple, easy to manufacture, and has an improved accuracy during reading compared to the prior art δ-memory device. An object of the present invention is to provide a word line tracking structure , Used to configure flash EEPROM memory cells into multiple sectors, convenient Avoid errors during reading. Another object of the present invention is to provide a word line tracking structure for flash EEPROM memory cells divided into a plurality of sectors, so as to match across the entire chip without regard to sector locations. Reference and segment core word line voltage. Another object of the present invention is to provide a word line tracking structure for flash EEPROM memory cells divided into a plurality of segments, the plurality of segments including a second VFXG The conductor line is operatively connected between the "far," segment and the segment word line of the reference memory cell minimum array. Printed in accordance with a preferred embodiment of the present invention by a consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is provided with a word line tracking structure for a semiconductor memory device having a flash EEPROM memory divided into a plurality of regions Body memory cell array. The word line tracking structure is used to match the reference of the segment position and segment core sub-line voltage across the entire chip. This word line chase structure includes a second VPXG conductor line, which is operatively connected between the "far" section and the section word line of the reference memory cell minimal array. The second VPXG conductor line is connected to the boost circuit and "Far, the first VPXG conductor line between the output of the segment sub-line of the segment has a substantially smaller size of this paper. The Chinese National Standard (CNS) A4 specification (210 X 297 mm) 91649 507201 A7 B7 4 Economy Printed by the Ministry of Intellectual Property Bureau's Consumer Cooperatives V. Invention Description (7) Time constant. [Brief description of the drawings] These and other objects and advantages of the present invention will become clearer from the following detailed descriptions and the accompanying drawings. The same reference numerals in the drawings indicate corresponding parts, where : Figure 1 is a simplified block diagram of a conventional 16 million-bit [Mb] EE PROM semiconductor integrated circuit memory device. The memory device has a memory cell array divided into a plurality of sections. · 2 Figures and Figure 3 show the individual “near,” and “far,” waveforms of various signals in the section “1”, which can be used to understand the problems encountered during reading; Figure 4 is constructed in accordance with the principles of the present invention. Simplified block diagram of a 16-Mbit EEPROM semiconductor integrated circuit memory device with word line tracking structure; Figures 5 and 6 show the individual "near," and "far," sections of Figure 4 The “Waveform” can be used to understand how to solve the reading problem. Figure 7 shows the waveforms of the reference cell word line voltage and the segment core word line voltage for the “far,” sections in Figures 1 and 4, respectively; And Figure 8 is a combination of Figure 4 Circuit diagram of the resistance and parasitic capacitance of the first and second vpxG conductor lines [Symbols] 10 Memory core array 11 H 99 r \ 12 Left half segment array [SO to S15] 14 Right half segment array [S16 to S31] 16 step-up circuit 18-column decoder This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 91649 -IIIIIIIIIIII — · II (Please read the precautions on the back before filling this page) · 507201 V. Description of the invention (8) A7-一 ___— B7 20 Reference section [minimum array] 21 Conductor lead S23 "Near" section S24 "Far" section 202, 204, 206 Curves 302 ~ 304, 306 Curve 400 Semiconductor integrated circuit memory device, please read back 410 memory core array 411 single chip 412 left half section 414 right half section note 416 boost circuit 420 reference section meaning 421 first VFXG conductor line 422 section Two VPXG conductor wires 1% 424 First end 426 Second end I S423 "Near" section S424 "Far" section 502, 504, 506 Curve 602, 604, 606 Curve 702, 704, 706 Curve [better Detailed description of the examples] Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the following will describe the zigzag tracking structure for flash EEPROM memory cells. In the following description, in order to fully understand the present invention, it is long: Many detailed instructions are given, such as specific circuit configurations, components, and so on. However, it is obvious to a person having ordinary skill in the art that the present invention is practical and does not require these specific detailed descriptions. In other examples, known processes, circuits, and control circuits are not particularly relevant to those who understand the operating principles of the present invention, and are omitted for clarity. Referring now to the drawings in detail, FIG. 4 shows a simplified block diagram of an EEPROM semiconductor integrated circuit memory device 400 formed on a single chip 411. This single chip 411 includes 16 million bits [Mb] Memory core array 4 1 0. Memory core array 4 1 0 by left half 4 12 and right 91649 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 507201 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs The invention description (9) is composed of half segments 4 and 14. The left half sector array 4 1 2 is composed of sixteen sectors S 4 0 to S 41 5. Similarly, the right half sector array 4 14 consists of sixteen sectors
S416至S431組成。區段S400至S431之各區段儲存512K 之資料位元，配置於5 12列和1 〇24行。應注意者複數個區 段S400至S431個別位於跨越整個晶片411。因此，角落 區段〔例如，區段S424〕和另一個角落區段〔例如，區段 S423〕之間之距離為非常長。再者，升壓電路416設於晶 片411之下左側部分，用來產生字線供應電壓VpxG。此 字線供應電壓VPXG經由列解碼器418和字線驅動器〔未 顯示〕通過於記憶體核心陣列4 1 〇中各不同區段之適當字 線。從升壓電路416來之字線供應電壓VPXG上升高於輸 入電源供應電位VCC。參考記憶胞極小陣列或參考區段 420定位於接近升壓電路416。參考區段42〇包括複數個配 置成列和行〔例如，20 x 20〕之參考記憶胞。再者，本發 明設有追蹤構造，用來以記憶體核心記憶胞之字線電壓而 追蹤參考記憶胞區段之字線電壓，不管含有記憶體核心記 憶胞之位置。 在詳細說明本發明之追蹤構造和其操作之前，藉由參 考起始說明於第1圖之EEPROM記憶體裝置中之施行讀取 操作，以及相關於第2圖和第3圖之有關問題，相信對於 對本發明之原裡之瞭解有所助益，並且可作為背景技藝。 、從第1圖和第2圖中可注意到，於讀取操作模式期間， 於選擇之“近，，區段S23之情況，開始於時間u，從升壓 電路之曲線202之上升電壓VPXG將上升高於輸入供 J^iIilii7i®S^NS)A4 (210 X 297 ) y — ” 91649 III —------- ---· I I I I ! I ! ^ « — IlilI — » (請先閱讀背面之注意事項再填寫本頁) 01 A7 B7S416 to S431. Each of the sections S400 to S431 stores 512K data bits and is arranged in 5 12 rows and 1024 rows. It should be noted that the plurality of sections S400 to S431 are individually located across the entire wafer 411. Therefore, the distance between the corner section [for example, section S424] and the other corner section (for example, section S423) is very long. Furthermore, a booster circuit 416 is provided on the left side under the wafer 411 to generate a word line supply voltage VpxG. This word line supply voltage VPXG is passed through the column decoder 418 and the word line driver [not shown] through the appropriate word lines in the different sections of the memory core array 4 10. The zigzag line supply voltage VPXG from the booster circuit 416 rises higher than the input power supply potential VCC. The reference memory cell minimal array or reference section 420 is positioned close to the boost circuit 416. The reference section 42 includes a plurality of reference memory cells arranged in columns and rows (e.g., 20 x 20). Furthermore, the present invention is provided with a tracking structure for tracking the word line voltage of the reference memory cell segment by the word line voltage of the memory core memory cell, regardless of the position of the memory core memory cell. Before explaining the tracking structure and operation of the present invention in detail, by referring to the reading operation performed in the EEPROM memory device illustrated in FIG. 1 and related problems related to FIG. 2 and FIG. 3, it is believed that It is helpful for understanding the original content of the present invention and can be used as background art. It can be noticed from FIG. 1 and FIG. 2 that during the read operation mode, in the case of the selected “near,” section S23, it starts at time u and rises from the voltage VVPSG of curve 202 of the boost circuit. Will rise higher than the input for J ^ iIilii7i®S ^ NS) A4 (210 X 297) y — ”91649 III —------- --- · IIII! I! ^« — IlilI — »(please (Read the notes on the back and fill out this page) 01 A7 B7
五、發明說明（10 ) 應電位VCC。因為參考區段20位於接近升壓電路16，· 於參考字線WLN上之曲線204之參考字線電壓將隨貝j 實質相等於上升電塵VPXG。當“近，，區段S23位於較參考 區段S20更遠離升壓電路16時，則字線wLn上之曲線\〇6 之字線電壓VPXG1將仍實質相等於上升電壓νρχ(}。再 者’當於時間t2發生實際讀取，則在參考字線電壓和“近” 區段字線電壓VPXGH僅有小的差值χ。此是可接受之 狀況且將不會引起讀取錯誤。 從第1和第3圖中可以注意到，於選擇“遠”區段S24 情況之讀取操作模式期間，於時間t3開始，從升壓電路16 之曲線302來之上升電壓VPXG將再上升高於供應電位 VCC。因為參考區段20是位於接近升壓電路丨6，則字線 WLN上之曲線304之參考字線電壓將再隨耦並實質相等於 上升電壓VPXG。然❿，因為“遠，，區段位於非常遠離升壓 電路16,則於曲段核心字線WLf上之曲線3〇6之字線電壓 VPXG2將不隨耦著上升電壓vpXG。此是由於於曲段字線 和參考字線至升壓電路之路徑之電阻和電容之不匹配的關 係。 此外，當於時間Η發生實際讀取，則在參考字線電壓 和區段字線電壓VPXG2之間會有大的差值γ。結果，由於 在感測電路中使用創造之較低的感測邊緣，則此電壓差將 在讀取中讀到錯誤。因此，施行於第丨圖中之讀取操作， 因為/又有追蹤參考子線電壓和區段字線電，則將承受造成 讀取錯誤之缺點。 · I I (請先閱讀背面之注意事項^寫本頁) 訂·5. Description of the invention (10) The potential VCC should be applied. Because the reference section 20 is located close to the boost circuit 16, the reference word line voltage of the curve 204 on the reference word line WLN will be substantially equal to the rising electric dust VPXG with j. When "close, the segment S23 is located farther away from the boost circuit 16 than the reference segment S20, then the word line voltage VPXG1 on the curve \ 06 on the word line wLn will still be substantially equal to the rising voltage νρχ (}.) 'When the actual reading occurs at time t2, there is only a small difference χ between the reference word line voltage and the "near" section word line voltage VPXGH. This is an acceptable condition and will not cause a reading error. From It can be noticed in Figs. 1 and 3 that during the reading operation mode in the case of the "far" section S24, starting at time t3, the rising voltage VPXG from the curve 302 of the booster circuit 16 will rise higher than Supply potential VCC. Because the reference section 20 is located close to the boost circuit 丨 6, the reference word line voltage of the curve 304 on the word line WLN is then coupled and substantially equal to the rising voltage VPXG. However, because "far, , The segment is located very far away from the boost circuit 16, then the word line voltage VPXG2 of the curve 306 on the core word line WLf of the curved section will not be coupled with the rising voltage vpXG. This is due to the curved section word line and the reference word The mismatch between the resistance and capacitance of the path from the line to the boost circuit. In addition, when the actual reading occurs at time 会有, there will be a large difference γ between the reference word line voltage and the segment word line voltage VPXG2. As a result, the lower sense created due to the use in the sense circuit Edge, this voltage difference will be read incorrectly during reading. Therefore, the reading operation performed in the figure 丨 will be subjected to reading due to / and tracking the reference sub-line voltage and section word line power. Disadvantages of Errors · II (Please read the precautions on the back ^ write this page) Order ·
經濟部智慧財產局員工消費合作社印製 本紙張尺錢财 CCNS)A4^ (210 x 297 ^) 10 91649 507201 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（11 ) 如此處所使用的，詞彙“邊緣，，定義為在記憶體核心位 元線和參考位元線之間所存在的電流之差。換言之，在感 測放大器能可靠地放大差值之前，在不同之電流之間必須 發展出適當之邊緣。再者，於位元線上之電流，將正比於 字線電壓和電晶體記憶胞之門限電壓之間的差值。因此， 若僅減少在區段中施加到記憶體核心記憶胞之字線電壓， 則差值電流將非常小，因此而引起讀取錯誤。 > 有鑑於此，本發明之發明人發展出字線追蹤結構，用 來匹配參考和區段核心字線電壓，跨越整個晶片而無關於 &段位置。換§之，相關於參考區段420於參考字線wxr 之電壓與相關於“遠’’區段或任何其間區段於區段核心字線 WLF之電壓之間之電壓差將維持很小而不管選擇之區段的 位置。因此，當讀取於陣列中之任何區段時，將要有充份 之感測邊緣，由此而避免任何錯誤。此是因為參考字線電 I壓追蹤區段核心字線電壓無關於區段位置之關係。 本發明之此種追蹤結構由更進一步延伸於第丨圖中來 自升壓電路16和返回至鄰接至升壓電路16位置之νρχσ 導體線的長度而達成。其次，升壓電路16之輸出節點ni 和相關於參考字線WLr之參考區段2〇之輸入之間之導體 線分開或脫接。因此，延長之VPXG導體線之末端結合參 考區段之輸入。 現回頭參照第4圖，能夠看出追蹤結構包括延長之或 具有第一端和第二端之第二VPXG導體線422。第二導體 線422之第一端連接於節點N3至原來的或第一 vpxG導 規格咖χ挪公爱1 91649 ------------I -ml —--^--1 ! ! !^^ (請先閱讀背面之注意事項再填寫本頁) 507201 A7 五、發明說明（12 ) (請先閱讀背面之注意事項Η 體線421之末端。應注意到原來的vpxG導體線々Η之末 端位於鄰接到相關於“遠，，區段S424之區段字線。導體線 422之第二端連接於節點N4之參考區段42〇。不像第1圖 之先前技藝，於升壓電路416之輸出之節點扪並不連接 到節點N4或參考區段420之輸入。由此種修飾模式，於 節點N4之參考字線WLr上之參考字線電麼將無關於區段 是在何位置，將接近追蹤於節點N3於區段字線之區 段核心字線電壓VPXG2。 ·Printed by a Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, a paper rule and money CCNS) A4 ^ (210 x 297 ^) 10 91649 507201 Printed by A7, a Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by A7 V. Description of the invention (11) As used here The word "edge" is defined as the difference in current between the core bit line and the reference bit line of the memory. In other words, before the sense amplifier can reliably amplify the difference, it must be between different currents. Develop a suitable edge. Furthermore, the current on the bit line will be proportional to the difference between the word line voltage and the threshold voltage of the transistor memory cell. Therefore, if only the core applied to the memory is reduced in the segment With the word line voltage of the memory cell, the difference current will be very small, which will cause a reading error. ≫ In view of this, the inventor of the present invention has developed a word line tracking structure to match the reference and segment core word lines Voltage across the entire chip without regard to the & segment position. In other words, the voltage associated with the reference segment 420 on the reference word line wxr and the voltage associated with the "far" segment or any interval in between The voltage difference between the voltage of the core wordline WLF will remain small regardless of the position of the selected segment. Therefore, when reading any section in the array, there will be sufficient sensing edges to avoid any errors. This is because the core word line voltage of the reference word line voltage tracking section has no relation to the position of the section. The tracking structure of the present invention is achieved by further extending the length of the νρχσ conductor line from the booster circuit 16 and returned to the position adjacent to the booster circuit 16 in the figure. Next, the conductor line between the output node ni of the booster circuit 16 and the input of the reference section 20 related to the reference word line WLr is separated or disconnected. Therefore, the end of the extended VXPG conductor is combined with the input of the reference section. Referring back to FIG. 4, it can be seen that the tracking structure includes an extended or second VFXG conductor line 422 having a first end and a second end. The first end of the second conductor line 422 is connected to the node N3 to the original or the first vpxG guide specification 挪 Nuo Gongai 1 91649 ------------ I -ml --- ^- 1!!! ^^ (Please read the precautions on the back before filling this page) 507201 A7 V. Description of the invention (12) (Please read the precautions on the back first) The end of the body line 421. The original vpxG conductor should be noted The end of the line is located adjacent to the word line of the segment related to "Far, S424. The second end of the conductor line 422 is connected to the reference segment 42 of the node N4. Unlike the prior art in Figure 1, The node 输出 at the output of the boost circuit 416 is not connected to the input of the node N4 or the reference section 420. With this modification mode, the reference word line on the reference word line WLr of the node N4 will have no relation to the section Where is it going to be close to the core word line voltage VPXG2 of the segment that is tracked from node N3 to the segment word line?
從第4和第5圖可以看出，於讀取操作模式期間，對 於選擇“近”區段S423之情況，從升壓電路416之曲線5〇2 之上升電壓VPXG開始於時間t5，將再上升高於電源供應 電位VCC。值得注意的是，於參考字線WLr上之曲線5〇4 之參考字線電壓將不隨耦著上升電壓VPXG。由於切斷節 點N1與N4與額外的第二VPXG導體線422之間之連接， 上升之電壓VPXG必須通過導體421和422以到達節點 N4。如所觀察之，曲線5〇4之參考字線電壓現將隨耦著並 實質相等於在字線WLN上之曲線506之字線電壓 經 濟 VPXG1 〇 再者， 於時間 t6， 當發生實 際讀 取時 ，仍有小的 部 智 差 值X 1在參考字線電壓和“ 近”區段字線電壓VPXG 1之 財 產 間 〇 局 員 工 從 第 4和第 6圖中 可看 到，對於 選擇 “遠” 區段S424 消 費 之 情況 之 操作讀 取模式 期間 ，從升壓 電路 416 之曲線602 合 作 社 之 上升 之 電壓VPXG , 開始: 於時間t7 ，將- 再上- 斤高於電源 印 製 供 應電 位 VCC 〇 然而， 於此 時間值得 注意 的是 ，曲線604 本紙張尺度適財關家鮮（CNS)A4規格石Q χ 297公爱）_ 91649 經濟部智慧財產局員X消費合作社印制衣 五、發明說明（13 y 之參考字線電壓將隨耦著並實質相等於曲線606之曲段字 線電壓VPXG2。於時間t8，當發生實際讀取時，顯示此時 仍有小的差值Y1在參考字線電壓和“遠”區段字線電壓之 間。其結果，於操作讀取模式期間，免除了錯誤發生之可 能性。 於本發明中’由於事實上從相關於選擇之區段s424 I之電谷器Cs之電各性負載係相當地大於相關於參考區段 420之電令器CR之電容性負載〔參考極小陣列之等效電 各〕’則於參考字線WLr上之電壓將隨耦著於區段核心字 線WLf之電壓。因此，沿著延長之VPXG導體線422上之 4號則進延遲為相當地減少，此延遲遭遇著沿著第一 VPXG導體線421。結果，經由相關導電體421之集總電 阻負載R1之延遲係主要由時間長數R1Cs主控。 於此技藝方面的相關技術人員將可清楚地瞭解到，若 _電容器Cs為沿著導體線421部分地連接〔例如，選用區段 S420〕’則從節點N2至區段S420之長度電阻值能考慮作 為具有由時間常數RlaCs主控結果延遲量之Rla值。於此 情況’集總電阻負載R2之實際值將是由於R2和延伸越過 選擇之區段S420之點R1之部分的總和。 然而，如上定義之對於多數的Rla值，延遲由時間常 數RlaCs為主，以及於節點N4之電壓由於相對較短時間 常數R2Cr的關係，則將緊隨著選擇之區段字線電壓。結 果’因為時間常數R1 aCs為主之關係，對於沿著導體線42 1 之任何位置之電容器Cs，於節點N4之電壓將實質地隨耦 n n ϋ n n n n n n n n ϋ I 0 i n 1 i- ti n u 訂——-----線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 13 91649 507201 A7 五、發明說明（14 著選擇之區段字線電壓。 於第7圖中’分別描繪了對於第1和第4圖中之“遠，， 區段於讀取模式期間參考字線電壓和區段核心字線電壓之 波形。曲線702表示於第i圖之先前技藝‘‘遠，，區段讀取期 間之參考子線電壓，而曲線7〇4表示讀取期間之區段核心 字線電壓。藉由比較曲線7〇2和曲線7〇4，能夠看出他們 之間之差值w顯示了存在參考字線電壓和區段核心字線電 壓之間的大電壓差。於另一方面，曲線706表示於第4圖 之本發明對於“遠，，區段讀取期間之參考字線電壓，而曲線 708表示讀取期間之區段核心字線電壓。藉由比較曲線7〇6 和曲線708，能夠看出他們之間之差值wl，顯示了參考字 線電壓和區段核心字線電壓之間存在了非常小之電壓差。 於第8圖中，顯示存在於第4圖之原有的或第一 VPXG 導體線421之升壓電路416和相關於“遠，，區段之區段字線 wlf之間之電阻和寄生電容，和相關於“遠，，區段之區段字 線WLF和相關於參考區段420之參考字線WLr之間延伸 的VPXG導體線422之電阻和寄生電容之電路圖。藉由本 發明之額外的延長VPXG導體線422，於節點N3和N4之 間於路徑上之延遲特性或時間長數將製得小於在節點N1 和N3之間原有的VPXG導體線421。 從則述之詳細說明，因此能瞭解到本發明提供一種用 於快閃EEPROM記憶體記憶胞之字線追縱結構，此等記憶 體記憶胞分成複數個區段以便能匹配參考和區段核心字線 電麼’跨越整個晶片而無關於區段位置。本發明之字線追 C請先閱讀背面之注意事項再_寫本頁) . 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 14 91649 507201 4 A7 B7 五、發明說明（15 ) 縱結構包括操作連接於“遠，，區段之區段字線和參考記憶胞 極小陣列之間之第二VPXG導體線。第二VPXG導體線較 之操作連接於升壓電路之輸出和“遠”區段之區段字線之間 之第一 VPXG導體線具有實質較小之時間常數。 雖然現在已考慮顯示並說明了本發明之較佳實施例， 然應瞭解到於此技藝方面之這些技術人員，可作各種之改 變和修飾，並將其元件作等效之替代，而仍不脫離本發明 之範圍。此外，可對本發明之教示作許多之修飾調整特定 之位置或材料，而仍不脫離本發明之中心範圍。因此，本 說明書並非欲以所考慮實施本發明而揭示作為最佳模式之 特殊實施例來限制本發明，而是本發明將包括所有落於所 附申請專利範圍内的所有實施例。 • I --^1! — — — - · 1 I (請先閱讀背面之注意事項再填寫本頁) •線· 經濟部智慧財產局員工消費合作社印製 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 15 91649It can be seen from FIGS. 4 and 5 that during the read operation mode, for the case of selecting the “near” section S423, the rising voltage VPXG from the curve 50 of the boost circuit 416 starts at time t5, and will be Rise above the power supply potential VCC. It is worth noting that the reference word line voltage of the curve 504 on the reference word line WLr will not be coupled with the rising voltage VFXG. Since the connection between the nodes N1 and N4 and the additional second VXPG conductor line 422 is cut off, the rising voltage VpxG must pass through the conductors 421 and 422 to reach the node N4. As observed, the reference word line voltage of curve 504 will now be coupled and substantially equal to the word line voltage economy VPXG1 of curve 506 on word line WLN. Furthermore, at time t6, when the actual reading occurs At the time, there is still a small intellectual difference X 1 between the reference word line voltage and the "near" section word line voltage VPXG 1. The staff of the bureau can see from Figures 4 and 6, that During the operation read mode in the case of consumption in section S424, the voltage VPXG rising from the curve 602 of the booster circuit 416 of the cooperative VC starts at: at time t7, it will be-again-higher than the power supply printed supply potential VCC. However, it is worth noting at this time that the curve 604 paper size is suitable for wealth and family (CNS) A4 size stone Q χ 297 public love _ 91649 Member of the Intellectual Property Bureau of the Ministry of Economic Affairs X Consumer Cooperatives printed clothes The reference word line voltage of 13 y will be coupled and substantially equal to the curved line word voltage VVPG2 of curve 606. At time t8, when the actual reading occurs, it shows that there is still a small difference Y1 at the time. Between the word line voltage and the word line voltage of the "far" section. As a result, during the operation read mode, the possibility of an error is avoided. In the present invention, 'as a matter of fact, it is related to the selected section s424 I The electric load of the electric valley device Cs is considerably larger than the capacitive load of the electric commander CR related to the reference section 420 (equivalent electric reference of the reference minimum array). Then the voltage on the reference word line WLr will be With the voltage coupled to the core word line WLf of the segment. Therefore, the delay along No. 4 on the extended VPXG conductor line 422 is considerably reduced, and this delay encounters the first VPXG conductor line 421. As a result, The delay of the lumped resistive load R1 via the relevant conductor 421 is mainly controlled by the time length R1Cs. Those skilled in the art will clearly understand that if the capacitor Cs is partially along the conductor line 421 Connect [for example, select section S420] ', then the length resistance value from node N2 to section S420 can be considered as the Rla value with the delay amount controlled by the time constant RlaCs. In this case, the actual value of the lumped resistive load R2 Value will be by Sum at R2 and the portion of R1 that extends beyond the selected section S420. However, for most Rla values as defined above, the delay is dominated by the time constant RlaCs, and the voltage at node N4 is due to the relatively short time constant R2Cr Relationship, it will closely follow the selected word line voltage. As a result, because the time constant R1 aCs is the main relationship, for the capacitor Cs at any position along the conductor line 42 1, the voltage at node N4 will be substantially Follow the coupling nn ϋ nnnnnnnn ϋ I 0 in 1 i- ti nu Order ------- line (Please read the precautions on the back before filling this page) This paper size applies Chinese National Standard (CNS) A4 specifications (210 x 297 mm) 13 91649 507201 A7 V. Description of the invention (14 The word line voltage of the selected sector. In FIG. 7 ', the waveforms of the reference word line voltage and the core word line voltage of the segment during the read mode are depicted in FIG. 1 and FIG. 4, respectively. The curve 702 is shown in FIG. The “previous technique” is far from the reference sub-line voltage during the segment read, and the curve 704 represents the core word line voltage of the segment during the read. By comparing curve 702 and curve 704, it is possible to It can be seen that the difference w between them shows that there is a large voltage difference between the reference word line voltage and the segment core word line voltage. On the other hand, the curve 706 shown in FIG. The reference word line voltage during a sector read, and curve 708 represents the core word line voltage during a sector read. By comparing curve 706 and curve 708, it can be seen that the difference w1 between them shows that there is a very small voltage difference between the reference word line voltage and the segment core word line voltage. In FIG. 8, the resistance and parasitic capacitance between the step-up circuit 416 of the original or first VPXG conductor line 421 existing in FIG. 4 and the word line wlf related to the “far,” section are shown. And a circuit diagram of the resistance and parasitic capacitance of the VFXG conductor line 422 extending between the segment word line WLF and the reference word line WLr of the reference segment 420. With the additional extension of the VFXG conductor line 422 of the present invention, the delay characteristics or the length of time on the path between the nodes N3 and N4 will be made smaller than the original VPXG conductor line 421 between the nodes N1 and N3. From the detailed description, it can be understood that the present invention provides a zigzag trace structure for flash EEPROM memory cells. The memory cells are divided into a plurality of sectors so as to match the reference and sector cores. The word line is 'spanned' across the entire wafer regardless of segment location. Please read the precautions on the back of the zigzag C of this invention before writing this page). Printed on the paper by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper applies the Chinese National Standard (CNS) A4 (210 X 297 mm) 14 91649 507201 4 A7 B7 V. Description of the invention (15) The longitudinal structure includes a second VFXG conductor line operatively connected between the segment word line of the "far," section and the minimum array of reference memory cells. The second VFXG conductor line It has a substantially smaller time constant than the first VPXG conductor line which is operatively connected between the output of the boost circuit and the section word line of the "far" section. Although the present invention has now been considered to show and illustrate the better of the present invention For the embodiments, it should be understood that those skilled in the art can make various changes and modifications, and substitute equivalent elements without departing from the scope of the present invention. In addition, the teachings of the present invention can be made. Many modifications are made to adjust a specific position or material without departing from the central scope of the present invention. Therefore, this description is not intended to disclose the specific implementation as the best mode in consideration of implementing the present invention. Examples to limit the present invention, but the present invention will include all embodiments falling within the scope of the attached patent application. • I-^ 1! — — —-· 1 I (Please read the notes on the back before filling (This page) • Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297 mm) 15 91649