504810 A7 B7 五 、發明说明（ 10 15 經濟部智慧財產局員工消費合作社印製 20 本發明係與晶片構裝有關，更詳而言之是指一種低應 力之晶片構裝。 由於一般的積體電路晶片皆極為脆弱，無法直接使用 或裝置’因此必須在該晶片之外部施以適當之構裝並將其 電性傳導於外，方能確保在使用時不易因外力之破壞而損 壞。 而一般習知之晶片構裝（1)，如笫一圖所示，乃具有一 載體(2)，該載體(2)形成有一開口向上之容室(2a); —積體 電路晶片（3)，係藉由一黏著物（4)塗佈於其一端面上，而 可黏貼於该载體（2)之容室（2a)底部（2b)，並藉由多數之銲 線（5)將其電性傳導於該載體（2)上，而可藉由該載體(2)與 外界連接’而將該晶片（3)之電性導通於外界者，該載體（2) 上更罩設有一封蓋（6)，係用以封閉該容室（2a)，使該晶片 (3)可不受外力之破壞或污染者。 惟’由於該載體（2)與該晶片（3)係分別由兩種完全不同 之材質所製成，該载體（2)—般係為塑膠或玻璃纖維（熱膨 脹係數為19X10·6)，而該晶片（3)則係為矽合金（熱膨脹係 數為4X10’ ；由於此兩種不同之材質，將使得該載體(2) 之熱膨脹係數約為該晶片（3)的四倍之多，使該構裝（1)在 進行模壓或運作之同時，該載體（2)與該晶片（3)極易遭受 周遭環境溫度改變之影響，會有類似Bimetal現象而產生 物理變化，致接合之兩者發生撓曲或變形之情形，並會使 得其應力集中在兩者之黏接處’且由於該晶片（3)係將其一 端面完全黏貼於該載體（2)上，使得黏接處之長度或面積大 請 先 閱 讀 背 面 之 項 裝 訂 -3· 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X 297公釐） 504810 A7 經濟部智慧財產局員工消費合作社印製 B7五、發明説明（） 增，進而使其黏接處之應力亦隨之增加（如笫二圖所示）， 將使得該載體(2)在發生撓曲之同時，會有牽動或壓迫該晶 片（3)發生撓曲或破裂之情事產生。 有鑑於上述之種種缺失，本案發明人乃經詳思細索， 5 並累積多年從事晶片構裝製造及研究開發之經驗，終而有 本發明之產生。 亦即本發明之主要目的乃在提供一種低應力之晶片構 裝，係可減低晶片所遭受之應力，而減少晶片掼壞之情形 者。 1〇 緣此，本發明所提供一種低應力之晶片構裝，其主要 包含有：一載體；一晶片單元，係藉由一黏著物之塗佈， 而以其一端面具有一局部貼接處貼接於該載體上，且該黏 著物係自該晶片之中心點向外於四周塗佈，並以不塗佈至 該晶片單元之周緣為原則；多數之銲線，係用以將該晶片 15 單元電性導通於該載體者；一罩體，係罩設於該載體上， 用以封閉該晶片單元，以避免該晶片單元受外力之破壞或 雜物之污染者。 為使審查委員能更詳細暸解本發明之實際構造及特 點，茲列舉以下實施例並配合圖示詳細說明如后，其中： 20 笫一圖係一種習用晶片構裝結構之剖視示意圖； 笫二圖係習用晶片構裝之撓曲示意圖； 笫三圖係本發明笫一較佳實施例之剖視圖； 笫四圖係本發明笫二較佳實施例之剖視圖； 笫五圖係本發明笫三較佳實施例之剖視圖；_^^_ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） (請先閲讀背面之注意事項再填| 裝·504810 A7 B7 V. Description of the invention (10 15 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 20 This invention is related to wafer fabrication, and more specifically refers to a low-stress wafer fabrication. Because of general integration Circuit chips are extremely fragile and cannot be used or installed directly. Therefore, proper construction must be applied to the outside of the chip and it must be electrically conducted to ensure that it is not easily damaged by external forces during use. The conventional wafer structure (1), as shown in the first figure, has a carrier (2), which is formed with a container chamber (2a) with an opening upward;-integrated circuit wafer (3), the system An adhesive (4) is coated on one end surface, and can be adhered to the bottom (2b) of the container (2a) of the carrier (2), and electrically charged by most of the bonding wires (5). Sexual conduction on the carrier (2), and the chip (3) can be electrically connected to the outside by connecting the carrier (2) to the outside, and a cover is provided on the carrier (2) (6) is used to close the container (2a) so that the wafer (3) can not be damaged or polluted by external force; Since the carrier (2) and the wafer (3) are made of two completely different materials, respectively, the carrier (2) is generally plastic or glass fiber (the coefficient of thermal expansion is 19X10 · 6), and the The wafer (3) is a silicon alloy (the thermal expansion coefficient is 4X10 '; due to the two different materials, the thermal expansion coefficient of the carrier (2) will be about four times that of the wafer (3), making the structure (1) While being molded or operated, the carrier (2) and the wafer (3) are extremely susceptible to changes in the ambient temperature, and there will be physical changes similar to the Bimetal phenomenon, which will cause the jointed two to flex. Or deformation, and will cause its stress to be concentrated on the bonding of the two 'and because the wafer (3) completely adheres one end surface to the carrier (2), the length or area of the bonding is large Please read the item binding on the back -3. This paper size is applicable to China National Standard (CNS) A4 specification (210X 297 mm) 504810 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Stresses The subsequent increase (as shown in the second figure) will cause the carrier (2) to flex or cause the wafer (3) to flex or rupture at the same time as the flexing occurs. In view of the above, Lack, the inventor of this case has carefully considered, 5 and accumulated years of experience in wafer assembly manufacturing and research and development, and finally has the invention of the invention. That is, the main purpose of the invention is to provide a low-stress wafer The structure can reduce the stress suffered by the wafer and reduce the damage of the wafer. 10 Because of this, the present invention provides a low stress wafer structure, which mainly includes: a carrier; a wafer unit, It is coated by an adhesive, and a part of the mask at one end is attached to the carrier, and the adhesive is applied from the center point of the wafer outwards and around, and does not apply. The principle is to distribute to the periphery of the wafer unit; most of the bonding wires are used to electrically connect the 15 units of the wafer to the carrier; a cover is set on the carrier to close the wafer unit, To avoid the wafer sheet By polluters or external damage of the debris. In order to enable the review committee to understand the actual structure and characteristics of the present invention in more detail, the following examples are described in detail with the illustrations as follows, where: 20 (a) is a schematic cross-sectional view of a conventional wafer structure; (2) The figure is a schematic diagram of the deflection of the conventional wafer structure; the third figure is a cross-sectional view of the first preferred embodiment of the present invention; the fourth figure is a cross-sectional view of the second preferred embodiment of the present invention; Sectional view of the best embodiment; _ ^^ _ This paper size is applicable to China National Standard (CNS) A4 (210X 297 mm) (Please read the precautions on the back before filling |
、1T 線- 笫六圖係本發明笫四較佳實施例之剖視圖； 笫七圖係本發明笫五較佳實施例之剖視圖； 請先參閱笫三圖，係本發明笫一較佳實施例所提供之 低應力晶片構裝（10) ’其主要包含有一載體、一晶片 單元（30)、一黏著物（32)、多數之銲線(40)及一罩體（50); 其中； 該載體(20)係可為塑膠、強化塑膠、玻璃纖維或陶瓷·. 等；f才質所製成之電路板(Printed Circuit Board，PCB)， 町作為該構裝結構（10)與外界電性連接之媒介；該載體(20) 具有一頂面（21)及一位於該頂面（21)反侧之底面（22)，該頂 面（21)向下凹陷延伸而形成有一容室（23)，該容室（23)具有 /底部（231)，該底部（231)更於其中心處向下凹陷而形成 /缺槽（232)，且該頂面（21)上佈設有呈預定數量及態樣之 電路（圖中未示）， 該晶片單元（30)，係為一積體電路晶片（31)，並藉由環 氣樹脂、矽樹脂、低溶點之玻璃或雙面膠帶…等其中之一 黏著物（32)，直接以其一端面黏著固定於該載體（2〇)容室 (23)之底部（231)上，且該黏著物（32)塗佈於該晶片（31)上 之面積’係自該晶片（31) —端面之中心點處，向四周延伸 蓋可足以固定及平衡該晶片（31)之最小寬度，但以不塗佈 爻該晶片（31)之周緣為原則，使該晶片（31)端面形成有一 局部貼接於該載體（20)上之貼接處，且該黏著物（32)係位 於該底部（231)之缺槽（232)中； 504810 A7 ______ B7 五、發明説明（） 該等銲線（40)，係由黃金或鋁等導電金屬材質所製 成，係利用打線技術先將該等銲線(4〇)之一端與該晶片（31) 連接，另一端則以幾近水平延伸之方式與該載體（2…頂面 (21)之電路呈電性連接； 5 該罩體（50) ’係由不透明之塑膠、金屬或透明之玻 璃、塑膠等材質所製成之板件，其具有一頂面（5丨）及一底 面（52);該底面（52)係藉由一黏結物（53)而結合於該載體 (20)之頂面（21)上，而可封抵住該容室（23)，以保護位在該 各室（23)中之晶片（31)不受外力破壞或雜物之污染者。 10 在此需特別說明的是，該黏著物（32)於該晶片（31)與該 載體（20)底部（231)間之黏結面積，係由該晶片（31)—端面 之中心點，向四周延伸至足可將該晶片（31)固定及平衡於 該載體（20)上之最小面積為原則，且係在不塗佈至該晶片 (31)之周緣下，使該晶片（31)可藉由該黏著物（32)而與該載 15 體(20)黏結固定；由於該晶片（31)與載體(20)間之黏結面積 經濟部智慧財產局員工消費合作社印製 及長度縮減，而可使該載體(20)在發生撓曲變形時，對該 晶片（31)所產生之應力相對縮減至最小，使該晶片（31)受 該載體（20)撓曲而破壞之情形大幅減少，並且由於該晶片 (31)與該載體（20)黏著時，該黏著物（32)係位於於該底部 2〇 (231)之缺槽（232)中，使該晶片（31)黏結之端面上未塗佈黏 著物（32)之處，可略與該底部（231)接觸，以增加黏接之兩 者間之結構強度，以避免於該晶片（31)上打線時發生偏斜 崩裂之情事。 ^_:_______ -6- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 五、發明説明（） 上述構裝（10)於使用時，可利用鍚銲或其它電性連接 之方式，將該載體（20)與組裝有必要電子元件之電路板（圖 中未示）連接即可。 請參閱笫四圖，係本發明笫二較佳實施例所提供之低 5應力晶片構裝（60)，其同樣包含有一載體（61)、一晶片單 元（62)、一黏著物（63)、多數之銲線(64)及一罩體（65);其 與上述實施例之主要差異在於： 其中’載體（61)之容室（611)底部（612)係佈設有呈預定 數量及態樣之電路（圖中未示），並藉由該等銲線（64)與該 10 晶片（62)呈電性連接者； 該罩體（65)，係由不透明之塑膠、金屬所製成之板 件，其具有一通孔（651)，該通孔（651)係對應該晶片（3〇)之 位置，且該通孔（651)中至少封設固定有一鏡片（652)，可 使外部之光線由該鏡片（652)穿透並照射於該晶片（62)上 b 者； 經濟部智慧財產局員工消費合作社印製 其次，該晶片（62)與該載體（61)間更設置有一墊片 (66)，該墊片（66)係位於該黏著物（63)之周邊，而可用以支 杈或增加該晶片（62)與該載體（61)間之連結關係強度者， 且由於該墊片（66)僅係置於該晶片（62)與該載體（61)間，並 2〇未與孩晶片（62)呈直接黏結，而可使該載體（61)不會藉由 該墊片（66)對該晶片（62)產生或傳導應力者。 請參閱笫五圖，係本發明笫三較佳實施例所提供之低 應力晶片構裝(70)，其同樣包含有一载體（71)、一晶片單 504810 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（） 元（72)、一黏著物（73)、多數之銲線(74)及一軍體（75);其 與上述實施例之主要差異在於： 該黏著物（73)係自該晶片（72)—端面之中心點處於外， 向四周延伸預定距離之位置上塗佈，且其塗佈之位置係未 5 超出於該晶片（72)之周緣，並且也不往内塗佈至晶片（72) 之中心點，使該晶片（72)端面上形成至少二左右對稱而互 不接觸，並以局部貼接於該載體（71)上之貼接處，而將該 晶片（72)貼接於該載體(71)之底部（711)上； 其次，該晶片（72)與該載體（71)間更設置有一墊片 10 (76)，該墊片(76)係位於該黏著物（73)之周邊（即係位於該 二貼接處之周邊），而可用以支撐或增加該晶片（72)與該載 體（71)間之連結關係強度，且不會對該晶片（72)產生或傳 導應力者。 請參閱笫六圖，係本發明笫四較佳實施例所提供之低 15 應力晶片構裝（80)，其同樣包含有一載體（81)、一晶片單 元（82)、一黏著物（83)、多數之銲線(84)及一罩體（85);其 與上述實施例之主要差異在於： 其中，該晶片單元（82)係具有一積體電路晶片（821)及 一載板（822);該晶片（821)係藉由一黏結物（823)以整面塗 2〇 佈之方式與該載板（822)之一端面黏結，而該載板（822)則 係以局部塗佈之方式藉由該黏著物（83)與該載體（81)之底 部（811)黏結，且該載體（81)之底部（811)形成有一缺槽 (812)，使該黏著物（83)可位於該嵌槽（812)之中，且該載板 -8- 本紙張尺度適用中國國家榡準（CNs ) A4規格（210'乂297公釐） (請先閲讀背面之注意事項再填、 裝· 訂 線 504810 A7 B7 五、發明説明（) (822)之熱膨脹係數係與該晶片（821)之熱膨脹係數相近 者； 藉由上述之結構可知，該載板（822)與該載體（81)間係 以局部黏著，可使得該載體（81)對該載板（822)產生不良影 5 響之情事大為減少，且由於該載板（822)之熱膨脹係數與該 晶片（821)之熱膨脹係數相近，更可使得與之黏結之晶片 (821)發生變形或撓曲之情事縮減，對該晶片（821)而言， 係具有雙重之保護效果。 請參閱笫七圖，係本發明笫五較佳實施例所提供之低 10 應力晶片構裝(90)，其同樣包含有一載體（91)、一晶片單 元（92)、一黏著物（93)、多數之銲線(94)及一罩體（95);其 與上述實施例之主要差異在於： 該晶片單元（92)具有二積體電路晶片（921 )(922)及一載 板（923);其中，該二晶片（921)(922)係置設於該載板（923) 15 上，並藉由該等銲線(94)將該晶片（921)(922)電性連接於該 載板（923)及該載體（91)之底部（911)上，使該構裝（90)可同 時具有二晶片（921)(922)之功效者，且該載板（923)與該載 體(91)間係具有二貼接處，係分別正對於該晶片（921)(922) 之下方者。 20 综上所述，本發明低應力之晶片構裝，確實具有縮減 對晶片產生應力之功效，實具其進步實用性，且在使用上 之方便，又，本發明於申請前並無相同物品見於刊物或公 開使用，是以，本發明實已具備發明專利要件，為保障發 明人之苦思，爰依法提出申請。 25 _____ 冬 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） (請先閲讀背面之.注意事項再填· 頁 、τ 經濟部智慧財產局員工消費合作社印製 504810 A7 B7 五、發明説明（ 10 15 經濟部智慧財產局員工消費合作社印製 20 簡單圖示說明： 笫一圖係一種習用晶片構裝結構之剖視示意圖 笫二圖係習用晶片構裝之撓曲示意圖。 笫三圖係本發明笫一較佳實施例之剖視圖。 笫四圖係本發明笫二較佳實施例之剖視圖。 笫五圖係本發明笫三較佳實施例之剖視圖。 笫六圖係本發明笫四較佳實施例之剖視圖。 笫七圖係本發明笫五較佳實施例之剖視圖。 圖號說明： 「笫一較佳實施例」 低應力晶片構裝（10) 載體(20) 頂面（21) 底部（231) 缺槽（232) 黏著物（32) 銲線(40) 底面（52) 黏結物（53) 「笫二較佳實施例」 低應力晶片構裝(60) 載體(61) 容室（611) 黏著物（63) 銲線(64) 鏡片（652) 墊片（66) 「笫三較佳實施例」 低應力晶片構裝(70) 載體(71) 底部（711) 請 先 閲 讀 背 面 之 注·Line 1T-Figure 26 is a sectional view of the twenty-fourth preferred embodiment of the present invention; Figure 7 is a sectional view of the twenty-fifth preferred embodiment of the present invention; please refer to Figure 3 first, which is the first preferred embodiment of the present invention. The provided low-stress wafer structure (10) 'mainly includes a carrier, a wafer unit (30), an adhesive (32), most bonding wires (40), and a cover (50); wherein; the The carrier (20) can be plastic, reinforced plastic, fiberglass, or ceramics, etc .; a printed circuit board (PCB) made of f is used as the structural structure (10) and is electrically connected to the outside world. The carrier (20) has a top surface (21) and a bottom surface (22) located on the opposite side of the top surface (21). The top surface (21) extends downwardly to form a container (23). The accommodating chamber (23) has a bottom portion (231), and the bottom portion (231) is recessed downward at a center thereof to form a slot (232), and the top surface (21) is provided with a predetermined number and state. Such a circuit (not shown in the figure), the chip unit (30) is a integrated circuit chip (31), and is made of an epoxy resin, a silicon resin, The melting point of glass or double-sided tape ... and one of the adhesives (32) is directly fixed on the bottom (231) of the carrier (20) container (23) with one end surface, and the adhesive ( 32) The area coated on the wafer (31) is from the center point of the end face of the wafer (31). The cover extending around can be sufficient to fix and balance the minimum width of the wafer (31), but it is not coated. The principle is to arrange the periphery of the wafer (31), so that the end surface of the wafer (31) is formed with an abutment portion that is locally attached to the carrier (20), and the adhesive (32) is located at the bottom (231) In the missing slot (232); 504810 A7 ______ B7 V. Description of the invention () These welding wires (40) are made of conductive metal materials such as gold or aluminum. They are firstly made using wire bonding technology ( 4〇) One end is connected to the chip (31), and the other end is electrically connected to the circuit of the carrier (2 ... the top surface (21) in a manner of almost horizontal extension; 5 the cover (50) 'system Plates made of opaque plastic, metal or transparent glass, plastic and other materials, which have a top surface (5 丨) and a bottom Surface (52); the bottom surface (52) is bonded to the top surface (21) of the carrier (20) by a sticker (53), and can be sealed against the receptacle (23) to protect the position Those wafers (31) in the chambers (23) are not damaged by external forces or contaminated by debris. 10 It should be particularly noted here that the adherent (32) is on the wafer (31) and the carrier (20) ) The bonding area between the bottom (231) is the minimum area extending from the center point of the chip (31) to the end face to the periphery to the minimum area where the chip (31) can be fixed and balanced on the carrier (20). And is not coated on the periphery of the wafer (31), so that the wafer (31) can be bonded and fixed to the carrier 15 (20) by the adhesive (32); because the wafer (31) The bonding area between the carrier and the carrier (20) is printed and shortened by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, so that when the carrier (20) is deformed, the stress on the wafer (31) is relatively reduced. To the minimum, the situation that the wafer (31) is damaged by flexing of the carrier (20) is greatly reduced, and because when the wafer (31) is adhered to the carrier (20), the The adhesive (32) is located in the notch (232) of the bottom 20 (231), so that the end where the wafer (31) is bonded is not coated with the adhesive (32), and can be slightly different from the bottom ( 231) contact to increase the structural strength between the two to avoid adhesion and cracking when the wire is wired on the chip (31). ^ _: _______ -6- This paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) V. Description of the invention () The above structure (10) can be used by welding or other electrical connections when in use. By way of example, the carrier (20) can be connected to a circuit board (not shown) in which necessary electronic components are assembled. Please refer to FIG. 4, which is a low 5 stress wafer structure (60) provided by the second preferred embodiment of the present invention, which also includes a carrier (61), a wafer unit (62), and an adhesive (63). The majority of the welding wires (64) and a cover (65); the main differences from the above embodiment are: Among them, the bottom (612) of the container (611) of the container (61) is provided with a predetermined number and state The circuit (not shown), and the electrical connection between the bonding wire (64) and the 10 chip (62); the cover (65) is made of opaque plastic, metal The plate has a through hole (651) corresponding to the position of the wafer (30), and at least a lens (652) is fixed and fixed in the through hole (651), so that the outside can be The light is penetrated by the lens (652) and shines on the wafer (62); the second is printed by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and there is a pad between the wafer (62) and the carrier (61) Sheet (66), the gasket (66) is located around the adhesive (63), and can be used to branch or increase the wafer (62) and the carrier (61) The strength of the connection relationship, and because the gasket (66) is only placed between the wafer (62) and the carrier (61), and is not directly bonded to the child wafer (62), the carrier can be made (61) Those who do not generate or conduct stress on the wafer (62) through the spacer (66). Please refer to Figure 5. This is the low stress wafer structure (70) provided by the preferred embodiment of the invention. It also contains a carrier (71) and a wafer sheet. 504810 A7 B7 Employees ’Intellectual Property Bureau Printed by the cooperative V. Description of the invention () Yuan (72), an adhesive (73), most of the welding wires (74) and an army (75); the main differences from the above embodiment are: the adhesive (73 ) Is applied from the wafer (72)-the center point of the end face is outside, and the coating is extended to a predetermined distance around the position, and the coating position is not more than 5 beyond the periphery of the wafer (72), and does not go It is internally applied to the center point of the wafer (72), so that at least two left-right symmetry is formed on the end face of the wafer (72) without contacting each other, and the wafer (72) is locally attached to the attachment place on the carrier (71). The wafer (72) is attached to the bottom (711) of the carrier (71). Second, a spacer 10 (76) is further provided between the wafer (72) and the carrier (71). The spacer (76) is Located on the periphery of the adhesive (73) (that is, on the periphery of the two joints), and can be used to support or increase the chip (7 2) The strength of the connection relationship with the carrier (71), and no stress will be generated or transmitted to the wafer (72). Please refer to FIG. 26, which is a low 15 stress wafer structure (80) provided by the fourth preferred embodiment of the present invention, which also includes a carrier (81), a wafer unit (82), and an adhesive (83). The majority of the bonding wires (84) and a cover (85); the main differences from the above embodiment are: wherein the chip unit (82) has an integrated circuit wafer (821) and a carrier board (822) ); The wafer (821) is bonded to one end surface of the carrier plate (822) by a 20% cloth coated with an adhesive (823), and the carrier plate (822) is partially coated. The way is that the adhesive (83) is bonded to the bottom (811) of the carrier (81), and the bottom (811) of the carrier (81) is formed with a notch (812), so that the adhesive (83) can be It is located in the recess (812), and the carrier board-8- This paper size is applicable to China National Standards (CNs) A4 specification (210 '乂 297mm) (Please read the precautions on the back before filling and loading · Order line 504810 A7 B7 V. Description of the invention (822) The thermal expansion coefficient is similar to the thermal expansion coefficient of the wafer (821); The carrier plate (822) and the carrier (81) are partially adhered, which can greatly reduce the adverse effects of the carrier (81) on the carrier plate (822), and because the carrier plate (822) The thermal expansion coefficient of) is similar to the thermal expansion coefficient of the wafer (821), which can reduce the deformation or deflection of the bonded wafer (821). For the wafer (821), it has a double protection effect. Please refer to Figure 27, which is a low-stress 10 wafer structure (90) provided by the preferred embodiment 25 of the present invention, which also includes a carrier (91), a wafer unit (92), and an adhesive (93). ), Most of the bonding wires (94) and a cover (95); the main difference from the above embodiment is that the chip unit (92) has a two-chip circuit chip (921) (922) and a carrier board ( 923); Among them, the two chips (921) (922) are arranged on the carrier board (923) 15 and the chips (921) (922) are electrically connected to the chip (921) (922) by the bonding wires (94). The carrier plate (923) and the bottom (911) of the carrier (91), so that the structure (90) can have the function of two wafers (921) (922) at the same time, and the carrier plate 923) and the carrier (91) have two attachment points, which are respectively located below the wafer (921) (922). 20 In summary, the low-stress wafer structure of the present invention does have a reduction The effect of generating stress on the wafer has its practicality of advancement and convenience in use. Also, the invention did not have the same article in the publication or public use before the application. Therefore, the invention already has the elements of an invention patent. In order to protect the inventor's hard thinking, he applied for the application according to law. 25 _____ The paper size of the winter paper is applicable to China National Standard (CNS) A4 (210X297 mm) (Please read the back. Please fill in the pages. Τ, printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives. 504810 A7 B7 5 、 Invention description (10 15 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 20 Simple illustrations: 笫 A diagram is a schematic cross-sectional view of a conventional wafer structure. 笫 A diagram is a flexural diagram of a conventional wafer structure. Figure 3 is a sectional view of the first preferred embodiment of the present invention. Figure 4 is a sectional view of the second preferred embodiment of the present invention. Figure 5 is a sectional view of the third preferred embodiment of the present invention. Figure 6 is the present invention. 24 is a cross-sectional view of the preferred embodiment. 27 is a cross-sectional view of the fifth preferred embodiment of the present invention. Figure Number Description: "First preferred embodiment" Low-stress wafer structure (10) Carrier (20) Top surface (21) Bottom (231) Notch (232) Adhesive (32) Welding wire (40) Bottom (52) Adhesive (53) "Second preferred embodiment" Low stress wafer structure (60) Carrier (61) ) Container (611) Adhesive (63) Welding wire (64 ) Lens (652) Spacer (66) "Third preferred embodiment" Low stress wafer structure (70) Carrier (71) Bottom (711) Please read the note on the back side first
I 填<i 頁 裝 底面（22) 容室（23) 晶片單元（30)晶片（31) 罩體（50) 頂面（51) 底部（612)晶片單元(62) 罩體（65) 通孔（651) 晶片單元（72) 黏著物（73) 銲線(74) 罩體(75) 墊片（76) -10- 本紙張又度適用中國國家標準（CNS ) A4規格（210 X 297公釐） 訂 線 504810 A7 B7 五、發明説明（） 「笫四較佳實施例」 低應力晶片構裝（80) 載體（81) 底部（811) 缺槽（812) 晶片單元（82) 晶片（821)載板（822) 黏結物（823) 黏著物（83) 5 銲線(84) 罩體（85) 「笫五較佳實施例」 低應力晶片構裝(90) 載體(91) 底部（911) 晶片單元(92)晶片（921)(922) 載板(923)黏著物(93)銲線(94) 罩體(95)I fill in < i-sheet bottom surface (22) container (23) wafer unit (30) wafer (31) cover (50) top surface (51) bottom (612) wafer unit (62) cover (65) through Hole (651) Chip unit (72) Adhesive (73) Welding wire (74) Cover body (75) Gasket (76) -10- This paper is also applicable to China National Standard (CNS) A4 specification (210 X 297 male) (Centimeter) Order line 504810 A7 B7 V. Description of the invention () "Fourth preferred embodiment" Low stress wafer structure (80) Carrier (81) Bottom (811) Notch (812) Wafer unit (82) Wafer (821 ) Carrier board (822) Adhesive (823) Adhesive (83) 5 Welding wire (84) Cover (85) "Twenty-five preferred embodiments" Low stress wafer structure (90) Carrier (91) Bottom (911 ) Wafer unit (92) Wafer (921) (922) Carrier board (923) Adhesive (93) Welding wire (94) Cover (95)
(請先閲讀背面之注意事項再填J •裝· 訂 經濟部智慧財產局員工消費合作社印製 _^_-11- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）(Please read the notes on the back before filling in J. Binding and printing. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _ ^ _- 11- This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm)