TW503588B - Semiconductor memory device using hemispherical grain silicon and method for the manufacture thereof - Google Patents

Abstract

A semiconductor device for use in a memory cell includes an active-matrix provided with a silicon substrate, at least one transistor formed on the silicon substrate, a number of bottom electrodes formed over the transistors, a plurality of conductive plugs to electrically connect the bottom electrodes to the transistors, respectively, and an insulating layer formed around the conductive plugs. In the device, a spacing between the bottom electrodes can be controlled by using a spacer during the formation of the bottom electrodes.

Description

本發明係關於半導體裝置；並更特定言之，係關於在其 中併入結構化電極之半導體記憶體裝置，以提供高密度貯 存電容器，及其製造方法。The present invention relates to a semiconductor device; and more particularly, to a semiconductor memory device in which a structured electrode is incorporated to provide a high-density storage capacitor, and a method of manufacturing the same.

已热知具有至少一個由電晶體及電容器組成的記憶體單 了之動態隨機存取記憶體（D R A Μ)具彳主要經由微小化減 乂尺寸之較咼程度之集成作用。但是，仍有減少記憶體單 元面積尺寸之需求。 為了符合藏需求，因此已提出許多方法，如溝渠型或堆 ®型電容器，將其以三度排列在記憶體裝置中，以減少適 用包谷器之單元面積。但是，製造三度排列的電容器之方 法是冗長且乏味的方法，因此造成高製造成本。因此，對 可以減少單元面積之新記憶體裝置有強烈的需求，其保證 訊息的取得容量，不需要複雜的製造步驟。 為了符合需求，已提出高密度動態隨機存取記憶體 (dram)，將其併入具有結構化表面形態學之底部電極 中。 在圖1中.，其展示說明熟知的高密度半導體記憶體裝置 1 0 0之橫截面圖示，其係揭示在以，，金屬-絕緣體-金屬電 谷器之粗糙金屬電極（Rugged Metal Electrodes for Metal-Insulator-Metal Capacitors)” 為標題之美國 -4 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) A7 B7It has been well known that dynamic random access memory (DR A M) having at least one memory unit composed of a transistor and a capacitor has a relatively large degree of integration, mainly by reducing the size. However, there is still a need to reduce the size of the memory cell area. In order to meet Tibetan requirements, many methods have been proposed, such as trench-type or stack-type capacitors, which are arranged in the memory device at three degrees to reduce the cell area of the valley wrapper. However, the method of manufacturing a three-dimensionally arranged capacitor is a tedious and tedious method, and therefore causes high manufacturing costs. Therefore, there is a strong demand for a new memory device that can reduce the cell area, which guarantees the capacity of obtaining information, and does not require complicated manufacturing steps. To meet the demand, high-density dynamic random access memory (DRAM) has been proposed, which is incorporated into a bottom electrode with a structured surface morphology. In FIG. 1, a cross-sectional view of a well-known high-density semiconductor memory device 100 is shown, which is disclosed in Rugged Metal Electrodes for Metal-Insulator-Metal Valleys (Rugged Metal Electrodes for "Metal-Insulator-Metal Capacitors)" as the title of the United States-4-This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm) A7 B7

專利申請案H & η 1 c & , ’ 5,986號中。半導體記憶體裝置100 并入金屬氧化物半導體（M 〇 S )電晶體中的動態矩陣 1 Q ’在動—1 〇頂端上形成的電容器結構β 在圖 2 A tj* 中，其例證製造半導體記憶體裝置l〇〇 包含的製造步驟。 氣k半導體，己憶體裝置1GG之方法首先是製備具有碎基 板2足動怨矩陣10，在其上形成MOS電晶體，隔離區 在Μ Ο S私晶體之間形成的位元線1 8，一對多插塞 16 ·在隔離區頂端形成的字線20及在MOS電晶體頂端 Φ成的第自隔離I 16。以化學氣相沉積作用（c v D )在 整個表面上形成例如由硼_磷_矽酸鹽玻璃（Β p S 〇 )製成的 絕緣層2 2。Μ 0 S電晶體包括一對當成來源及排放裝置之 擴散區6、栅格氧化物8、間隙壁14及柵格線12。 在後續的步驟中’在動態矩陣1 0頂端形成由如磷矽酸 鹽（PSG)之類的物質製成的犧牲層24，並形成預定的圖 型，藉以開啟多插塞丨6的頂端部份，如圖2 Β之展示。 在隨後的步驟中，依序形成缓衝層1 8、第一個金屬層 20、介電層22及第二個金屬層24,如圖2Α的展示。 緩衝層18是由鈦（丁丨）製成的及第一個金屬層20是由鉑 (P t)製成的。介電層2 2是由鐵電體物質製成的。以濺射 沉積緩衝層18、第一個金屬層22及第二個金屬層24, 並以自轉塗佈介電層20。 本紙張尺度適用中國國豕標準(CNS) A4規格(210X297公爱) 503588Patent application H & η 1 c &, '5,986. The semiconductor memory device 100 is incorporated into a metal oxide semiconductor (MOS) transistor with a dynamic matrix 1 Q 'capacitor structure formed at the top of a moving -10 β In FIG. 2 A tj *, an example of which makes a semiconductor memory The manufacturing steps included in the body device 100. The method of the gas-k semiconductor and the memory device 1GG is to first prepare a matrix 10 with a broken substrate 2 and form a MOS transistor thereon, and a bit line 18 formed between the isolation region and the MOS crystal. One-to-many plugs 16 A word line 20 formed at the top of the isolation region and a self-isolated I 16 formed at the top of the MOS transistor. An insulating layer 22 made of, for example, boron-phosphorus-silicate glass (B p S 0) is formed on the entire surface by chemical vapor deposition (c v D). The M 0S transistor includes a pair of diffusion regions 6 serving as source and discharge devices, grid oxides 8, barrier walls 14 and grid lines 12. In the subsequent steps, a sacrificial layer 24 made of a substance such as phosphosilicate (PSG) is formed on the top of the dynamic matrix 10 and a predetermined pattern is formed to open the top end of the multi-plug 6 As shown in Figure 2B. In the subsequent steps, the buffer layer 18, the first metal layer 20, the dielectric layer 22, and the second metal layer 24 are sequentially formed, as shown in FIG. 2A. The buffer layer 18 is made of titanium (butylene) and the first metal layer 20 is made of platinum (Pt). The dielectric layer 22 is made of a ferroelectric substance. The buffer layer 18, the first metal layer 22, and the second metal layer 24 are deposited by sputtering, and the dielectric layer 20 is spin-coated. This paper size applies to China National Standard (CNS) A4 specification (210X297 public love) 503588

然後，以低壓化學氣相沉積作用（L P c v D)在犧牲層2 4 及動態矩陣.1 0的頂端形成例如以非晶形矽（a - S i)製成的 第一個導電層23，如圖2C的展示。 然後，以平面化法（如化學機械拋光（CMp)或各向異性 蝕刻）除去第一個導電層頂端的大部份部位，直到露出犧 牲層2 4為止。接著利用如濕蝕刻之類的方法除去犧牲層 24 ’藉以獲得電極結構25，如圖2d的展示。 在下一個步驟中，使電極結構2 5受到高真空退火，在 其内部及外部兩者上形成半球粒狀聚矽（HSGs)26。可在 高真空下使用快速熱處理（RTp)，以進一步促進hsg形 成作用。 / 在隨後的步驟中，依序在電極結構25的HSGs26頂端 上形成介電層28及第二個導電層3〇,如圖2?的展示。 介電層25係由鐵電體物質製成的，如鳃鉍鈕酸鹽 (SBT)、鉛锆鈦酸鹽（ρζτ)或類似物，並利用如旋轉塗 佈、化學氣相沉積作用(CVD)或類似的方法形成該層。 在該記憶體裝置100中，介電層28具有電容器薄膜的作 用及第二個導電層3〇具有參考電極的作用。 上述的半導體記憶體裝置1〇〇的其中一個主要缺點是有 可能在鄰接的電極結構外側之間形成HGSs架橋”，=為 在鄰近的電極結構之間的間隔會使現行的高密度^存電容 m 裝 訂Then, a low-pressure chemical vapor deposition (LP cv D) is used to form a first conductive layer 23 made of, for example, amorphous silicon (a-Si) on the top of the sacrificial layer 24 and the dynamic matrix .10, such as Display of Figure 2C. Then, a planarization method (such as chemical mechanical polishing (CMp) or anisotropic etching) is used to remove most of the top portion of the first conductive layer until the sacrificial layer 24 is exposed. The sacrificial layer 24 'is then removed by a method such as wet etching to obtain the electrode structure 25, as shown in Fig. 2d. In the next step, the electrode structure 25 is subjected to high vacuum annealing to form hemispherical granular polysilicon (HSGs) 26 on both the inside and the outside thereof. Rapid heat treatment (RTp) can be used under high vacuum to further promote hsg formation. / In a subsequent step, a dielectric layer 28 and a second conductive layer 30 are sequentially formed on top of the HSGs 26 of the electrode structure 25, as shown in FIG. 2A. The dielectric layer 25 is made of a ferroelectric material, such as gill bismuth button salt (SBT), lead zirconate titanate (ρζτ), or the like, and utilizes such as spin coating, chemical vapor deposition (CVD ) Or a similar method. In this memory device 100, the dielectric layer 28 functions as a capacitor film and the second conductive layer 30 functions as a reference electrode. One of the main disadvantages of the above-mentioned semiconductor memory device 100 is that it is possible to form HGSs bridges between the outer sides of adjacent electrode structures. "= The distance between adjacent electrode structures will cause the current high density capacitors. m binding

線 -6-Line -6-

五、發明説明（ 粗:二:發明的目的係提供併入許多具備㈣侧表面及 對=表面之電極的半導體裝置，其中使粗以 相對於底邵的粗糖表面以預定的角度傾斜。 =以自目的係提供-種製造半導體裝置之方 面：ί:半導體中併入許多具備粗輪侧表面及粗縫底部表 :广其中使_表面以相對於底部 預疋的角度傾斜。 的丰：：發明的一個覜點’其係提供在記憶體單元中使用 ，姐裝置：其包含具備半導體基板之動態矩陣、許多 在丰導體基板上形成的電晶體及以電與電晶體連接之導插 塞、及許多具有在動態矩陣頂端上形成的粗縫表面之底部 I極’每一個底部電極具有底部位及側部位，其中使側部 位以相對於底部表面以預定的角度傾斜。 根據本發明的另一個觀點，其係提供製造在記憶體單元 中使用的半導體裝置之方法，該方法包含步驟·· ^製備且 備至少一個電晶體之動態矩陣，許多以電與電晶體及在導 插塞周圍形成的第一個絕緣層連接之導插塞，· b)在動態麵 陣的頂端上形成犧牲層及形成預定的圖型，藉以獲得圖型 之犧牲層’· c)在模塑之犧牲層側面上形成間隙壁；d)在圖 型之犧牲層、間隙壁及動態矩陣頂端上形成導電層；幻利 用化學機械拋光（CMP)蝕刻在圖型之犧牲層頂端曰上的導 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 5 5 五 發明説明（ 電層部份；f)除去犧牲層及 — 構；及g)在底部電極社的^㈣獲得底部電極結 (HSG)〇 構的表面上形成半球矽顆粒 麗形的簡要說明 由以下結合所附圖形提供的較 且一 以明白本發明以上及其它目的及特點ΓΓΓ例的說明得 裝先前技藝具有結構化電極之半導體_ 圖2A至2F是例證用於製止主 姑蓺m 導體記憶體裝置之先前 技藝万法<圖示橫截面圖； 圖3是說明根據本發明的半導體裝置之橫截面圖；及 圖4A i 4H是說明根據本發明用於製造半導體記憶體 裝置之方法之圖示橫截面圖； 詳魎麗_明的具體皆竑叫 、圖及4A i 4H提供在憶體單元中使用的半導體 裝置2〇〇之橫截面圖及說明根據本發明較佳的具體實： 例製裝置《方法之橫截面圖。應該注意的是以相同的 參考號碼代表出現在圖3及4A至4H中相同的部件。 在圖3中，其係提供包含動態矩陣2丨〇及電極結構 227之本發明半導體裝置2〇〇之橫截面圖。動態矩陣 210包括矽基板202,在矽基板202頂端上形成的電晶 體’用隔離電晶體.之隔離區2〇4、多插塞219、位元線 -8 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)V. Description of the invention (coarse: two: The purpose of the invention is to provide a semiconductor device incorporating many electrodes having a side surface and an opposite surface, wherein the coarse is inclined at a predetermined angle with respect to the surface of the raw sugar of the bottom. From the purpose of providing a kind of semiconductor device manufacturing aspects: ί: semiconductor incorporated with a number of rough wheel side surface and rough seam bottom table: wide which makes the surface inclined at an angle with respect to the bottom. Feng :: Invention A point of view 'is provided for use in a memory unit. The device includes a dynamic matrix with a semiconductor substrate, a plurality of transistors formed on a conductor substrate, and a conductive plug connected to the transistor, and Many bottom electrodes having a quilted surface formed on the top of a dynamic matrix. Each bottom electrode has a bottom position and a side portion, wherein the side portion is inclined at a predetermined angle with respect to the bottom surface. Another aspect according to the present invention , Which provides a method for manufacturing a semiconductor device for use in a memory cell, the method including the steps of preparing and preparing at least one transistor Matrix, many conductive plugs connected with electricity and transistors and the first insulating layer formed around the conductive plug, b) forming a sacrificial layer on the top of the dynamic area array and forming a predetermined pattern to obtain a graph Type sacrificial layer '· c) forming a spacer on the side of the molded sacrificial layer; d) forming a conductive layer on the patterned sacrificial layer, the spacer and the top of the dynamic matrix; using chemical mechanical polishing (CMP) etching on The paper size of the guide on the top of the sacrificial layer of the pattern is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm). A brief description of the formation of hemispherical silicon particles on the surface of the bottom electrode structure obtained from the bottom electrode junction (HSG) structure is provided by the following in conjunction with the accompanying drawings to understand the above and other objects and features of the present invention ΓΓΓ Examples illustrate the use of semiconductors with structured electrodes of the prior art. Figures 2A to 2F are illustrations of the prior art methods used to stop the main conductor memory device < illustrated cross-sectional view; Figure 3 is an illustration based on The semi 4A i 4H are diagrammatic cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to the present invention; detailed descriptions are provided by howls, drawings, and 4A i 4H A cross-sectional view of a semiconductor device 2000 used in a memory cell and a description thereof according to a preferred embodiment of the present invention are as follows: A cross-sectional view of an example device "Method". It should be noted that the same reference numerals are used to represent the same components appearing in Figs. 3 and 4A to 4H. In FIG. 3, a cross-sectional view of a semiconductor device 200 of the present invention including a dynamic matrix 20 and an electrode structure 227 is provided. The dynamic matrix 210 includes a silicon substrate 202, and a transistor formed on the top of the silicon substrate 202 is an isolation transistor. The isolation region 204, the multi-plug 219, and the bit line -8-this paper size applies to Chinese national standards ( CNS) A4 size (210X297 mm)

218及字線220。每一個電晶體具有擴散區2〇6、柵格氧 化物2 0 8、柵格線2丨2、字線硬質遮板2丨3及側壁 2 1 4 〇 在半導體裝置200中，將位元線218以與其中一個擴 散區206連接，施以電位。將每一個電極結構227經由 多插塞2 16以電與其它的擴散區2〇6連接。雖然位元線 218實際上係以旁通多插塞216的右及左方向延伸，但 疋圖开y未展示出位元線的這些部件。可將電極結構 與板線（未展示）連接，施以共同的固定電位。 最好以如聚矽、非晶形矽（a-Si)或類似物之類的材料製 成電極結構。而且，每一個電極結構227也具有以不增 加其檢尺寸擴大電極表面積之結構化表面2 2 8。在較佳的 具體實施例中，電極結構22 7具有底部位及以相對於底 部位以預定角度傾斜之側部位。預定角度大於9 0度。 圖4 A至4 Η係說明根據本發明用於製造半導體記憶體 裝置2〇〇之方法之圖示橫截面圖。 用於製造半導體記憶體裝置2〇〇之方法首先是製備包括 矽基板202、隔離區204、擴散區2〇6、柵格氧化物 2〇8、柵格線212、側壁214、位元線218、多插塞 及絕緣層222之動態矩陣2 1〇，如圖4Α的展示。將位 元線218以電與至其中一個擴散區2〇6連接，施以電 位。將每一個多插塞216分別以電與至其它的擴散區218 and word line 220. Each transistor has a diffusion region 206, a grid oxide 208, a grid line 2 丨 2, a word line hard mask 2 丨 3, and a sidewall 2 1 4. In the semiconductor device 200, a bit line is formed. 218 is connected to one of the diffusion regions 206, and a potential is applied. Each electrode structure 227 is electrically connected to the other diffusion regions 206 through the multiple plugs 2 16. Although the bit line 218 actually extends in the right and left directions of the bypass multi-plug 216, these components of the bit line are not shown in FIG. The electrode structure can be connected to a plate wire (not shown) to apply a common fixed potential. The electrode structure is preferably made of a material such as polysilicon, amorphous silicon (a-Si), or the like. Moreover, each electrode structure 227 also has a structured surface 2 2 8 that increases the surface area of the electrode without increasing its inspection size. In a preferred embodiment, the electrode structure 227 has a bottom portion and a side portion inclined at a predetermined angle with respect to the bottom portion. The predetermined angle is greater than 90 degrees. 4A to 4 are diagrammatic cross-sectional views illustrating a method for manufacturing a semiconductor memory device 2000 according to the present invention. The method for manufacturing a semiconductor memory device 2000 is to first prepare a silicon substrate 202, an isolation region 204, a diffusion region 206, a grid oxide 208, a grid line 212, a sidewall 214, and a bit line 218. The dynamic matrix 2 10 of the multi-plug and insulation layer 222 is shown in FIG. 4A. The bit line 218 is electrically connected to one of the diffusion regions 206, and a potential is applied. Each multi-plug 216 is electrically connected to other diffusion regions.

裝 訂 气 -9- 503588Binding gas -9- 503588

2 0 6連接雖然位元線2 1 8實際上係以旁通多插塞2 j 6 的右及左方向延伸，但是圖形未展示出位元線的這些部 件。可將電極結構2 2 7與板線連接（未展示），以施以其 共同的固定電位。絕緣層222係由例如硼·磷-矽酸鹽破 璃（BPSG)製成的。 在隨後的步驟中，利用電漿增強化學氣相沉積作用 (P E C V D )在動怨矩陣2 i 〇頂端上形成例如& ^ p s G製 成的犧牲層，並形成預定的圖型，藉以獲得模塑之犧牲層 2 2 4如圖4 B的展示。應該注意的是在形成犧牲層之 則，可先在動態矩陣210頂端上形成作為蝕刻終止層之 氮化物層（未展示）。 然後，利用熱的熱氧化作用（HT〇)在模塑之犧牲層224 及動態矩陣2 1 〇頂端上形成例如以二氧化矽（§丨〇 2 )製成 之氧化物層2 2 3 ’如圖4 C的展示。有可能利用氧化物之 中等溫度沉積作用（MTO)形成氧化物層22 3。 在以下的步驟中，將氧化物層22 3乾㈣，以形成在圖 型之犧牲層224側面上的間隙壁22 5，如圖4D的展 示0 在下一個步驟中，在模塑之犧牲層224、間隙壁225 及動態矩陣210頂端上形成例如以聚矽製成之導電層 22 6 ’如目4E的展示。在較佳的具體實施例中，導電層 226具有從约400埃至約5〇〇埃之厚度範圍。 -10-The 2 0 6 connection Although the bit line 2 1 8 actually extends in the right and left directions of the bypass multi-plug 2 j 6, these parts of the bit line are not shown in the figure. The electrode structure 2 2 7 can be connected to a board line (not shown) to apply a common fixed potential to it. The insulating layer 222 is made of, for example, boron-phosphorus-silicate glass (BPSG). In a subsequent step, a plasma enhanced chemical vapor deposition (PECVD) is used to form a sacrificial layer made of & ^ ps G on the top of the moving matrix 2 i 〇 and form a predetermined pattern to obtain a mold The plastic sacrificial layer 2 2 4 is shown in FIG. 4B. It should be noted that when the sacrificial layer is formed, a nitride layer (not shown) as an etch stop layer may be formed on the top of the dynamic matrix 210 first. Then, an oxide layer 2 2 3 ′ made of, for example, silicon dioxide (§ 丨 〇2) is formed on the top of the molded sacrificial layer 224 and the dynamic matrix 2 10 using thermal thermal oxidation (HT). Figure 4C shows. It is possible to form the oxide layer 223 using the medium temperature deposition (MTO) of the oxide. In the following steps, the oxide layer 22 3 is dried to form a spacer 22 5 on the side of the patterned sacrificial layer 224, as shown in FIG. 4D. In the next step, the sacrificial layer 224 is molded. A conductive layer 22 6 ′ made of, for example, polysilicon is formed on the top of the partition wall 225 and the dynamic matrix 210, as shown in FIG. 4E. In a preferred embodiment, the conductive layer 226 has a thickness ranging from about 400 angstroms to about 500 angstroms. -10-

503588 A7 _— —_ B7 五、發明説明（。） 8 ’ 然後’在導電層226的整個表面上形成光阻層（未展 示）。光阻層具有從約8,000埃至約1 5,5 0 0埃之厚度範 圍。並接著利用如化學機械拋光（C Μ P )或類似的方法除 去光阻層及導電層226，直到露出模塑之犧牲層224為 止’如圖4 F的展示。並也可以利用如反應性離子蝕刻 (RIΕ)之類的方法以反蝕刻光阻層及導電層2 2 6。 並接著利用濕蚀刻除去模塑之犧牲層2 2 4及間隙壁 22 5，藉以獲得電極結構22 7，如圖4Ρ的展示。在較佳 的具體實施例中，以改變間隙壁22 5厚度可以控制在介 於電極結構2 2 7之間的間隔。也可以改變間隙壁2 2 5厚 度控制電極結構2 2 7圖型。 最後’以引晶及退火法完成電極結構2 2 7，以產生粗糙 表面2 2 8，其具有約5 〇至約2 5 〇毫微米之相對大的聚結 晶矽顆粒，藉以獲得電極22 9，如圖4Η的展示。退火法 可以包括將如聚矽或二氧化矽之類的物質分散在電極結構 227表面上之步驟，以產生核晶位置。並且退火法也包括 在核晶位置上累積矽之步驟，藉以形成具有粗表面形態之 粗糙表面2 2 8。生成之表面型態經常由相對大的聚結晶體 、、且成的，將其稱為半球矽顆粒（H s G)。可以進行其它的步 驟以利用作為在鐵電體隨機存取記憶體（F e R A M )裝置 中的底部電極之電極229。 入先則技蟄比較，本發明可以獲得足以避免以H s 〇形 -11 -503588 A7 _ — —_ B7 V. Description of the invention (.) 8 'Then, a photoresist layer (not shown) is formed on the entire surface of the conductive layer 226. The photoresist layer has a thickness ranging from about 8,000 Angstroms to about 15 500 Angstroms. Then, the photoresist layer and the conductive layer 226 are removed by a method such as chemical mechanical polishing (CMP) or the like until the molded sacrificial layer 224 is exposed 'as shown in FIG. 4F. It is also possible to use a method such as reactive ion etching (RIE) to reverse etch the photoresist layer and the conductive layer 2 2 6. Then, the mold sacrificial layer 2 2 4 and the spacer 22 5 are removed by wet etching to obtain an electrode structure 22 7, as shown in FIG. 4P. In a preferred embodiment, the interval between the electrode structures 2 2 7 can be controlled by changing the thickness of the spacers 22 5. The thickness of the spacer 2 2 5 thickness control electrode structure 2 2 7 can also be changed. Finally, the electrode structure 2 2 7 is completed by seeding and annealing methods to produce a rough surface 2 2 8 having relatively large polycrystalline silicon particles of about 50 to about 250 nm to obtain an electrode 22 9, As shown in Figure 4Η. The annealing method may include a step of dispersing a substance such as polysilicon or silicon dioxide on the surface of the electrode structure 227 to generate a nuclear crystal site. In addition, the annealing method also includes a step of accumulating silicon on the nuclei, thereby forming a rough surface 2 2 8 having a rough surface morphology. The resulting surface type is often formed from relatively large polycrystalline bodies and is referred to as hemispherical silicon particles (H s G). Other steps may be performed to utilize the electrode 229 as a bottom electrode in a ferroelectric random access memory (F e R A M) device. In comparison with the prior art, the present invention can obtain enough to avoid H s 〇 -11-

503588 A7 B7 五、發明説明（9 ) 成作用造成在電極2 2 9之間架橋的間隔。其係利用在電 極結構2 2 7形成期間的間隙壁達到的。 雖然已以相關的特殊具體實施例說明本發明，但是，那 些熟諳此項技藝者將會明白可以不達背如以下申請專利範 圍所定義的本發明範圍進行各種變化及改良。 -12- 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐)503588 A7 B7 V. Description of the invention (9) Interaction between the electrodes 2 2 9 caused by the action. This is achieved using a partition wall during the formation of the electrode structure 2 2 7. Although the present invention has been described with specific specific embodiments, those skilled in the art will understand that various changes and improvements can be made without departing from the scope of the present invention as defined by the following patent applications. -12- This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)

Claims (1)

申請專利範圍 到露出模塑之犧牲層為止； 0除去犧牲層及間隙壁，藉蔣 土稽以獲侍展邵電極結構；及 g)在展部電極結構的表面 .』 成丰球顆粒（liSGs)。 6 ·根據申請專利範圍第5項之 闺不 貝 < 万法，其中導電層係由非 阳形矽製成的。 7 ·根據申請專利範圍第6項之古、本 .,^ 闺不〇貝足万去，其中導電層具有從 约400埃至5〇〇埃之厚度範園。 8, 根據申請專利範圍第6項之方法，其中犧牲層係以 〇3_PSG利用電裝增強化學氣相沉積法（PECVD)製成 的。 9. 根據中請專利範圍第8項之方法，其中犧牲層具有從 约8,000埃至15,〇〇〇埃之厚度範圍。 瓜根據中請專利範圍第9項之方法，其中間隙壁係利用 熱的熱氧化作用（Η T 0 )製成的。 11·根據申請專利範圍第10項之方法，其中間隙壁係利用 氧化物之中等溫度沉積作用（ΜΊΓ0)製成的。 12·根據申請專利範圍第9項之方法，其中間隙壁具有從 約1 〇 0埃至約2 5 0埃之厚度範圍。 其中以間隙壁厚度 其中以控制間隙壁 其中係利用化學機 13·根據申請專利範圍第5項之方法 控制在底部電極結構之間的間隔。 14.根據申請專利範圍第5項之方法 圖型改變底部電極結構之圖型。 15·根據申請專利範圍第5項之方法 -14 - 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐) 50358! 8 8 8 8 A BCD 申請專利範圍 械拋光（CMP)進行步騾e)。 16.根據申請專利範圍第1 5項之方法，其中係利用反蝕刻 法（如離子反應性蝕刻（RIE))進行步騾e)。 -15 本紙張尺度適用中國國家標準(CNS) A4規格(210 x 297公釐)The scope of the patent application is until the molded sacrificial layer is exposed; 0 The sacrificial layer and the spacer are removed, and Jiang Tuji is used to obtain the exhibition electrode structure; and g) On the surface of the electrode structure of the exhibition department. ). 6 · According to item 5 of the scope of patent application < Wanfa, where the conductive layer is made of non-yang silicon. 7 · According to the ancient and the present article No. 6 of the scope of the patent application, there is no shortage of good friends, in which the conductive layer has a thickness ranging from about 400 angstroms to 500 angstroms. 8. The method according to item 6 of the scope of patent application, wherein the sacrificial layer is made of 〇3_PSG using electrical enhanced chemical vapor deposition (PECVD). 9. The method according to claim 8 in which the sacrificial layer has a thickness ranging from about 8,000 angstroms to 15,000 angstroms. The method according to item 9 of the Chinese Patent Application, wherein the partition wall is made by thermal thermal oxidation (Η T 0). 11. The method according to item 10 of the scope of patent application, wherein the partition wall is made by isothermal deposition of oxides (ΜΊΓ0). 12. The method according to item 9 of the scope of patent application, wherein the partition wall has a thickness ranging from about 100 angstroms to about 250 angstroms. Among them, the thickness of the gap wall is used to control the gap wall, which uses a chemical machine. 13. The interval between the bottom electrode structures is controlled according to the method in the fifth item of the patent application. 14. Change the pattern of the bottom electrode structure according to the method of the scope of the patent application No. 5. 15 · Method according to item 5 of the scope of patent application -14-This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) 50358! 8 8 8 8 A BCD patent application scope mechanical polishing (CMP) e). 16. The method according to item 15 of the scope of patent application, wherein step (e) is performed by a reverse etching method (such as ion reactive etching (RIE)). -15 This paper size applies to China National Standard (CNS) A4 (210 x 297 mm)