TW502413B - Semiconductor chip encapsulation structure with passive device - Google Patents

Semiconductor chip encapsulation structure with passive device Download PDF

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Publication number
TW502413B
TW502413B TW90125847A TW90125847A TW502413B TW 502413 B TW502413 B TW 502413B TW 90125847 A TW90125847 A TW 90125847A TW 90125847 A TW90125847 A TW 90125847A TW 502413 B TW502413 B TW 502413B
Authority
TW
Taiwan
Prior art keywords
passive device
substrate
semiconductor chip
dielectric layer
encapsulation structure
Prior art date
Application number
TW90125847A
Other languages
Chinese (zh)
Inventor
Chin-Chen Wang
Cheng-Lan Tseng
Tzung-Li Hung
Shui-Ching Lee
Hui-Chin Fang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW90125847A priority Critical patent/TW502413B/en
Application granted granted Critical
Publication of TW502413B publication Critical patent/TW502413B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor chip encapsulation structure with a passive device comprises a substrate, a chip, a plurality of bonding wires, a passive device, a dielectric layer, and an encapsulation body. The chip and the substrate are connected by wires. The passive device is connected to the substrate by a surface mounting technique. A dielectric layer is used to cover the surface of the passive device. Since the dielectric layer has an insulative function, a short circuit will not occur even a wire contacts the passive device in a wire bonding procedure.

Description

502413502413

第3頁 502413 修正 案號 90125847 六、申請專利範圍 1. 一種具有被動元件之半導體封裝構造，包含 一基板； 、 Η Μ 圓滑面； 一晶片，其係設於該基板上； f 複數條接線，其電連接該晶片與該基板； 一被動元件，其係電連接於該基板上； 一介電層，其完整包覆該被動元件且形成 及 一封膠體，其包覆該晶片、該等接線、該被動元件 :及該介電層。 委 員 :造 如申請專利範圍第1項之具有被動元件之半導體封裝構 ，其中該介電層係由二氧化矽所構成。 1由η厚 1係 第係 第之 第件 圍層 圍層 圍元 範電 範電 範動 利介 利介 利被 專該 專該專該 請中 請中 請中 申其 申其. 申其 如， 如， 如， .it必 · .4 3 i 4 i 5 i ,:;;s;r-->-;f:口®0¾ % f ^$ 被 有 具 之 項 構 裝 封 體 導 半 之 件 元 所 物 合 聚 子 分 高 有 具 之 項 於 大 係 度 成 構 裝 封 體 導。 半S) 之11 件(m 元爾 動米 被 構 裝 封 體 導 半 之 件 元 被 有 具 之 項 容 電 構 裝 封 體 導 半 之 件 元 被 有 具I 之感 -<電 項$ 1係 第件 圍元 利被 專該 請中 申其 如， 3.造Page 3, 502413, Amendment No. 90125847 6. Scope of Patent Application 1. A semiconductor package structure with passive components, including a substrate; Μ smooth surface; a chip, which is arranged on the substrate; f a plurality of wiring, It is electrically connected to the chip and the substrate; a passive element is electrically connected to the substrate; a dielectric layer which completely covers the passive element and forms and a colloid which covers the chip and the wiring The passive element: and the dielectric layer. Member: The semiconductor package structure with passive components, such as the scope of patent application No. 1, where the dielectric layer is composed of silicon dioxide. 1 by η thick 1 series of the first layer of the enclosing layer of the enclosing layer enclosing Yuan Fandian Fandian Fandian Li Jie Li Jie Li was specialized in this specialty should be invited to apply for it to apply for it. Shen Qiru For example, .it must be .4 3 i 4 i 5 i,:; s; r->-; f: 口 ®0¾% f ^ $ The convergent sub-elements of the element are divided into high-level items to form a package body guide. Half of S) of 11 pieces (m yuan, moving rice, structuring, sealing body, guide, semi-conductor, component, component, electrical, structuring, sealing body, guide, semi-conductor, component, I,-< electricity item $ Yuan Li was the first to be asked to apply for it in the first series. 3.

第11頁 502413 _案號90125847_年月曰 修正_ 六、申請專利範圍 7. 如申請專利範圍第1項之具有被動元件之半導體封裝構 造，其中該被動元件係電阻。 8. 如申請專利範圍第1項之具有被動元件之半導體封裝構 造，其中該被動元件係以表面黏著技術電連接於該基板。 9. 如申請專利範圍第1項之具有被動元件之半導體封裝構 造，其中該接線係金線。 1 0.如申請專利範圍第1項之具有被動元件之半導體封裝構 造，其中該封膠體之係由熱固性塑膠所構成。Page 11 502413 _Case No. 90125847_ Years of Amendment_ VI. Patent Application Scope 7. For example, if you apply for a semiconductor package structure with a passive element in the first item of the patent scope, the passive element is a resistor. 8. For example, a semiconductor package structure with a passive component in the scope of the patent application, wherein the passive component is electrically connected to the substrate using a surface mount technology. 9. For the semiconductor package structure with passive components as described in the scope of the patent application, the wiring is gold wire. 10. The semiconductor package structure with passive components according to item 1 of the scope of the patent application, wherein the sealant is made of thermosetting plastic.

第12頁Page 12

TW90125847A 2001-10-18 2001-10-18 Semiconductor chip encapsulation structure with passive device TW502413B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW90125847A TW502413B (en) 2001-10-18 2001-10-18 Semiconductor chip encapsulation structure with passive device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW90125847A TW502413B (en) 2001-10-18 2001-10-18 Semiconductor chip encapsulation structure with passive device

Publications (1)

Publication Number Publication Date
TW502413B true TW502413B (en) 2002-09-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW90125847A TW502413B (en) 2001-10-18 2001-10-18 Semiconductor chip encapsulation structure with passive device

Country Status (1)

Country Link
TW (1) TW502413B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8072081B2 (en) 2007-02-06 2011-12-06 Advanced Semiconductor Engineering Inc. Microelectromechanical system package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8072081B2 (en) 2007-02-06 2011-12-06 Advanced Semiconductor Engineering Inc. Microelectromechanical system package

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