TW494551B - Wafer level die packaging method using anodic bonding - Google Patents

Abstract

A wafer level die vacuum packaging method using anodic bonding is disclosed, wherein the anodic bonding method is used to perform anodic bonding of etched glass piece and device chip at the temperature close to 350 DEG C to 450 DEG C, so as to achieve the requirement of high gas sealing. Also, if the environment to perform the anodic bonding is vacuum, the inner chamber of the device after die packaging can maintain high vacuum, and the signal can be retrieved by the back side penetration method or directly from the front side, so as to raise the sensitivity of the device, reduce the device volume after packaging and reduce the packaging cost.

Description

494551494551

五、發明說明（1) 【發明的範圍】 本發明係有關於一種元件之封裝方法，利用陽極接合 法（Anodi c Bonding)將完成之元件辱片與封蓋之玻璃片|占 合之後切割，以完成封裝。其封裝後之元件大小為晶粒級 之尺寸，且由於其陽極接合是可以在真空環境下執行，封 裝完成後其腔體内也因此可選擇性的保持真空，而許多元 件在真空下皆可以提高其信號及靈敏度。而此種封裝方 法’亦；9b大幅降低使尽一般封裝材料所須花費之封裝材料 成本，並縮小封裝後之元件尺寸。其並適用於一般半導體 元件、光通訊元件、無線通訊元件、生醫檢測分析元件、 生物晶片及其他各種微機電之封裝。 【發明背景】 件封裝 黏合技 式封裝 隨著新 封裝技 電元件 其運用 題；或 下： 前各類半導體元件、微機電元件、及新興的被動元 方法，大都沿用，一般傳統元件的封裝，如SMT(表面 術 surface mount techno logy )、DIP(雙列直插 :dual ln line)和Metal Can(金屬罐）（τ〇)等。但 ，或新應用所伴隨之新規格的發展，在 與積體二=:片需求二:如微機電元件或微機 覆晶（F 1 i d α .、 …、線通afL同頻元件等，在 其在切割 、令所面臨之良率問題等，其整理如 試’當新產品開發測 4夕4：)：)丄 五、發明說明（2) 測試出不合格晶粒，並加以渡除，而封聚製程及不良品所 反映的成本約佔總成本的9〇%，故可利用晶圓級晶粒封裝 (Wafer Level Chip Scale Package」WLCSP)技術，來大 幅降低晶片：割後再封裝測試所造成的相關固定成本。 (二） 在晶片之切割方面，對於微機電元件言，由於微 機電式的各種元件大都利用所謂的矽微細加工（SiHc〇n m1Cr〇maChining)製作，通常會有所謂的不同平面 (out-off plane)之立體微結構，在矽晶片表面非等向性 蝕刻出凹槽，或利用犧牲層蝕刻等技術，製作出浮板么士 構。因此，含有微機電元件之矽晶片在完成製程後，= 現今之？準切割製程，則在一開始晶片切割時就可能 對浮板等微結構的傷害，如果利用晶粒封裝（csp)的封 術，在切割前就對元件先行加以封裝保護，再進行切^孜 則可以大幅降低對於元件的傷害，換言之，將可大=丄 良率。 田杈咼 (三） 以CSP技術封裝元件適合量產低成本批次式 裝製造技術，由於可省略黏粒、甚至打線之製程，•故封 提高其生產速度’是故WLCSP有很大的利基。 (四） 就紅外線感測元件（111丨(：^〇];)〇1〇11]以^)或共振 感測元件（resonant based sensors)或其他無線通訊、式 而言，若其内部能維持氣密的真空狀態，則可大幅古一 件之特性與靈敏度，故真空封裝為元件封裝中之重要=兀 術。然而現今之真空封裝多為軍用電子元件所用之技 通常是在完成初步覆晶、打線與封蓋後，尚·須由外^亩 具 4^4551V. Description of the invention (1) [Scope of the invention] The present invention relates to a method for packaging a component, using an anodic bonding method (Anodi c Bonding) to cut the completed component and the cover glass | cutting after occupation, To complete the package. The size of the packaged components is grain-level, and because the anodic bonding can be performed in a vacuum environment, the cavity can be selectively maintained in a vacuum after packaging, and many components can be vacuumed. Improve its signal and sensitivity. And this kind of packaging method 'also; 9b greatly reduces the cost of packaging materials required to make the most of the general packaging materials, and reduces the size of the packaged components. It is also suitable for general semiconductor components, optical communication components, wireless communication components, biomedical detection and analysis components, biochips and other various micro-electromechanical packaging. [Background of the Invention] Component packaging, bonding technology packaging, and the use of new packaging technology and electrical components; or the following: the former types of semiconductor components, micro-electro-mechanical components, and emerging passive element methods are mostly used, generally traditional component packaging, Such as SMT (surface mount techno logy), DIP (dual in line: dual ln line) and Metal Can (metal tank) (τ〇) and so on. However, or the development of new specifications accompanied by new applications, is the same as chip two =: chip demand two: such as micro-electromechanical components or microcomputer flip-chip (F 1 id α.,…, Line through afL co-frequency components, etc.) The yield problems faced by cutting and ordering, etc., are sorted out as a test, when the new product is developed and tested 4: 4 :): 5. Description of the invention (2) The unqualified grains are tested and eliminated, The cost of the packaging process and defective products accounts for about 90% of the total cost, so wafer level chip scale package (WLCSP) technology can be used to significantly reduce the wafer: cut and repackage test The associated fixed costs. (2) In terms of wafer dicing, as for micro-electro-mechanical components, most of the micro-electro-mechanical components are produced by so-called silicon microfabrication (SiHcOm m1CrOmaChining), so there are usually so-called out-off planes plane) three-dimensional microstructure, the grooves are anisotropically etched on the surface of the silicon wafer, or the sacrificial layer is etched to produce a floating plate structure. Therefore, after the silicon wafer containing the micro-electromechanical components is completed, is it the present day? In the quasi-cutting process, damage to floating structures and other microstructures may occur at the beginning of wafer cutting. If csp sealing is used, the components are packaged and protected before cutting, and then cut. It can greatly reduce the damage to the components, in other words, it can be large = 丄 yield. Tian Zhuye (3) Packaging components with CSP technology is suitable for mass production and low-cost batch-type manufacturing technology. Because sticky particles and even wire bonding processes can be omitted, it is very beneficial for WLCSP to increase its production speed. base. (4) As far as infrared sensing elements (111 丨 (: ^ 〇];) 〇1〇11] to ^) or resonance based sensors (resonant based sensors) or other wireless communication, the internal The air-tight vacuum state can greatly improve the characteristics and sensitivity of the old one, so vacuum packaging is important in component packaging = Wushu. However, today's vacuum packaging technology is mostly used by military electronic components. After the initial flip-chip, wire bonding and capping are completed,

空：浦將所封裝的元件内部之氣體抽出，ilt為一高成本且 耗^之工作。而用WLCSP將可批次完成大量元件之封裝。 (五）現今~般10所常用之覆晶（JF1 ip Chip)技術，需 要在晶片黏合之後下填（Under fi 1 1)晶片底下之空隙，而而 此種技術，為其填充物會破壞感測器之功能或結構，故並 不適用於單晶片IC感測器等之封裝。而使用晶圓級晶粒 裝因不須下填晶片，故可避免此一問題。 、 (/、）至於利用微機電技術所製作之立體結構電感，也 因填充物會影響改變其特性，而並不適用需要下填之覆晶 技術。而使用晶圓級晶粒封裝因不須下填晶片，故可曰曰 此一問題。 兄鲁 總結上述特點，CSP晶粒封裝有下列重要考量與優點 ^)大幅降低封裝後測試費用，（2)可避免封裝時對元件的 ^ 3 )元件切告彳良率提面，（4 )可降低封裝成本，（5 ) 了，擇性的達到晶圓級真空封裝的需求，（6)並可避免覆 晶時的下填結構破壞元件問題。故WLCSP技術之開發，對 70件特性之增進與良率的提高，有相當重要的意義。 <先前技藝之描述> CSP晶粒封裝的技術發展，現今可分為幾個要點： (一）CSP的封裝牽涉一個很重要的問題就是導線問 _ 題，如何使CSP方式製作的元件内的金屬電路與系統的電 路相配合是一個技術，一般利用其機械加工或蝕刻出V型 凹槽亚，相對應的矽晶片上鍍上一個金屬墊a i pad)等石夕曰曰片與封盍晶片相互接合後，再用金屬或導電、Air: Pu pumps out the gas inside the packaged components. Ilt is a costly and expensive task. With WLCSP, a large number of components can be packaged in batches. (5) JF1 ip Chip technology commonly used today ~ 10, need to fill the gap under the chip (Under fi 1 1) after the chip is bonded, and this technology, its filling will destroy the feeling The function or structure of the sensor is not suitable for the packaging of single-chip IC sensors. This problem can be avoided because wafer-level die mounting does not require wafer filling. (/,) As for the three-dimensional structure inductor made by micro-electromechanical technology, its characteristics will be changed due to the filler, and it is not applicable to the flip-chip technology that needs to be filled. The use of wafer-level die packaging does not require a wafer to be filled, so this problem can be said. Xiong Lu summarized the above characteristics, CSP die package has the following important considerations and advantages ^) Significantly reduces the post-package test cost, (2) can avoid the component ^ 3 during packaging) The component must be improved, (4) It can reduce the packaging cost, (5), and selectively meet the requirements of wafer-level vacuum packaging, (6) and avoid the problem of underfill structure damage to the component during chip-on. Therefore, the development of WLCSP technology is of great significance to the improvement of 70 characteristics and the improvement of yield. < Description of previous techniques > The technical development of CSP die packaging can be divided into several points today: (1) CSP packaging involves a very important issue is the problem of wires, how to make CSP components The matching of the metal circuit and the system circuit is a technology. Generally, V-shaped grooves are machined or etched, and the corresponding silicon wafer is plated with a metal pad (ai pad). After the wafers are bonded to each other, metal or conductive,

第6頁 494551 五、發明說明（4) 树月曰填滿V型凹槽，因此形成了 一個金屬墊，可再利用打 、、泉來和其匕元件或系統相配合；或直接將金屬線固定於導 電樹脂中’直接完成電性上的連結（參考資料[1 ])。 (二）CSP應用於微機電元件的封裝時，由於微機電的 元件（MEMS)是一種立體的結構，而非如1(：之平面上的結 構，故在氣洽、的％境下操作，可避免直接與大氣接觸而減 少水氣對於元件的可靠度產生影響，比如壓力計即有可能 造成零點漂移6在1(：產業中，常用樹脂（epoxy)灌入封蓋 ^ λ!將1 C完全封住以達到氣密的效果。但與1 C不同之處則 是微機電元件是一種將光、機械或化學電動勢等能量轉變 =訊號的轉能器，所以它必須與外界接觸，因此樹脂封 :巧不J用於MEMS元件，故其應該在封」裝外 好虱密的考量。 石夕接= ’又稱為電埸辅助玻璃- Γ :在：ί!;?的軟化點將玻物接合的-種方 式其在黏合強度與黏合密閉度上昏义日者* f 的部份先被組合後，置於電熱柄 田又子。在欲接合 ’將1流電源供應器的正室曰溫片加熱至 於破璃則為負極，當施加於坡 在夕:' 片上，而相對 時，此玻璃與矽界面接合在一 /、、電壓至幾百伏特 第1圖所示。 ’此種陽極接合設備乃如 1%極接合過程的作用主要θPage 6 494551 V. Description of the invention (4) Shuyue Yue fills the V-shaped groove, so a metal pad is formed, which can be used with the dagger element or system to match; or directly connect the metal wire Fixing in the conductive resin 'directly completes the electrical connection (Reference [1]). (2) When CSP is applied to the packaging of micro-electro-mechanical components, since the micro-electro-mechanical components (MEMS) is a three-dimensional structure, rather than a structure on the plane of 1 (:), it is operated in a consistent environment. It can avoid direct contact with the atmosphere and reduce the impact of water and gas on the reliability of the component. For example, a pressure gauge may cause zero point drift. 6 In 1 (: industry, common resin (epoxy) is poured into the cover ^ λ! 1 C Completely sealed to achieve an air-tight effect. But the difference from 1 C is that the micro-electromechanical element is a transducer that converts energy such as light, mechanical or chemical electromotive force = signal, so it must be in contact with the outside world, so the resin Seal: It should not be used for MEMS components, so it should be considered in the package. Shi Xijie = 'Also called electric auxiliary glass-Γ: In the softening point of ί!;? Joining-a method in which the part of the stunner * f on the bonding strength and the tightness of the bonding is first combined and placed in the electric heating handle Matako. When you want to join the 'main room of the 1-stream power supply, The warm film is heated to break the glass is the negative electrode, when applied to Po Zai Xi: 'on the sheet When the relative, this interface between the bonding glass and silicon in a / ,, voltage to several hundred volts as shown in FIG. 1. "such as anodic bonding apparatus is the main function θ 1% electrode bonding process

1〇Μ)的移動，當溫度上升^疋破璃中流動離子UobiU 的移動率（mobi lity)也在辦加 玻璃中帶正電的鈉離子 曰口，亚党到在玻璃表面的負,10M), when the temperature rises, the mobility (mobi lity) of mobile ions UobiU in the glass is also added to the positively charged sodium ions in the glass.

494551 五、發明說明（5) 極的吸引而移動。而在玻璃中受束缚的負離子與鄰近的矽 表面形成一電荷層’在初始階段電壓平均分佈於玻璃中， 但在納離子向負極漂移後，於玻璃亭陽極之間的介面形成 一大的電壓降，而產生一強大的電場。而在此兩者間的電 場乃將其拉緊而接觸在一起。當使用較低溫度時，為了形 成好的接合，必須使用較南的電壓，在除去電壓之後，此 結構仍接合在一起，因為此種接合過程是不可逆的。 陽極接合對玻璃亭金屬平板的電場強度達到E = 3、X U6v/Cm而其強度達到2.4MPa。由於陽極接合溫度係在3〇〇 C—500 °C，當降至室溫時會因熱膨脹係數不同，產生熱 應力，導致彎曲或破裂。矽與玻璃的陽極接合，以康宜、、、 ί:1: 774〇(PyreX)玻璃的熱膨脹係數最接近石夕的：膨 脹係數，使用此種玻璃為接合基板的材 ^ 與元件日後使用時的信賴性。 了更、加接合 【發明之總論】 因此，本發明之目的在提出一拉 晶圓級晶粒封裝方法，且 =用％極接合之元件 造的特性。 八有衣&谷易、可以大量批次製 用石夕ΤΐΪΓΐ此種元件之晶圓級晶粒封裝方法，1## 在真空中進行陽極作有各種元件之石夕晶片 具不需焊接材料，f程？耸接合具有真空密合性佳， ρ可得到多數個相同的元件。採用； 第8頁 五、發明說明（6) 但能，簡化元件的製造過程，龙且具有批次量產的優胃占。 诱明1!，本發明之此種晶圓級晶粒封裝方法，由於使用 片做為封1，做其對乎並不-定需要使用特 ，二=、、泉之連接，亦提出了正面與背面兩種方法做為解決 “；二二面之？線連接自接合面底下拉出金屬墊，在切 =、刀副封蓋層，俾使進行晶片切割時位於金屬墊上 % t ^ f片段可自動脫落，使得金屬墊在晶片切割完成之 ί ί接暴露在元件外圍，®而能夠直接進行後續的電路 Ϊ 而！需經過進一步的處理。，面之導線連接則在 衣兀牛之刚之矽晶片上之背面先進行凹槽之姓刻，使得 正面元件之導線可經由此一貫穿晶片之凹槽自背j拉：传 此方去可使彳§唬直接自背面取出而不須特殊之切割製程， 而4曰匕種、、”構可再經由打線拉出信號，亦可直接將切割完成 之晶片以表面黏合技術（SMT)黏合於電路板上。 【較佳具體實施例的詳細描述】 、、、^下來針對本發明較佳實施例的晶圓級晶粒級封裝方 法進行插述。此處之實施例以熱阻型感測器為封裝之元 件，但實際之封裝應用並不以此種感測器為限，可應用於 其他類型之元件。在實施例一中採用背面取出導線的方 f、而在貫施例一中則採用正面取出導線的方法。實施例 二為第二種背面取出導線的方法。實施例四為利用上述三 種方法之矽基板-玻璃—矽基板封裝結構描述。實施例五則 亦利用只施例一至四的封裝，使用吸氣劑（Getter)以提高 494551 五、發明說明（7) 封裝腔内之真空度。另外，實施例六則使用電感偶合式電 聚钱刻（ICP)，再配合以電錄（£iectro piating)或導電性 粉粒注入（Power injection)法製造_貫穿基板之導電柱， 以k为面取出7Ό件之電氣信號。 【實施例一】 第2 (a)圖為自背面取出導線之熱阻型感測器的俯視 圖，第2(b)圖則為其仰視圖；第3圖為其自A-A，切線之 面圖。整個元件製作於矽基板丨之上；正面第一導線2 佈於懸洋浮板3上之導線，做為感測溫度之電阻線之用， 並由其下層之正面絕緣層4，與其上之正面保護層5所包園 住，而此一正面絕緣層—第一導線—正面保護層之結構，亦 為整個懸浮浮板3之機械支樓結構，懸浮浮板3為將底 jj::刻方式掏空之結構，用以提高其熱效應做為感測 凰轨ίΓ面第一導線2自浮板拉出至其末端之複數之正面金 屬，墊6垃繼而從複數之正面第二導線7連接之複數之連接孔 ’此^8貫穿基板之表層，連接至複數之背面第一 面/成面弟叙一導線9自複數之背面V型凹槽1 〇爬坡至背面表’ 面形”數之底部金屬墊m此與外部連接 1 2，以所入不’整個元件將以钱刻有凹槽之玻璃封蓋 i =接合法以接合界面13為接合面 進行，封蓋後之腔體14内將可保“空： 怨，以提高元件之響應度。 于/、工狀 如弟4(a)〜(n)圖所示，為實施例一之實際製程494551 V. Description of the invention (5) The pole attracts and moves. The bound negative ions in the glass form a charge layer with the adjacent silicon surface. 'In the initial stage, the voltage is evenly distributed in the glass, but after the nano ions drift to the negative electrode, a large voltage is formed at the interface between the glass pavilion anodes. Drop, and a powerful electric field is generated. The electric field between them is pulled and brought into contact with each other. When a lower temperature is used, in order to form a good bond, a souther voltage must be used. After removing the voltage, the structure is still bonded together because the bonding process is irreversible. The electric field strength of the anodic bonding on the glass pavilion metal plate reached E = 3, X U6v / Cm and its strength reached 2.4 MPa. Since the anodic bonding temperature is between 300 ° C and 500 ° C, when the temperature is lowered to room temperature, thermal stress will be generated due to different thermal expansion coefficients, resulting in bending or cracking. The anodic bonding of silicon and glass is based on the thermal expansion coefficient of Kangyi, 1: 774 (PyreX) glass that is closest to that of Shi Xi: the coefficient of expansion. Use this type of glass as the material for the substrate ^ and when the component is used in the future Reliability. In addition, the invention [summary of the invention] Therefore, the purpose of the present invention is to propose a pull-wafer level die packaging method, and the characteristics of the components with% pole bonding. Bayou & Gu Yi, a wafer-level die packaging method that can be used in a large number of batches of this kind of device, 1 ## The anode in a vacuum is used as a material for all kinds of components. No need for welding materials. , F Cheng? Tower bonding has good vacuum adhesion, and ρ can obtain many of the same elements. Adopted; Page 8 V. Description of the invention (6) However, it can simplify the manufacturing process of the components, and it has the advantage of mass production in batches. Enlightenment 1! The wafer-level die packaging method of the present invention, because the chip is used as the package 1, it does not necessarily need to use special, two = ,, and the connection of the spring, and also proposed a positive Two methods are used to solve the problem: "Two or two sides? The wire connection pulls out the metal pad from the bottom of the joint surface, and cuts the cutting layer on the metal pad, so that it is located on the metal pad when cutting the wafer.% T ^ f fragment It can be automatically peeled off, so that the metal pad is exposed to the periphery of the component after the wafer is cut, and the subsequent circuit can be directly carried out! And further processing is needed. The back surface of the silicon wafer is first engraved with the groove, so that the wires of the front component can be pulled from the back through the groove that runs through the wafer: pass this method to make it possible to take out the back directly without special The dicing process can be used to pull out signals through wire bonding, and the diced wafer can be directly bonded to the circuit board by surface bonding technology (SMT). [Detailed description of the preferred embodiment] The following describes the wafer-level die-level packaging method of the preferred embodiment of the present invention. The embodiments herein use a thermal resistance sensor as the packaged component, but the actual packaging application is not limited to this type of sensor, and can be applied to other types of components. In the first embodiment, the method of f taking out the lead wire from the back is adopted, and in the first embodiment, the method of taking out the lead wire from the front is adopted. The second embodiment is a second method for removing a lead from the back. The fourth embodiment is a description of a silicon substrate-glass-silicon substrate package structure using the above three methods. In the fifth embodiment, only the packages of the first to fourth embodiments are used, and a getter is used to improve 494551 V. Description of the invention (7) The vacuum degree in the package cavity. In addition, in the sixth embodiment, an inductive coupling type electro-polymerized coin (ICP) is used, which is then manufactured by £ iectro piating or conductive powder injection (Power injection). Take out 7 pieces of electrical signals. [Embodiment 1] Figure 2 (a) is a top view of a thermal resistance sensor from which a wire is taken out from the back, and figure 2 (b) is a bottom view thereof; and figure 3 is a plan view from AA and tangent line . The entire component is fabricated on a silicon substrate; the first lead 2 on the front is a wire on the floating board 3 as a resistance wire for temperature sensing, and the lower front insulating layer 4 and the upper insulating layer 4 The front protective layer 5 is covered by the garden, and the structure of this front insulating layer—the first wire—the front protective layer is also the mechanical branch structure of the entire floating floating plate 3. The floating floating plate 3 is the bottom jj :: 刻The structure is hollowed out to improve its thermal effect. As a sensing front rail, the first lead 2 is pulled out from the floating plate to the end of the plural front metal, and the pad 6 is then connected from the plural front second lead 7 The plurality of connection holes' this ^ 8 penetrates the surface layer of the substrate, and is connected to the first surface of the plural back surface / conducted wire 9 from the plural V-shaped grooves on the back surface 〇 climbing to the back surface 'surface shape' number The bottom metal pad m is connected to the outside 12. The entire component will be covered with a grooved glass cover i = the bonding method is performed with the bonding interface 13 as the bonding surface, and the cavity 14 after the capping The inside will be able to keep the "empty: complaint" to improve the responsiveness of the components. As shown in Figure 4 (a) ~ (n), this is the actual manufacturing process of Example 1.

第10頁 494551Page 10 494551

首先在一石夕基板1之上沉積正面絕緣層4，及背面第一 絕緣層1 5 (如第4 (a )圖），其後在背面第一絕緣層i 5罩幕定 義並蝕刻第一背面絕緣層以形成複枣之背面蝕刻窗丨6 (如 第4 ( b)圖）；其後將晶片置入蝕刻液中以蝕刻出複數之v型 凹槽1 0 (如第4 ( c)圖）；其後以蝕刻方式去除剩餘篦一北 面絕緣層(如第4⑷圖），並“溫爐管中以形； 第二背面絕緣層17(如第4(e)圖），其後在背面鍍上背面金 屬層，並以蝕刻或舉離法（Lift off)之方式定義出背面第 一導線9及底部金屬墊11 (如第4 ( f )圖）。 其次為製作正面元件之製程，首先在正面絕緣層4上 鍍上正面第一金屬層，並以蝕刻或舉離法（Lift off)之方 式定義出正面第一導線2(如第4(g)圖），其後在其上沉積 正面保護層（如第4(h)圖）；其後罩幕定義並蝕刻部分正貝面 保護層以形成複數之正面第一接觸窗18(如第4(i)圖）；其 ί罩幕定義並蝕刻另一部分正面保護層以形成複數之正面 第二接觸窗19及複數之正面蝕刻孔20 (如第4(j)圖）；其後 罩幕定，義並蝕刻另一部分正面保護層以形成接合界面/、 lj (如第4 (k)圖）；其後鏡上正面第二金屬|，並 舉離法am.。⑴之方式定義出複數之正面第二導線(= j4(l)圖）；最後以正面矽體型蝕刻方式自蝕刻孔“蝕刻 π板底下之矽基板以使該浮板懸浮（如 成元件部份之製程。 主此兀 上罩：：義Ϊ:!:!蓋’ ☆一與石夕基板相同型狀之玻璃基板 罩幕疋義亚蝕刻凹槽，以形成封蓋晶片12，使其與前述Firstly, a front insulating layer 4 and a first back insulating layer 15 (as shown in FIG. 4 (a)) are deposited on a stone substrate 1, and then a first back surface is defined and etched on the back first insulating layer i5. Insulating layer to form a back etch window of complex date (see Figure 4 (b)); then the wafer is placed in an etching solution to etch a plurality of v-shaped grooves 10 (see Figure 4 (c)) ); After that, the remaining north insulation layer (as shown in FIG. 4) is removed by etching, and “shaped in the furnace tube; the second back insulation layer 17 (as shown in FIG. 4 (e)), and then on the back The back metal layer is plated, and the back first wire 9 and the bottom metal pad 11 are defined by etching or lift off (as shown in FIG. 4 (f)). Next is the manufacturing process of the front component, first A front first metal layer is plated on the front insulation layer 4 and the front first lead 2 is defined by etching or lift off (as shown in FIG. 4 (g)), and then deposited on it Front protective layer (as shown in Figure 4 (h)); the back cover defines and etches a portion of the front protective layer to form a plurality of front first contact windows 18 (as shown in Figure 4 (i)) ; Its mask defines and etches another part of the front protective layer to form a plurality of front second contact windows 19 and a plurality of front etching holes 20 (as shown in Figure 4 (j)); the back mask defines, defines and etches another Part of the front protective layer to form the bonding interface /, lj (as shown in Figure 4 (k)); the front side of the second metal | on the rear mirror, and lift off method am .. ⑴ way to define a plurality of front second wires (= Figure j4 (l)); Finally, the front side silicon body type etching method is used to etch the silicon substrate under the π plate from the etching hole to suspend the floating plate (such as the process of forming a component part.) !:! 盖 '☆ A glass substrate cover with the same shape as Shi Xi substrate 疋 亚 etched grooves to form the cover wafer 12 and make it the same as the aforementioned

之感測器相對應；再划田撼 片與元件晶片相互；或t面對準機將此玻璃封蓋 封蓋片層與元件晶片。將固定後之 的破璃封蓋片與元γ片的：f:完成黏合的程序。黏合後 得凹槽内形成一直相對位置如第4(n)圖所示。使 使得氣體4损失；。4:元！：於此真空腔之内，因而 序，此後只要經過切=之真空封裝程 為“虎之輸出入，使用封裝内之微機電元件。 做 7:^裝好之日日片’可由背面金屬墊打線拉出信號，亦 口 (、，月面金所屬塾^^作錫球，或稱錫凸塊（Solder^ ^ %質通常為錫或錫之合金，可將其以表面黏合 某：上TeChn〇1〇gy)，黏合於電路板或陶'吏 基板上使用，如弟1 3 (a)圖所示。 尤 【實施例二】 第5圖為自正面取出導線之熱阻型感測器的俯視 第6圖為其〃自B-B，切線之斷面圖。整個元件製作於矽基板 bl之上；第一導線b2為一佈於懸浮浮板b3上之導線， 感測溫度之電阻線之用，並由其下層之正面絕緣層μ，2 其上之正面保護層b 5所包圍住，而此一正面絕緣層一正 第一導線-正面保護層之結構，亦為整個懸浮浮板b3之 械支樓結構，懸浮浮板b3為將底下矽基板以蝕刻方式掏* 之結構，用以提高其熱效應做為感測溫度之用。 二 正面第一導線b2自浮板拉出至其末端之複數金屬塾 494551 五、發明說明（ίο) b 6，並由此與外部連接。 整個元件將以蝕刻有凹槽之破璃封細 合法以接合界面bl3為接合面加以封蓋，由於 直； 中進行，封蓋後之腔體b 14内g ^ 现’、工 元件之響應度。 ㈣了保持真空狀態，以提高 如圖所示，為實施例二之實際製程 百基板bl之上沉積正面絕緣層b4(如第7(a) 圖），其後在正面絕緣層b4上鍍上正面笼入μ @弟（） 蝕刻或舉離法（Lift off)之方弟一金屬層，並以 b2(如第7⑻圖），其後在其上沉積正面保誤m 7(c)圖）；其後罩幕定義並蝕刻部分正面保9声j = 面第-接觸窗Μ8(如第7⑷圖）；其後罩幕定； 分正面保護層以形成正面姓刻孔㈣（如第7(e=另 『後以正面矽體型蝕刻方式自蝕刻孔蝕刻浮板之 板以使該浮板懸浮（如第7(f)圖） 丛之夕基 程。 、^ ;，至此兀成凡件部份之製 接著製作封蓋，在一與石夕基板相同型狀之玻 定義並蝕刻凹槽’以形封蓋晶片Μ2，使1鱼二板上 鱼測=相對應；再利用雙面或單面對準玻、則述之 ;片=件晶片移至真空陽極接合機内，進ft 4 玻：^壓、加壓力的步驟而完成黏合的程序。私二二 坡螭封蓋片與元件晶片其相對位 &合後的 凹槽內拟# _古〜 夏^ ^ K S )圖所示。佶焊 乂成”工腔bl4。元件位於此真空腔之 1 囚而The sensor corresponds to the sensor; then the field wafer and the element wafer are reciprocated; or the t-side alignment machine covers the glass to cover the wafer layer and the element wafer. After fixing the broken glass cover sheet and the element γ sheet: f: complete the bonding process. After bonding, the relative position formed in the groove is always shown in Figure 4 (n). So that gas 4 is lost; 4: Yuan! ： In this vacuum cavity, therefore, as long as the vacuum encapsulation process after cutting = is the tiger's input and output, use the micro-electromechanical components in the package. Do 7: ^ The assembled sun-chips can be backed by metal pads. Hit the wire to pull out the signal, and also use (,, 月 ^^ to which the lunar gold belongs as a solder ball, or tin bump (Solder ^ ^% quality is usually tin or an alloy of tin, which can be adhered to the surface with some: on TeChn 〇1〇gy), used on a circuit board or ceramic substrate, as shown in Figure 1 3 (a). [Embodiment 2] Figure 5 is a thermal resistance sensor from the front of the wire The top view of Figure 6 is a cross-sectional view taken from BB and tangent line. The entire device is fabricated on a silicon substrate bl; the first wire b2 is a wire arranged on the floating floating plate b3, and the resistance wire for sensing temperature And it is surrounded by the lower front insulating layer μ, 2 and the front protective layer b 5 above it, and the structure of this front insulating layer, the positive first wire-front protective layer, is also the entire floating floating plate b3 In the mechanical support structure, the floating floating plate b3 is a structure in which the underlying silicon substrate is etched * to improve its thermal effect. It is used for temperature sensing. The two front first wires b2 are pulled from the floating plate to the end of the metal 塾 494551 5. Invention Description (ίο) b 6 and connected to the outside. The entire component will be etched with The broken glass seal of the groove is sealed with the joint interface bl3 as the joint surface. Since the process proceeds straightly, the cavity b 14 in the cavity b 14 after the capping is present, and the responsiveness of the working element is maintained. In order to improve, as shown in the figure, the front insulation layer b4 is deposited on the substrate 100 b of the actual manufacturing process of the second embodiment (as shown in FIG. 7 (a)), and then the front insulation layer b4 is plated with a front cage into μ @ Brother () Etching or lifting off (Lift off) a metal layer and using b2 (as shown in Figure 7⑻), and then depositing a front-side security m 7 (c) on it; Define and etch part of the front surface to protect 9 sounds j = surface-contact window M8 (as shown in Figure 7); the rear cover is set; divide the front protective layer to form the front-face engraved hole ㈣ (such as No. 7 (e = another "back" The plate of the floating plate is etched from the etching hole by the front silicon body type etching method to suspend the floating plate (as shown in FIG. 7 (f)). The formation of this part is followed by the production of a cover. A glass with the same shape as that of the Shixi substrate is used to define and etch the groove 'to cover the wafer M2 in a shape, so that the fish on the two boards corresponds to the fish; Then use double-sided or single-sided glass alignment, as described; wafer = piece of wafer is moved into the vacuum anodizing machine, into the ft 4 glass: ^ pressure, pressure steps to complete the bonding process. Private Er Er Po seal The relative position of the cover sheet and the component wafer is shown in the following figure. _ 古 ～ 夏 ^^ KS). The welding is completed into a working cavity bl4. The component is located in one of the vacuum chambers.

第13頁 494551 五、發明說明（11) :得ϋ:傳損失大幅減少。完成晶 序，此後先經第一次切割，使盆 ^工封裝私 經第二次切割分離各 弟-金屬塾之後，再 f分儿什μ兀成早兀元 圖）’此後可經由正面之金屬墊，做 用封裝内之微機電元件。 琥之輸出入，使 【實施例三】 第8(a)圖為第二種自背面取出 俯視圖，第8⑻圖則為其仰視圖；第…圖：二則器： 線之斷面圖。整個元件製作於石夕基！為：πPage 13 494551 V. Description of the invention (11): Success: The transmission loss has been greatly reduced. After completing the crystal sequence, after the first cut, the potting package is separated by the second cut to separate the younger brothers-metal puppets, and then f points are formed into early elements)) Metal pads are used as micro-electromechanical components in the package. The input and output of Hu are as follows: [Embodiment 3] Figure 8 (a) is the second top view taken from the back, and Figure 8 (b) is its bottom view; Figure…: Second device: cross-sectional view of the line. The entire element is made in Shi Xiji! For: π

線c2為一佈於懸浮浮板c3上之 ，正面弟一 V 缘之用，计A盆nr a — 天做為感測溫度之電阻 琛之用亚由其下層之正面絕緣層c4，鱼1 層C5所包圍住’而此—正面絕緣 」、導 == 亦為整個懸浮浮板3之機械支樓： =ί:二基板以姓刻方式掏空之結構，用；提… 效應做為感測溫度之用。 攸门％ 屬浮板拉出至其末端之複數之正面金 ίί *第一金屬層直接經由貫穿基板表層之連接 孔C8 ’連接至複數背面第一導線c 板==接 數之背Μ型凹槽Cl。攸坡至背面表面；:”C9自複 墊c"，並由此與外部連接。 面也成稷數之底部金屬 整個元件將以钱刻有凹槽之破璃 合法以接合界面Cl3為接合面加以封，二以陽極接 士、在> 了盒，由於封蓋在直办 中進仃，封蓋後之腔體C14内將可保持直* 裎: 元件之響應度。在部份情形下，如金屬、^狀/，以獒面 复屬墊周邊平整度不佳‘ 、發明說明（12) 2 ’如第9(b)圖所示，可以於玻螭封蓋ci2在相含 蝕刻凹槽cl5，以加強接合之完整性。 而其結構之製程可參考實施例—之 :型凹槽Cl。頂端之背面第一導線。9貫穿基板表層 導線c2形成電氣性連接即可。 :封裝好之晶4，可由背面金屬墊打線拉出 在八背面金屬墊上製作錫球了，或稱錫凸塊，月 \ =黏合技術，黏合於電路板或陶瓷基板上使用 13(d)圖所不。 【貫施例四】 由於陽極接合法適用於玻璃與矽基板之接合 元件之封裝亦可做成矽基板—玻璃-矽基板之三^ 將^上製作有元件之矽晶片與一蝕刻有貫穿孔之 打陽極合，而使元件之位置落於該貫穿孔内，再 之晶片與另一矽基板進行陽極接合，形成矽基板 ，板之三層結構，第1 〇圖為其應用於背面取出信 第11圖為其應用於正面取出信號之例；第1 2圖為 第二種背面取出信號之例；其上層之矽基板亦可 濾光片，如此則可做為紅外線感測之應用元件的 用0 而封裝好之jg面取出導線石夕基板~坡壤—石夕基 可由背面金屬墊打線拉出信號，亦可在背面金2 錫球T ’將其以表面黏合技術，黏合於電路板戋p 上使用，如第1 3 (b )〜（c )圖所示。 吁位置處 接將背面 與正面第 信號，亦 「將其以 ，如第 ’故以上 結構，先 玻璃片進 將此接合 -玻璃-石夕 號之例； 其應用於 為紅外線 封裝之 板晶片’ 墊上製作 句瓷基板 494551 五、發明說明（13) 【實施例五 吸氣二封Λ時一㈣^ 。w 、此吸軋劑Α可通¥電流或加溫（〜40ϋ 辦，以堆持肿內活性化之吸氣劑可吸附腔體内之稀薄氣 ;二=高真空度，並避免因腔壁或腔内元件材 ^ 口 〇釋放氣_ut gassing)所造成之真空度的破 。(：：：I 士 ί陽極華合在黏合之時需加溫至約35°〜450 C.，故右f則述之實施例中，若在元件製作過程中在腔體 内置入吸氣劑，則可Α、# —私人认门士 、枉甲社腔篮 之古W將盆、、壬W养在進订*的同4，利用陽極接合時 釋放出來的氣體，而維持腔内較高之真空】材=:所 〜（f)圖所示。 又如弟14(a) 【實施例六】 另外，晶圓級晶粒封裝之導線拉出方法， ，式電漿钮刻(ICP)，在基板底部打出貫穿亦二使之用， 穿孔，再以電鍍(Electro plating)或導電性粉ς注入貝 (Power inject10n)法將貫穿孔内填滿金屬， 性之導電柱d 1，再以錫球或金屬墊與外 、、' 之連接。如第15(a)、15⑻圖所卜^電路形成電氣性 本發明雖然以六種較佳實施例對本發明 熟習本技藝者當能在不脫離本發明之實卩汉、11 惟 況下，做出種種變化及修改。因此，本=神及範圍的情 列專利申請範圍所界定。 “明之範，當由下The line c2 is a cloth on the floating floating plate c3, the front edge is a V edge, and the basin A is nr a — the sky is used as a temperature sensing resistor. The front insulation layer c4 is below it, and the fish 1 The layer C5 is surrounded by 'and this—front insulation', the guide == is also the mechanical branch of the entire floating board 3: = ί: the structure of the two substrates hollowed out by the last name carved, used; For temperature measurement. The first metal layer is a plurality of frontal gold that is pulled out to the end of the floating plate. The first metal layer is directly connected to the plurality of first wire c-plates on the back surface through the connection hole C8 'through the surface layer of the substrate. Slot Cl. Youpo to the back surface; "" C9 self-recovering pad c ", and thus connected to the outside. The bottom metal surface of the entire element will also be broken glass with a groove engraved with money and the bonding interface Cl3 as the bonding surface. Sealed, the second is the anode connection, and the box is in>. Since the cap is inserted in the direct processing, the cavity C14 after capping will be kept straight * 裎: the responsivity of the component. In some cases , Such as metal, 状 /, the flatness of the peripheral surface of the pad is not good, and the description of the invention (12) 2 'As shown in Figure 9 (b), the ci2 can be etched on the glass cover. The groove cl5 is used to enhance the integrity of the joint. For the structure of the structure, please refer to the embodiment—the groove C. The first wire on the top and the back. 9 The electric wire c2 can be formed through the surface layer of the substrate. The crystal 4 can be pulled out from the back metal pad to make tin balls on eight back metal pads, or tin bumps. The monthly bonding technology is used to adhere to the circuit board or ceramic substrate using 13 (d). [Example 4] Because the anodic bonding method is suitable for packaging components of glass and silicon substrates, Make a silicon substrate-glass-silicon substrate three ^ Combine the silicon wafer with the element fabricated on ^ and an anode with a through-hole etched so that the position of the component falls within the through-hole, and then the wafer and another The silicon substrate is anodically bonded to form a three-layer structure of the silicon substrate and the board. Fig. 10 is an example of the application of the back-side extraction letter. Fig. 11 is an example of the application of the front-side extraction signal. Examples of signals; the upper silicon substrate can also be used as a filter, so it can be used as an infrared sensing application component. Use 0 to encapsulate the jg side. Take out the wire stone substrate ~ slope soil-Shi Xiji can be back metal Pad the wire to pull out the signal, and it can also be used on the backside of the gold 2 solder ball T 'to adhere to the circuit board 戋 p, as shown in Figures 1 (b) to (c). Connect the signal on the back and front, and also "make it as in the above structure, the first example is the glass piece into this joint-glass-Shi Xihao; it is applied to the board chip for infrared packaging" making sentence Porcelain substrate 494551 V. Description of the invention (13) [ Example 5: Two seals when inhaling, one time ^. W. This suction agent A can be charged with ¥ current or warmed (~ 40ϋ), and the activated getter that accumulates in the tumor can absorb the thinness in the cavity. Gas; two = high vacuum, and avoid breaking the vacuum caused by the cavity wall or the component material in the cavity ^ 〇 gas release (ut gassing). (::: I Shi Hua anode need to be bonded at the time of bonding Warm to about 35 ° ~ 450 C., so in the embodiment described on the right, if the getter is built into the cavity during the component manufacturing process, then A, # —Private Adviser, Biejia Society The ancient basket of the cavity basket is kept in the same place as the order *, and the gas released during the anodic bonding is used to maintain a high vacuum in the cavity.] = = So (f) shown in the figure. Another example is Brother 14 (a) [Embodiment 6] In addition, the method of pulling out the wires of the wafer-level die package, using a plasma plasma engraving (ICP), punching through the bottom of the substrate is also used, perforation, and then Fill the through hole with metal by electroplating or conductive powder injection method (Power inject10n), and then use conductive balls d 1, and then connect to the outer, and 'by solder balls or metal pads. As shown in Figures 15 (a) and 15, the circuit is formed electrically. Although the present invention is familiar to the skilled person in the present invention with six preferred embodiments, it can be done without departing from the actual practice of the present invention. 11 Various changes and modifications. Therefore, the scope of this patent application is defined by the scope of this patent. "Ming Zhifan, the moment

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第17頁 494551 圖式簡單說明 第1圖顯示陽極接合之裝置設置圖。 第2 (a)圖顯示自背面取出導線之晶圓級晶粒封裝元件 之俯視圖。 _ 第2 (b)圖顯示自背面取出導線之晶圓級晶粒封裝元件 之仰視圖。 第3圖顯示圖1 (a)自A-A’橫切之斷面圖。 第4 ( a)〜（η)圖顯示自背面取出導線之晶圓級晶粒封 裝元件之製作流程。. 弟5圖顯不自正面取出導線之晶圓級晶粒封裝元件之 俯視圖。 第6圖顯示第4圖自Β-Β’橫切之斷面圖。 第7 ( a)〜（h )圖顯示自正面取出導線之晶圓級晶粒封 裝元件之製作流程。 第8 ( a)圖顯示第二種自背面取出導線之晶圓級晶粒封 裝元件之俯視圖。 第8 (b)圖顯示第二種自背面取出導線之晶圓級晶粒封 裝元件之仰視圖。 第9圖顯示圖8(a)自C-C’橫切之斷面圖。 第1 0圖用來說明自正面取出導線之矽基板-玻璃-矽基 板晶圓級晶粒封裝元件結構。 第11圖用來說明自背面取出導線之矽基板-玻璃-矽基 板晶圓級晶粒封裝元件結構。 第12圖用來說明第二種自正面取出導線之矽基板-玻 璃-矽基板晶圓級晶粒封裝元件結構。Page 17 494551 Brief description of the drawings Figure 1 shows the arrangement of the anodic bonding device. Figure 2 (a) shows a top view of a wafer-level die-package component with leads removed from the back. _ Figure 2 (b) shows a bottom view of a wafer-level die-package component with leads removed from the back. Fig. 3 is a cross-sectional view taken from A-A 'in Fig. 1 (a). Figures 4 (a) ~ (η) show the manufacturing process of a wafer-level die-packaged component with leads removed from the back. Figure 5 shows a top view of a wafer-level die-package component that does not remove wires from the front. Fig. 6 shows a cross-sectional view of Fig. 4 taken from B-B '. Figures 7 (a) ~ (h) show the manufacturing process of a wafer-level die-packaged component with leads removed from the front. Figure 8 (a) shows a top view of a second wafer-level die-packaging component with wires removed from the back. Figure 8 (b) shows a bottom view of a second wafer-level die-packaging component with wires removed from the back. Fig. 9 shows a cross-sectional view of Fig. 8 (a) taken from C-C '. Figure 10 is used to illustrate the structure of a silicon substrate-glass-silicon substrate wafer-level die package component with wires taken out from the front. Figure 11 is used to illustrate the structure of a silicon substrate-glass-silicon substrate wafer-level die package component with wires removed from the back. Figure 12 is used to explain the second silicon substrate-glass-silicon substrate wafer-level die package component structure with wires taken out from the front.

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圖式簡單說明 第13(a)〜（d)圖用來說明晶圓級晶粒真空封裝利用錫 球之表面黏著封裝技術。 第14(a)〜（f)圖用來說明晶圓％晶粒真空封裝在腔體 内置放吸氣劑（Gatter)以提高其真空特性。 一 第1 5 ( a )圖用來說明晶圓級晶粒封裝使用I 與電^戈 導線，粉粒（如金屬粉粒等）注人法經由金屬墊拉出'導^二 莫的ΐb)圖用來說明晶圓級晶粒封裝使用1CP與電鍍或 V、、泉性粉粒注入法經申錫球拉出導線。 〆Brief Description of Drawings Figures 13 (a) ~ (d) are used to illustrate wafer-level die vacuum packaging using the surface-adhesive packaging technology of solder balls. Figures 14 (a) to (f) are used to illustrate the wafer's% die vacuum package in the cavity. A getter (Gatter) is built in to improve its vacuum characteristics. A first 15 (a) diagram is used to illustrate the use of I and electrical wires in wafer-level die packaging. Powder particles (such as metal powder particles) are injected through a metal pad to pull out the lead. The diagram is used to illustrate the use of 1CP and electroplating or V, spring powder implantation method for wafer-level die package to pull out the wires through the solder balls. 〆

圖式中元件名稱與符號對 矽基板 正面第一導線 懸浮浮板 正面絕緣層 正面保護層 正面金屬墊 正面第二導線 連接孔 10 11 12 13 14Component name and symbol pair in the diagram Silicon substrate Front first lead Floating board Front insulation layer Front protection layer Front metal pad Front second lead Connection hole 10 11 12 13 14

背面第一導線 V型凹槽 背面金屬墊 坡螭封蓋晶片 接合界面 真空腔First wire on the back V-groove Back metal pad Poll cover wafer Bonding interface Vacuum chamber

第19頁 494551 圖式簡單說明 、 1 5 :背面第一絕緣層 1 6 :背面蝕刻窗 ♦ 1 7 :背面第二絕緣層 _ 18 :正面第一接觸窗 19 :正面第二接觸窗 2 0 :正面钮刻孔 b 1 :矽基板 b 2 :正面第一導緣 b3 :懸浮浮板 b 4 :正面絕緣層 · b 5 :正面保護層 b 6 :正面金屬墊 bl2 ·玻璃封盡晶片 bl3 :接合界面 b 1 4 :真空腔 bl8 :正面第一接觸窗 b20 :正面蝕刻孔 c 1 :矽基板 c 2 :正面第一導線 c3 :懸浮浮板 · c4 :正面絕緣層 c 5 :正面保護層 c8 :連接孔 c 9 :背面第一導線Page 19, 494551 Brief description of the drawings, 1 5: First back insulating layer 16: Back etching window 17: Back second insulating layer _ 18: Front first contact window 19: Front second contact window 2 0: Front button cut hole b 1: Silicon substrate b 2: Front first guide edge b3: Floating floating plate b 4: Front insulation layer b 5: Front protective layer b 6: Front metal pad bl2 · Glass seal wafer bl3: Bonding Interface b 1 4: Vacuum cavity bl8: Front first contact window b20: Front etching hole c 1: Silicon substrate c 2: Front first lead c3: Floating floating plate c4: Front insulation layer c 5: Front protective layer c8: Connection hole c 9: the first wire on the back

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第21頁Page 21

Claims (1)

494551 90102709 年 y日修經正/補充 修煩 正翁 有 無！ 1¾ 客 是 否 准 予 修 正 听 % 择蓋 互 \、申請專利範圍 1 · 一種晶圓級晶粒封裝方法’經由該力法封裝後之元 件具有一基座、一黏合於該基座上方的玻璃封蓋、及一位 於該基座與該玻璃封蓋之間的元件體；其封裝方法包含下 列步驟： 在做為基座之矽基板上之背面利用異方性蝕刻製作複 之V型之凹槽，此凹槽之深度貫穿基板並在正面露出一 苧小接觸窗，而凹槽内並鍍有金屬層，且從凹槽内之接觸窗 w延伸至晶片背面表層，使得製作於正面之元件之電氣訊號 可以經由該接觸窗及金屬層自背面輸出及輸入； - 於基座正面製作元件體，另一黏合於該基座上方的封 為一 Ί虫刻有凹槽之玻璃晶片’將該玻璃晶片與該基座相 、士》 、.二 r-r-y _Λ- 到-〒业四足 ， 將對準且固定的玻璃晶片、與該基座置於真空環境 中；以及 使該玻璃晶片與該基座升溫到陽極接合所須之溫度， 並施加壓力及電壓於該玻璃晶片與該基座，使其界面得以 黏合；並使該封蓋晶片與該基座之間的空間維持氣密狀 態° 2. —種晶圓級晶粒封裝方法，經由該方法封裝後之元 件具有一基座、一黏合於該基座上方的玻璃封蓋、及一位 於該基座與該玻璃封蓋之間的元件體；其封裝方法包含下 列步驟： 在做為基座之矽基板正面製作元件體；另一黏合於該 基座上方的封蓋為一蝕刻有凹槽之玻璃晶片，將該玻璃晶 —i ilvaartf.494551 90102709 Years Scripture Correction / Additional Remedy Zheng Weng Yes No! 1¾ Whether the customer is allowed to amend the choice of the cover, the scope of the patent application 1 · A wafer-level die packaging method 'The component packaged by the force method has a base and a glass cover glued on the base And a component body located between the base and the glass cover; its packaging method includes the following steps: using anisotropic etching to make a complex V-shaped groove on the back surface of the silicon substrate as the base, The depth of this groove penetrates the substrate and exposes a small contact window on the front side. The groove is also plated with a metal layer, and extends from the contact window w in the groove to the surface layer on the back of the wafer, so that the electrical components made on the front side are electrically The signal can be output and input from the back through the contact window and the metal layer;-a component body is made on the front of the base, and another glass chip with a groove inscribed on the base is sealed on the base. With the pedestal, taxi, and two rry _Λ- to-professional four-legged, place the aligned and fixed glass wafer and the pedestal in a vacuum environment; and heat the glass wafer and the pedestal To the sun The temperature required for electrode bonding, and applying pressure and voltage to the glass wafer and the pedestal so that the interface is adhered; and the space between the cover wafer and the pedestal is maintained airtight. A wafer-level die packaging method. A component packaged by the method has a base, a glass cover adhered to the base, and a component body located between the base and the glass cover. The packaging method includes the following steps: a component body is fabricated on the front surface of the silicon substrate as a base; another cover bonded to the base is an etched glass wafer, and the glass crystal is i ilvaartf. ϋϋ ϋ 第22頁 .差盒—9010270922 Page 22 .Differential Box—90102709 六、申請專利範圍 片興該基座相互對準並固定， 將對準並固定的破璃θ 中； ‘日日 、/、该基座置於真空環境 、，使該玻璃晶片與該基座升溫刭陪, f施加壓力及電壓於該玻璃晶片| ^合所須之溫度， 黏合；並使該封蓋晶片盥爷美之、=土座，使其界面得以 態； Λ 土座之間的空間維持氣密狀 其中元件之導線绫由 $ 並形成金屬墊，在切割時將:1 =底下拉出元件之腔體外 盍，再切割分離單元元#以刀*此金屬墊上方之部份封 仟以利打線。 3 · —種日日圓級晶粒封 件具有一基座、一黏合於^美庙i!由該方法封裝後之元 於該基座與該玻螭封罢=二A上方的玻璃封蓋、及—位 列步驟： 間的元件體；其封裝方法包括下 在做為基座之矽基板上 漿蝕刻技術，InclUct Ί· Va Γ ^ 利用1CP(電感耦合式電 、 Lj I ϊ— \ΎΤ^ J -y U電鍍或粉粒注入法將I # 路出一小接觸窗，再 成一導電柱，以完成電;二==滿金屬或導電.物質，形 :之電氣訊號可以經由該接觸=全：:，於正面之元 ， ”屬柱自为面輸出及輸 - 於基座正面製作元件體；另—★ 1為一蝕刻有凹槽之坡螭:片—黏合於該基座上方的封 互對準並固定，· ’將該破璃晶片與該基座相 494551 案號 901027096. Scope of patent application: The base shall be aligned and fixed with each other, and the aligned and fixed broken glass θ shall be placed; 'Day and / or, the base is placed in a vacuum environment, so that the glass wafer and the base When the temperature rises, f applies pressure and voltage to the temperature required for the glass wafer. ^ Adheres to the temperature required for the glass wafer; and makes the cover wafer beautiful, = soil seat, so that the interface can be in a state; Λ between the soil seat The space is kept airtight. The wire of the component 绫 is formed by $ and forms a metal pad. When cutting: 1 = bottom out of the cavity of the component 盍, and then cut the separation unit element # with a knife * to seal the part above the metal pad.仟 Eli hit the line. 3 · —Japanese-Japanese-grade die seals have a base and an adhesive bonded to 美 美 寺 i! The element sealed by the method on the base and the glass seal is a glass cover above two A, And-steps: the component body in between; its packaging method includes a silicon substrate sizing etching technique as a base, InclUct Va · Va Γ ^ using 1CP (inductive coupled electric, Lj I ϊ — \ ΎΤ ^ J -y U electroplating or powder injection method will pass I # out of a small contact window, and then form a conductive pillar to complete electricity; two == full metal or conductive. Substance, shape: the electrical signal can pass through the contact = full ：: The element on the front side, "Column output and output on its own-make the component body on the front side of the base; another — ★ 1 is an etched groove with a groove: sheet — the seal glued to the top of the base Align and fix each other, · 'Phase the broken glass wafer with the base 494551 Case No. 90102709 六、申請專利範圍 --------- 將對準且固定的玻螭晶片、 & π俨产 中· 興邊基座置於真空土 兄 璃晶片* $基座升溫到陽之溫度， 黏合；並使該封蓋晶片與該基座’使其界面得以 。 、^基座之間的空間維持氣密狀 4·如申請專利範圍第i項 法，其封蓋方物晶片―以：2片項；弟3項所述之方* 晶片組合。 坡螭曰曰片—矽晶片結構或複數之 5.如申請專利範圍第丨項或第2項或方 法，其中封裝好之晶片係以錫球直 項所^方 以利後續封裝流程（Assembly)者。仃表面黏合技術， ^如申請專利範圍第丨項或第2項或第3項所述之 空特：I在腔體内置有吸氣劑』改善其封裝後腔内之真 班士7·如申請專利範圍第4項所述之方法，其中在腔r内 且有吸氣劑，以改善其腔内之真空特性者。 旦 8·如申請專利範圍第5項所述之方法，其中在腔體内 置有吸氣劑，以改善其腔内之真空特性者。Sixth, the scope of patent application --------- Put the aligned and fixed glass wafer, & π production in production · Xingbian pedestal is placed on the vacuum earth glass wafer * $ The susceptor is heated to the temperature of the sun And bonding; and the interface between the cover wafer and the base is made. The space between the bases is kept airtight. 4. According to item i of the scope of patent application, it covers the cube wafers:-2 wafers; the method described in 3 *. Po yue yue—Silicon wafer structure or plural 5. If the scope of application for the patent application item 丨 or item 2 or method, the packaged wafer is the solder ball direct item ^ to facilitate subsequent packaging process (Assembly) By.仃 Surface bonding technology, ^ As described in item 丨 or item 2 or item 3 of the scope of patent application: I have a getter built into the cavity. 』Improve the real class inside the cavity after packaging. 7 · 如The method described in item 4 of the scope of patent application, wherein a getter is in the cavity r to improve the vacuum characteristics in the cavity. Once the method according to item 5 of the scope of patent application, wherein a getter is placed in the cavity to improve the vacuum characteristics in the cavity.