TW490771B

TW490771B - Integrated high frequency module and its wafer level manufacture and package method

Info

Publication number: TW490771B
Application number: TW090109115A
Authority: TW
Inventors: Jeng-Guo Li; Jiun-Shian Li; Shu-Huei Tsai
Original assignee: Asia Pacific Microsystems Inc
Priority date: 2001-04-17
Filing date: 2001-04-17
Publication date: 2002-06-11

Abstract

This invention provides a novel wafer level high frequency module manufacture process, which can integrate and modulate individual device manufacture process in wafer level, and integrated wafer level package technique. Various active devices are made first using most cost-effective and yield-advantaged manufacture process, various passive devices are made then through a wafer level integrated manufacture process, and integrated process flow is completed by wafer level package technique, which provide complete function of the high frequency module and protect devices from being damaged during package dicing and thus yield loss. The inventive method avoids the use of underfill process to prevent modulated various devices from damage in the underfill process. Moreover, the inventive method also provides wafer level test and burn-in for the high frequency module, which can reduce cost in package and test.

Description

〈發明之背景〉 t發明係關於一種整合型高頻模組及其製造與封 f，特別是利用低成本高精度之薄、厚膜整合性前段製，，與後段晶圓級晶粒封裝或晶圓級覆晶（fUp chi/) 封裝程序進行各類打線及製作錫鉛球以完成各元件與外界，性連結（interconnection)與界面封裝之新型積體化1 鬲頻模組。〈先前技術之描述〉 X ♦行動通訊之蓬勃發展加速了相關高頻無線電子零件之需求。無線通訊產品的行動能力端賴於零組件的尺寸及電_ 池續航力。零件製造商也致力於開發更微小、價格更便宜且性能更好的元件。微小化的最終作法就是將其與I c整合，成為系統晶片（System-on-chip, S0C )。但系統晶片說來容易做來難，尤其在整合來自不同公司，不同智慧財誇（Intellectual property, IP)之獨特設計時，常常須要耗費相當多的時間作整合及轉換工作。因此必須發 j展厂種系統層級的整合技術以快速地將不同設計公司、不同晶圓、不同製程的晶粒（Di e )進行整合，同時個別的晶粒可先完成測試，即K G D ( Κ η 〇 w n G ο 〇 d D i e )流程，再進行系統層級之模組組裝（assemb ly )，之後可再更進一® 步進行晶圓級測試，來提升良率且減少不必要的封裝成本。對客戶端而言，透過客制化（Customization )的設、計，可以縮短產品的設計時間、減少產品體積、耗電及降低電磁干擾（EM I )。因此，通訊系統為了達到體積小、五、發明說明（2) =性2及降低系統整合複雜度的目標，目前別功能的電路先以高密度的積體電路方式來貝現，再將屬於不同萝圭十梦方十伽4叙-放杜^ 或晶圓材料的主動元件以 *裝方式與被動兀件整合在一起形成高頻模組 (System-in-a-package)的技術。需要：：i ::㊁：整合主被動元件的高頻模組，首先 2 ^ ^ - 4 ^ ° 1兀1件。以整合型被動元件的應用為 :二Jd:技術令1前比較具有成本及功能 : 如下：—種為低溫共燒陶究 4§ r έ 4lJ ^ 一種即為與Ic製程相容的薄膜型整合高痛。低溫共燒陶純組產品的最大好處是對高頻 = 高，但是待解決的問題則相當，，包括線 ί於末取-::在5°mm以上）、量測上的困難、上游陶是=末取件不易寺，並且製程上陶£會發生收縮而使 g模挺結果偏差很大，且不易修整。基本上，就製作費去，製程相容的薄膜型整合高頻模組與低溫共燒，陶;竞兩者之製作費用大致卜i ^ ! ·^ ^ ,衣卞買用大致上相差不多，但是目前薄膜型整面頻模組的優勢在於可以製作出尺寸更小且精度更言尚0模組，並且在元件模型的建立上可整合主動元件= ，電性貧料來實現系統化的整體電路模擬分析，並在社人《完整且系、统化的模擬資料*與扎實的製程資料庫後，動通訊高頻模組之開發成本及進入市場所需的研發牯間（Time to Market )。第la圖及第lb圖即為美國Intarsia公司分別在2〇㈣年第5頁 490771 五、發明說明（3) 8月與12月於Wireiess Systems Design所揭示的一個以薄膜製程製作的整合型被動元件高頻模組（參考資料1、2 )。第la圖為形成電阻的步驟，而第lb圖為利用與IC製程相容的薄膜製程來製作包含電感、電容，以及電阻等之整合型被動元件。如第1 a圖所示，薄膜電阻的形成，首先在玻璃基板10上沈積並定義電阻層n，其後沈積並以蝕刻或剝離法（Lift-off)的步驟定義第一金屬圖案12。此第一金屬圖案12作為電阻r兩端電極。其後，沈積並定義第二介電層1 5作為隔絕用途。又如第丨b圖所示，形成積體化整合型被動元件係首先在基板丨〇上沈積並定義電阻層丨丨，其_ 後，積並以蝕刻或以剝離法的製程定義第一金屬圖案丨2 了此第一金屬圖案1 2作為電阻!^兩端電極；其後，沈積第一介，層13及第二金屬圖案14，第一介電層13與上下包夾的第一金屬圖案1 2、第二金屬圖案丨4而形成電容[;其，:’在電阻R及電容C上形成用來隔絕用的第二介電層1 5 ; 第二介電層1 5必須具有足夠的厚度以覆蓋元件並均$塗佈丨於，基板上；其後在第二介電層i 5上定義導線引孔，再形成 =電=連，以及與後續金屬導線17間之附著力的緩衝層 :並·定羞U签〇Γ adheSi〇n Uyer)，之後，於沈積並疋義弟二金屬圖案17時·，同時構成電裝完成電性連接的錫錯球（solder bumper):金=封 (metal pad ) 〇而此類元件一般所使用的半導體積體電路的封裝式’如❿圖及第Η圖所示。如第1〇圖，首先上<Background of the invention> The invention relates to an integrated high-frequency module and its manufacturing and sealing, especially the use of a low-cost, high-precision thin, thick-film integrated front-end system, and a wafer-level die package or wafer at the later stage. The fUp chi / package process performs all kinds of wire bonding and tin-lead balls to complete the new integrated 1-frequency module of each component and the outside world, sexual connection (interconnection) and interface packaging. 〈Description of the prior art〉 X ♦ The vigorous development of mobile communications has accelerated the demand for related high-frequency wireless electronic parts. The mobility of wireless communication products depends on the size of the components and battery life. Parts manufacturers are also working to develop smaller, cheaper, and better-performing components. The final method of miniaturization is to integrate it with I c to become a system-on-chip (S0C). However, the system chip is easier said than done. Especially when integrating unique designs from different companies and different Intellectual property (IP), it often takes a considerable amount of time for integration and conversion. Therefore, it is necessary to develop system-level integration technology at the factory to quickly integrate the dies of different design companies, different wafers, and different processes. At the same time, individual dies can be tested first, that is, KGD (Κ η 〇wn G ο 〇d D) process, and then system-level module assembly (assembly), and then can go one step further for wafer-level testing to improve yield and reduce unnecessary packaging costs. For the client, through the customization design, the design time, product volume, power consumption, and electromagnetic interference (EM I) of the product can be shortened. Therefore, in order to achieve the small size, the fifth, the invention description (2) = 2 and the goal of reducing the integration complexity of the system, the circuits of other functions are now implemented as high-density integrated circuits, and then belong to different The technology of Luogui Shimengfang Shiga 4G-Fu Dufang or wafer materials is integrated with passive components to form a high-frequency module (System-in-a-package) technology. Requires :: i :: ㊁: High-frequency module integrating active and passive components, first 2 ^ ^-4 ^ ° 1 unit. The application of integrated passive components is as follows: Two Jd: Technology makes it more cost-effective and functional before 1. It is as follows:-a kind of low-temperature co-fired ceramics 4§ r 4lJ ^ a kind of film-type integration compatible with Ic process High pain. The biggest advantage of the low-temperature co-fired pure ceramic products is high-frequency = high, but the problems to be solved are equivalent, including the line from the end to the end-:: above 5 ° mm), measurement difficulties, upstream ceramics Yes = the last part is not easy, and the ceramics will shrink during the manufacturing process, which will make the g mold result very different, and it is not easy to trim. Basically, in terms of production costs, the process-compatible thin-film integrated high-frequency module is compatible with low-temperature co-firing, ceramics; the production costs of the two are roughly ^! · ^ ^, And the purchase of clothing is generally similar, but at present The advantages of the thin-film type full-frequency module are that it can produce smaller modules with less accuracy and 0, and can integrate active components in the establishment of the component model =, electrical system to achieve a systematic overall circuit simulation Analysis and after the company's "Complete and systematic simulation data * and solid process database, the development cost of mobile communication high-frequency modules and the time to market required to enter the market (Time to Market). Figures la and lb are the United States Intarsia company's 5th page 490771 of the year 20, 5. Description of the invention (3) An integrated passive film manufacturing process disclosed by Wireiess Systems Design in August and December Component high-frequency module (references 1, 2). Figure la illustrates the steps of forming a resistor, and Figure lb illustrates the use of a thin film process compatible with the IC process to fabricate integrated passive components including inductors, capacitors, and resistors. As shown in Fig. 1a, the formation of a thin film resistor firstly deposits and defines a resistance layer n on a glass substrate 10, and then deposits and defines a first metal pattern 12 by a step of etching or lift-off. The first metal pattern 12 serves as an electrode at both ends of the resistor r. Thereafter, a second dielectric layer 15 is deposited and defined as an insulation use. As shown in FIG. 丨 b, the integrated integrated passive element is firstly deposited and defined on the substrate 丨〇, and then _ is used to define the first metal by etching or by a lift-off process. Pattern 丨 2 The first metal pattern 12 is used as a resistor! ^ Both electrodes; thereafter, a first dielectric layer 13 and a second metal pattern 14 are deposited, the first dielectric layer 13 and the first metal sandwiched between the upper and lower layers. Pattern 1 2. The second metal pattern 丨 4 to form a capacitor [; which: 'formed a second dielectric layer 15 for isolation on the resistor R and the capacitor C; the second dielectric layer 15 must have sufficient The thickness is to cover the components and all are coated on the substrate; subsequently, the lead-through holes are defined on the second dielectric layer i 5, and then formed = electrical = connected, and the adhesion with the subsequent metal wires 17 Buffer layer: 定定羞 Usign 〇Γ adheSi〇n Uyer), and then, when the second metal pattern 17 is deposited and deposited, at the same time, a solder bumper is formed to complete the electrical connection of the assembly: gold = Package (metal pad) 〇 And such components are generally used in semiconductor integrated circuit package type 'as shown in the figure and figure Shows. As shown in Figure 10, first

、發明說明（4) 方式球18，其後以覆晶接合（flip-chip b〇nding) (向分子基板封蓋19接合後，進行填膠2 Ο 1 d圖 _ ； ’错此增加錫鉛接點的可靠性。或者如第板1〇上不’先以覆晶接合方式將主動元件21接合在玻璃基式與古^再在金屬層上成長锡叙球1 8 ’其後以覆晶接合方俊=Γ!分子基板封蓋19接合後，進行填膠20。此封裝方式増加真膠步驟，其材料2 0係靠毛細現象自然流動，雖然易精二，錯接點的可靠性，然而因其流動性及流動時間不產2。莩控，會使製程良率降低，且其固化時間長，影響件制Ξ此本發明旨在晶圓階段提供一能整合模組的各類元完整二ί!新型製程及積體化封裝技術，來提供高頻模組的 ^良^巧’且保護元件免於遭受到封裝切割時的傷害而造程广=t失。此外，此一技術尚須能夠避免使用填膠製丨其&枳組的各類元件不會在此填膠製程中遭受破壞，尤 ^咸^古整合微機電系統（mems )技術所製作的螺旋管式電 •丨11 頻開關等立體結構時（參考資料3 )。因此本發明來'政提向製程良率。目前，此一相關技術尚未被開發出個要2今微機電之晶圓級晶粒封裝技術的發展，可分為幾《是雷I 一晶圓級晶粒封裝，其牽涉一個很重要的問題，就 t艇虱4輪線之問題，如何使晶圓級晶粒封裝方式製作的 q TL件内之傳輸線與系統的電路相配合是一個重要的技2. Description of the invention (4) Mode ball 18, followed by flip-chip bonding (after bonding to the molecular substrate cover 19, and then filling with glue 2 Ο 1 d picture _; The reliability of the contact. Or, as on the first board 10, the active element 21 is first bonded to the glass substrate and the glass substrate by a flip-chip bonding method, and then a tin ball 1 8 is grown on the metal layer. Bonding Fang Jun = Γ! After the molecular substrate cover 19 is bonded, it is filled with glue 20. This packaging method adds a real glue step, and its material 20 flows naturally by capillary phenomenon. Although it is easy to refine, the reliability of the wrong contact, However, due to its fluidity and flow time, it is not produced. 2. Control will reduce the process yield, and its curing time is long, which affects the part manufacturing. This invention aims to provide a variety of components that can integrate modules at the wafer stage. Complete two new! New manufacturing process and integrated packaging technology to provide high-frequency module ^ good ^ clever 'and to protect components from damage during package cutting and manufacturing process = t. In addition, this technology must be Able to avoid the use of fillers 丨 All components of its & 枳 group will not be used in the filler process When it is damaged, especially the three-dimensional structure such as the spiral tube electric • 11-frequency switch manufactured by the ancient integrated micro-electro-mechanical system (mems) technology (Reference 3). Therefore, the present invention comes to the 'yield of the political process to the process.' At present, this related technology has not been developed yet. The development of today ’s MEMS wafer-level die packaging technology can be divided into several types. “I am a wafer-level die packaging, which involves a very important issue. Regarding the problem of the four-wheel line of the boat, how to make the transmission line in the q TL part manufactured with the wafer-level die packaging method match the circuit of the system is an important technique.

五、發明說明（5) 術。一般利用機械加工、基板上鈹上一或蝕刻出V型凹槽並在相對應的矽後，再用金屬戋導雷’待矽基板與封蓋基板相互接合金屬塾，… 凹槽、…形成了 1 接將金屬線固定於導带:匕凡件或系統相配合；或直 (參考資料4 )。兒曰中’直接完成電性上的連結面結構1 = t是—種立體的結構，而非如1C之平以減少水氣對作，可避免直接與大氣接觸可能造成零點漂移。在Ic: ς J生”，比如壓力計即有入封蓋内，將Ic —人知業中，㊉用樹脂（epoxy )灌罐之處則是：微機G二：Ϊ到氣密的效果。但與IC不同此樹=轉能器，所以它必須與外界接觸，因外你=:二於微機電元件，這時就必須在封裝 7卜;Λ又之界面做好氣密的考量。 ^三曰）另外，微機電元件之產業與1C業有一最大的不同 ^占，’ Ρ疋許多微機電的元件常需要在真空的條件下操作。如，此可以提高振動元件的靈敏度，例如使用微機電方法的微機械震盪器（micr〇-mechanical res〇nat〇r)所製作的 IF與RF的濾波器的響應度。所以，對一些微機電的產品而| 言’一方面不僅要與1C產品一樣考量電子元件的散熱問題；另一方面更要減少空氣對元件運作與訊號強度的影響’而晶圓級晶粒封裝技術應可能是克服此一問題最有效而低成本的方法。第8頁 490771 五、發明說明（6) 綜合上述各點’本發明之整合型高頻模組及其晶的製造與封裝方法，應用了新型的微機電技術可以模組提供一個整合各式主被動元件的晶圓級晶粒封穿了並且避免了使用填膠製程，更可以有效提高製程良率广摇供高頻模組的完整效能。且從〈發明之總論〉本明之目的為解決上述先前技術之缺點。以提：i:!ΐ整合型高頻模組及其製造與封裝方法，可一目的。° '動兀件的晶圓級晶粒封裝，此為本發明之依本發明之高頻模組及其晶圓級土 ^ 可以提供所製作的高頻模组亩，、封裝方法， .,Ί 1貝棋、、且直接進仃晶圓級測試 (wafer - level testing )詈制古相伊》〆圓級預燒（一n) 組之糸統特性與晶，，為了達到上述目的太為明之-目的。 |製造與封裝方法係分別利用—叙、f八曰曰圓級的 :與:,石夕基板蝕刻而成的封罢、破動70件的玻璃基板 VCadhes.ve 1 ay er ^ ^ ^ ^ 拉出於基板正面的金屬塾，1 Μ 的方式完成界面接合，所 {取出訊號，以完成封裝，而^ ^線或是製作錫鉛球的方式晶圓級晶粒封裝。前述 / 此整合式主被動元件的< 為了達到上述目的，螭基板f矽基板可互換使用。製造與封裝方法係分別利之高頻模組及其晶圓級的與矽基板蝕刻而成的封笔一衣作主被動元件的玻璃基板 ^。去或利用接著層接5. Description of the invention (5). Generally, V-grooves are etched or be etched out of beryllium on the substrate and the corresponding silicon is used. Then, the metal substrate is used to guide the lightning. In order to fix the metal wire to the guide belt, it can be matched with the system or the system; or straight (Reference 4). The structure of the electrical connection is directly completed. The surface structure 1 = t is a three-dimensional structure, not as flat as 1C to reduce water-gas interaction, which can avoid direct contact with the atmosphere, which may cause zero drift. In Ic: ς J 生 ”, for example, the pressure gauge is put into the cover, and in Ic, which is a well-known industry, the place where epoxy resin is used is: microcomputer G2: the effect of airtightness. But Different from IC, this tree = transducer, so it must be in contact with the outside world. Because of you == two are compared with micro-electromechanical components, then it must be packaged in the package 7; the airtight consideration of the interface. In addition, the industry of micro-electro-mechanical components has the biggest difference with the 1C industry. Many of the micro-electro-mechanical components often need to be operated under vacuum. For example, this can improve the sensitivity of vibration components, such as those using micro-electro-mechanical methods. Responsiveness of IF and RF filters made by micro-mechanical oscillators (micr〇-mechanical res〇nat〇r). So, for some micro-electromechanical products | On the one hand, it is necessary not only to consider electronics like 1C products The problem of heat dissipation of components; on the other hand, it is necessary to reduce the effect of air on component operation and signal strength. And wafer-level die packaging technology may be the most effective and low-cost method to overcome this problem. Page 8 490771 V. Invention Description (6) General At the above points, the integrated high-frequency module of the present invention and the method for manufacturing and packaging the crystal, applying the new micro-electromechanical technology, can provide a module-level wafer-level die that integrates various active and passive components, and avoids The use of the filling process can effectively improve the complete efficiency of the process yield and wide-range high-frequency module. And from the <General Summary of the Invention> the purpose of this invention is to solve the shortcomings of the above-mentioned prior art. To mention: i:!: Integrated high-frequency mode The assembly and its manufacturing and packaging method can serve one purpose. ° 'Wafer-level die packaging of moving parts. This is the high-frequency module of the present invention and its wafer-level soil. ^ The manufactured high-frequency module can be provided. Acres, packaging methods, .. 1 棋 chess, and directly into wafer-level testing (wafer-level testing) production of ancient phase Yi 〆 round-level burn-in (one n) group system characteristics and crystal In order to achieve the above-mentioned purpose, it is too clear-purpose. | Manufacturing and packaging methods are used respectively-Syria, f eight days, and round-level: and :, sealed by Shi Xi substrate etching, breaking 70 pieces of glass Substrate VCadhes.ve 1 ay er ^ ^ ^ ^ It is pulled out of the metal substrate on the front of the substrate, and the interface bonding is completed by 1 μm, so {take out the signal to complete the package, and ^ ^ wire or wafer-level die packaging method. The aforementioned / This integrated main In order to achieve the above purpose, the passive substrate f silicon substrate can be used interchangeably. The manufacturing and packaging methods are respectively high-frequency modules and their wafer-level sealing and etching made of silicon substrates as the glass of the active and passive components. Substrate ^. Go or use lamination

第9頁规’以陽極接人、、土斗、i， 490771Page 9 Rule ‘People with anode, earth bucket, i, 490771

五、發明說明（8) \ u合式主破動元件的晶圓級晶粒封裝。馬了達到上述目的，；☆ _ 衣方法係分別利巧的刻=前述高頻主被動元件的S再件的晶圓級晶粒封裝。裝，而獒供此一整合式主被動元製造與封裝方法=:利本發明之高頻模組及其晶圓級的接合各式主被利反為基板，於其上太八被動兀件的晶圓級晶粒封裝。 _ 本發明上述目的及政它佟赴比γ· 作之描述更清楚了解。/、匕4點，白可參考下列依附圖所 <較佳具體實施例之詳細描述〉，結構示中整合被動元件之高頻模卜級U曰曰粒封裝^法!=佳實施例的高頻元件模組的晶圓 j,，装方法進打描述。在第一者# A丨士 " 作，主被動元件的玻璃基板，盘：二=中，係以其上製 •:製程進：= ϊ板正面以打線方式拉出導線的主被ΪΓ術。第三實施例則為其上製Ϊ 、極接合法接合後於玻璃基板背；3=的封蓋，以陽程進行封裳；第四實施例則製作^線方式拉出導線的製貝她例幻衣作錫鉛球於基板背面金屬五、發明說明（9) 墊，於背面取出訊號的製程； (adhesive layer )來接人五貫施例為利用接著層例為將欲整合的主被動元；=基板的製程。第六實施板背面的製程方法。第七實施上製作高頻元件的基元件，與其上製作主被動元件$ J盍基板士製作主動或接著層接合法接合以完成：二;基板第合法個其上製作主被動元件的義祐衮的衣耘，弟八只施例為兩 =以％極接合法或接著層接合法接合的製程；第九= 1 可挽性軟板為基板’接合主被動元件與各式砂基鱼 f石夕基元件f其上的製造與封裝方式。第十實施例說明;· 叙明可以進行晶圓級測試與晶圓級預燒的方式。第2a圖至第2 j圖為本發明之高頻元件模組，利用打線的方式在基板正面取出訊號的晶圓級晶粒製造與封裝方法。第2a圖至第2h圖為一整合主被動元件的製造流程。首先声基板2 01上沈積並定義電阻層2〇2(請參第2&圖）；其後，沈積並以蝕刻或剝離法的方法定義第一金屬層2 〇 3， j此1第一金屬層203分別形成於電阻層20 2的兩端，形成一個電♦,阻結構R ’此外，第一金屬層延伸於基板2 〇 I上，以作為正面第一導線及金屬墊（請參第2b圖）。然後，沈積並定 •義第一保護層2 0 5以絕緣第一導線與之後封裝後封蓋基板《上的金屬層（清參弟2c圖），其後’先後沈積並定義介電層206及第二金屬層207 (請參第2d圖），此介電層與上下、包夾的第一金屬層20 3、第二金屬層207形成一個金屬層/ 介電層/金屬層的電容結構（請參第2e圖）；其後，以例V. Description of the invention (8) The wafer-level die package of the combined main breaking element. To achieve the above-mentioned purpose, the ☆ _ method is a clever engraving = wafer-level die packaging of the S-component of the aforementioned high-frequency active and passive components. This method is used to manufacture and package an integrated active and passive element. =: The high-frequency module of the present invention and its wafer-level bonding. Various types of active and passive components are used as substrates, on which crystals of passive components are mounted. Round die package. _ The above purpose of the present invention and its implementation are more clearly understood than the description made by γ ·. /, 4 points, white can refer to the following detailed description of the preferred embodiment according to the drawings>, the structure shows the integration of passive components in the high-frequency mode of the U-chip package ^ method! = High frequency of the preferred embodiment The method for mounting the wafers of the component module is described. In the first one, the glass substrate of the active and passive components, the plate: two = medium, is based on the above system: •: The process is advanced: = the main board of the front panel is pulled out by a wire. The third embodiment is a glass substrate backed by a top-up and pole-joint method; a cover of 3 = is closed by a male process; and a fourth example is a manufacturing example of a wire drawn by a wire. Phantom clothing is used as a tin-lead ball on the back of the substrate. 5. Description of the invention (9) The process of taking out the signal on the back; (adhesive layer) To access the five consecutive embodiments is to use the following layers as the active and passive elements to be integrated; = Substrate manufacturing process. Sixth implementation The manufacturing method of the back of the board. In the seventh embodiment, the base element for the high-frequency component is fabricated, and the active and passive components are fabricated on it. The substrate is fabricated by active or adhesive bonding to complete: Second, the substrate is the first to be used for making active and passive components. Yi Yun ’s eight examples are two = the process of bonding by% pole bonding method or layer bonding method; the ninth = 1 a flexible soft board as the substrate 'joining active and passive components with various types of sand-based fish f stone The manufacturing and packaging method of the evening element f. The tenth embodiment explains; · Describes the manner in which wafer-level testing and wafer-level burn-in can be performed. Figures 2a to 2j are wafer-level die manufacturing and packaging methods for high-frequency component modules according to the present invention. Figures 2a to 2h show a manufacturing process of integrated active and passive components. First, a resistive layer 202 is deposited and defined on the acoustic substrate 2 01 (see Figure 2 &Figure); thereafter, a first metal layer 2 03 is deposited and defined by an etching or peeling method. Layers 203 are formed at both ends of the resistive layer 202 to form an electrical resistive structure R ′. In addition, the first metal layer extends on the substrate 201 to serve as the front first lead and metal pad (see section 2b). Figure). Then, a first protective layer 205 is deposited and defined to insulate the first wire from the metal layer on the substrate after encapsulation and after encapsulation (Figure 2c), and then 'the dielectric layer is deposited and defined 206 And the second metal layer 207 (see FIG. 2d), the dielectric layer and the upper and lower layers sandwiching the first metal layer 20 3, the second metal layer 207 forms a metal layer / dielectric layer / metal layer capacitor structure (Please refer to Figure 2e);

第12頁 490771 五、發明說明（ίο) 如旋佈（spin-on)等方式形成保護層2〇9 (請參第2fgj );此俤護層2 0 9為具有低介電係數的介電材質，具有足夠的厚度以包覆電阻、電容等被動元件並均勻塗佈於基板 201上；之後，於保護層209上定義出接觸窗210，且沈積並定義第三金屬層211，以形成正面的第二導線（請參第 2g 圖）。在完成第三金屬層之後，可於保護層2〇9上利用各種方式接合組裝（assembly )製作各種主被動元件。以電鍍製程為例，可以利用先前定義的第二導線為電鍍結構的底層下電極，再依-般電鐘程序，即可形成被動元件如微機# 電型立體電感L (如第2h圖）、主動元件如微波開關L (nncrowave SWltch)等。另外，再以覆晶接合方式將石夕基訊號處理I C晶粒與砷化鎵系列的功率放大器等主動元 212接合組裝於第二金屬層2U的適當位置上。不動界件搭配包覆於保護層2 0 9内的被動元件，可 |種"功能互異的模組。 &风合 y如第2a圖至第2h.圖製作完成一包含主被組·.之後，可利用另一基板213作為封蓋進行接合， ^ 保護於基板封蓋213内’經由不同的設計，模組 '可以有不同的引出方式。第2丨圖及第2」圖為在封^ 金屬墊打線拉出信號的一種實施例結構。此^ 利用另-晶圓級基板213製作封蓋。在 γ列百先 ,201相同尺寸形狀的基板213上，分^級基板板2i3背面定義並蝕刻出封蓋外型，之土板213正面與基 ^之後在封蓋内側凹Page 12 490771 V. Description of the invention (ίο) A protective layer 2009 is formed by spin-on (see 2fgj); this protective layer 2 9 is a dielectric with a low dielectric constant. Material, with sufficient thickness to cover passive components such as resistors and capacitors and uniformly coated on the substrate 201; then, a contact window 210 is defined on the protective layer 209, and a third metal layer 211 is deposited and defined to form a front surface (See Figure 2g). After the third metal layer is completed, various active and passive components can be fabricated on the protective layer 209 by various methods. Taking the electroplating process as an example, the previously defined second wire can be used as the bottom lower electrode of the electroplated structure, and then follow the normal electrical clock procedure to form a passive component such as a microcomputer # electric type three-dimensional inductance L (as shown in FIG. 2h), Active components such as microwave switches L (nncrowave SWltch). In addition, the Shi Xiji signal processing IC chip and the active element 212 such as a power amplifier of the GaAs series are bonded and assembled at a proper position of the second metal layer 2U by a flip-chip bonding method. The fixed boundary parts are matched with passive components enclosed in the protective layer 209, which can provide different types of modules. & Wind y as shown in Figures 2a to 2h. After completing the production of a figure including the main quilt ..., another substrate 213 can be used as a cover for bonding, ^ Protected in the substrate cover 213 'through different designs , Module 'can have different ways of exporting. Figures 2 丨 and 2 ″ show the structure of an embodiment in which a signal is pulled out from a metal pad. In this case, a cap is fabricated using another wafer-level substrate 213. On the substrate 213 of the same size and shape of γ 100, the rear surface of the graded substrate plate 2i3 defines and etches the shape of the cover, and the front surface of the soil plate 213 and the base are concave on the inside of the cover.

第13頁五、發明說明（11) 二"，積金屬216，此即完成基板封蓋213之製作。之後， π，㈣蓋213與前述製作於晶圓級基板2〇1 頻板組2 1 4相對應，風μ m μ t ^ n , ^ ^ 再利用雙面或早面對準機，將此基板封蓋2 1 3與基板2 〇 1相互對進，夕户你後之封蓋213與基板201 :夂之。將固定 Ψ m ^ , η -η ^ 私至Β日片接合機内，進行加溫或加 & 粹次刖述方式之複數使用步驟，而完置如第=後基盍13與基板201之相對位為全d 凹槽内形成一空腔215，空腔内壁，可以保護内部元件不受外部電磁波干擾，刖Μ的问頻模組2 1 4則位於此空腔2丨5之内。完曰· 級晶粒之封裝程序之德，铖％日日圓’ τ ^ ^ ^ 後、、工過切副，便可如第3 b圖所示由 ^面弟-導線所形成的金屬塾進行打線217，以拉出传芸其刼«Τ屯士* 序便。兀成。丽述之基板201與封板:★玻璃基板，或積基丨基、板。領，丨矽基板與玻璃 ·:利用第2a圖至第2h圖所製作穿点沾古相-从，可刹田六I T二冰丨^ 70成的r^頻％件模組’亦利用在f板正面製作錫鉛球的方式，在Page 13 V. Description of the invention (11) Second " Accumulator 216, the production of the substrate cover 213 is completed. After that, π and ㈣ cover 213 correspond to the above-mentioned wafer-level substrate 021 frequency board group 2 1 4. The substrate cover 2 1 3 and the substrate 2 001 face each other, and the cover 213 and the substrate 201 in the back of the house are irrelevant. Place the fixed Ψ m ^, η -η ^ in the B-chip bonding machine, and perform multiple steps of heating or heating in the manner described below, and complete the installation as described below. A cavity 215 is formed in the full d groove, and the inner wall of the cavity can protect internal components from external electromagnetic waves. The RF frequency module 2 1 4 is located in the cavity 2 丨 5. After completing the packaging process of grade-level die, 铖% yen and yen 'τ ^ ^ ^ ^ After the cutting process, you can carry out the metal 塾 formed by ^ face brother-wire as shown in Figure 3b Call 217 to pull out the prelude to the «T Tunshi *. Wucheng. Lishu's substrate 201 and sealing plate: ★ glass substrate, or substrate, board. Collar, 丨 Silicon substrate and glass ·: Using the points made in Figures 2a to 2h to penetrate the ancient phase-from, can be used in six IT two ice 丨 ^ 70% r ^ frequency% module module is also used in The method of making the tin shot on the front side of the f board.

=，以完成晶圓級晶粒的製造與封裝。第 3D 說明此封裝之實施例。首先利 a m ^ ^弟3d圖即 44 ^ y , 用另一晶圓級基板3 01制柞封盍。在一個與晶圓級基板3 〇 0 衣作封蓋用基板301上，分別由基板3〇1正面愈美，狀北的晶圓級蝕刻出封蓋外型，之後，在封芸 ^板月面定義並封盍内侧凹槽中沈積金屬層= To complete wafer-level die fabrication and packaging. Section 3D illustrates an embodiment of this package. Firstly, a 3 ^ 3d picture is 44 ^ y, and another wafer-level substrate 3 01 is used for sealing. On a wafer-level substrate 300, which is used as a capping substrate 301, the front surface of the substrate 301 is more beautiful, and the shape of the cap is etched at the wafer level of the north. Surface defines and seals a metal layer in the inner groove

第14頁 490771 五、發明說明（12) 304 ’ f即完成基板封蓋3〇1之製作。之後，使此基板封蓋 301與：述製作於基板3〇〇之高頻模組3〇2 雙^單面對準機將此封蓋基板m與基板_相互對準， $曰y &入^ 將固疋後之封蓋基板301與基板30 0移二曰曰片接a機内，進行加溫或加電壓或加壓力的步驟，或 ^述方ί之複數使用步驟，而完成接合的程序。接合後的 =板封蓋301與基板3 0 0其相對位置如第3a圖所示。使得凹成-空腔3 0 3，空腔内壁為可以保護内部元件不受夕卜：電磁波干擾的金屬層3〇4，而前述的高頻此空腔之内。 ^ 在封盍基板301與晶圓級元件基板3〇〇接合後，再自正電鍍方式沈積，或是以導電樹脂塗佈方式來製，此步驟沈積金屬連結基板3 0 0上的第-金屬』㈣的階梯覆蓋性（step c〇verage)使金 σ :二设於封蓋基板3 0 1的外緣側壁，再藉由罩程序在封蓋基板301上定義出金屬墊307，接著， •匕:i厲思3〇7上衣作錫鉛球308，或是製作錫鉛球3 0 9於覆屬層3 05的封蓋凹槽中，如圖心及％所示。則此後只 =過切割便可完成此一模組的完整晶粒級封裝程序，，以由錫斜球利用表面接著技術（Surface M〇unting序了Page 14 490771 V. Description of the invention (12) 304 ′ f The production of the substrate cap 3301 is completed. After that, the substrate cover 301 and the high-frequency module 3002 double-sided single-side alignment machine manufactured on the substrate 300 are aligned with the cover substrate m and the substrate_, The cover substrate 301 and the substrate 300, which have been fixed, are moved into the machine, and then the steps of heating, voltage, or pressure, or plural use steps are performed to complete the bonding process. After joining = the relative position of the board cover 301 and the substrate 300 is as shown in FIG. 3a. The cavity is formed into a cavity 303, and the inner wall of the cavity is a metal layer 304 that can protect internal components from electromagnetic interference, and the aforementioned high frequency is within this cavity. ^ After the sealing substrate 301 is bonded to the wafer-level element substrate 300, it is then deposited by positive electroplating, or is made by conductive resin coating. This step deposits the first metal on the metal connecting substrate 300. ’㈣ ’s step coverage (step comonage) makes gold σ: two are set on the outer side wall of the capping substrate 301, and then a metal pad 307 is defined on the capping substrate 301 by a mask procedure, and then, • Dagger: i Lisi 307 coat as a tin shot 308, or make a tin shot 3 0 9 in the cover groove of the covering layer 3 05, as shown in the heart and%. After that, the complete die-level packaging process of this module can be completed only by over-cutting, and the surface bonding technology (Surface M〇unting sequence)

Technology )’將此高頻模組接合於電路板或陶瓷基板芙板30^他/件/模組整合使用。前述之基板3 00與封蓋二 V、、、玻璃基板與高阻值矽基板，或為玻璃基板與 ’、 ’尤積’丨電層之矽基板，亦可分別為高阻值矽基板第15頁 ^〇77i 五、發明說明（13) Μ破璃基板，或為其上公雷板。巧上預先沈積，丨電層之矽基板與玻璃基前述之高頻元件模組完成後，亦屬墊打線的方式，取出替H 2由在基板月面金蛊钮括哲/回取出°孔遽’以兀成其晶圓級晶粒的製造盥:J。弟4a圖至第4m圖為本發明利用晶圓級晶粒的梦造 S ΐ技％ ΐ裝商頻元件模組，並*穿基才反，自*板背面所干:出信號之製程示意圖。如第4a圖及第4b圖斤不，百先在基板4〇〇上沈積並定義電阻層4〇2，其後沈積 :以蝕刻或剝離法的製程定義第一金屬層4〇3。&第一金屬層403與電阻層4G2可形成—個電阻結構R。其後如第& ，至第4〕圖所示，自背面钮穿基板4qq，形成接觸窗4〇5，再沈積背面第二金屬層406，使此金屬層連接正面第一金屬層403，並覆蓋接觸窗4〇5的側壁，延伸於基板4〇〇的背面。經由罩幕定義的方式，便可在基板4〇()的背面定義出以/月面第一導線與金屬墊4 〇 6。待完成背面導線與金屬墊 4〇6之後，便可繼續將主被動元件4〇7整合製程於晶圓級基 I板4 0 0的正面，並將晶圓級封盍基板4 〇 1接合於玻璃基板丨40¾上，如第4k圖所示。之後，進行晶粒的切割，所形成. 的個別晶粒如第4 1圖所示。在打線4 〇 8於基板背面的金屬 (墊40 6後，即可經由玻璃基板4〇〇的背面將信號取出，完成春此，高頻模組的封裝。前述之基板4〇〇與封蓋基板4〇1同樣可為玻璃基板與高阻值矽基板，或為玻璃基板與其上預先沈、，介電層之矽基板，亦可分別為高阻值矽基板與玻璃基 :板’或為其上預先沈積介電層之矽基板與玻璃基板。Technology) ’This high-frequency module is bonded to a circuit board or a ceramic substrate. Fu board 30 ^ he / piece / module is integrated for use. The aforementioned substrate 300 and the cover V, glass substrate, and high-resistance silicon substrate, or the silicon substrate of the glass substrate and the ',' youji ', electric layer, can also be high-resistance silicon substrates. Page 15 ^ 〇77i V. Description of the invention (13) Μ broken glass substrate, or a public lightning board. Pre-deposited on the surface, after the completion of the silicon substrate of the electrical layer and the aforementioned high-frequency component module of the glass-based module, it is also a way of wire bonding. Take out and replace the H 2 by the gold button on the substrate moon. To manufacture its wafer-level die: J. Figures 4a to 4m are diagrams of the present invention using wafer-level dies to make S technology. The commercial frequency component module is installed, and the base is reversed, and it is done from the back of the board. . As shown in FIG. 4a and FIG. 4b, the resistive layer 402 is deposited and defined on the substrate 400 first, and then deposited: the first metal layer 403 is defined by an etching or peeling process. & The first metal layer 403 and the resistance layer 4G2 may form a resistance structure R. Thereafter, as shown in FIGS. & 4 to 4, the substrate is pushed through the substrate 4qq from the back to form a contact window 405, and then a second metal layer 406 on the back is deposited so that this metal layer is connected to the first metal layer 403 on the front, It covers the side wall of the contact window 405 and extends to the back of the substrate 400. Through the way of the screen definition, the first wire on the back of the substrate 40 () and the metal pad 406 can be defined. After the back wires and metal pads 406 are completed, the process of integrating the active and passive components 407 on the front side of the wafer-level base I-board 400 can be continued, and the wafer-level sealing substrate 401 can be bonded to On the glass substrate 丨 40¾, as shown in Figure 4k. After that, the grains are cut, and the individual grains formed are shown in Figure 41. After wiring 408 to the metal on the back of the substrate (pad 406, the signal can be taken out through the back of the glass substrate 408 to complete the packaging of the high-frequency module. The aforementioned substrate 408 and the cover substrate 4 〇1 can also be a glass substrate and a high-resistance silicon substrate, or a silicon substrate with a pre-sinked, dielectric layer on the glass substrate, or a high-resistance silicon substrate and a glass-based: plate 'or on it. A silicon substrate and a glass substrate with a dielectric layer deposited in advance.

第16頁 490771 五、發明說明（14) p 高頻元件模組亦可經由不同的製程設計，在基板月面衣作錫鉛球取出訊號。第5a圖至第5m圖為本發明利用晶囫、級晶粒的製造與封裝技術封裝高頻元件模会且，並蝕穿，板，f晶圓級基板背面以製作錫錯球的方式取出信號之二私不思目。如第5a圖及第5b圖所示，首先在晶圓級基 /Λ積並定義電阻層5 02，其後沈積並以蝕刻或剝離法的衣私疋義第—金屬層5〇3。此第一金屬層與電 …可形成-個電阻結_。其後如第5c圖至第面钱穿基板，形成接觸窗50 5，再沈積背面第二金屬金屬層連接正面第一金屬層503，並覆蓋接觸（由5 0 5的側壁，延伸於晶圓級基板5〇〇的背面。經由罩幕定’ 義的方式，便可在晶圓級基板5〇〇的背面定義出以背面一導線，金屬塾5 0 6。待完成背面導線與金屬塾5〇6之後，便可如弟2a圖至第2h圖將整合型主被動元件5〇7製作於晶圓與基板500的正面，並將晶圓級封蓋基板5〇1接'^合於'曰ss 級:基板5㈣上，如第5k圖所示。之後，如第5ι圖所示，曰曰即丨可,在晶圓級基板5 0 0的背面金屬墊5〇6上製作錫鉛球5〇8於 •金〈屬墊，將信號取出。亦可如第5m圖製作錫錯球5〇9於蓋金屬層的接觸窗50 5内，將信號取出，禮 500與封蓋基板5G1可為玻璃基板與高阻值m 璃基板與其上預先沈積介電層之矽基板，亦可分別為= 玻璃基板，或為其上預先沈積介電層之“板第17頁 490771 五、發明說明（15) 第6a圖至第6e圖說明另一利用接著層（adhesive iayer) ‘來做為接合封蓋與基板的界面，用以封裝高頻元件模組。f先依第2a圖至第2h圖所示的製程方法，在晶圓級基板_上製作包含主被動元件的高頻模組6〇2，再利用另一晶圓級基板601來製作封蓋，依序將其鍍上金屬層 6 03、蝕刻以形成封蓋外型，如第“圖所示。再使封蓋基板上沾附接著層6 04。此接著層6 04可為錫鉛球、光感樹脂 (UV Epoxy) 、BCB ,或其他能增進封蓋基板6〇1與基材 6^0上介電保護層606或金屬層6〇7接合能力的材料（參考貝料5 )。之後，將晶圓級封蓋基板601與晶圓級基材60 0 . 對準、壓合，接著層6 04便能將封蓋基板6〇1與基材6〇〇接合。接合後的晶圓級封蓋601與晶圓級基板6〇〇其相對位置如第6b圖所示。接著如第6cW、第6d圖與第6e圖所示，先後對曰曰圓級封盍6 0 1與晶圓級基板6 q 〇進行切割，再打線泛至晶粒上的金屬墊，即可完成此一高頻模組。與第一貫:施例相同，此實施例前述之基板6〇〇與封蓋基板6〇1可為 ;璃基板與高阻值矽基板，或為玻璃基板與其上預先沈積 J介::電層之矽基板，亦可分別為高阻值矽基板與玻璃基板，或為其上預先沈積介電層之矽基板與玻璃基板。第7 a圖至第7 f圖為本發明之第6實施例，當高頻元件· 模.級完成於晶圓級基板的正面之後，相關需要整合的主被動元件亦可以晶片接合的方式接合在晶圓級基板的背面，气製程方法如第7a圖至第7f圖所示。首先依第2a圖至第2h _的製程方法，在晶圓級玻璃基板7 0 0上製作高頻模組第18頁 490771 五、發明說明（16) ---~--- 7〇2，之後，再以放電加工、帛分子雷射、超音波或乾、㈣刻等方式钮穿基板7〇〇，形成正面與背面導線連結的引孔704。另外，利用另一晶圓級矽基板7〇1來製作封蓋，依序將其鍍上金屬層703、蝕刻以形成封蓋外型，如第圖。其後，利用前述陽極接合或接著層接合等方式將前述晶圓級玻璃基板70 0與晶圓級矽封蓋基板7〇1相接合，再自晶圓級玻璃基板70 0背面沈積金屬7 0 5於基板背面與引孔 7 〇 4中，το成正面與背面的電性連結。在經過切割封蓋基板7 0 1與玻璃基板7 0 〇之後，便形成如第7d圖所示的晶粒。之後，也可如第7 e圖，在其玻璃基板的背面以晶粒接合的方法接合上需要整合的主被動元件7 〇 6，如濾波器、石夕基訊號處理IC晶粒、石申化鎵系列的功率放大器等，再以打線 7 〇 7方式完成彼此連結並取出其信號，最後進行封膠7 〇 8即可完成此一模組。另一方面，亦可在完成如第7d圖之晶粒後“’以覆晶接合的方式將需要整合的主被動元件7 〇 6接合在:基板7 0 0的背面’再以封膠709的方式即可完成如第了 f圖 ;之模組的製造與封裝。此外，亦可在完成如第7d圖之晶粒 •I後;’將須整合的主被動元件7 0 6以前述的晶粒接合及後續打\線、封膠的方式，或是以覆晶接合與封膠的方式，合在 ;基板7 0 0的背面後，以金屬蓋7 1 0或前述石夕封蓋7 1 〇來與基籲板7 0 〇接合以保護基板7 0 0背面的元件，其結果如第7 g圖與第7h圖。而所完成如第7g圖及第7h圖之結構體亦可如前述 t實施例所提之打線或锡錯球之方式來完成最後對外的電性 :連結。Page 16 490771 V. Description of the invention (14) p The high-frequency component module can also be designed by different processes, and the signal can be taken out as a tin shot on the substrate moon coat. Figures 5a to 5m are diagrams showing the packaging of high-frequency components using the manufacturing and packaging technology of crystalline silicon and grade dies. The back of the wafer and f wafer-level substrates is taken out by making tin balls. The second signal is private. As shown in FIG. 5a and FIG. 5b, the resistive layer 502 is firstly defined and defined at the wafer level, and then the first metal layer 503 is deposited and then etched or stripped. This first metal layer can form a resistive junction with electricity. Thereafter, as shown in FIG. 5c to the first surface, the substrate is penetrated to form a contact window 505, and then a second metal metal layer on the back is deposited to connect the first metal layer 503 on the front and cover the contact (extended from the side wall of 505 to the wafer). The back of the level substrate 500. By defining the mask, the back of the wafer-level substrate 500 can be defined with a back wire, metal 塾 506. To be completed back wire and metal 塾 5 After 〇6, as shown in Figures 2a to 2h, the integrated active and passive components 507 can be fabricated on the front side of the wafer and the substrate 500, and the wafer-level capping substrate 501 can be connected to the ^ SS level: on the substrate 5㈣, as shown in FIG. 5k. After that, as shown in FIG. 5i, it is possible to make a tin-lead ball 5 on a metal pad 506 on the back of the wafer-level substrate 500. 〇8 于 • 金〈It is a pad to take out the signal. You can also make a tin ball 509 as shown in Figure 5m in the contact window 50 5 of the cover metal layer, and take out the signal. The gift 500 and the cover substrate 5G1 can be Glass substrate and high-resistance m glass substrate and silicon substrate with pre-deposited dielectric layer on it, can also be = glass substrate, or pre-deposited dielectric on it "Board 17th page 490771 V. Description of the invention (15) Figures 6a to 6e illustrate another use of adhesive iayer 'as the interface between the cover and the substrate for packaging high-frequency component molds. F. First, according to the process method shown in Figures 2a to 2h, a high-frequency module 60 including active and passive components is fabricated on a wafer-level substrate_, and then another wafer-level substrate 601 is used to make a cover. Then, it is sequentially plated with a metal layer 603, and etched to form a cover shape, as shown in the figure. Then, an adhesion layer 6 04 is attached to the cover substrate. This adhesion layer 604 can be a tin-lead ball, Photosensitive resin (UV Epoxy), BCB, or other materials that can improve the bonding ability of the capping substrate 6101 and the dielectric protective layer 606 or the metal layer 607 on the substrate 6 ^ 0 (refer to Shell Material 5). The wafer-level capping substrate 601 and the wafer-level substrate 60 0 are aligned and pressed, and then the layer 6 04 can bond the capping substrate 601 to the substrate 600. The bonded wafer The relative position of the stage cover 601 and the wafer-level substrate 600 is shown in Fig. 6b. Then, as shown in Figs. 6cW, 6d, and 6e, the round-shaped stage is successively described. This sealing is performed by cutting 601 and wafer-level substrate 6 q 〇, and then wiring to the metal pad on the die to complete this high-frequency module. It is the same as the first embodiment: the substrate described in this embodiment The 600 and the capping substrate 601 can be; a glass substrate and a high-resistance silicon substrate, or a glass substrate with a J substrate :: electrical layer silicon substrate deposited thereon, or a high-resistance silicon substrate and A glass substrate, or a silicon substrate and a glass substrate on which a dielectric layer is deposited in advance. Figures 7a to 7f are the sixth embodiment of the present invention. When the high-frequency components and modes are completed at the wafer level After the front side of the substrate, related active and passive components that need to be integrated can also be bonded to the back side of the wafer-level substrate in a wafer bonding manner. The gas manufacturing method is shown in Figures 7a to 7f. First, according to the manufacturing process of Figures 2a to 2h_, a high-frequency module is fabricated on a wafer-level glass substrate 700. Page 18 490771 V. Description of the invention (16) --- ~ --- 7〇2, Then, the substrate 700 is pushed through the substrate 700 by means of electrical discharge machining, holmium laser, ultrasonic or dry, engraving, etc., so as to form a lead-through 704 connecting the front and back wires. In addition, another wafer-level silicon substrate 701 is used to make a cap, which is sequentially plated with a metal layer 703 and etched to form a cap shape, as shown in the figure. Thereafter, the aforementioned wafer-level glass substrate 70 0 is bonded to the wafer-level silicon capping substrate 700 by the aforementioned anodic bonding or adhesive bonding, and then a metal 70 is deposited from the back of the wafer-level glass substrate 70 0. 5 In the back surface of the substrate and the lead hole 704, το is electrically connected to the front surface and the back surface. After cutting and capping the substrate 701 and the glass substrate 700, the crystal grains shown in FIG. 7d are formed. After that, as shown in Figure 7e, the passive and active components that need to be integrated are bonded on the back of the glass substrate by die bonding, such as filters, Shi Xiji signal processing IC die, Shi Shenhua Gallium series power amplifiers, etc., are connected to each other and the signals are taken out by way of wiring 707, and finally the module is sealed by 708. On the other hand, after completing the die as shown in FIG. 7d, “the passive and active components 7 0 6 that need to be integrated are bonded to the back side of the substrate 7 0 by the flip-chip bonding method” and then sealed with the sealant 709. The method can complete the manufacturing and packaging of the module as shown in Figure f. In addition, after completing the die • I as shown in Figure 7d; 'the active and passive components that must be integrated 7 0 6 Grain bonding and subsequent hitting, wire bonding, or sealing, or flip-chip bonding and sealing, are combined on the back of the substrate 7 0 0 with a metal cover 7 1 0 or the aforementioned Shi Xi cover 7 1 〇 is bonded to the base plate 70 〇 to protect the components on the back of the substrate 7000, the results are shown in Figure 7g and 7h. And the completed structure as shown in Figure 7g and Figure 7h can also be as described above t The wire or tin ball method mentioned in the embodiment is used to complete the final external electrical property: connection.

第19頁五、發明說明（17) 前述第6實施例所使用之晶圓、級玻璃圓級高阻值矽基板或其上先 / /UU 了改以曰曰實：蓋基板701與石夕封蓋710改以玻璃上利ΓΛ為本/明之第7實施例’首先在晶圓級基板_ 亡Ϊ : : Ϊ之製作包含主被動元件之高頻模組8〇2， ::卜在晶圓級基板801上製作主動元件8〇3或以晶粒接合的方式將主動元件803接合在基板801上，之後， =合或是前述之接著層接合的方式，將晶圓級基板8〇〇 ίΓ金=基板8G1對準接合，完成其封裝。此晶圓級基板< /、土板^0 1之材料選擇，可皆為矽基板，或皆為玻璃基板，而以前述接著層接合的方式接合，或是一者為矽基板而另一者為玻璃基板，而以陽極接合或是前述之接著層接合的方式’將基板800與基板8〇1對準接合。 ί第^圖為本發明之第8實施例，首先在晶圓級基板900 上利用前述方法製作包含主被動元件的模組9〇2，另外，用另二晶圓級基板9〇1，利用前述方式製作高頻模組 _··, °之後’再以另一晶圓級基板9 04為接合基板來接合此二基板90 0、901 ,首先在晶圓級基板9〇4上定義並蝕穿基板以形成放置尚頻模組9 0 2與9 0 3的空間，之後再將晶圓_ ，基板90 0、904、901至於晶片接合機内予以接合，完成南頻模組的封裝。此晶圓級基板9 0 0與基板901之材料選擇Y可皆為石夕基板，而接合基板9 〇 4為玻璃基板，彼此利用陽極接合法接合；或者前述晶圓級基板90 0與基板901皆 ^U771 五、發明說明（18) 為玻璃基板，而接合基板9 〇4為矽基板，彼此亦利用陽極接合法接合；亦可選擇晶圓級基板9 0 0、9〇4、9〇1任為矽基板或玻璃基板等各式材質，而以前述之接著層接合的式，將其對準接合，以完成其模組的封裝程序。第1 0圖說明以運用可撓性軟板為基板來整合前述方式所‘作的整合型積體化被動元件的高頻模組製造與封裝方法。如第1 0圖，基板1 〇〇〇為一具有可撓性的材料，如聚乙醯胺等。在基板上製作緩衝層1〇〇1後，沈積金屬層以&作金屬墊1 0 0 2 ’在金屬墊1 0 0 2上可成長錫鉛球1〇〇3，其後，須組裝的整合型積體化被動元件丨〇〇4便可藉由表面接著術（Surface Mounting Technology )中的標準製程回熔錫鉛球來固定在可撓性基板上，其他各種以不同製程來製作的石夕基主動元件丨0 0 5或其他非矽基主動元件1〇〇6亦可^ 此類方式組裝於可撓性基板1〇〇〇上，之後可以運用現行的封舞或加上金屬蓋的製程來完成模組的製作。而本發明之 ^ ;程中所提的1 0 〇 4元件可利用前述第2 a圖至第2 h圖之第一 ;實施例所提的方式來完成。 •丨。·’： W述各實施例均能以各種製程方式實現高頻模組之晶圓級晶粒封裝，此一封裝製程亦具有提供晶圓級測試與晶〔·圓級預燒的優點。如第1 1圖，為前述封裝製程在進行封蓋鲁接合前的示意圖，在晶圓級基板丨丨〇〇上製作了各式主動元件1 1 0 1與被動元件丨丨〇 2，在進行封蓋接合與切割之前，便 k可在此階段進行晶圓級測試，將基板置於控制了溫溼度的腔體1103中的熱墊板11〇4上，以探針（pr〇be ) 11〇5來量Page 19 V. Description of the invention (17) The wafers, glass-grade, high-resistance silicon substrates used in the foregoing sixth embodiment or the first // UU are changed to the following: cover substrate 701 and Shi Xi The seventh embodiment of the cover 710 is changed from glass to glass ΓΛ. This is the first example at the wafer level substrate _::: Ϊ The production of high-frequency module 802 including active and passive components, :: bu at the wafer level An active device 803 is fabricated on the substrate 801 or the active device 803 is bonded to the substrate 801 by die bonding. After that, the wafer-level substrate 80% gold is bonded by the above-mentioned method or the above-mentioned bonding method. = Substrate 8G1 is aligned and bonded to complete its packaging. The material selection of this wafer-level substrate < /, soil plate ^ 0 1 can be all silicon substrates, or all glass substrates, and are bonded by the aforementioned bonding method, or one is a silicon substrate and the other This is a glass substrate, and the substrate 800 and the substrate 801 are aligned and bonded in the manner of anodic bonding or the aforementioned bonding layer bonding. Figure ^ shows the eighth embodiment of the present invention. First, a module 902 containing active and passive components is fabricated on the wafer-level substrate 900 by using the foregoing method. In addition, another wafer-level substrate 901 is used. The high-frequency module is produced in the manner described above. After ° ', another wafer-level substrate 9 04 is used as the bonding substrate to bond the two substrates 90 0 and 901. First, the substrate is defined and etched on the wafer-level substrate 904. In order to form a space for placing the still frequency modules 902 and 903, the wafers, substrates 90, 904, and 901 are then bonded in the wafer bonding machine to complete the packaging of the south frequency module. The material selection Y of the wafer-level substrate 900 and the substrate 901 may both be Shi Xi substrates, and the bonding substrate 904 is a glass substrate, which are bonded to each other by an anodic bonding method; or the aforementioned wafer-level substrate 900 and substrate 901 All ^ U771 V. Description of the invention (18) is a glass substrate, and the bonding substrate 9 04 is a silicon substrate, and they are also bonded by anodic bonding; wafer-level substrates 900, 900, and 900 can also be selected. It can be made of various materials such as silicon substrate or glass substrate, and it can be aligned and bonded by the above-mentioned adhesive layer bonding method to complete the module packaging process. Fig. 10 illustrates a method of manufacturing and packaging a high-frequency module of an integrated integrated passive component made by the aforementioned method using a flexible flexible board as a substrate. As shown in Fig. 10, the substrate 100 is a flexible material, such as polyethylene. After the buffer layer 001 is made on the substrate, a metal layer is deposited with & as the metal pad 1002 '. On the metal pad 1002, a tin-lead ball 1003 can be grown. After that, it must be assembled and integrated. The integrated passive components can be fixed on the flexible substrate by remelting tin-lead balls in a standard process in Surface Mounting Technology. Other various Shi Xiji manufactured by different processes Active components 丨 0 05 or other non-silicon-based active components 006 can also be assembled on a flexible substrate 10000 in this way, and then the current process of sealing and dancing or adding a metal cover can be used to Complete the production of the module. The 104 element mentioned in the process of the present invention can be completed by using the method mentioned in the first embodiment of the foregoing FIG. 2a to FIG. 2h. • 丨. · ': Each of the embodiments described above can realize wafer-level die packaging of high-frequency modules in various manufacturing methods. This packaging process also has the advantages of providing wafer-level testing and wafer-level burn-in. As shown in FIG. 11, which is a schematic diagram of the aforementioned packaging process before capping and bonding, various types of active components 1 1 01 and passive components 丨〇 2 are fabricated on a wafer-level substrate 丨丨〇 2 Before the cover is joined and cut, a wafer-level test can be performed at this stage. The substrate is placed on a hot pad 11104 in a cavity 1103 with a controlled temperature and humidity, and a probe (pr〇be) 11 is used. 〇5 amount

第21頁 490771 五、發明說明（19) ' ----- 測各條件下系統級的特性，挑選出可用晶片（Kn〇wn G〇〇d D 1 e，KGD )來繼績進行封蓋接合。而藉此量測結果可發現不良的晶粒，、再利用雷射等方式進行修整（trimming )以達到規格要求，或是挑選出不良的晶粒以回收進行重工 (rework )在封盍接合前進行晶圓級測試可以避免使用不良的曰曰粒‘致產生不良的積體化模組，且前述之晶圓級曰曰粒封1均不而要使用填膠（unde r f i丨i )的步驟，因此可允許重工。由前所述，本發明可基於特定實施例及附圖所描述。 =何熟習此技術者，皆可參考此描述而更清楚了解此描述貝施例之不同的改良及結合及其它發明之實施例。因此，上述貝例係作為描述本發明，而非限制此發明。參考資料： ^ 1. C. Faulkner, ,f RF modules enables an integrated approach to system design, n Wireless Systems Design, Dec. 2000, pp· 37-40. I , •丨：，2· G· Ronald，nThin-film pass i ve integration yields tiny Bluetooth module,丨，Wireless Systems •.Design, Aug. 2000, pp. 23-30. 鲁 3. J.J. Yao, ,fRF MEMS from a device perspective, ,f Journal of Micromechanics and Microengineering, 10, pp.9-38, 2000. 4. M. Esashi, M Encapsulated Micro mechanicalPage 21 490771 V. Description of the invention (19) '----- Test the system-level characteristics under each condition, and select the available chips (Kn〇wn G〇〇d D 1 e, KGD) to cover the performance. Join. Defective grains can be found through the measurement results, and then trimming is performed by laser and other methods to meet the specifications, or defective grains are selected for recycling for rework before sealing and bonding. Performing wafer-level testing can avoid the use of bad chips, which can cause bad integrated modules, and the aforementioned wafer-level chip seals 1 do not require the step of filling (unde rfi 丨 i). , So heavy industry is allowed. From the foregoing, the present invention can be described based on specific embodiments and the accompanying drawings. Anyone familiar with this technology can refer to this description to understand this description more clearly. Different modifications and combinations of the examples and other embodiments of the invention. Therefore, the above examples are intended to describe the present invention, but not to limit the invention. References: ^ 1. C. Faulkner,, f RF modules enables an integrated approach to system design, n Wireless Systems Design, Dec. 2000, pp · 37-40. I, • 丨:, 2. G · Ronald, nThin -film pass i ve integration yields tiny Bluetooth module, 丨, Wireless Systems • .Design, Aug. 2000, pp. 23-30. Lu 3. JJ Yao,, fRF MEMS from a device perspective,, f Journal of Micromechanics and Microengineering , 10, pp.9-38, 2000. 4. M. Esashi, M Encapsulated Micro mechanical

第22頁 490771 五、發明說明（20) sensors, ,f Microsystem Technologies, 1, pp. 2 — 9， 1 994. 5. F. Niklaus， P. Ennoksson, E. Kalvesten, and G. Stemme，丨丨 Low-temperature full wafer adhesive bonding，" Journal of Micromechanics and Microengineering, 11, pp.100-107, 2001.Page 22 490771 V. Description of the invention (20) sensors,, f Microsystem Technologies, 1, pp. 2-9, 1 994. 5. F. Niklaus, P. Ennoksson, E. Kalvesten, and G. Stemme, 丨丨Low-temperature full wafer adhesive bonding, " Journal of Micromechanics and Microengineering, 11, pp. 100-107, 2001.

490771 圖式簡單說明第1 a圖至第1 d圖為先前技術中整合被動元件高頻模組的結構示意圖。 ' 弟2 a圖至弟2 j圖為本發明利用晶圓級晶粒封裝 (Wafer Level Chip Scale Package， WLCSP)技術中，其上製作高頻模組的基板與另一基板製成之封蓋相互接合後於基板正面以打線方式取出信號之流程圖。第3 a圖至第3 d圖為本發明利用晶圓級晶粒封装技術中，其上製作高頻模組的基板與另一基板製成之封蓋相互接合後於基板正面以製作錫鉛球的方式取出信號之程圖。 ( 第4a圖至第4m圖為本發明利用晶圓級晶粒封裝技術中，其上製作高頻模組的基板與另一基板製成之封苗相互接合後於基板月面以打線方式取出L就之流程圖。第5a圖至第5m圖為本發明利用晶圓級晶粒封裝技術中〆其上製作高頻模組的基板與另一基板製成之封蓋相互接:合後於基板背面以製作錫鉛球的方式取出信號之流程 :圖。」:第6 a圖至第6 e圖為本發明利用晶圓級晶粒封裝技術中' 其上製作高頻模組的基板與另一基板製成之封蓋 <，利 (用接著層接合法相互接合後，於基板正面以打線方2取出( 信號之流程圖。 > 第7a圖至第7h圖為本發明利用晶圓級晶粒封裝技術中，其上製作咼頻模組的基板與另一基板製成之封罢，利用陽極接合法或接著層接合方式相互接合後，於基板背面490771 Brief description of the drawings Figures 1a to 1d are schematic diagrams of the structure of a passive component high-frequency module integrated in the prior art. '' Brother 2a to Brother 2j are diagrams in the present invention using wafer level chip scale package (WLCSP) technology, the substrate on which the high-frequency module is fabricated and the cover made of another substrate are bonded to each other A flowchart of taking out signals by wiring on the front of the substrate. Figures 3a to 3d show the method of making a tin-lead ball on the front side of the substrate after the substrate on which the high-frequency module is fabricated and the cover made of another substrate are bonded to each other in the wafer-level die packaging technology of the present invention. Take out the signal map. (Figures 4a to 4m show the use of wafer-level die packaging technology in the present invention. The substrate on which the high-frequency module is fabricated and the sealing seedling made of another substrate are bonded to each other. The flowcharts in Figures 5a to 5m illustrate the use of wafer-level die packaging technology in the present invention where the substrate on which the high-frequency module is fabricated and the cover made of another substrate are connected to each other: the substrate is fabricated on the back of the substrate after fabrication. The process of taking the signal out of the tin-lead ball method: Figure. "Figures 6a to 6e are the seals made of the substrate on which the high-frequency module is fabricated and another substrate in the present invention using wafer-level die packaging technology. Cover <, (After bonding to each other by the adhesive bonding method, take out the signal 2 on the front side of the substrate (signal flow chart.) Figures 7a to 7h show the use of wafer-level die packaging technology in the present invention. After the substrate on which the audio module is made and the other substrate are sealed, they are bonded to each other by anodic bonding or adhesive bonding, and then on the back of the substrate.

1式簡單說明妾口，動元件之製程流裎圖。第8圖為本發明利用s 作高頻模組的基板與另一㈤复®、.及晶粒封裝技術中，其上製合以完成高頻模組製作之=上接合主動元件的基板相互接 ^ π 取1F〈流程圖。弟9圖為本發明利用曰上製作高頻模組的基板盘8Θ另及晶粒封裝技術中，兩個其合以完成高頻模組之流程圖y基板製成之接合基板相互接第10圖為本發明利用曰撓性軟板為基板，在i卜:®、、及曰曰粒封裝技術中，利用可元件之製程流程圖。’、接合各式矽基與非矽基之主被動弟11圖為本發明利用曰曰 ^ 作的高頻模组直 a阳囫、·及日日粒封裝技術中，將所製性盘曰圓级箱造灯BB圓級測試量測高頻模組之系統特注Η日日圓級預燒之示意圖- 圖示之參考數字及其名稱對照〉 ' 10 、201 、300 、400 、500 、600 、700 、800 、900 、 901、1 0 0 0、110〇 :基板 ,11、2 0 2、4 0 2、5 0 2 :電阻層 ” 12 、 203 、 403 、 503 :第一金屬圖案 k 14、2 0 7 :第二金屬圖案 .17、211:第三金屬圖案 13 :第一介電層 1 5 :第二介電層 '1 8 :第三介電層Type 1 is a simple description of the process flow diagram of the gate, moving element. Fig. 8 shows the substrate of the present invention using s as a high-frequency module, and another compound ®, ..., and die packaging technology, which is fabricated on top to complete the production of high-frequency modules = the substrates with active components are connected to each other ^ π take 1F <flow chart. Figure 9 is a substrate plate 8Θ of the present invention using a high-frequency module. In the die packaging technology, two bonding substrates made of a high-frequency module to complete the flowchart of a high-frequency module are connected to each other. Figure 10 is the present invention The flexible flexible board is used as the substrate, and the process flow chart of the component can be used in the i.e. '11. The active and passive brothers joining various silicon-based and non-silicon-based devices are shown in Figure 11. This is a high-frequency module made by the present invention. Box lamp BB round-level test and measurement of high-frequency module system special note Η Japanese yen-level burn-in schematic diagram-the reference numerals and their names in the diagram> '10, 201, 300, 400, 500, 600, 700, 800, 900, 901, 1 0 0 0, 1 10: substrate, 11, 2 0 2, 4 0 2, 5 0 2: resistance layer "12, 1, 203, 403, 503: first metal pattern k 14, 2 0 7: Second metal pattern. 17, 211: Third metal pattern 13: First dielectric layer 15: Second dielectric layer '18: Third dielectric layer

第25頁Page 25

圖式簡單說明 16 ： L :缓衝層微波開關的結構電感結構或微機電g 電阻結構電容結構 205 206 207 209 210 213 封蓋基板 904 214 1101 ,215 ；216 306 第一保護層介電層第二金屬層保護層接觸窗 301 、 401 、 501 601 、 701 、 710 、 801 、 1007 接合基板 302 、 407 、 :高頻模組 3 0 3 :空腔 304 、 603 、第一金屬層 507 ^ 602 > 702 ^ 802 > 902 ^ 903 703、：金屬層 3 0 5、5 0 6、70 5 :金屬墊 3 0 8、3 0 9、5 0 8、1 0 0 3 :錫鉛球 212、706、803、1004、1005、1006、1102 :主被動元件 405、505、704 :接觸窗 604 :接著層 217 、 408 、 6 0 5 、 70 7 ：打、線Brief description of the drawing 16: L: Structure of the buffer layer microwave switch Inductive structure or MEMS g Resistor structure Capacitive structure 205 206 207 209 210 213 Covering substrate 904 214 1101, 215; 216 306 Two metal layer protective layer contact window 301, 401, 501 601, 701, 710, 801, 1007 Bonding substrate 302, 407: High-frequency module 3 03: Cavities 304, 603, first metal layer 507 ^ 602 > 702 ^ 802 > 902 ^ 903 703 ,: metal layer 3 0 5, 5, 0 6, 70 5: metal pad 3 0 8, 3 0 9, 5 0 8, 1 0 0 3: tin-lead ball 212, 706, 803, 1004, 1005, 1006, 1102: Active and passive components 405, 505, 704: Contact window 604: Adhesive layer 217, 408, 6 0 5, 70 7: Hit, wire

第26頁 490771Page 490 771

第27頁Page 27

Claims

490771 修正案號 90109115 六、申請專利範圍 1, 一種整合主被動元件之高頻模組，包括：一絕緣基板；沈積於絕緣基板上之電阻層；形成於電阻層兩端部上並延伸於絕緣基板上，以構成電阻結構與正面第一導線及金屬墊之第一金屬層；形成於第一金屬層延伸於絕緣基板上之部份的第一保護層；形成於所述電阻層上之所述第一金屬層上之介電層；形成於所述介電層上之第二金屬層，如此，第一金屬490771 Amendment No. 90109115 Scope of patent application 1. A high-frequency module integrating active and passive components, including: an insulating substrate; a resistive layer deposited on the insulating substrate; formed on both ends of the resistive layer and extending on the insulating substrate A first metal layer constituting a resistance structure and a front first wire and a metal pad; a first protective layer formed on a portion of the first metal layer extending on the insulating substrate; and the first layer formed on the resistance layer A dielectric layer on a metal layer; a second metal layer formed on the dielectric layer, so that the first metal

層、介電層與第二金屬層乃構成電容結構；包覆電阻、電容等被動元件並均勻塗佈於絕緣基板上之第二保護層；形成於所述第二保護層上之接觸窗；沈積並定義於第二保護層上之第三金屬層；以及形成於第二保護層與第三金屬層上之主被動元件。 2. —種整合主被動元件之高頻模組之製造方法，包括步驟如下：提供一基板；，在基板上沈積並定義電阻層；Layer, dielectric layer and second metal layer constitute a capacitor structure; a second protective layer that covers passive elements such as resistors and capacitors and is evenly coated on an insulating substrate; a contact window formed on the second protective layer; A third metal layer deposited and defined on the second protective layer; and a main and passive element formed on the second protective layer and the third metal layer. 2. A method for manufacturing a high-frequency module integrating active and passive components, including the following steps: Provide a substrate; Deposit and define a resistance layer on the substrate;

沈積並定義第一金屬層；沈積並定義第一保護層作為第一金屬層與封裝後封蓋上的金屬層之隔絕；沈積並定義介電層及第二金屬層；以旋佈方式（sp i n-on )形成第二保護層；Deposit and define a first metal layer; deposit and define a first protective layer as a first metal layer to be isolated from a metal layer on a cap after packaging; deposit and define a dielectric layer and a second metal layer; i n-on) forming a second protective layer;

第28頁牛六正、申請專^* 於宽一屬層，以護層上定義出接觸f ’且沈積並定義第三金 * %成正面的第二導線； 3在第二保護層上製作各種主被動元件。二保護專利範圍第1項之高頻模級，其中形成於第 lc、非‘2 屬層上之主被動元件如矽基訊號處理 )、或放大器、快閃記M(flash — 八双位訊號處理器等。主被4動H請ί利範圍第2項之m造方法，其中製作各種電極，來包括利用第二導線為電鍍結構的底層下可變電型電感或是微開關元件或是微機電型寻之梦驟者。步驟5如;種整合主被動元件之高頻模組的封裝方法，包括提供第一基板及第二基板；在第一基板上製作高頻模組；在第二基板上製作封蓋；在作為封蓋之第二基板内側凹槽中沈積金將此作為封蓋之第二基板與含高頻且’ 互對準，然後以夾具固定之；模、且之弟一基板相 a板封蓋的第二基… 基板移至θ曰片接合機内，進行加溫或加電壓弟^ 驟，或前述三方法的複數使用的步驟 — 的乂進行切割，並由正面第一導線所序; 線，以拉出信號。、屬墊進仃打Page 28 Niu Liuzheng, apply for a special ^ * on the first layer of Kuan, define the second wire that contacts f 'on the protective layer and deposit and define the third gold *% to the front; 3 make on the second protective layer Various active and passive components. The second protection patent covers the first high-frequency mode stage, in which active and passive components such as silicon-based signal processing are formed on the lc, non-'2 layer, or amplifier, flash M (flash — eight dual-bit signal processor, etc.) The main method is described in item 2 of the scope of the invention, in which various electrodes are fabricated to include a variable electrical type inductor or a micro-switching element or a micro-electro-mechanical type under the bottom layer using a second wire as a plating structure. Step 5: If a method for packaging high-frequency modules integrating active and passive components includes providing a first substrate and a second substrate; making a high-frequency module on the first substrate; making a cover on the second substrate; Deposit gold in the inner groove of the second substrate as the cover, and align the second substrate as the cover with a high frequency and ', and then fix it with a jig; The second base of the cover ... The substrate is moved into the θ-sheet bonding machine, and the heating or voltage step ^ is performed, or the plural steps of the foregoing three methods are used to cut the 乂 and is ordered by the first lead on the front; To pull out Number., Is playing into the Ding pad

第29頁 490771 六、申請專利範圍步驟如下：整口主被動兀件之高頻模組的封震方法，包括提供第一基板及第二基板；，第基板上製作高頻模組；在第二基板上製作封蓋· j作為封蓋之第=基板内侧凹將此作為封蓋之第二其^ ^ /積金屬，互對準，然後以夹具固^二；/、3向頻模組之第一基板相將固疋後之作為封芸 — 基板移至晶片接合機内，推f二基板與含高頻模組的第一 ;，或前述三方法的；數；：：；;戈加而電f;加壓力的步序；驟而元成接合的程自正面形成金屬層且連釺金屬層可爬坡於作為封蓋^ 了土板上的第一金屬層使在作為封蓋之第二卜緣側壁；上製作錫鉛球；疋義出金屬墊，並在金屬墊 7進：Γ割’完成晶圓級晶粒封裝程序。如申請專利範圍第H 1展往斤内側凹槽内形成一空腔，封6項之封裝方法1中封蓋的功能元件不受外部電磁波;壁為金屬層，以保護内部位於此空腔之内。擾，且高頻模組的功能元件 8· 一種整合主被動元件古步驟如下： < 阿頻模組的封裝方法，包括提供第一基板； 490771 ———二 --------年月六、申請專利範圍在第一基板上沈積並定義電阻層及第一金屬層，· 自背面姓穿第一基板，形成接觸窗； μ接著在第一基板背面沈積第二金屬層，使此金屬層連接第一基板正面第一金屬層，並覆蓋接觸窗的側壁，延於第一基板的背面；在第一基板的背面定義背面第一導線與金屬墊；接續主被動元件的整合製程於第—基板的正進行切割； 9在！：ί;”面金屬墊上以打線方式將信號取出。 9 · 一種整合主被動元件之高頻槿步驟如下： π肩模組的封裝方法，包括提供第一基板及第二基板；在第一基板上製作高頻模組；；蝕穿第一基板，以形成基板孔；卸與月面導線連結的引在第一基板上製作封蓋，· 在作為封蓋之第二基板内侧凹沈將此作為封蓋之第二基板鱼含積金屬；互對準，然後以夾具固定之；”阿須模組之第一基板相將固定後之作為封蓋的第二基古基板移至晶片接合機内，進行加溫3咼頻模組的第一驟，或前述三方法的複數使用或加塵力的步序；而70成接合的程沈積並定義金屬於引孔與基板背面；六、申請專利範圍在第—基板背面的金屬墊製作锡妒 “ 1〇.如申請專利範圍第8或第9項之°封拉出h號。盖内側凹槽内形成-空腔，封蓋内壁為:裝//，其中封件位於此空腔之内。“磁波干擾’且高頻模組的功能元 11 · 一種整合主被動元件之高括步驟如下·· 貝镆組的封裝方法，包提供第一基板及第二基板；在第一基板上製作高頻模組；在第二基板上製作封蓋；蝕刻以形成封蓋外型依序在第二基板上鍍上金屬層使封蓋基板上沾附接著層；將第一基板與第二基板對準、壓人，加壓力’或前述二者之複數使用方式：熱處理或外二經過切二打線，便可完成此_模組括步X種整合主被動元件之高頻模組的封:^^ ，提供第一基板及第二基板；在第一基板上製作高頻模組； #穿第一基板，以形成基孔；月面導線連結的弓丨在弟二基板上製作封蓋；在做為封蓋之第二基板的内侧凹槽中沈積金屬； 490771 曰修正 i號 9(η_κ 六、申請專利範圍將此作為封蓋之第二基板與互對準，然後以失具固定之；」、、、且之第一基板相將固定後之作為封蓋的第二基板盥葙基板移至晶片接合機内，進行加溫或加電=吴二的第一驟，或前述.三方法的複數使用力的步序；而凡成接合的程沈積並定義金屬於引孔與基板背面；切割，並將須整合的元件接合於基板在基板背面的金屬墊上打線，以拉出俨， =封膠或金人屬^切基封蓋覆蓋基板。之元件。括步驟如下，主被動凡件之向頻模組的封裝方法，包提供第一基板及第二基板；在第一基板上製作高頻模組；钮穿第-基板，以形成基板正面與背面導線連結的引子L· ，在第二基板上製作封蓋；在做為封蓋之第二基板的内側凹槽中沈積金屬；將此作為封蓋之第二基板與含高頻模組一互對準，然後以夾具固定之；弟基板相將固定後之作為封蓋的第二基板與含高頻模組的第一基板移至晶片接合機内，進行加溫或加電壓或加壓力的驟，或前述三方法的複數使用的步驟，而完成接合的程序； °Page 29 490771 VI. The steps for applying for a patent are as follows: a method for sealing a high-frequency module of a whole mouth of active and passive components, including providing a first substrate and a second substrate; and, making a high-frequency module on the second substrate; making on the second substrate Cover · j is used as the first part of the cover, and the inner side of the substrate is used as the second part of the cover. ^ ^ / Build-up metal, aligned with each other, and then fixed by a fixture; /, the first substrate of the 3-way frequency module After the solid phase is sealed, the substrate is moved into the wafer bonding machine, and the two substrates and the first containing the high-frequency module are pushed; or the three methods described above; number;: ;; Goga and electricity f; pressure The step of joining elements suddenly forms a metal layer from the front and the flail metal layer can climb on the first metal layer on the soil plate as a cover ^ on the side wall of the second edge of the cover; The tin-lead ball is produced on the surface; the metal pad is defined, and the metal pad 7 is entered: Γ cut to complete the wafer-level die packaging process. For example, in the scope of patent application H1, a cavity is formed in the inner groove of the kilogram, and the functional elements covered in the encapsulation method 1 of item 6 are not subject to external electromagnetic waves; the wall is a metal layer to protect the interior of the cavity. . Disturbance, and high-frequency module functional components8. An ancient step of integrating active and passive components is as follows: < A frequency module packaging method, including providing a first substrate; Sixth, the scope of the application for the patent deposits and defines the resistance layer and the first metal layer on the first substrate, and penetrates the first substrate from the back to form a contact window; μ then deposits a second metal layer on the back of the first substrate to make this metal Layer is connected to the first metal layer on the front surface of the first substrate and covers the side wall of the contact window and extends to the back surface of the first substrate; defines the first back wire and metal pad on the back surface of the first substrate; — The substrate is being cut; 9 in! : ""; The signal is taken out by wire bonding on a surface metal pad. 9 · A high-frequency chip integrating active and passive components is as follows: π shoulder module packaging method, including providing a first substrate and a second substrate; Make high-frequency modules on the top; etch through the first substrate to form substrate holes; remove the lead connected to the lunar surface to make a cover on the first substrate; The second substrate of the cover contains metal deposits; they are aligned with each other, and then fixed with a clamp; "The first substrate phase of the ASU module moves the fixed second base substrate as a cover to the wafer bonding machine, and adds The first step of the temperature 3 audio frequency module, or the multiple use or dusting steps of the foregoing three methods; and 70% of the bonding process deposits and defines the metal on the back of the lead-through hole and the substrate; —The metal pad on the back of the substrate is made of tin jealousy. 10. If the 8th or 9th degree of the scope of the patent application is applied, the seal is pulled out. The cavity inside the cover forms a cavity, and the inner wall of the cover is: // Where the seal is located in this cavity Inside. "Magnetic interference" and high-frequency module functional element 11 · A high-level integration step of active and passive components is as follows: · Behr group packaging method, including providing a first substrate and a second substrate; making a high-frequency mode on the first substrate Group; making a cover on the second substrate; etching to form a cover shape, plating a metal layer on the second substrate in order to attach an adhesive layer to the cover substrate; aligning the first substrate with the second substrate, Press people, add pressure 'or the plural use methods of the foregoing: heat treatment or external two cut two lines, you can complete this _ module includes step X kinds of high-frequency module integration of active and passive components: ^^, provide the first A substrate and a second substrate; making a high-frequency module on the first substrate; #passing through the first substrate to form a base hole; a bow connected by a lunar wire 丨 making a cap on the second substrate; Metal is deposited in the inner groove of the two substrates; 490771 is the amendment i No. 9 (η_κ VI. The scope of the patent application is to align the second substrate as a cover with each other, and then fix it with a missing piece; ",,, and The first substrate phase moves the fixed second substrate, which is the cover, into the wafer bonding machine, and performs heating or electricity = the first step of Wu Er, or the steps of using the plural methods of the foregoing three methods. ; Where the process of joining deposits and defines the metal on the lead-through and the back of the substrate; cuts and joins the components to be integrated on the substrate and wire on the metal pad on the back of the substrate to pull out 俨, = sealant or gold ^ The cutting base cover covers the substrate. The components include the following steps. The method of packaging the active and passive components to the frequency module includes providing a first substrate and a second substrate; making a high frequency module on the first substrate; A substrate to form a lead L · that connects the front and back wires of the substrate, and make a cover on the second substrate; deposit metal in the inner groove of the second substrate as the cover; Align with a high-frequency module and fix it with a clamp. The second substrate will move the fixed second substrate as a cover and the first substrate with the high-frequency module into the wafer bonding machine for heating or heating. Pressure or applied pressure step, or a plurality of steps used in the aforementioned three methods, the program is completed engaged; [deg.]

490771490771

Μ 號 9010911R 申請專利範圍沈積並定義金屬於引孔與基板背面；將須整合的主被動元件覆晶接合於美北以封膠或金屬蓋或石夕美射芸灣：g：甘月、， 1 4 一插敕入盍基板背面之元件。 14. 一種整合主被動元件之高頻模括步驟如下： ^了装方法，包提供第一基板及第二基板；在第一基板上製作高頻模組；在第二基板上製作封蓋； Γΐί合的主動元件接合在做為封蓋之第-美板上· 互對準，然後以夾具固定之；、衩、、且之弟一基板相將固定後之作為封芸的莖—其 A 基板移至晶片接合機内T進抒7$ 1、3面頻模組的第一驟，或前述=方法3 L ΐ 電壓或加壓力的步 4别返一方去的複數使用的步驟， 4 y 序。 /种而兀成接合的程 15· 一種整合主被動元件之高頻模組的封, 括步驟如下： …对褒方法，包提供第一基板、第二基板以及第三基板；，在f 一基板上製作高頻模組；在第二基板上製作高頻模組；在f三基板上定義並形成接合基板之外型；之；將第-基板與第三基板相互對準’然後以失具固定將固定後之第一基板與第三基板移至晶片接合機内No. 9010911R patent application scope deposits and defines the metal on the back of the via and the substrate; flip-chip bonding of the active and passive components to be integrated in North America with a sealant or metal cover or Shixi Meishe Yunwan: g: Gan Yue ,, 1 4 A component inserted into the back of the substrate. 14. A high-frequency module integration step of integrating active and passive components is as follows: a method for mounting, including providing a first substrate and a second substrate; making a high-frequency module on the first substrate; making a cover on the second substrate; The components are bonded on the first-beauty board as the cover. Align each other, and then fix it with a clamp. The substrate phase of the substrate is to be used as a sealed stem after the substrate phase is fixed. The A substrate is moved to the wafer. In the bonding machine, T enters the first step of 7 $ 1, 3 surface frequency module, or the aforementioned = method 3 L ΐ step of voltage or pressure 4 do not return to the plural steps, 4 y sequence. / Kind of process of joint 15 · A seal of a high-frequency module integrating active and passive components, including the following steps:… confrontation method, including providing a first substrate, a second substrate and a third substrate; on the f-substrate Making high-frequency modules; making high-frequency modules on the second substrate; defining and forming a joint substrate outside shape on the three substrates; of; aligning the first substrate and the third substrate with each other; The first substrate and the third substrate are moved into the wafer bonding machine

六、申請專利範圍或前述三方法的複數進行加溫或加電壓或加壓力的步屬使用的步驟，而完成接合的程序；將第二基板與包含第一基板金互對準，然後以夾具固定之；/、弟二基板之複合基板相將固定後之第二基板與包含合基板移至晶片接合機内，進 if板與第三基板之複步驟，或前述三方法的複數使用加電壓或加壓力的序。 V驟’而完成接合的程 16· —種整合主被勤分放丄括步驟如下：向頻模組的封裝方法，包基板；以構成正面第一導線及4 提供第一可撓性軟板與第形成於第一可撓性軟板上屬墊的第一金屬層；幵> 成於金屬墊上的锡斜球；將須整合的矽基主動开二種元件之複數，接合於锡鉛^石夕基主動元件，或前i 將須整合的如申請專利範’ 體化整合型被動元件接合於錫鉛$上項或第2項中所提之ί ，在第二基板上製作封蓋· ’ 將此作為封蓋之第二基板盘含基板相互對準，然後再以— 。、、、且之第一可撓七並完成封裝；、又、裝^程之常用方法固定3 將固定後之作為封蓋的_ 可撓性基板移至晶片接合機=了 ς，，含高頻模組的第- 铖内進盯加溫或加電壓或加I 案號 9010911R6. The scope of patent application or the plural of the three methods mentioned above are the steps of heating or voltage or pressure to complete the bonding process; align the second substrate with the gold containing the first substrate, and then use jigs Fix it; /, the composite substrate phase of the second substrate moves the fixed second substrate and the combined substrate to the wafer bonding machine, and enters the multiple steps of the if board and the third substrate, or uses the voltage or Order of pressure. The process of completing the joining step 16 is as follows: A kind of integration of the main and sub-stations includes the following steps: The packaging method of the frequency module, the substrate is covered; the first flexible lead and the first flexible flexible board are provided. And the first metal layer formed on the first flexible flexible board as a pad; 幵 > a tin slanting ball formed on the metal pad; a silicon-based active-opening of a plurality of two components to be integrated and bonded to tin-lead ^ Shi Xiji active component, or the former i will be integrated as described in the patent application, the integrated integrated passive component is connected to the tin lead, as mentioned in the above item or item 2, and a cover is made on the second substrate. · 'Use this as the cover of the second substrate tray with the substrates aligned with each other, and then-—. ,,, and the first flexible seven and complete the package; ,,, the common method of the assembly process fixed 3 Move the fixed _ flexible substrate to the wafer bonding machine = ς, including high-frequency mode No.-Inner Star Warming or Voltage or I Case No. 9010911R

六、申請專利範圍而完成接合包括步力的步驟’或前述三方法的複數使用的步驟的程序。 ’其中所提及 ’其中所提及 ’其中所提及 ^ 17·如申請專利範圍第丨6項之封裝方法的第二基板可為金屬材質封蓋。 1 8 ·如申請專利範圍第1 6項之封裝方法的第二基板亦可為含金屬被覆膜之矽基板。々1 9 ·如申請專利範圍第1 6項之封裝方法的第二基板亦可為破璃基板。 2 0 · —種可進行高頻模組晶圓級測試的方驟如下：挽供笫 _ 於晶圓級第一基板上製作高頻模組；旦士，以探針或普羅卡（probe card)在晶圓級基板』里測向頻模組之系統特性。 21. 如申請專利範圍第18項之方法，於測試過可回收與置換有問題的主動元件。任T 22. 如申請專利範圍第18項之方法’於測試過程 ::用田射加工：¾ (Laser trimming)及其他業界常用方式於晶圓階段來修整被動元件的特性。 23. 如申請專利範圍第18項之方法，於完成測試及曰 ^級封純，可將仍處於晶圓狀態的模組置於環曰曰中，再輔以探針或晶圓級普羅卡來施加外界交流電訊j墙或直流偏壓來進打長時間預燒（burn_in)等加速老化^ (aging treatment )的動作。6. The scope of the patent application to complete the process of joining including the step of step 'or a plurality of steps of the foregoing three methods. ‘Mentioned in’ ‘Mentioned in’ Mentioned in ^ 17. The second substrate of the packaging method according to item 6 of the patent application may be a metal material cover. 1 8 · If the second substrate of the packaging method No. 16 of the patent application scope is a silicon substrate containing a metal coating film. 々19 · If the second substrate of the packaging method No. 16 of the scope of patent application is used, the second substrate may be a broken glass substrate. 2 0 · — A method for performing wafer-level testing of high-frequency modules is as follows: 笫制作制作 Make high-frequency modules on a wafer-level first substrate; use a probe or probe card on the wafer The system characteristics of the directional frequency module in the "level substrate". 21. If the method in the scope of patent application No. 18 has been tested, the active components in question can be recovered and replaced. Any T 22. If the method of applying for the scope of patent No. 18 is used in the test process :: using field shot processing: ¾ (Laser trimming) and other common methods in the industry to trim the characteristics of passive components at the wafer stage. 23. According to the method of applying for the item No. 18 of the patent scope, after the test is completed and the grade is sealed, the module still in the wafer state can be placed in the ring, and then supplemented with a probe or wafer-level proca To apply external AC telecommunication wall or DC bias to perform long-term burn-in and other accelerated aging treatments.