TW488052B - Manufacture process of bumps of double layers or more - Google Patents
Manufacture process of bumps of double layers or more Download PDFInfo
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- TW488052B TW488052B TW090111669A TW90111669A TW488052B TW 488052 B TW488052 B TW 488052B TW 090111669 A TW090111669 A TW 090111669A TW 90111669 A TW90111669 A TW 90111669A TW 488052 B TW488052 B TW 488052B
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Description
488052 A7 B7 五、發明説明(/) 發明領域: 本發明是關於一種無電鍍形成雙層以上金屬凸塊之製 釭’4寸別是關於一種異方性導電膜(anisotropic conductive fllm, ACF)方式應用在LCD、一般IC及射頻元件(RI^封裝時, 完成良好披覆效果之高厚度金屬凸塊製程。 發明背景: 按’現今的半導體技術日新月異且競爭激烈,所有的半 ‘體製造與封裝業者無不竭心盡力企圖研發出體積更小、效 能更而、且成本更低的積體電路元件。除了積體電路晶片(IC Chip)的生產技術已邁入深次微米與十二吋晶圓(Wafcr)的 製权之外,在晶片的封裝技術上亦有長足的進步。從傳統的
‘線呆封裝(Lead Frame Package )、錫球陣列封裝(BGA
Package)、到基板自動接合錫球陣列封裝(ΤΑβ BGA),目 前的封裝技術已可使積體電路元件的元件尺寸更小、更薄, 且晶片執行效能與生產效率卻更高。 疡知種新穎之異方性導電膜(anisotropic conductive fllm,ACF)方式應用在LCD、一般1C及射頻元件(radiation frequency,Rp)封裝。其係利用一種積體電路晶片或半導體 基板上的銲墊(pad)設計,可利用導線層再透過金屬凸塊 (bump)與外界相導通,如此不論是作位置變更或電性檢測 等,均可依實際需求作不同之佈線設計。目前一般金屬凸塊 之a又什皆為以電鍍(dectn叩丨姐呢)一導電金屬為主體。但 是電鍍凸塊乃―片片的處理’若考慮其電鍍均勻度時,其製 I ί I - — - Ί - —--·- - - - - - I -- ϋ (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 488052 A7 五、發明説明(> ) =成本將’且其產能亦受限。其次如果凸塊是長在忙晶 t ’則需要在晶圓廠中藉由晶圓製程來進行製造 "/、貝目^脆的^^族化合物轉體上。因此就有 構裝基板上成長凸塊的方式來取代1C晶片上長凸塊之势 f。習知以異方性導電膜(ACF)方式可細在LCD、一般 C及射頻讀(RF)封裝上,其成長之金屬銅凸塊需具獅 /m以上之面度;而若以_鍍方式形成金私塊則無法 =厚度要求,且即使快速無紐銅速率亦僅約4师浙。而 在厚度太高時不但須耗費長時間,且其披覆效果亦不佳。 因此’本發明提出一種可簡化金屬凸塊之製程,且製造 成本相對降低’不僅於製程條件控制與技術複雜度均相對更 H品良率相對增高,可進行批次生產,且製造成本也可 大幅減少。 〜十b J 發明概述:
雔声的,”在提供—種低成本無電鑛形成 又層孟屬凸塊之製程’特別是關於一種異方性導電膜(A =應用在LCD、1C及射頻元件(RP)封裝時,以完成良好 披復效果之高厚度金屬凸塊製程。 本發明之另一目的,是在提供一種無電鑛形成雙層金屬 凸塊之製程’其具良好導電躲及賴元件的麵特性(skm effect)卩達到以無電n方式應用於射頻元件封裝。 為達上述之目的’於本發明之較佳實施例t,該無電鍵 請 先 聞 讀 背 意 事 項 再 填 寫 本 頁 # 訂 本,,,氏張尺度適用令國國家標準(⑽)Μ規格 (210X297公釐) A7 五、發明説明 形成鎳/銅(Ni/Cu)或鎳/金(Nl/Au)凸塊之製程,係可包括 有下列步驟: 、步恥(1) ·提供一設有若干銲墊(pad)之積體電路晶片 或基板。 步驟(2):塗佈上—第—介電層,該第一介電層係裸露 ^墊’可使用化學或物理方式將重分佈路線表面粗化,再 將/、/舌化以利無電鍍沈積,例如,接著塗佈上一 第二介電層,以定義出重分佈(rcdlstnbut麵)之路線。 ッ驟(3)·以無電錢方式(eiectr〇iesspiati叩)在該既定 之重刀佈路線巾沈積導線層,透賴導線層可使得銲塾作位 置變更而與外界相導通。 步驟(4):形成―光阻_,該光阻圖案並裸露出導線 層之右干預设位置,以作為重分佈後續金屬凸塊佈設之處。 、v驟(5 ) ·接著對各該預設位置表面進行活化㈤_〇η) 以產生活化劑(activat〇r)。 v驟⑹·以無電鍍(electroless plating)方式形成一預 定厚度之金屬凸塊(bump)於該鮮塾之上。 步驟⑺:移除該光阻圖案,完全裸露出該金屬凸塊。 V驟(8).覆上—第三介電層,其厚度較該金屬凸塊之 ,又低’並設有尺寸較金屬凸塊略大之開口,以裸露出該金 屬凸塊。 人^ Ο再以無I鍍方式形成—外圍金屬層完整披覆 外圍’此外圍金屬層的導電性或高頻特性較内 口Ρ金屬為佳,並與該導線層連通。 ^度適用中國 Ί! —; Ί--,·--衣-- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財4笱8工消費合作社印製 488052 經濟部智慧財產局員工消費合作社印製 A7 發明說明(ψ) 本發明無論於技術與功效上均與習知不 雔 在射頻元件⑽)完 之沾度金屬凸塊製程’其具良好導電特性及射頻元 頻元件封裝。 ,、、、電鍍方式應用於射 為使貴審查委員對於本發明能有更進一步的了解與認 同,茲配合圖式作一詳細說明如后。 ^ 圖式之簡單說明: 圖-A至圖-F係為本發明第一實施例以無電鑛形成錦 /銅(Ni/Cu)凸塊之製程之示意圖。 、 圖二A至圖二I係為本發明第二實施例以無電鑛形成錦/ 銅(Ni/Cu)凸塊之製程之示意圖。 ” 圖號說明: 100-基板 105-銲墊 110-保護層 115,225-光阻圖案 120,230-活化劑 125, 240-金屬凸塊 130,250-外圍金屬層 200-積體電路晶片 205-銲墊 L紙張尺度適用中國國家標準(CNS)A4 (請先閱讀背面之注意事項再填寫本頁) I ϋ - - s n n I / 丨、1 n n ·ϋ n I I n ____ _ 1=口 ------------------------ 488052 A7 _______B7 五、發明説明(/ ) 210-第一介電層 215-第二介電層 220-金屬層 245-第三介電層 發明之較佳實施例詳細說明: 本發明之在1C封裝基板上形成凸塊之方法及結構,主要 是藉由。以下將以兩具體實施例詳細說明之。 弟一實施例 請麥閱圖-A至圖-F,為本發明無電錢形成鎳/銅 (Ni/Cu)凸塊之製程之第—較佳實施例的實施步驟流程圖, 包括有下列步驟: 步驟⑴:如圖—A所示,提供-設有若干銲墊(pad) 105之基板100,各該銲墊1〇5之周圍並覆有一保護層&咖呢 layer) 110,以保護該銲墊1〇5免受外界傷害。其中所述之輝 塾105係可為銅銲墊(Cu_pad)或叙銲墊(Α]μ_其中一種。 步驟⑵·如圖-Β所示,形成一光阻圖案ιΐ5,該光阻 圖案115並裸露出各該銲墊1〇5,該光阻圖案115之厚度需大於 17〇 —步驟⑶:對該銲墊祕表面進行清潔,以去除其表面辦 巧及乳化物;係如可使_%猶(H抓)作清潔劑。如 圖一c所示,對各該銲細表面進行活化(触她n)以產 生活化劑⑽贿>〇 120,該活化劑12〇對銅輝塾來說可為 種晶(Pd-Seed);而難銲塾來說可為鋅種晶(Zn-Seed)。 (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財4局員工消費合作社印製 本紙張尺度s _鮮(— _____ 488052
五、發明説明( 經濟部智慧財產局員工消費合作社印製 .步驟⑷:下述為本發明重點之一,以無電鑛(electroless platmg)方式形成一預定厚度之金屬凸塊(bump)⑵於該鲜 墊105之上’如圖一〇所示;該金屬凸塊125以錄⑽為最 佳,其成長速率較銅快很多,其厚度可控制在ls〜2〇㈣之 間。 步驟⑸:移除該光阻圖案115,完全裸露出該金屬凸塊 '125 ’如圖一E所示。 /步驟(6):下述亦為本發明重點之一,再以無電鑛方式 形成-外圍金屬層130覆蓋住該金屬凸塊125外圍,該外圍金 屬層130最佳為金屬銅層,因而形成―“銲墊/鎳/銅”結構, 其中,金屬凸塊外圍金屬層130之厚度約在4μιη以下。 第二實施例 本發明之無電鍍形成鎳/銅(Nl/Cu)凸塊之製程亦可應用 於針對晶片之佈線需求或電性測試時,而對銲墊作位置變換 或外拉之情形。請參閱圖二A至圖二!,為本發明無電鍛形成 錄/銅(Ni/Cu)况鬼之製程之第二較佳實施例的實施步驟流 程圖,其係包括有下列步驟: 步驟(1) ··如圖二A所示,提供一設有若干銲墊(pad) 205之積體電路晶片200。其中所述之銲墊2〇5係可為銅銲墊 (Cu-pad)或鋁銲墊(Al-pad)其中一種。 步驟(2) ··塗佈上一第一介電層21〇,該第一介電層21〇 係裸露出銲墊205,接著,再塗佈上一第二介電層215,以定 義出重分佈(redistribution)之路線,如圖二6所示。當然, 备该It*塾205之周圍已覆有一保護層(passiveiayer),覆上第 度適用中國國家標準(CNS ) A4規格(210X2^^ -------- (請先閱讀背面之注丄思事項再填寫本頁)
經濟部智慧財產局員工消費合作钍印製 ^8052 Μ —___^___ 五、發明説明(/ ) 一介電層210之步驟則可省略,而在其表面亦需進行活化或及 粗化。 步驟(3) ··如圖二C所示’以無電錢方式在該既定之重分 佈路線中沈積導線層22〇,該導線層22〇以金屬層為較佳,最 佳者為金屬銅層,透過轉導線層220可使得銲墊2〇5作位置變 更而與外界相導通,當然,該導線層220係可依實際需求作出 各種不同之佈線設計。 下述各步驟為本發明重點: 步驟(4):如圖二D所示,形成一光阻圖案225,該光阻 圖案225並裸露出導線層220上之若干預設位置225a,該預設 位置225 a即是作為重分佈後續金屬凸塊佈設之處。同樣的, 該預設位置225a係可依實際需求作出各種不同之佈線設計。 步驟(5) ·•對該銲墊預設位置225 a表面進行清潔,以去 除其表面髒污及氧化物;可使用10%硫酸(h2S〇4)作為清 潔劑。接著對各該預設位置225&表面進行活化(3比¥組〇11) 以產生活化劑(activator) 230,該活化劑12〇對銅銲墊來說可 為種晶(Pd-seed),較佳者可選擇只吸附於銅銲墊表面之 具選擇性之溶液;而對鋁銲墊來說可為鋅種晶, 如圖二E所示,。 、步驟(6) ·如圖二ρ所示,以無電鍍(elec_ess卿㈣) 方式形成-敢厚度之金如塊(bump) 24鱗塾2〇5之 上’。亥至屬凸塊24〇以成長較快的金屬如鎳(⑹為最佳。 步驟⑺:移除該光阻圖案225,完全裸露出該金屬凸塊 240,如圖二g所示。 (請先閲讀背面之注意事項再填寫本頁)
五、發明說明(/) 步_ (8) ··覆上-第三介電層245,該第三介電層施之 厚度較該金屬凸塊240之高度低,並設有尺寸較金屬凸塊24〇 略大之開口,以裸露出該金屬凸塊24〇,如圖所示。 步驟⑼·再以無電鍍方式形成-外圍金屬層25〇完整彼覆住該金 屬凸齡40外圍’並與该導縣220連通,該外圍金屬層测以電性或高 頻特陳佳的金屬如銅或金Μ佳。其中,所述金屬凸社外圍金屬 層250之厚度約在4 pm以下,如圖二I所示。 如此,該銲墊2〇5可利用導線層no再透過金屬凸塊24〇 與外界相導通,不論是作位置變更或電性檢測等,均可依實 際需求作不同之佈線設計,達到良好功效。 、 其中,所述介電層之材質係選驗佳結合能力(附著能 力)的材質所構成,該介電層可選擇以化學氣相沈積 (CVD)、真空濺鑛(Sputtering)、旋轉塗佈(spinc〇ating) 介電材料(BCB、Π等)或是貼合方式形成。 綜上所述,本發明之無電鍍形成鎳/銅(Ni/Cu)或鎳/金 (Ni/Au)凸塊之製程•至少具有下列優點: ⑴習知以異方性導電膜(acf)方式應用在lcd、ic 及麵元件(RF)封裝時,金屬凸塊需具備2〇//m以上之高 度;然而’若以無電鍍方式形軸凸制無法達到此厚度的 品質要求,且-般即使快速無電鍍速率亦只有4 μπι/ίΐΓ,在厚 度太高時其披覆效果亦不佳。本發明之無電鍍形成鎳/銅 (Ni/Cu)雙層凸塊可兼顧電性及高雜性需求而輕易完成高 厚度之金屬凸塊製寧。 ⑵-Ί又射頻元件之導電多集中在表面處,以本發明無 9 488052 經濟部智慧財產局S工消費合作社印製 A7 B7 五、發明説明(,) ~ 弘槪/成决速开v成金屬凸塊(Ni),在於其外圍無電鍵上良好 導電性之外圍金屬層(Cu)或金(Au),如此結合外圍金屬 層之良好$電4寸性及射頻元件的表面特性(咖偷以即多數 電流傳⑽發生於金屬凸塊之外圍金屬層)。如此達到以無電 錢方式應用於射頻元件封裝。 (3)本發明可簡傾/銅凸塊之製程,且製造成本相對降 低·因本發明主要以無電鑛方式形成鎳/銅⑽⑻凸塊之 製程的技術,可進行批次生產,於單一設備中大量處理產品,· 且不需昂貴的設備,製造成本也可大幅減少。 ,⑷本發明銲墊可卿導線層再透過金屬凸塊與外界相 導通,如此不論是作位置變更或電性檢測等,均可依實際需 求作不同之佈線設計,達到良好功效。 綜上所述,本發明實施之具體性,誠已符合專利法中所 規定之發明專利要件,謹請f審查委員惠予審視,並賜准 專利為禱。 以上所述係利用一較佳實施例詳細說明本發明,而非限 制本發明之範圍,而且熟知此類技藝人士皆能明瞭,適當而 作些微的改變及調整,仍將不失本發明之要義所在,亦二脫 離本發明之精神和範圍。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) (請先閱讀背面之注意事項再填寫本頁)
Claims (1)
- '申請專利, 2. 3. 經濟部智慧財產局員工消費合作社印製 4· 5. 種無電锻形成兩層以上金屬凸塊之製程,係包括有下 列步驟: 提供一設有若干銲墊(pad)之基板,各該銲墊之周 圍並覆有一保護層(passive layer); ()形成一光阻圖案,該光阻圖案並裸露出各該銲墊;)對各该#墊表面進行活化(activation)以產生活化 劑(activator); ⑷以無電鍍(dectr〇less plating)方式形成一預定厚度 之内層金屬凸塊(bump)於該銲墊之上; (e)移除該光阻圖案; ()以無甩錢方式形成一外圍金屬層完全包覆住該金屬凸 塊外圍。 如申請專利範圍第1項所述之無電鍍形成兩層以上金屬 鬼之‘私,其中所述之銲墊係可為銅銲墊或錦銲墊其 中一種。 如申請專利範圍第1項所述之無紐形成兩層以上金屬 凸塊之製程,其中所述之光阻圖案之厚度在15_以上。 如申請專利範圍第1項所述之無電鑛形成兩層以上金屬 凸塊之製程’其中所述步驟⑻之後可包括—步驟⑽: 對所述銲墊表面進行清潔動作。 如申明專利範圍第2項所述之無電鑛形成兩層以上金屬 ,塊之製程,其中所述銅銲墊之活化劑係可為金屬種 曰曰(Pd seed ),所述紹銲墊之活化劑係可為金屬鋅種晶(办 娜尺度適用中國 ^--\----ίί^------- (請先閱讀背面之注意事項再填寫本頁) 訂 I A8 B8 C8 申請專利^----- seed )。 如申π專利範圍第丨項所述之無電鍍形成兩層以上金屬 ^塊之製程,其中所述内層金屬凸塊係可為鎳材質,其 局度在15〜2〇iLlm之間。 7 申叫專利乾圍弟1項所述之無電鑛形成兩層以上金屬 凸塊之製程,其中所述外圍金屬層係為金屬銅層或金 (Au )層。 8_ ^申請專利範圍第卜6或7項所述之無電卿成兩層以上 金屬凸塊之製程,其中所述内層金屬凸塊之高度加上外 圍金屬層之厚度總共至少在18 μιη以上。 • 種無電鍍形成兩層以上金屬凸塊之製程,係包括有下 列步驟: (a) 设上一第一介電層於設有若干銲墊(pad)之晶片上, 以定義出重分佈(redistribution)路線; (b) 以表面粗化及活化處理以使用無電鍍方式在該重分 佈路線中沈積導線層·; (〇形成一光阻圖案,該光阻圖案並裸露出若干預設位 置; 咬 (d) 對各該預設位置處表面進行活化(activati〇n)以產 生活化劑(activator); (e) 以無電鍍(electroless plating)方式形成一預定厚声 之金屬凸塊(bump)於該預設位置上; (f) 移除該光阻圖案; (g) 覆上一第二介電層,該第二介電層並設有尺寸較金 .--:----.ΙΛ--4.---- (請先閱讀背面之注意事項再填寫本頁} 、一一a. b 經濟部智慧財產局員工消費合作社印製 12 H-OOUJZ 經濟f f 、申請專利範圍 屬凸塊略大之開π ’以裸露出該金屬凸塊; ::方式形成-外圍金屬層完全包覆住該金屬 j 項所述之無電娜成兩層以上全屬 :=:r—周圍並可覆有 11· t申料利範圍第9項所述之無電細彡成兩層以上 勺2衣私’其中所述之步驟(a)與步驟(b)之間更可 匕括-步驟:形成-介電層覆在該銲墊周圍。 σ 2. 、:广之峨形成兩層以 鮮塾私,其中所述之鲜塾係可為·塾或銘 13.青翻範圍第9項所述之無電鑛形成兩 中所述步驟⑷之後可包括—步驟(dt) 子所述銲墊表面進行清潔動作。 14.21’Γ範圍第13項所述之無_成兩層以上金屬 鬼之衣輊,其中所述對所述銲墊 10%硫酸(财〇4)進行之。 月f、動作係可以 15.==ΓΓ2項所述之無電鍍形成兩層以上金屬 曰⑻衣Η 述銅輝塾之活化劑係可為金屬種 =)。㈣)’所述鱗墊之活化劑係可為金屬鋅種晶(办 替 訂---------線#1 f請先閱讀背面之注意事項再填寫本頁) 16.=請=範圍第9項所述之無魏形成兩相上金屬 ▲之衣知’其中所述金屬凸塊係可為鎳材質,其高度本紙 S)A4規格X 297公爱 甲請專利範圍 在15 μηι以上。 17' (Au)層、中所述外圍金屬層係為金屬銅層或金 18.如申請專利範圍第9、16或1?項所述之無電鑛形成兩層以 上金屬凸塊之f程’其巾職金屬凸塊之高度加上外圍 金屬層之厚度總共需大於該第二介電層厚度至少在18 μπι以上。 111.]!#! (請先閱讀背面之注意事項再填寫本頁) 、1Τ 經濟部智慧財產局員工消費合作社印製 14 本紙張尺度適用中國國家樣準(Cns ) Α4規格(210 X 297公董)
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TW090111669A TW488052B (en) | 2001-05-16 | 2001-05-16 | Manufacture process of bumps of double layers or more |
US09/887,074 US6653235B2 (en) | 2001-05-16 | 2001-06-25 | Fabricating process for forming multi-layered metal bumps by electroless plating |
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TW090111669A TW488052B (en) | 2001-05-16 | 2001-05-16 | Manufacture process of bumps of double layers or more |
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Cited By (2)
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US7312142B2 (en) | 2005-04-13 | 2007-12-25 | Mutual Pak Technology Co., Ltd. | Method for making cable with a conductive bump array, and method for connecting the cable to a task object |
US9478512B2 (en) | 2015-02-11 | 2016-10-25 | Dawning Leading Technology Inc. | Semiconductor packaging structure having stacked seed layers |
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KR20070023140A (ko) * | 2005-08-23 | 2007-02-28 | 엘지전자 주식회사 | 유전체 디스펜싱 장치 및 이를 이용한 플라즈마 디스플레이패널의 제조방법 |
JP4379413B2 (ja) * | 2005-12-06 | 2009-12-09 | セイコーエプソン株式会社 | 電子部品、電子部品の製造方法、回路基板及び電子機器 |
DE102006028811A1 (de) * | 2006-06-21 | 2007-12-27 | Qimonda Ag | Verfahren zum Aufbringen von Lot auf Umverdrahtungsleitungen |
WO2008007327A2 (en) * | 2006-07-10 | 2008-01-17 | Nxp B.V. | Integrated circuit, transponder, method of producing an integrated circuit and method of producing a transponder |
US20090233436A1 (en) * | 2008-03-12 | 2009-09-17 | Stats Chippac, Ltd. | Semiconductor Device Having High-Density Interconnect Array with Core Pillars Formed With OSP Coating |
TW200941666A (en) * | 2008-03-19 | 2009-10-01 | Chipmos Technologies Inc | Conductive structure of a chip and method for manufacturing the same |
US8841782B2 (en) * | 2008-08-14 | 2014-09-23 | Stats Chippac Ltd. | Integrated circuit package system with mold gate |
DE102008042107A1 (de) * | 2008-09-15 | 2010-03-18 | Robert Bosch Gmbh | Elektronisches Bauteil sowie Verfahren zu seiner Herstellung |
TWM397591U (en) * | 2010-04-22 | 2011-02-01 | Mao Bang Electronic Co Ltd | Bumping structure |
US8435881B2 (en) | 2011-06-23 | 2013-05-07 | STAT ChipPAC, Ltd. | Semiconductor device and method of forming protective coating over interconnect structure to inhibit surface oxidation |
WO2013067659A1 (zh) * | 2011-11-11 | 2013-05-16 | Chu Tse-Ming | 晶圆焊垫的凸块结构及其制造方法 |
WO2015030670A1 (en) * | 2013-08-28 | 2015-03-05 | Institute Of Technical Education | Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device |
TWI572257B (zh) * | 2015-10-19 | 2017-02-21 | 欣興電子股份有限公司 | 柱狀結構及其製作方法 |
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US5172473A (en) * | 1990-05-07 | 1992-12-22 | International Business Machines Corporation | Method of making cone electrical contact |
US6320263B1 (en) * | 1999-02-18 | 2001-11-20 | Advanced Micro Devices, Inc. | Semiconductor metalization barrier and manufacturing method therefor |
-
2001
- 2001-05-16 TW TW090111669A patent/TW488052B/zh not_active IP Right Cessation
- 2001-06-25 US US09/887,074 patent/US6653235B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7312142B2 (en) | 2005-04-13 | 2007-12-25 | Mutual Pak Technology Co., Ltd. | Method for making cable with a conductive bump array, and method for connecting the cable to a task object |
US7999191B2 (en) | 2005-04-13 | 2011-08-16 | Mutual Pak Technology Co., Ltd. | Method for making cable with a conductive bump array, and method for connecting the cable to a task object |
US9478512B2 (en) | 2015-02-11 | 2016-10-25 | Dawning Leading Technology Inc. | Semiconductor packaging structure having stacked seed layers |
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US6653235B2 (en) | 2003-11-25 |
US20020173073A1 (en) | 2002-11-21 |
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