TW486855B

TW486855B - Method and device for controlling the acceleration and deceleration of pulse command

Info

Publication number: TW486855B
Application number: TW89120711A
Authority: TW
Inventors: Chin-Yu Chao; Kan-Lin Chou
Original assignee: Ind Tech Res Inst
Priority date: 2000-10-05
Filing date: 2000-10-05
Publication date: 2002-05-11

Abstract

This invention is a control method and device of acceleration/deceleration under the pulse signal, including a displacement buffer, an upper-and-lower counter, a digital differential analyzer (DAD) circuit. By inputting a constant velocity pulse signal into that displacement buffer, and summing the total number of pulses in that buffer by that upper-and-lower counter, through the output frequency of the above-mentioned digital differential analyzer being proportional to the total number of the pulses of that upper-and-lower counter; thus by inputting a uniform pulse, the pulse output may be transformed to one having equivalent counts and a acceleration and deceleration pattern, thereby the control of acceleration and deceleration motion of the motor may be completed.

Description

案號 89 j 207" 五、發明說明（〗）、本發明係為—種脈衝指尤指一種藉由脈衝指令控，速控制方法與裝置，。制馬違加减速運動的方法與裝置針對一般步進馬達哎^ 析器（DDA ·· D…Tm’可使用-數位微分分 AL ANAL YZER) f I FFERENT j 動，電路可以產生等時間間二脈==制其運 ’馬達運動方式為一等速運動進=或司服馬達時 ’此運動方式在馬達啟動與停；u圖所示）生很大的振動。為改善此項缺失，心：運動而產止時加入-加速與減速的程序:會，馬達啟動與停第1-2圖所示），來改善振動現=用：線型加減速（如至等速或等速至減速之轉換時因且=此種方式在加速不連續馬達在運轉過程中仍會有線的斜率變化產生。因此在控制馬達運動上為求复；j = R κ)現象 ◦OTH)，則有S型加減速（：第，轉二為平滑（SM 的產生，由於其加減速曲線具連續十3圖所示）方式動與停止時的振動降低到最小。以可以將馬達啟知方達運轉並使其產生加減速曲線運動，習如第2圖所示），即依照加) ’（卜3圖所示），設計一加減如第1-2、 3逐格存放於該表内。在加速階段1將脈衝間隔時間數值加減速表2的第一格取出一數值，，運動控制程式從該 486855 曰修正案號 891207η 五、發明說明（2) 出時脈（C L·〇c K ) 5驅動之計數器6内門數至零時，提出—中斷要求7送至一始=倒器8執行中斷服務程式，送出-輪出脈衝‘然減速表2取出下一格的數值放至計數哭: 4 0 ，藉此逐漸縮小每次輸出脈衝9 ; 〖:人，行倒數當速度m以相等之脈衝間隔時間數值3】匕 Θ内，並以相等時間間距送出脈衝使 σ :在減速階段•，則依照上述加= 放至計數器㈠，倒數至零時，送出—輸出脈衝=取= 逐漸延長母次輸出脈衝9之間隔時間，使馬達停止。此種方式要點在於加速、減速時的脈衝間隔時間數值mi卜而其主要缺點在於，依表進行減速的時機必須辜捏=二否則會造成過早或過晚送出減速脈衝，使得馬達減速後停止位置錯誤，θ此在馬達加速及等速進行的同時’必須時刻以程式檢查減速時機，在適當時間開始增加輸出脈衝9送出之間隔時間使馬達開始進行減速，以確使馬達依表減速後停止的位置正確無誤，如果沒有進行此檢查工作，而發生上述過晚送出減速脈衝的情況，將使輸出之脈衝數目超過原先設計之脈衝總數，為改善此情形，有時會以強制停止的方式來使馬達停止於正確位置，如此將使得減速圖樣錯誤，而且造成馬達振動的產生；再者，在應用於步進或伺服馬達二軸同動情形時，由於使用同一加減速表2，加減速斜率固定，較慢速之軸加減速時間較短，較快速之軸加減速時間較長，二軸之加減速動作無法同時f成，因此若二軸非等速，在加速及減速階段將 — ___V Ι.·1ΙΡ.>Ι> JMl _ __ 第5頁 MM 89120711五、發明說明（3) 無法依照規劃的直線間隔時間數值3之讀電腦的軟體運算，亦麦是，本發明之免缺失的存在，本發知到一具有加減速曲之停止位置正確而無再者，本發明的 ’因其加減速時間可加減速動作為同時完劃之直線運動軌跡。又’本發明的另算工作，構件單純並構造之裝置將輸出之降低馬達運轉的振動為達上述之目的等速脈衝指令輸入一計數器計算上述移位一加法器累加其數值精此輸入等速脈衝方一加減速圖樣之脈衝之位元數目與比較器算具加減速曲線圖樣有關本創作之詳明如下：曰路徑行取與減耗費相主要目明係以線圖樣須檢查次要目 s又疋一成，如走；又，速時機檢當的處理的，在於輸入一等的脈衝輸何時得開的，在應樣，所以此二軸之此類加逮與查工作通常器8運算資解決上述之速脈衝之方出結果始減速。用於二車由同在馬達運轉運轉可以完減速脈衝是利用微源。缺失，避式，便能達減速後動情形時時各軸之全依循規一目的，在於無郎省成本。而且脈衝之加減速曲 ’本發先進先暫存器 ’經由式將之輪出。内存之之脈衝細說明明所運用出之移位内部暫存一比較器轉換成為整個過程數值，而輸出。及技術内須使用處理器進行運可以串聯複數個相同線修飾的更為平滑，之裝置及方法係將— 暫存器，再以一上下之脈衝總數，並透過判斷是否輸出脈衝，相等脈衝數目且具有僅需控制移位暫存器不需以微電腦軟體運容，現就配合圖式說Case No. 89 j 207 " V. Description of the invention (〗) The present invention is a kind of pulse finger, especially a method and device for speed control by pulse command. The method and device for restraining the horse from accelerating and decelerating movements are aimed at ordinary stepping motors. ^ Analytical devices (DDA ·· D… Tm 'can be used-Digital Differential AL ANAL YZER) f I FFERENT j, the circuit can generate two Pulse == control its operation 'Motor movement mode is a constant speed movement = or when the motor is serviced' This movement mode starts and stops at the motor; u picture shows) generates a lot of vibration. In order to improve this defect, the mind: add the program of acceleration and deceleration during the production and end of the exercise: Yes, the motor starts and stops as shown in Figure 1-2) to improve the vibration. Now use: linear acceleration and deceleration (such as to When the conversion from speed or constant speed to deceleration is caused by and = this way, there will still be a change in the slope of the line during the acceleration of the discontinuous motor during operation. Therefore, it is necessary to control the movement of the motor; j = R κ) phenomenon ◦ OTH ), There are S-type acceleration and deceleration (: the first, the second turn is smooth (the generation of SM, because its acceleration and deceleration curve is shown continuously in Figure 13)) to reduce the vibration when running and stopping to a minimum. In order to start the motor Know that Fonda is running and make it generate acceleration and deceleration curve movements, as shown in Figure 2), that is, according to the acceleration) '(shown in Figure 3), design a plus and minus and store it in the grid one by one as shown in Figures 1-2 and 3. Table. In the acceleration phase 1, the value of the first division of the pulse interval time acceleration and deceleration table 2 is taken out, and the motion control program is from the 486855 amendment number 891207η. 5. Description of the invention (2) Clock (CL · 〇c K) When the number of internal gates driven by the counter 5 reaches zero, a request is made—an interrupt request 7 is sent to the beginning = the inverter 8 executes the interrupt service routine, and a send-round pulse is sent. : 4 0 to gradually reduce the output pulse 9 each time; 〖: person, line countdown when the speed m is equal to the value of the pulse interval time 3] within Θ, and send pulses at equal time intervals to make σ: during the deceleration phase • , According to the above add = put to the counter ㈠, when the countdown reaches zero, send out-output pulse = take = gradually increase the interval between the mother and the secondary output pulse 9 to stop the motor. The main point of this method is the value of the pulse interval time mi during acceleration and deceleration. The main disadvantage is that the timing of deceleration according to the table must be pinched = 2. Otherwise, it will cause the deceleration pulse to be sent too early or too late, and the motor will stop after deceleration. Position error. Θ While the motor is accelerating and performing at the same speed, 'it must always check the deceleration timing in a program, and start to increase the output pulse 9 at an appropriate time to start the deceleration of the motor to ensure that the motor decelerates according to the table and stops. The correct position is correct. If this check is not performed and the above-mentioned situation of sending deceleration pulses too late will cause the number of output pulses to exceed the total number of originally designed pulses. In order to improve this situation, sometimes it will be forced to stop. Stopping the motor at the correct position will cause the deceleration pattern to be wrong and cause the vibration of the motor. Furthermore, when it is used in the case of stepping or servo motor two-axis simultaneous movement, the same acceleration and deceleration table 2 is used, and the acceleration and deceleration slopes are the same. Fixed, slower axis acceleration and deceleration time is shorter, faster axis acceleration and deceleration time is shorter The acceleration and deceleration of the two axes cannot be achieved at the same time, so if the two axes are not constant speed, during the acceleration and deceleration phases will be — ___V Ι. · 1ΙΡ. &Gt; Ι > JMl _ __ Page 5 MM 89120711 V. Description of the invention ( 3) It is impossible to read the software calculation of the computer according to the planned linear interval value of 3, which is the absence of the present invention. The present invention found that a stop position with acceleration and deceleration is correct and no more. The present invention Because of its acceleration and deceleration time, the acceleration and deceleration action can be a linear motion trajectory completed simultaneously. Also, according to another calculation of the present invention, the device having a simple structure is used to reduce the output of the motor. The constant-speed pulse command is input to a counter to calculate the above-mentioned shift, and the adder accumulates the value. The number of bits of the pulse square one acceleration and deceleration pattern and the comparator calculation tool acceleration and deceleration curve pattern are detailed as follows: The main purpose of the path selection and consumption reduction is to use the line pattern to check the secondary objective s. Yiyicheng, such as walking; also, the processing of the prompt timing check is based on when the first-level pulse input is opened, and the application is in progress, so this kind of capture and check of the two axes usually requires 8 computing resources. The solution to the above-mentioned speed pulse results in deceleration. For two cars running by the same motor, the deceleration pulse can be completed by using a micro source. In the absence of avoidance, you can achieve the deceleration and post-movement situation. The purpose of all axes is to comply with regulations. The goal is to save costs. And the acceleration and deceleration of the pulse ‘the first register of the present’ is rotated out through the formula. The pulse of the memory is explained in detail. The shift used is internally temporarily stored by a comparator and converted into the value of the entire process and output. In the technology, a processor must be used for operation. A plurality of identical lines can be connected in series to make it smoother. The device and method are-a register, then the total number of pulses up and down, and by determining whether to output pulses, the number of equal pulses And it only needs to control the shift register and does not need to use microcomputer software to carry capacity.

第6頁 486855 __案號89120711_年月曰修正_ 圖式簡單說明【圖式之簡單說明】第1 — 1圖，係典型控制馬達運動等速圖樣之示意圖。第1 一 2圖，係典型控制馬達運動線型加減速圖樣之示意圖。第1 一 3圖，係典型控制馬達運動S型加減速圖樣之示意圖。第2圖，係習知之脈衝指令加減速處理方法示意圖。第3圖，係本發明之脈衝指令加減速處理裝置示意圖。第4圖，係本發明之脈衝指令加減速處理方法流程圖。第5 — 1圖，係本發明之實施例示意圖。第5 — 2圖，係本發明之實施例結果示意圖。第5 — 3圖，係本發明實施例之等速脈衝輸入示意圖。第5 — 4圖，係本發明實施例之線型加減速脈衝輸出示意圖。第5 — 5圖，係本發明實施例之S型加減速脈衝輸出示意圖。第6圖，係以單晶片與R A Μ達成本發明之架構流程圖。請參閱『第3圖』所示，係本發明之脈衝指令加減速處理裝置示意圖，如圖所示：每次時脈電路4送出一個時脈5時，輸入脈衝1 0 —方面移入具有複數個位元數1 1 的移位暫存器1 2 (假設其位元個數為X )，到上下計數器1 3處做往上計數1 4 ，另一方面脈衝移出移位暫存器 1 2時，則到上下計數器1 3處做往下計數1 5 ，該上下計數器1 3内數值即為移位暫存器1 2内部暫存之脈衝總數（假設該脈衝總數為C );接下來使用一數位微分分析Page 6 486855 __Case No. 89120711_ Year Month Revision _ Brief Description of the Drawings [Simplified Description of the Drawings] Figures 1-1 are schematic diagrams of a typical control motor motion isokinetic pattern. Figures 1 to 2 are schematic diagrams of the linear acceleration / deceleration pattern of a typical control motor movement. Figures 1 to 3 are schematic diagrams of typical S-type acceleration and deceleration patterns for controlling motor movement. Figure 2 is a schematic diagram of a conventional pulse command acceleration / deceleration processing method. FIG. 3 is a schematic diagram of a pulse instruction acceleration / deceleration processing device of the present invention. FIG. 4 is a flowchart of a pulse instruction acceleration / deceleration processing method of the present invention. Figures 5-1 are schematic diagrams of the embodiment of the present invention. Figures 5-2 are schematic diagrams of the results of the embodiment of the present invention. Figures 5 to 3 are schematic diagrams of a constant velocity pulse input according to an embodiment of the present invention. Figures 5 to 4 are schematic diagrams of linear acceleration / deceleration pulse output according to the embodiment of the present invention. Figures 5-5 are schematic diagrams of S-type acceleration / deceleration pulse output according to the embodiment of the present invention. Figure 6 is a flow chart of the architecture of the invention with a single chip and RAM. Please refer to the "Figure 3", which is a schematic diagram of the pulse instruction acceleration and deceleration processing device of the present invention, as shown in the figure: each time the clock circuit 4 sends out a clock 5, the input pulse 1 0-there are multiple The shift register 1 2 with the number of bits 1 1 (assuming that the number of bits is X), counts up to the up and down counters 1 and 14 and the pulse is shifted out of the shift register 12 , Then go to the up and down counter 13 to count down 1 5, the value in the up and down counter 13 is the total number of pulses temporarily stored in the shift register 12 (assuming that the total number of pulses is C); next use a Digital Differential Analysis

486855 _案號 891207Π_年月日__ 圖式簡單說明器1 6 (DDA)電路送出頻率與上下計數器1 3内數值成正比例的輸出脈衝9 ;該電路含一加法器1 7、一比較器1 8 ，其作用如下：上述之上下計數器1 3的數值輸入加法器1 7進行累加（假設累加值為A，即A = A + C ) ，然後到比較器1 8與上述之X值比較，若A - X，則送出一個輸出脈衝9 ，且A值減去X值後存回加法器1 7 ; 若A<X，則不輸出脈衝，且A值不變。整體觀之，上述之脈衝輸入本發明之方法與裝置後，由比較器1 8判斷後輸出之脈衝，為一具有加減速圖樣之脈衝輸出。486855 _Case No. 891207Π_ 年月日 __ Schematic description device 16 (DDA) circuit sends output pulse 9 whose frequency is proportional to the value in up and down counter 1 3; the circuit contains an adder 1 7 and a comparator 18, its role is as follows: the numerical input of the up-down counter 13 above the adder 17 for accumulation (assuming the accumulation value is A, that is A = A + C), and then to the comparator 18 to compare with the above X value, If A-X, an output pulse 9 is sent, and the value of A is subtracted from the value of X and stored back to the adder 17; if A < X, no pulse is output and the value of A is unchanged. As a whole, after the above-mentioned pulses are input into the method and device of the present invention, the pulses output after being judged by the comparator 18 are a pulse output with an acceleration / deceleration pattern.

請參閱『第4圖』所示，係本發明之脈衝指令加減速處理方法流程圖，如圖所示：每個時脈5動作時依流程運轉一次，在步驟S 1内判斷是否有輸入脈衝9進入，如果有，則進入步驟S 2 ，以π 1 π移入具有複數個位元（假設該位元數11之數目為X)的先進先出之移位暫存器12 ，如果沒有，則進入步驟S 3，以” Ο π移入上述移位暫存器1 2 ;進行至步驟S 4時，以上下計數器1 3計算上述移位暫存器1 2内脈衝總數，若有脈衝移入該移位暫存器 1 2 ，則上下計數器1 3往上數加一，若有脈衝移出該移Please refer to the "Figure 4", which is a flowchart of the pulse instruction acceleration and deceleration processing method of the present invention, as shown in the figure: each clock 5 operates once in accordance with the flow, and determines whether there is an input pulse in step S1 9 is entered, if there is, then it proceeds to step S 2, and shifted into FIFO 1 with a plurality of bits (assuming that the number of bits 11 is X) by π 1 π. If not, then Go to step S 3 and move into the above-mentioned shift register 1 2 with “Ο π; when proceeding to step S 4, the up-down counter 13 calculates the total number of pulses in the above-mentioned shift register 12. Bit register 1 2, the up-down counter 1 3 counts up by one, if there is a pulse shifted out of the shift register

位暫存器1 2 ，則上下計數器1 3往下數減一；接著進入步驟S 5 ，以加法器1 7累加步驟S 4中計算之脈衝總數值；再進入步驟S 6 ，將此加法器1 7累加數值與比較器 1 8的内存數值X作一比較（此内存數值X設定成與上述移位暫存器1 2之位元數1 1相同），判斷累加之脈衝總數是否大於等於X，如果是，則進入步驟S 7 ，送出一個脈衝，並將該加法器1 7内累加之脈衝總數減去X，存回Bit register 1 2, then the down counter 1 3 counts down by one; then proceed to step S 5 to accumulate the total number of pulses calculated in step S 4 with adder 17; and then proceed to step S 6 to add this adder 1 7 The accumulated value is compared with the memory value X of the comparator 18 (this memory value X is set to be the same as the number of bits 1 1 of the above-mentioned shift register 12) to determine whether the total number of accumulated pulses is greater than or equal to X If yes, go to step S7, send a pulse, and subtract X from the total number of pulses accumulated in the adder 17 and store it back

第8頁圖式簡單說明 =法态1 7内，如果否，則進入步驟s 8 ，不輸出脈衝，二】流程在一個時脈1動作完成；如此再回到步驟s 1 ，繼續進行步驟S 1〜S 8。明參閱『第5〜1圖』所示，係本發明之實施例示意二屮t圖所示··將一等速脈衝1 9輸入本發明之裝置，則二入1一線型加減速脈衝2 〇 ;將該線型加滅速脈衝2 〇輸ί:明之裝置，則輸出為- S型加減速脈衝2 i。睛參閱『第 +咅同/ ， 2圖』所示，係本發明之實施例結果不思團，如圖所干 · — 丘？只加V ^ ^·本貫施例以8個時脈輪入一個脈衝、第一組事ί之二i i例，設有二組本發明之加減速裝置，設計為ίΠ::Γ%器12 (圖中未示）之位元數11 時間，第二組穿署即加速、減速時間為ί 2 8個時脈數設計為6 4個位^移:立暫存器丄、2 (圖中未示）之位元間，如圖，等速脈徐Ρ加速、減速時間為6 4個時脈時 7，並與第二經過上下計數器"與加法器1 8 (圖中未示）比置之内存值為1 2 8的比較器1 加減速脈衝2 〇 ;再骑L其知出之脈衝整體觀之即為線型速處理裝置的輪入，經：線型加減速輸出作為下一組加減並與第二組力”咸速裝置"與加法器i 7，其輸出結果整體觀之 J 4的比較器比較後，裝置之加诘r + 馬S t加减速脈衝時脈。4(或減逮）時間即為12“62:」== 請參閱『第5〜『 1 圖』所示，係本發明實“之等】脈奶 6855 ——89120711 圖式簡單說明 --±__n a 施例之線型加減速脈衝輪屮—立脈衝輸出示意圖，如圖出不忍圖及實施例之S型加減速輪入一個脈衝、丘9 v示本實施例以前述之8個時脈之加減速裝置，第一 ^脈衝輸入為例，設有二組本發明 )之位元數X丄設計為 '"置之移位暫存器1 2 (圖中未示為1 2 8個時脈（°c τ'、、n 2 8個位元，即加速、減速時間暫存器1 2 (圖中未示）C κ )時間，第二組裝置之移位加速、減速時間為6 :個數設計為6 4個位元，即出等速脈衝輪入（如二、日、間:如圖，由圖形中可看衝輪出（如第5 一 4圖 :3圖所示）轉成線型加減速脈輪出作為下—紐，诸$ f不）之結果，與將此線型加減速脈衝輪*(如第Γί，裝s的輸心轉“型加減速請參m圖所示：之結果。 :明之架構流程圖，：：：干係：：：片與：A Μ達成本由隨機記憶體R A Μ 2 ? 女則述之移位暫存器1 2可數目為X )來件卷，5 2 (有複數個位址2 4 ，假設其來替代，而該上下許^ ^動位兀之動作藉由移動位址指標可由程式軟體來取代·=二3二加，器1 7與比較器χ 8 s 9内判斷是^:古終，σ圖，母個時脈5動作時，在步驟 S10=有輸^脈衝9進人，如果有，則進入步驟 1，設定輸：：ί ϊ ί於1 ;如果沒有’則進入步驟s 1 數參數2 3请本ί 〇，接著進行至步驟s 1 2 ，以一計 2 4 處，再Brief description of the diagram on page 8 = Normal state 17; if not, go to step s8, no pulse is output. Second] The process is completed in a clock 1; so go back to step s1 and continue to step S 1 ~ S 8. Refer to "Figures 5 to 1", which is an example of the embodiment of the present invention, as shown in the second figure t. Input a constant velocity pulse 1 9 into the device of the present invention, then enter 2 linear acceleration and deceleration pulse 2 〇; If the linear acceleration / deceleration pulse 2 is inputted 〇: Ming device, the output is-S-type acceleration and deceleration pulse 2 i. Please refer to the "Figure + Same / / 2", which is the result of the embodiment of the present invention. Add only V ^ ^ The present embodiment takes one pulse from 8 chakras, the second one is the second one, and two sets of acceleration and deceleration devices of the present invention are provided, which are designed as Π :: Γ% 器 12 (Not shown in the figure) the number of bits is 11 time, the second group wears the acceleration and deceleration time is ί 2 8 clocks are designed to be 6 4 bits ^ shift: standing register 丄, 2 (in the figure (Not shown), as shown in the figure, the isokinetic pulse P accelerates and decelerates time is 6 4 clock hours 7, and is compared with the second passing up-down counter " and the adder 1 8 (not shown). The comparator 1 with the memory value set to 1 2 8 is the acceleration / deceleration pulse 2 〇; then the overall view of the pulse that L knows is the turn of the linear speed processing device, and the linear acceleration / deceleration output is used as the next group of acceleration and deceleration. And compared with the second set of force "salt speed device" and the adder i 7, the output of the overall view of the J 4 comparator, the device plus 诘 r + horse S t acceleration and deceleration pulse clock. 4 (or Minus arrest) time is 12 "62:" == Please refer to the "5th ~" 1 figure ", which is the" equivalent "of the present invention] pulse milk 6855 ——89120711 simple illustration of the diagram-± __n a Case line Type acceleration / deceleration pulse wheel 屮-vertical pulse output diagram, as shown in the figure and the example of the S-type acceleration and deceleration wheel into a pulse, mound 9 v shows this embodiment with the aforementioned eight clocks acceleration and deceleration device, the A pulse input is taken as an example, and two sets of the present invention are provided. The bit number X 丄 is designed as a shift register 1 2 (not shown in the figure as 1 2 8 clocks (° c τ ',, n 2 8 bits, that is, acceleration and deceleration time register 1 2 (not shown in the figure) C κ) time, the shift acceleration and deceleration time of the second group of devices is 6: the number is designed to be 6 4 bits, that is, a constant-speed pulse turns in (such as two, day, and between: as shown in the figure, the impulse wheel can be seen in the figure (as shown in Figures 5 to 4: 3)) into linear acceleration and deceleration pulses Turn-out is the result of the next-new button, and the $ f is not), and the linear acceleration and deceleration pulse wheel * (such as Γί, the ins and outs of the "s" type acceleration and deceleration, please refer to the figure m: the result .: The flow chart of Ming's architecture, ::: related ::: and: A Μ 由 The cost is determined by the random memory RA Μ 2? The shift register 1 2 described by the female can be a volume, 5 2 ( There are multiple addresses 2 4, which is assumed to replace, and the vertically movable ^ ^ Xu Wu bits of the address pointer can be moved by operation of software programs to substituted-3 = two plus two, and the comparator 17 is χ 8 s 9 ^ is determined : Ancient end, σ diagram, when the mother clock 5 moves, in step S10 = there is an input ^ pulse 9 to enter the person, if there is, then go to step 1, set to lose :: ϊ ϊ ί at 1; if not 'then enter Step s 1 count the number of parameters 2 3 and then proceed to step s 1 2 to a total of 2 4 places, and then

RAM22i®^fAM22 (前述之移位暫存器12由輸入值（2T η目前位址24所存之值，並加上上述入），然後;字於’枯5表無脈衝輸入’ 1代表-個脈衝輪 486855 年RAM22i® ^ fAM22 (the above-mentioned shift register 12 is composed of input values (the value stored in the current address 24 of 2T η, plus the above input), and then; the word in 'Dry 5 table without pulse input' 1 represents one Pulse wheel 486855

位址累號 89120711Address Cumulative 89120711

即將指標指向下 _ &，、 ;在步驟s 1 3中判斷位址2 4 B不然後進入步驟之位址總數X，如果是，則進入步驟S 大於等於上述 4減去X，即將指標重新指向起始位址，=，將該位址2 5 ;如果否，則直接進入步驟s 1 5 ; f進入步驟s工上述之計數參數2 3之值累加到加法表驟S 1 5中對行步驟S 1 6 ’判斷該加法參數2 5内=2 5 β，然後進位址總數X，如果是，則進入步驟s 值是否大於等於 =力:法參數2 5内數值減去位址總數；出-個脈衝，數2 5内，如果否，則進入步驟s丄 Χ，存回加法參此再回到步驟S 9，等下拓不輪出脈衝；如 9〜s 1 8。生再繼續進行步驟S 圖式簡單說明將位址2 4加 S 1 ：正體觀之，前述之移位暫存器丄制馬達加速（或減速）㈣間，^位元數目即可控段之脈衝間隔時間即為輸入之等速：上之脈衝，其等速階之脈衝為-冑速脈衝1 9，則經本::間隔時㈤；若輸入後輸出為一線型加減迷脈衝2 〇本—^之方法與裝置處理加減速脈衝2 〇，則經本發明之方=輸入之脈衝為一線型一 S型加減速脈衝2 2 。 ’與裝置處理後輸出為惟以上所述者，僅為本發明之 —> 能以之限定本發明實施之r 鬏佳貫轭例而已，當不範圍所作之均圍：：大凡依本發明申請專利範圍内。化，、G飾，白應仍屬本發明專利涵蓋之【圖式之符號說明】加減速表······ 9 ^ ,, 乙脈衝間隔時間數值·.· 3That is, the indicator points downwards _ &,;; In step s 1 3, it is judged that the address 2 4 B does not then enter the total number of addresses in the step X. If it is, then enter step S is greater than or equal to the above 4 minus X, that is, the indicator is restarted. Point to the starting address, =, the address 2 5; if not, go directly to step s 1 5; f go to step s and add the value of the above counting parameter 2 3 to the addition table in step S 1 5 Step S 1 6 'Judge the addition parameter 2 5 = 2 5 β, and then enter the total number of addresses X, if yes, then go to step s whether the value is greater than or equal to = force: value within the method parameter 2 5 minus the total number of addresses; -A pulse, within the number of 25, if not, go to step s × X, save the addition parameters and then return to step S 9, wait for the extension to not rotate the pulse; such as 9 ~ s 1 8. The student then proceeds to step S. The diagram briefly explains the address 2 4 plus S 1: From the perspective of the body, the aforementioned shift register controls the motor to accelerate (or decelerate) for a while, and the number of bits can control the segment. The pulse interval time is the constant velocity of the input: the pulse of the constant velocity step is-胄 speed pulse 1 9, then through the :: interval time; if input, the output is a linear plus and minus pulse 2 〇 this — The method and device for processing the acceleration and deceleration pulse 2 0, then the method of the present invention = the input pulse is a linear S-type acceleration and deceleration pulse 2 2. 'The output after processing with the device is the only one described above, which is only the present invention— > It can only be used to limit the implementation of the present invention; Within the scope of patent application. The G, G, and white should still be covered by the patent of the present invention. [Explanation of Symbols in the Schematic] Acceleration and Deceleration Meters ... 9 ^ ,, B Pulse Interval Time Values ... 3

$ π頁 486855$ πpage 486855

案號89120711 _年月日修正圖式簡單說明時脈電路· · 4 時脈...... 5 計數器· · · 6 中斷要求· · · · 7 處理器· · · 8 輸出脈衝· · · · 9 輸入脈衝·· • 1 0 位元數..... • · 1 1 移位暫存器· • · • 1 2 上下計數器· · · • · 1 3 往上計數·· • 1 4 往下計數· · · · • · 1 5 數位微分分析器· • 1 6 加法器..... • · 1 7 比較器· · · • 1 8 等速脈衝· · · · • · 1 9 線型加減速脈衝· • 2 0 S型加減速脈衝· • · 2 1 RAM· · · • 2 2 計數參數· · · · • · 2 3 位址· · · · • 2 4 加法參數· · · · • · 2 5 步驟· · · S 1〜 S 1 8Case No. 89120711 _ Year, month, day correction diagram, simple description of the clock circuit · 4 clocks · 5 counters · · · 6 interrupt requirements · · · · 7 processors · · · 8 output pulses · · · · 9 input pulses · · · 10 number of bits ... · · 1 1 Shift register · · · · 1 2 Up and down counter · · · · · 1 3 Count up · · 1 4 Go Countdown · · · · · · 1 5 Digital Differential Analyzer · • 1 6 Adder .... · 1 7 Comparator · · · · 1 8 Constant Velocity Pulse · · · · · · 1 9 Linear Addition Deceleration pulses • 20 S-type acceleration and deceleration pulses • • 2 1 RAM • • • 2 2 Counting parameters 2 5 stepsS 1 to S 1 8

第12頁Page 12

Claims

486855 修正_ 89120711 六'申請專利範圍 1. -種脈衝指令的加減速控制方法，係包括： :：先’⑯-脈衝指令輸入—移位暫存器；二總數上下計數器計算上述移位暫存器内部暫存之脈下4赵' m數位被分分析器（D D A )電路送出頻率與上加ίΐΜ算之脈衝總數成正比例的輪出脈衝，得到—具加減速圖樣之脈衝輸出丄 Πΐ專利範圍第1項所述之脈衝指令的加減速控制方法，/、中该脈衝指令為一等速脈衝指令。本士 I I專利範圍第1項所述之脈衝指令的加減速控制方 =間:中該移位暫存器内部暫存之位元數為加速或減速的 t如ί ί專利範圍第1項所述之脈衝指令的加滅速控制方、一八i ΐ數位微分分析器（D D A )電路包含一加法器 Λ $ ί t益，係將前述上下計數器計算之脈衝總數透過該 ί 1 其數值，經由該比較器判定是否輸出脈衝，得〃加減速圖樣之脈衝輸出。 %如！ ΐ專利範圍第1項所述之脈衝指令的加減速控制方 ’ ，/、中輸出之加減速脈衝為一線型加減速脈衝。 Π ΐ專利範圍第1項所述之脈衝指令的加減速控制方沄，/、中該移位暫存器可由隨機記憶體R Α Μ來代替，其移動位元之動作由位址指標的移動來替代。〜 7速ί Π ί利範圍第1項或第4項所述之脈衝指令的加減控制方法’該上下計數器、加法器與比較器亦可由程式486855 Modification _ 89120711 Six 'patent application scope 1.-A kind of acceleration / deceleration control method of pulse instruction, including: :: first-⑯-pulse instruction input-shift register; two total up and down counters to calculate the above shift register The 4 Zhao'm digital sub-analyzer (DDA) circuit under the pulse temporarily stored in the device sends out a round-out pulse whose frequency is proportional to the total number of pulses calculated by adding ΐΜ, and obtains the pulse output with acceleration and deceleration patterns. The acceleration / deceleration control method of the pulse command described in the first item, wherein the pulse command is a constant-speed pulse command. The accelerating and decelerating control party of the pulse instruction described in Item 1 of the patent scope of the patent = time: the number of bits temporarily stored in the shift register is accelerating or decelerating. The pulse command acceleration / deceleration control method, the 18-bit digital differential analyzer (DDA) circuit includes an adder Λ $ ί tyi, which passes the total number of pulses calculated by the up-down counter through the value of ί 1 through The comparator determines whether to output a pulse and obtains the pulse output of the acceleration / deceleration pattern. %Such as!加 Acceleration / deceleration control method of pulse command described in item 1 of the patent scope, and /, the acceleration / deceleration pulse output in // is a linear acceleration / deceleration pulse. Π 沄 The acceleration and deceleration control method of the pulse instruction described in the first item of the patent scope, where the shift register can be replaced by random memory R Α M, and the movement of its bit is determined by the movement of the address index. To replace. ~ 7-speed Π ί The addition and subtraction control method of the pulse instruction described in item 1 or item 4 of the profit range ’The up-down counter, adder and comparator can also be programmed

第13頁 486855 曰修正 89120711_ 六、申請專利範圍軟體來取代。 8.如申請專利範圍第丄、2、3 的加減速控制方法，該方法再串接2 5項所述之脈衝指令構造之加減速裝置，則可將該線型一個以上之相同減速脈衝輪出，其加減速時間等於減速脈衝轉為S型加存之位元傭數總和。、厅有移位暫存器内部暫 9· 一種脈衝指令的加減速控制裝 -剩存器，係用以移位暫存輸入=·: 下计數器，用以計算上述移暫’ 總數；存為内部暫存之脈衝 :J:微分分析器（D D A )電路，係用亡下计數器計算之脈衝總數成正 k出頻率與該二由上述動作而得到一具有力姻 .如申凊專利範圍第9項所述之脈衝’指八雨出。 3置，其中該脈衝指令為一等速脈衝指令7。、減速控制申叫專利範圍第9項所述之脈衝指八的、、 2 *其中該移位暫存器具有複數個位元，复^減速控制位几數為加速或減速之時間。兀其内部暫存之 1姑2·恶如申請專利範圍第9項所述之脈衝指令的，# 加法，:;位微分分析器（D D A)電路至少包含一透過該力”去器累加其數值，，經由該比較；;t脈衝總數衝，得到-具加減速圖樣之脈衝輸出。° j疋疋否輸出脈 13.如申請專利範圍第9項所述之脈衝指令的加減速控制Page 13 486855 said amendment 89120711_ Sixth, the scope of the patent application software to replace. 8. If the acceleration / deceleration control method in the scope of patent application Nos. 3, 2, and 3, this method is further connected with the acceleration / deceleration device with the pulse instruction structure described in item 25, then one or more linear deceleration pulses of the same deceleration can be output. , Its acceleration and deceleration time is equal to the sum of the number of bit commissions when the deceleration pulse is turned into S-type plus storage. There is a shift register in the hall. 9. A pulse command acceleration / deceleration control device-remaining register is used to shift the temporary storage input = ·: a down counter to calculate the total number of the temporary shifts; Stored as internal temporary stored pulses: J: Differential Analyzer (DDA) circuit, which uses the total number of pulses calculated by the dead counter to be a positive k output frequency and the two obtained a powerful marriage from the above actions. For example, the patent applied for The pulse in the range item 9 refers to the eight rains. Set to 3, where the pulse command is a constant speed pulse command 7. 2. Deceleration control The pulses described in item 9 of the patent scope refer to eight, 2 *, where the shift register has multiple bits, and the number of complex deceleration control bits is the time for acceleration or deceleration. There are 1 internal pulses temporarily stored in it. 2. The pulse instructions described in item 9 of the scope of the patent application, # Addition :: The bit differential analyzer (DDA) circuit contains at least one component that accumulates its value through the force. ， Through the comparison ;; t pulse total number of pulses to get-pulse output with acceleration and deceleration pattern. ° j 疋疋 no output pulse 13. Pulse command acceleration and deceleration control as described in item 9 of the scope of patent application

第14頁 486855 _ 案號 8912071^ 六、申請專利範圍裝置，其中輸出之加減速脈衝為 1 4 ·如申請專利範圍第9項戈第… 加減速控制裝置，該裝置亦可— Μ來達成，其中該移位暫存器可 f 2，動作藉由移動位址指標來 σ /為與比較器可由程式軟體來 1 如申請專利範圍第9 、1 〇脈衝心令的加減速控制裝置，該個以上之相同構造之加減速裝置衝轉為S型加滅速脈衝輸出，其暫存器内部暫存之位元數總和Γ 曰复JL 一線型加減速脈衝。項所述之脈衝指令的 :晶片與隨機記憶體R A 來代#，其移動 :代，而該上下計數器、取代。 1 1或第1 3項所述之裝置其後再串才妾一個或一 ’則可將該、線型加減速脈加減速時間等於所有移位第15頁Page 14486855 _ Case No. 8912071 ^ Sixth, the scope of the patent application, the output of the acceleration and deceleration pulse is 1 4 · If the scope of the patent application of the 9th Gordian ... Acceleration and deceleration control device, this device can also be achieved by -M, The shift register can be f 2 and the action is determined by the mobile address index σ / and the comparator can be used by the program software. 1 As for the acceleration and deceleration control device of the patent application range 9 and 10 pulse impulse, the The acceleration / deceleration device of the same structure as above has an S-type acceleration / deceleration pulse output, and the total number of bits temporarily stored in its register Γ is a complex JL linear acceleration / deceleration pulse. The pulse instruction described in the item: chip and random memory R A to #, and its movement: generation, and the up and down counter, replace. 1 1 or item 13 The device can only be connected one or one after it is connected. ’The linear acceleration and deceleration pulses can be accelerated and decelerated for all shifts. Page 15