TW486633B - Bridge between parallel buses over a packet-switched network - Google Patents
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486633 五、發明說明(1) 相關申請案之交互參考·· 二此申請案是與另一專利申請案有關,同一天 請,標題為π經由封包交換式模組之 渡太衷刹由枝安44 心十订匯流排通訊丨丨亦讓 專和申咕案之委託人,於此亦作為泉 發明領域: 1〃亏貝科。 包系Γ㈣一般電腦系統’且特別有關於使用封 匕乂換式杈、、且之系統以連接一電腦主機至 發明背景·· 门建衣置。 、在目前世代電腦中,中央處理機(CPU)是藉由一羊杆 匯流排連接至系統記憶體及周邊裝置 9 、色六六ΛΑ J您衣直此千仃匯流排如普 遍存在的周邊零件介面(Peripheral C⑽pQnent Interface」PCI)匯流排。而隨著時日路徑—寬度擗 Ϊ脈速度變快,為了維持系統需求平行匯流排變‘價柊昂 :及j雜。對於電腦工業是快速進展的反應, =輸輸出(1/〇)匯流排結構之中,電腦主機 置疋^:交換網路連#,—般是指為交換模組 之二些結構已被提出,包括”下一世代I/0,,(NGI〇)及”未來 I/O (F 10),達到最咼點之"無窮頻帶”結構,其是由一工 mr包括英特爾、昇陽、惠普、國際商務機器 、康柏、戴爾及微軟)來主導發展。儲存區域網路( Storage Area Network)提供一類似、封包化― 方法來高速儲存存取亦可使用一無窮頻帶模組來 現。 只 PG1.區域匯流排會限制可連接於其上之不同裝置之數486633 V. Description of the invention (1) Cross-reference of related applications ... This application is related to another patent application. On the same day, please, titled π through the packet exchange module. The Heart Ten Order Bus Newsletter 丨 丨 also allows the client of the special and Shen Gu case, and also serves as the spring invention field: 1 The package is a general computer system, and more particularly, it relates to a system that uses a sealing blade to connect a computer host to the background of the invention. In the current generation of computers, the central processing unit (CPU) is connected to the system memory and peripheral devices through a sheep pole bus. 9 、 Color six six ΛΑ J. You are as straight as a thousand buses, such as ubiquitous peripheral parts. Interface (Peripheral C⑽pQnent Interface "PCI) bus. As the time-day path—the width—the pulse speed increases, in order to maintain the system demand, the parallel bus changes ‘the price is high and the price is complicated. The response to the rapid development of the computer industry, = In the input / output (1/0) bus structure, the host computer is set to ^: 开关 网络 连接 #, which generally means that some structures for the switching module have been proposed. , Including the "next generation I / 0," (NGI〇) and "future I / O (F 10), reaching the highest point of the" infinite frequency band "structure, which is composed of a single mr including Intel, Sun, Hewlett-Packard, International Business Machines, Compaq, Dell, and Microsoft) are leading the development. The Storage Area Network provides a similar, packetized-method for high-speed storage access using an infinite-band module. Only PG1. Regional bus will limit the number of different devices that can be connected to it
486633 五、發明說明(2) 量且於所允許實體距離内允許連接於匯流排上之任何兩裝 置間。要克服此&限制,Pdl-to-PCI(P2P)橋接器是用來 連接兩個或更多PC I區域匯流排。橋接器必須能使在此些 匯流排之一匯流排上之一裝置自其他匯流擦上之裝置寫入 及讀取,而不會違反匯流排通訊協定及處理順序規則。未 遵守匯流排規則會導致死^结及錯誤。PC I匯流排通訊協定486633 V. Description of the invention (2) Any two devices connected to the busbar shall be allowed to be connected in a quantity and within the allowed physical distance. To overcome this & limitation, a Pdl-to-PCI (P2P) bridge is used to connect two or more PC I area buses. The bridge must be able to enable a device on one of these buses to write to and read from a device wiped on the other bus without violating the bus protocol and processing sequence rules. Failure to follow bus rules can result in death and errors. PC I bus communication protocol
及規則是詳細說明在PCI Special Interest Group (Hillsboro,Oregon)所出版之PCI區域匯流排說明書第2· 2版( 1 998),於此亦作為參考資料,特別是請查閱3· 2· 5 節(40-44頁)π處理順序及宣告”及附錄Ε(267-277頁),,系統 處理順序π。The rules and regulations are detailed in the PCI Special Bus Group (Hillsboro, Oregon) PCI Area Bus Specification, Version 2 · 2 (1 998), which is also used as reference material, especially please refer to Section 3.2. 5 (Pages 40-44) π Processing Sequence and Declaration "and Appendix E (Pages 267-277), the system processing sequence π.
依據此說明書’有9種型式之P C I匯流排處理可分為兩 類,宣告及非宣告基„於它們如何藉由一中間媒介體,如一 橋接器來處理。宣告處理是在它們到達它們的終極目的裝 置前完成於來源(主要)裝置,因此在宣告處理到達終極目 的裝置前主要裝置可以進行其他工作,包括其他匯流排處 理。主要裝置接收實際目的裝置之資料且承擔確保存取在 目的裝置正確完成之責任,P C I匯流排規格須要宣告記憶 體寫入(包括記憶體寫入及記憶體寫入而無效)。 P CI匯流排上之非宣告處理是在它們到達它們的終極 目的裝置時才會完成於來源裝置,在宣告處理完成及自目 的裝置返回前主要裝置無法進行任何其他相關工作。在一 讀取處理之例子中,此意謂已自目的裝置返回。對於一寫 入處理,須回傳一寫入確認。依據PC I規格,記憶體讀取According to this description, there are 9 types of PCI bus processing that can be divided into two categories, declarative and non-declarative. They are based on how they are handled by an intermediate medium, such as a bridge. The declaration processing is when they reach their ultimate The destination device is completed before the source (main) device, so the main device can perform other tasks, including other bus processing, before the announcement process reaches the ultimate destination device. The main device receives the data of the actual destination device and is responsible for ensuring that the access to the destination device is correct Responsibility for completion, PCI bus specifications need to declare memory writes (including memory writes and memory writes to be invalid). The non-declaration processing on the P CI buses is only when they reach their ultimate destination device Completed at the source device, the main device cannot perform any other related work before the completion of the processing and return from the destination device. In the example of a read process, this means that it has returned from the destination device. For a write process, it is necessary to return Pass a write confirmation. Memory read according to PC I specifications
5019-3607-PF.ptd 第7頁 486633 五、發明說明(3) 處理(記憶體讀取、記憶體讀取列及記憶體讀取多重列), 及結構處理(結構讀取、結構寫入)及輸出/輸入(I/O)處理 (I/O讀取及I/O寫入)是非宣告的。 表1總結識別PC I匯流排處理,它們是基於整體PC I位 址空間分配進入記憶體、I /0及結構位址空間: 表1 PCI匯流排處理 處理名稱 意義 宣告 i/O讀取 址空間 否 1/0寫入 寫入資料至媒介體映射至1/0位址空間 吝 結構讀取 由媒介體讀取資料映豺至1/0妞址空間 否 結構寫入 窝入資料至媒介體映豺至結構拉址空間 否 &己憶韻[寫入 寫入資料至媒介體映豺至記憶艘拉址空間 是 記憶體寫入 而無效 窝入資料至媒介體映射至記憶艘拉址空間, 以一完整的快速緩程ί儲存區之列最少的轉移 是 記憶镀讀取 由媒介體讀取資料映財至記愧艘拉址空間 記憶體讀取 列 由媒介體讀取快速緩種f儲存區之列之資料映 射至記憶體位址空間 否 記愧體讀取 多重列 由媒介艚讀取快速緩街儲存區之多重列之資 斜映財至記憶體拉址空間 其他PCI匯流排循環包括中斷確認、特殊循環及雙位址循 環,如上述PC I匯流排規格,雙位址循環是利用32位元裝 置以存取兩相中之64位元位址空間,且必須藉由P2P橋接 器支援。中斷確認及特殊循環之支援是選用的。 傳統上,一P2P橋接器於兩PCI匯流排之各匯流排上包 括一橋接裝置,其是以一邏輯及實體連接於橋接裝置間以 連結至匯流排。當一第一匯流排上之一主要裝置要使用一5019-3607-PF.ptd Page 7 486633 V. Description of the invention (3) Processing (memory reading, memory reading row and memory reading multiple rows), and structure processing (structure reading, structure writing ) And output / input (I / O) processing (I / O read and I / O write) are undeclared. Table 1 summarizes and identifies the PC I bus processing, which is based on the overall PC I address space allocation into memory, I / 0, and structural address space: Table 1 PCI bus processing processing name meaning declaration i / O read address space No 1/0 write write data to media map to 1/0 address space 吝 structure read from media read data map to 1/0 girl address space No structure write data into media map豺 To the structure pull address space & Ji Yiyun [Write the written data to the media map to the memory ship pull address space is a memory write and the invalid nested data to the media is mapped to the memory ship pull space, With a complete fast cache, the least transfer of storage area is the memory plating read from the media to read the data to reflect the memory of the ship's pull-out space. The data in the row of the area is mapped to the memory address space. Is it regretful to read the multiple rows? The media reads the multiple rows of the fast and slow storage area. The oblique mapping of the data to the memory address space. Confirmation, special cycle Dual address cycle, as described above PC I bus specifications, the use of dual address cycle is 32 yuan 64 yuan means to access the address space of the two phases, and must be supported by P2P bridges. Interrupt confirmation and special loop support are optional. Traditionally, a P2P bridge includes a bridge device on each of the two PCI buses. It is a logical and physical connection between the bridge devices to connect to the bus. When a main device on a first bus is to use a
5019-3607-PF.ptd 第8頁 486633 五、發明說明(4) 第二匯流排上之一目的裝置來初始化一處理時,其傳送適 當的匯流排命令至第一匯流排位址空間中之目的裝置之一 位址’其在開機時指定目的裝置,此位址是在第一匯流排 上之橋接裝置所屬之位址範圍内。橋接裝置是設定成,,主 張(Cl,aimr定址到第二匯流排上之目的裝置之所有循環, 在^張(c 1 a 1 m )此循環後,第一匯流排上之橋接裝置將其 傳送至第二匯流排上之橋接裝置,第二匯流排上之橋接裝 置傳送此循環到最終的目的裝置。5019-3607-PF.ptd Page 8 486633 V. Description of the invention (4) When a destination device on the second bus initiates a process, it sends an appropriate bus command to the first bus address space. One address of the destination device 'specifies the destination device when it is turned on. This address is within the address range of the bridge device on the first bus. The bridge device is set to claim all cycles of the destination device (Cl, aimr addressed to the second bus), and after this cycle (c 1 a 1 m), the bridge device on the first bus will Send to the bridge device on the second bus, and the bridge device on the second bus sends this cycle to the final destination device.
當此命令為一宣告記憶體寫入命令時,橋接裝置立即 ,認此命令,且傳送要寫入資料至目的裝置。其他的、非 旦告寫入命令、及讀取命令是分別當作延遲寫入請求 (Delayed Write Requests,DWRs)及延遲讀取請求 (Delayed Read Requests,DRRs),當橋接裝置接收此一 延遲請求,其回傳再試回應至主要裝置及經由此橋接裝置 傳送此適當命令至第二匯流排。之後橋接裝置等待一適當 延遲寫入兀成(delayed write completion, DWC),記述When this command is a declaration memory write command, the bridge device immediately recognizes the command and sends the data to be written to the destination device. The other write commands and read commands are regarded as Delayed Write Requests (DWRs) and Delayed Read Requests (DRRs) respectively. When the bridge device receives this delayed request , Which returns a retry response to the primary device and sends the appropriate command to the second bus via the bridge device. Then the bridge device waits for an appropriate delayed write completion (DWC), describing
寫入是否成功施行,或延遲讀取處理(delayed read transact ion,DRC),回傳請求資料,經由橋接裝置自目 的裝置返回。此處理僅當橋接裝置回傳DWC或DWR至來源 (主要)裝置才完成。 為避免錯誤及可能的死結,橋接裝置必須服務所有處 理依照PC I匯流排通訊協定之處理順序規則,上述pc I匯流 排說明書之附錄E下列橋接裝置必須遵守之順序規則: 1 · 一被傳送至橋接目的裝置之後面的PMW不能超越一Whether the write was successfully performed, or delayed read processing (DRC), returns the requested data, and returns it from the destination device via the bridge device. This process is done only when the bridge device returns DWC or DWR to the source (primary) device. In order to avoid errors and possible deadlocks, the bridge device must service all processing in accordance with the processing order rules of the PC I bus communication protocol. Appendix E of the above PC I bus specification must comply with the following order rules of the bridge device: 1 · One is transmitted to The PMW behind the bridge destination device cannot exceed one
5019-3607-PF.ptd 第9頁 486633 、發明說明(5) 先蝻所接收的PMW,即PMW處理必須依照它們所被接收的順 序來完成。 2· — 延遲讀取請求(delayed read request, DRR)處 里必須促使宣告寫入資料向前以維持順序,讀取處理不能 超越PMW。 ' _ 3· 一非宣告寫入(DWR)處理必須促使宣告寫入資料向 前以維持順序,DWR不能超越PMW。 4·於完成一讀取處理(DRC)前,任何寫入資料必須先 被推回到此讀取處理之來源匯流排上,即DRC不能超越 PMW(假定於讀取處理完成前,此寫入命令於第二匯流排上 被接受)。 5· — PMW必須被允許超越一DRR或DWR以避免死結。 6· —延遲完成(DWC或DRC)處理必須被允許超越一延遲 請求(DWR或DRR)處理以避免死結。 7· — PMW必須被允許超越一DWC 4DRc以避免死結。 其他對之處理沒有順序限制且可藉由橋接裝置依照任 何方便順序來處理。 由於PC I匯流排本身是一平行匯流排,大部分已知之 P2P橋接裝置使用類似平行架構,然而,最近加州Santa Clara的德儀半導體集團發表一pci—t〇_pci橋接/無線電收 發晶片組,宣稱其可於雙絞線上傳送連載的pc I達到理論 的最大之PCI匯流排速度132MB/S。此晶片之設計可使得藉 由一雙絞線電纜連結兩分離Pc丨平行匯流排而擴展及延伸 超越正常P C I平行匯流排之距離限制。5019-3607-PF.ptd Page 9 486633, Invention Description (5) First, the received PMW, that is, the PMW processing must be completed in the order in which they were received. 2 · — The delayed read request (DRR) must promote the declaration of the written data to maintain the order, and the read processing cannot exceed the PMW. '_ 3 · A non-declaration write (DWR) process must cause the declaration write data to be forwarded to maintain order, and DWR cannot exceed PMW. 4. Before completing a read process (DRC), any write data must be pushed back to the source bus of the read process, that is, the DRC cannot exceed the PMW (assuming that the write is completed before the read process is completed The order is accepted on the second bus). 5 · — The PMW must be allowed to exceed a DRR or DWR to avoid dead knots. 6. · Delayed completion (DWC or DRC) processing must be allowed to go beyond a delayed request (DWR or DRR) processing to avoid deadlocks. 7 · — PMW must be allowed to pass a DWC 4DRc to avoid dead knots. The other processes are not limited in order and can be processed by the bridging device in any convenient order. Since the PC I bus is a parallel bus, most of the known P2P bridge devices use a similar parallel architecture. However, the Texas Instruments Group in Santa Clara, California recently published a pci-t0_pci bridge / radio transceiver chipset. It claims that it can transmit serial PC I on twisted pair cable to reach the theoretical maximum PCI bus speed of 132MB / S. The design of this chip can extend and extend beyond the normal P C I parallel bus distance by connecting two separate Pc 丨 parallel buses with a twisted pair cable.
4獅 五、發明說明(6) 發明概述: 流排ί::::3:點之目的在於提供改良之於兩平行羅 排間二=r:器,且特物兩周邊零件介面匯流 本發明之一些觀點更有— 式網^ $ τ / ” 目的在於提供經由封包交換 橋接於兩平行-匯-流排間之方法及装£。 介面::::::些觀點更有—目的在於提供映射周邊零件 令至序列資料封包且反之亦'然,而遵守周邊 零件”面匯流排處理之順序規則。 1遠 網路ίί發L月之較佳實施例,,一橋接器經由封包交換式 = —平行匯錢至—第二、遠端平行匯流排。 =本,明之原理是其他型式可用之匯流排及網路, ;:μ土為’弟一及第二平行匯流排包括周邊零件介面匯流 =而封包交換式網路包括-無窮頻帶網路。橋接器接收 周邊零件介面匯流排讀取及寫入命令, -匯流排上之一主要裝置發出1它們轉“二K 經由此網路傳輸,之後再將它們轉移返回進入適當的周邊 零件介面匯流排命令以傳送至第二匯流排上之一目的裝置 執行。目的裝置之回應是類似於經由橋接器轉移及傳^返 回至主要裝置(由第二匯流排上之主要裝置及第一匯流排 上之目的裝置所發出之命令較佳是以同樣的方式處理)。 於傳輸及處理IB封包中,橋接器遵守所有周邊零件介 面匯流排處理之順序規則。 橋接為於各個第一及第一周邊零件介面匯流排上包括4 Lion V. Description of the invention (6) Summary of the invention: The purpose of the flow row ί :::: 3: points is to provide an improvement between the two parallel rows of two = r: devices, and the interface of the two peripheral parts of the special feature converges the present invention. Some of these views are even more—style network ^ $ τ / ”The purpose is to provide a method and equipment for bridging between two parallel-sink-flow buses through packet switching. Interface ::::: Some views are more-the purpose is to provide Map peripheral parts to sequence data packets and vice versa, and follow the order of peripheral parts "surface bus processing". 1 remote network is a preferred embodiment of L month, a bridge is exchanged through a packet =-parallel transfer of money to-a second, remote parallel bus. = Ben, Ming's principle is that other types of buses and networks are available;: μ soil is the first and second parallel buses including peripheral component interface buses = and packet-switched networks include-infinite band networks. The bridge receives the peripheral part interface bus read and write commands,-one of the main devices on the bus issues 1 they transfer "two K" via this network, and then transfers them back to the appropriate peripheral part interface bus The command is transmitted to one of the destination devices for execution on the second bus. The response of the destination device is similar to the transfer and return via the bridge to the main device (from the main device on the second bus and the first bus The commands issued by the destination device are preferably processed in the same way.) In transmitting and processing the IB packet, the bridge follows the order rule of the bus processing of all peripheral parts interface. The bridge is for each first and first peripheral part interface Included on the bus
5019-3607-PF.ptd 第11頁 486633 五、發明說明(7) :各別的橋接裝置,各橋接裝置較佳包括一目標通道轉接 二(T C A )、連接至各匯流排,及一網路介面,連接至I b網 =。較佳為,此網路介面包括一交換器,但實際上任何遵 守Ιβ規則之介面亦可使用。目標通道轉接器轉換各PCI讀、 取,寫入up令,目標通道轉接器接收讀取及寫入命令進入 IB讀取及t寫入封包以藉由Ιβ模組經由此介面來傳送。較佳 為,TCA指定一各別IB網路通道至關聯讀取及寫入命令之 位址空間,如此使得PCI記憶體、結構及處理 f由此網路各取得它們自己的固定通道。本文中之通 = :特別:徑及-服務(或優先權)層級,Ϊ 排上之不同型式之記憶體讀取處理較佳 ^猎由指定一適當值至對應Ιβ讀取 域以識別。 c τ心貝抖長度區 排上空間之各別通道是預先指定且是目標匯流 TCA接收一讀取或寫」封已知的。當此目標 否於此目標匯流排上發出一圮愔 匕之通迢疋 路通道之此種應用,^中维2;'”或1/〇命令。網 務延遲讀取及寫^ 隹持封包順序,意謂傳送及服 之前執行,如PCI$則所g,各κ 取及寫入命令 緩衝儲存器,最佳為包括—先又=為包祜一請求服務 。當目標匯流排上之目標通道轉==FIFQ)、缓衝儲存器 、轉接裔經由橋接裝置接收一5019-3607-PF.ptd Page 11 486633 V. Description of the invention (7): Each bridge device, each bridge device preferably includes a target channel transfer two (TCA), connected to each bus, and a network Road interface, connected to I b net =. Preferably, the network interface includes a switch, but in fact any interface that complies with the Iβ rule can also be used. The target channel adapter converts each PCI read, fetch, and write up command. The target channel adapter receives the read and write commands and enters the IB read and t write packets for transmission through this interface through the Iβ module. Preferably, the TCA assigns a respective IB network channel to the address space of the associated read and write commands, so that the PCI memory, structure, and processing f each obtain their own fixed channel from the network. The pass in this article =: Special: Path and-service (or priority) level, different types of memory read processing on the row are better ^ hunting by specifying an appropriate value to the corresponding Iβ read field to identify. c τ heartbeat length area The individual channels in the space above the row are pre-designated and the target sink TCA receives a read or write packet. When this target issues such an application on the target bus, a dagger-like channel is used, ^ Zhongwei 2; '”or 1 / 〇 command. Network services delay reading and writing ^ Hold packets Sequential means execution before transmission and service, such as PCI $, each κ fetches and writes to the command buffer memory, the best is to include-first again = to serve a request for the service. When the target on the target bus Channel transfer == FIFQ), buffer memory, transfer
486633 五、發明說明(8) 延遲讀取或寫入命令,其將此命令置放於緩 等待執行。然而,無論何時TCA接收一宣告寫入么^、斋中以 認為一寫入封包來自於此網路之通道 /令(破確 J) ’其立即將此命令置放於目標匯流排上為:上體處 存器中之延遲命令。 k、後衝鍺 在本發明之一些較佳實施例中,3個或 是經由一普通IB網路橋接在一起,此些較件實 ^流排 匯流排具有-橋接裝置以施行此些功能,且網路、甬、各 =對橋接裝置間作為傳輸讀取及寫入;包㈣J = 所已知之橋接器,不管是平行或序列僅可以ί接^知技術 PCI匯流排之間(或其他 了 ^橋接於—對 路匯浠排砗Η π西夕 丁 a极排間),所以當要連接多 多路橋接器。由於本發明之較佳:二 受此限制。 )作為橋接,所以它們不會 很據本發明之 囚此 第一及第二平行匯流排間之,提供一種橋接486633 V. Description of the invention (8) Delay the read or write command, which places this command on hold and waits for execution. However, whenever the TCA receives a declaration write ^, Zhai Zhong believed that a write packet came from a channel / order (broken J) of this network 'It immediately placed this command on the target bus as: Delay command in upper body register. k. Backflushing germanium In some preferred embodiments of the present invention, three of them are bridged together through an ordinary IB network. These more practical busbars have a -bridge device to perform these functions. And network, network, each = read and write as a transmission between bridge devices; including J = known bridges, whether parallel or serial, can only be connected between known technology PCI buses (or other ^ Bridge-to-road junction (浠 xi Xi Ding a pole row), so when connecting multiple multiplex bridges. Because of the advantages of the present invention: Second, this limitation. ) As a bridge, so they will not be very close to the first and second parallel busbars according to the invention, providing a bridge
於順序規則控制執行,此方法包括: 此處理組合中之一 _ ^目标位址接收—匯流排命令,結 一來源裝置發出用此命令是藉由於第一匯流排上 行; 由於第二匯流排上之一目的裝置In order to control the execution of the sequence rule, the method includes: one of the processing combinations _ ^ destination address reception-bus command, a command issued by a source device is because the first bus goes up; because the second bus goes up One-purpose device
偟,4 ^包乂換式網路上之此第一匯法排上之此E 址傳迗包含此所接吹 A "丨L札上之比E 匯流排上之一主I j E^卩令之一資料封包至il 王要位址;以及偟, 4 ^ Includes the E address on the first bus line on the switch network, including the received A " R on the ratio E bus one of the main I j E ^ 卩Order one of the data packets to the address of king il; and
五、發明說明(9) 規則位;:二此所接收之資料封包,…順序 較佳排f此目的裝置傳送此匯流排命令。 面匯流排:而此封f第一平打匯流排包括—周邊零件介 較作為ί t父換式網路包括一無窮頻帶網路。 筐一二為於此目標位址接收此匯流排命令包括於…a 排上至—橋接裝置之-位址空間内ί=:;Η 為,指定此位址ίΐ::此位址範圍包括目標位址。最佳 ,及映射此各個=圍=诒指定多個位址範圍至此橋接裝置 中傳送此封包包括:t =至此網路中之一各別通道’且其 射目標位址==通;傳送此封包至包含此所被映 個位址範圍包括,定:圍/在一較佳實施例中’指定此多 個複數個位址;二;此:接裝置於此第-匯流排上之各 位址空間包括記情體::址範圍中,此複數個 、 、、、Ό構及輸出/輸入(I / 0)位址空間。 附加的或另.一 43? ^ 排命令包括映射接;=經由此第二匯流排傳送此匯流 ^ ,,, 接收此封包之此通道至此第二匯流排上之 稷數個位址空間中之一個位址空間。 附亡的或另一選擇為,#妾收此命令包括於此指定範圍 之靶圍内之一或多個位址接收多個命令,且其中映射 此目標位址範圍包括映射此範圍内之所有一或多個位址至 此相同通道如此传彳旱+ 一 此1史传此夸封包以在橋接裝置所被接收順序 經由此網路之此通道被傳送。 較佳為’接收此匿流排命令包括接收一讀取命令以藉 由目的裝置來執行,且其中傳送此資料封包包括傳送,.„ 網V. Description of the invention (9) Rule bit: Secondly, the data packet received here, in order, preferably, the destination device transmits the bus command. Surface bus: The first bus driver of this package includes—the peripheral parts are introduced. As a parent switching network, it includes an infinite frequency band network. Basket one or two for receiving this bus command at this target address is included in row a to-bridge device-in the address space ί = :; Η is to specify this address ΐ :: This address range includes the target Address. The best, and mapping each of these = circumference = 诒 specify multiple address ranges to this bridge device to send this packet includes: t = to a respective channel in this network 'and its target address = = pass; send this The packet to include the mapped address range includes, set: surround / In a preferred embodiment, 'specify the plurality of addresses; two; this: connect the addresses of the device on the-bus The space includes memory :: In the address range, this multiple, ,,, and structure and output / input (I / 0) address space. Additional or another. A 43? ^ Bus command includes mapping; = send this bus through this second bus ^ ,,, the channel that receives this packet to one of several address spaces on this second bus An address space. Incidental or another option is that # 妾 Receive this command includes receiving multiple commands at one or more addresses within the target range of the specified range, and mapping this target address range includes mapping all of the addresses in this range One or more addresses have been transmitted to the same channel so far. + This packet is transmitted via this channel of this network in the order received by the bridge device. Preferably, 'receiving the streaming command includes receiving a read command for execution by a destination device, and wherein transmitting the data packet includes transmitting,.
路讀取請求 令以由結合 且其中傳送 設定一資料 為’接收此 封包。更佳為 此目的 此網路 長度區 命令以 體讀取一或多個快 附加的 二匯流排接 包含所接收 括接收第一 括延遲傳送 封包回應此 附加的 寫入命令以 包括傳送一 令之目的裝 由此網路主 或另一 收資料 資料至 及第二 此第二 第一 或另一 藉由目 網路寫 置在主 要位址 讀 裝置之一 言買取請求 域回應此 讀取此給 速緩衝儲 選擇為, ’且由此 目標位址 讀取命令 讀取命令 取命令被 選擇為, 的裝置來 入請求封 要位址經 傳送一回 接收此讀 記憶體讀 封包包括 給定量。 定量包括 存區之列 由目的裝 網路主要 。較佳為 ,且其中 直到包含 傳送止。 接收此匯 執行,且 包。較佳 由第二匯 應封包回 取邱今、a枯接收 取一給定量之資料, 於此讀取請求封包中 附加的或另一選擇 接收一命令以由記憶 〇 置在主要位址經由第 位址傳送一回應封包 ’接收此讀取命令包 傳送此匯流排命令包 所接收資料之此回應 流排命令包括接收一 其中傳送此資料封包 為,由執行此寫入命 流排接收一癌認,且 應此確認至目標位址 » 二匯、=佺為’接收此匯流排命令包括接收一請求以執行第 =珠=排上5 一延遲處理,接續完成此延遲處理之前藉由 1¾ = ^ t執仃第二匯流排上之一宣告處理,且其中傳送此 匯流排命令句#私^ L 土匕枯於兀成此延遲處理之前服務此宣告處理。 更佳為’傳送此匯流排命令包括置放此延遲處理請求 ; 要位址之一緩衝儲存器中,且允許此宣告處理請求The way to read the request is to combine this with the transmission and set a data as ‘to receive this packet. More preferably for this purpose this network length zone command reads one or more fast-attached two buses including received packets including received first delayed transmission packets in response to this additional write command including sending an order The purpose is to load data from this network owner or another to the second this second first or another device that is written at the primary address by the target network to read the request field in response to this read this to The cache is selected as', and thus the target address read command read command fetch command is selected as the device's incoming request packet and the address is transmitted once to receive this read memory read packet including a given amount. Quantitative includes the list of storage areas. It is preferably, and among them until transmission is included. Receive this sink to execute and package. It is preferred that Qiu Jin is retrieved by the second sink packet, and a given amount of data is received by the receiver. Here, an additional or another option is received in the read request packet to receive a command to be placed in the main address by the memory. Send a response packet at the address' receive this read command packet and send the data received by this bus command packet. This response stream command includes receiving a packet where the data packet is transmitted, and by executing this write bus, a cancer recognition is received. And it should be confirmed to the target address »Erhui, = 佺 for 'Receiving this bus command includes receiving a request to perform the 5th bead = row 5 delay processing, before continuing to complete this delay processing by 1¾ = ^ Perform one of the announcement processing on the second bus, and send the bus command line # 私 ^ L earth dagger to service this announcement processing before the delay processing. More preferably, 'transmitting the bus command includes placing the delayed processing request; to one of the addresses in the buffer memory and allowing the declaration to process the request
第15頁 486633 五、發明說明(π) 越過此缓衝儲存器。附加的或另一選擇為,由在主要位址 經由第二匯流排接收一對於此延遲處理請求之回應,且於 接收此宣告處理請求之前由主要位址經由第二匯流排傳送 一包含此回應之回應封包至目標位址,其中服務此宣告處 理包括置放此回應於此目標位址之一缓衝儲存器中且僅在 服務此宣告處理之後傳送此回應至來源裝置。 附加的或另一選擇為,接收此匯流排命令包括接收一 請求以執行第二匯流排上之一宣告處理,接續完成此宣告 處理之前藉由一請求以執行第二匯流排上之另一處理,且 其中傳送此匯流排命令包括於服務此另一處理之前確保此 _ 宣告處理被完成。 厂 根據本發明之一較佳實施例,亦提供一種橋接於一來 i源平行匯流排及第一及第二目標平行匯流排間之方法,所 有此等匯流排具有一匯流排處理之普通組合及此等處理之 順序規則控制執行,此方法包括: 指定此來源匯流排上至一橋接裝置之一位址空間内之 第一及第二位址範圍以分別與此第一及第二目標匯流排通 訊; 分別於第一及第二範圍内之第一及第二目標位址接收 匯流排命令’此匯流排命令結合此組合中之一或多個處理 _ 且是藉由於此來源匯流排上之至少一來源裝置發出用以藉 由分別於第一及第二目標匯流棑上之第一及第二目的裝置 I執行; 由此橋接裝置經由各別序列連結傳送包含此所接收之Page 15 486633 V. Description of the invention (π) Go over this buffer storage. Additionally or alternatively, a response to the delayed processing request is received at the primary address via the second bus, and a response including the response is sent by the primary address via the second bus before receiving the announcement processing request. The response packet is sent to the destination address, where serving this announcement processing includes placing the response in one of the buffers of this destination address and sending this response to the source device only after servicing this announcement processing. Additionally or alternatively, receiving the bus command includes receiving a request to perform a declaration process on one of the second buses, and performing a request to perform another process on the second bus before continuing to complete the announcement process. , And transmitting the bus command includes ensuring that this _ declaration processing is completed before servicing this other processing. According to a preferred embodiment of the present invention, the factory also provides a method for bridging between a source parallel bus and a first and second target parallel bus. All of these buses have a common combination of bus processing. The sequential rules of these processes are controlled and executed. The method includes: specifying the first and second address ranges from the source bus to an address space of a bridge device to converge with the first and second destinations, respectively. Bus communication; Receive bus commands at the first and second target addresses within the first and second ranges respectively. 'This bus command combines one or more processing in this combination_ and is due to this source bus The at least one source device sends out to execute by the first and second destination devices I on the first and second target buses respectively; and thus the bridge device transmits the received data including the received data through respective serial links.
486633 五、發明說明(12) " '~" ' '~— — 目 及f二資料封包至分別於第-及第 才示匯流排上之第一及第二主要位址;以及 及第· 於此主要位址回應此所接收之 規則經由此第一及第-目;^應、☆ 4 、"、匕’依照此順序 此匯流排命;。第…排至此各別目的裝置傳送 徑,定::Γ]ίΓ括經由—封包交換式網路之路 t弟二位址範圍至此網路上之各別射=個弟-中傳送此封包包括分別經由此第一 ,道,且其 及第二資料封包。 弟一通逼傳送此第一 根據本發明之一較佳實施例, 及第二周邊零件介面匯流排間“;=種橋接於第- 之普通組合及此等處理之順序勃 ®流排處理 括: 兄幻衩制執仃,此方法包 零件3::介:ΪΪ排上之目標位址接收-周邊 "甶匯抓排命令,此命令是藉由於 匯〜排上之一來源裝置發出周f:件:: 面匯流排上之-目的裝置實現一周iC零;介 ; 门運令件介面匯流排處理 列連= 標位址經Η 第二;邊零件介面匯流排包至此 件介面順序規則經由此第二周邊。1+2,依照周邊零 η义令件;丨面匯流排至此目的486633 V. Description of the invention (12) " '~ "' ~~ — The data of the target and f are packaged to the first and second major addresses on the first and second buses respectively; and · Respond to the rules received at this primary address via this first and first item; ^ ying, ☆ 4, quotation, dagger 'in this order; Rank ... then the transmission path of the device for each destination, determine :: Γ] ίΓ includes the route of the packet-switched network, the address range of the two brothers to the individual shots on this network = brother-the sending of this packet includes separately After this, the first, the second, and the second data packet. Yi Yitong forced to transmit this first according to a preferred embodiment of the present invention, and the second peripheral part interface bus between the "; = a common combination that bridges to the-and the sequence of these processes. Brother magic control system, this method includes part 3 :: introduction: target address on the queue receive-peripheral "quote" command to capture the queue, this command is issued by the source device on the source : Piece :: The target device on the surface bus-iC zero for one week; the interface; the door processing order interface interface processing bus connection = the address of the address Η second; the edge parts interface bus package to this interface interface order by This second perimeter. 1 + 2, according to the perimeter zero η order; 丨 surface bus to this end
5019-3607-PF.ptd5019-3607-PF.ptd
第17頁 五、發明說明(13) 裝置傳送此匯流排命令。 較佳為,接收此周邊零件介 結I^ φ / 進流排命令包括接收由 、口構β貝取、輸出/輸入(1/〇)讀 二 讀取列乃9产雕夕去士 人a、 、吕己憶體讀取、記憶體 貝取夕丨〗及δ己憶體多重讀敗命令中 介面藤、、六姐居而入人 ^ '^取多重型式之周邊零件 ’丨®匯机排碩取命令,而其中傳 等多曹刑彳5 - ? ^ 丁、此貧料封包包括映射此 卞夕更坦式至一早一型式之讀取过 妗偯於7灶& ί 明求封包以經由此序列連 、、口傳輸。取佳為,映射此等多重 ^ 輪出/給人Γ τ / η、> & t式包括指定結構讀取、 利ffi /翰入(I/O)讀取、記憶體 道,於:i κ ^ π & +、 及項取至此序列連結之不同通 附加的或另-選要被傳輸之此命令。 ϋ Λ =| & ^ i+ ^ " 、射此等多重型式包括指定值 王此。貝取凊求封包中之一 包括一印产蝴^ 、抖長度區域以回應是否此命令 〇 心 項取列或記憶體讀取多重命令 附加的或另一選遲么 令包括接收由結構寫收此周邊零件介面匯流排命 寫入及記憶體寫入而益效輸入(1/〇)冑入、記/體 介面匯流排寫入命令,、,、、ί二=甲選取多重型式之周邊零件 等多重型式至一單一剞其中傳送此資料封包包括映射此 結傳輸。 式之寫入請求封包以經由此序列連Page 17 5. Description of the invention (13) The device transmits this bus command. Preferably, receiving the peripheral parts to intersect I ^ φ / inflow command includes receiving by, mouth structure β shell fetch, output / input (1 / 〇) read second read row is 9 engraved priests a, , Lu Jiyi ’s body reading, memory fetching 丨〗 and δ Ji Yi ’s multiple read failure command interface, vine, and six sisters come into the house ^ '^ take multiple types of peripheral parts' 丨Take the order, and it is said that DAO Cao's punishment is 5-? ^ D. This poor material packet includes a map that reads this more elegantly to an early one and reads it in 7 stoves & This sequence is connected to and from the port. It is better to map these multiple ^ round out / give Γ τ / η, > & t formula includes the specified structure read, ffi / Han input (I / O) read, memory path, in: i κ ^ π & +, and terms are taken from the different or additional-selected commands to be transmitted. ϋ Λ = | & ^ i + ^ ", such multiple types include the specified value Wang this. One of the request packets includes a printable area and a jitter length area in response to this command. Heart ordering or memory read multiple commands. Additional or alternative options include receiving by the structure to write this. Peripheral parts interface bus write and memory write and benefit input (1 / 〇) Enter, write down / record the interface bus write command ,,,,, ί = A Select multiple types of peripheral parts, etc. Multi-heavy to a single frame where transmitting this data packet includes mapping this node transmission. Write request packet to connect via this sequence
F 附加的或另一選煜 令包括接收由結構命人為h接收此周邊零件介面匯流排命 命令中選取多重 7 、輸出/輸入(I/O)命令及記憶體 而其中傳送i資料ί ΐ式之周邊零件介面匯流排命令, 至此連結上之in々匕匕括映射此等不同型式之各個命令 J通逼如此使得包含不同型式之命令F Additional or another selection order includes receiving the structure command, receiving the peripheral parts interface, bus command, selecting multiple 7, output / input (I / O) commands, and memory, and transmitting i data. The peripheral parts interface bus command, so the in々dagger on the link maps each of these different types of commands J through forcing so that contains different types of commands
第18頁 486633 被傳送。 合併此等通 /輪入(I/O) 收此等多重 接收此等匯 由此等各別 之順序。 送此匯流排 周邊零件介 此主要位址 回應此匯流 應封包至此 命令包括於 最佳為’傳 第二周邊零 宣告記憶體 五、發明說明(14) 之資料封包經由此各別通道上 較佳為,指定此命令包括 零件介面匯流排之結構、輸出 間中之各別位址範圍。 附加的或另一選擇為,接 流排命令包括依一連續的順序 中傳送此資料封包包括保存經 資料封包間之此等匯流排命令 附加的或另一選擇為,傳 匯流排命令之型式以在此第二 以回應接收此封包之此通道。 較佳為,由此目的裝置在 零件介面匯流排接收一回應以 此連結傳送一包含此回應之回 面匯流排上之目標位址。 更佳為,接收此周邊零件 延遲處理請求,接續完成此延 體寫入,且其中傳送此匯流排 之前服務此宣告記憶體寫入。 包括置放此延遲處理請求於此 之一緩衝儲存器中,且允許此 儲存器。 道與此苐一周邊 及記憶體位址空 、不同型式之匯 >;IL排命令,卫甘 通道傳輸之此等 命令包括決定此 面匯流排上傳送 經由此第二周邊 排命令,且經由 第二周邊零件介 介面匯流排命令包括接收— 遲處理之如接績一宣告記憶 完成此延遲處理 送此匯流排命令 件介面匯流排中 寫入越過此緩衝 根據本發明之一較佳實施例,亦提供一種橋接於第一 及第二平行匯流排間之裝置,具有一匯流排處理之普通組Page 18 486633 was transmitted. Merge these pass / roll-in (I / O) receive these multiple receive these sinks in their respective order. Send the peripheral parts of this bus to the main address to respond to this bus. This command should be packaged to this order. It is best to include the second peripheral zero-declaration memory. 5. The data packet of the invention description (14) is better on this channel. To specify, this command includes the structure of the part interface bus and the respective address ranges in the output room. Additionally or alternatively, receiving the bus command includes transmitting the data packets in a continuous sequence, including storing these bus commands between the data packets. Additionally or alternatively, transmitting the bus command in the form of The second response is to the channel that received the packet. Preferably, the destination device receives a response on the part interface bus, and this link sends a target address on the return bus containing the response. More preferably, the peripheral part receives a delayed processing request, and then completes the extended writing, and the service writes the announcement memory before transmitting the bus. This includes placing this deferred processing request in one of these buffer memories and allowing this memory. The channel and the peripheral and memory address are empty, different types of confluences> The IL command, these commands transmitted by the Weigan channel include the decision to transmit on this bus via this second peripheral command, and via the second 2. The peripheral part interface interface bus command includes receiving-if the processing is delayed, the memory is announced, the delay processing is completed, and the delay processing is sent to the bus command interface. The bus interface writes over the buffer according to a preferred embodiment of the present invention. Provide a device bridged between the first and second parallel busbars, with a common set of busbar processing
486633 五、發明說明(15) 合及此等處理之順序規則控制執行,此裝置包括: 一目標通道轉接益,其設定於第一匯流排上之目標位 址接收一匯流排命令,結合此處理組合中之一處理,^命 令是藉由於第一匯流排上之一來源裝置發出用以藉由於^ =匯流排上之一目的裝置執行且產生包含所接收匯流排命 令之一資料封包;以及 一網路介面轉接器,設定經由一封包交換式網路上傳 达此貧料封包至此第二匯流排上之一主要位址,如此使得 ^t^ί位址回應此所接收之資料封包,&照此順序規則 ! t苐二匯流排至此目的裝置傳送此匯流排命令。 較佳為,一位址範圍包括此第一匯流排上之一位址空 標位址被指定至此目標通道轉接器。更佳為, 裝置映彻:且此各個位址鍾^ 此封包至包含此所被映射目標位址之 排上之% r此多個位址範圍包括於此第一匯流 個位址空間内之-各別位址範圍。 排命令,= ,此匯流排命令包括—發出的匯流 巨標通道==包包括-發出的資料封包,而其中此 一目標星分,甘、立 出的匯流排命令且映;=接收在此第一匯流排上之此發 封包之此通道;以及、u卩令之此位址至要傳送此發出的 一 ^適用於接收來自於此第二匯流排上此486633 V. Description of the invention (15) The order and control of the execution of these processes are controlled. The device includes: a target channel transfer benefit, a target address set on the first bus receives a bus command, and combines this In one of the processing combinations, the ^ command is issued by a source device on the first bus for execution by a destination device on the ^ = bus and generates a data packet containing the received bus command; and A network interface adapter configured to transmit this lean packet to a primary address on this second bus via a packet-switched network, so that the ^ t ^ ί address responds to the received data packet, & Follow this order! t 苐 The second bus to this destination device sends the bus command. Preferably, the one-bit address range includes one address space on the first bus, and the target address is assigned to the target channel adapter. More preferably, the device maps through: and each address clock ^% of this packet to the row containing the mapped target address r The multiple address ranges are included in the first confluent address space -Individual address ranges. Bus command, =, this bus command includes-the sent bus giant channel == packet includes-the data packet sent out, and one of the target star points, the bus command issued by Gan and Li, and is reflected; = received here This channel for sending packets on the first bus; and, the address of the u order to the one to send this ^ is suitable for receiving from this second bus on this
第20頁 五、發明說明(16) 網路之另一通道所傳送之— 包’適用於映射此另一通首封包且回應此進入的封 址及適用於傳送—進入的2此弟一匯流排上之—給定位 的封包。 °卩7此給定位址以回應此進入 附加的或另一選揠 用以藉由此目的裝置此”排命令包括1取命令 轉接器適用於產生—網,回應此讀取命令此目样‘; 。在-較佳實施例中取請求封包而在此網路 ,,取請求封包包括包括1出的讀取:; 目標通逭轉接器包括·· x出的項取睛求封包,而其中此 曰私早兀,复 出的讀取命令且適用二:=此第1流排 一 ΐ要單元,其適用於ίί:;;::1取請求封包;以: -匯流排上傳送—進入:=:讀取封包,適用於此第 較佳為,此主^,頃取命令。 f此3入的讀取命令:::f:進入的讀取資料以回 貝料要被傳送至此第二匯流排二一回應封包包含所接收 :道括-發出的寫入請寫八命令,此 知接為包括*· 封包,而其中此目標Page 20 V. Description of the invention (16) The packet transmitted by another channel of the network is applicable to the address that maps the first packet of this other channel and responds to this entry, and is applicable to the transmission-entry 2 this brother-bus Upper—The packet for positioning. ° 卩 7 This gives the location address in response to this entry. Additional or another option is used to install this for this purpose. The "row" command includes 1 fetch command adapter, which is suitable for generating-net, and responds to this read command. '; In the preferred embodiment, the request packet is fetched and in this network, the fetch request packet includes a read including: 1; the target communication adapter includes ... Among them, the private command is called early, and the read command that comes back is applicable to two: = This first stream is a key unit, which is suitable for ί: ;; :: 1 to fetch the request packet; to:-transfer on the bus- Enter: =: Read the packet. It is better to apply this command. This master ^ is a command. F This 3-input read command: :: f: The incoming read data is sent here as a reply. The second bus response packet contains the received: Dao-send out the write please write eight commands, this is known as including * · packet, and this target
5019^3607-PF.ptd 第21頁 以藉由目的裝置來執:為回排命令包括-寫入命令 '適用於產生-網路寫入嗜;封J入命令此目標通道轉接 施例中’此寫入而在此網路上傳輸。在 五、發明說明(17) 一目標單元 出的寫 一主要 一進入 一匯流 根 源平行 有此等 順序規 空間内 匯流排 及第二 合中之 來源裝 第一及 匯流排 及第二 及第二 資料封 至此各 根 及第二 入命令且 ασ 一 早凡,其 的寫入封 排上傳送 據本發明 匯流排及 匯流排具 則控制執 目標通道 之第—及 通訊,日 目標位址 一或多個 置發出用 第二目的 命令之第 網路轉接 資料封包 主要位址 包,依照 別目的裝 據本發明 周邊零件 ,其適 適用於 適用於 包且回 一進入 之一較 第一及 有一匯 行,此 轉接器 第二位 適用於 接收匯 處理且 以藉由 裝置執 一及第 器,設 至分別 ’如此 此順序 置傳送 之 較 用於接收在 產生此發出 接收來自於 應此進入的 的寫入命令 佳實施例, 第二目標平 流排處理之 裝置包括: ,其指定此 址範圍以分 分別於此第 流排命令, 是藉由於此 分別於第一 行,且適用 二資料封包 定分別於各 於第一及第 使得於此主 規則經由此 此匯流排命 佳實施例, 流排間之裝 此第一匯流排上之此發 的寫入凊求封包;以及 此第二匯流排所傳送之 寫入封包,適用於此第 〇 亦提供一種橋接於一來 行匯流排間之裝置,所 普通組合及此等處理之 來源匯流排上之一位址 別與此第一及第二目標 一及第二範圍内之第一 此匯流排命令結合此組 來源匯流排上之至少一 及第二目 於產生包 ;以及 別序列連 二目標匯 要位址回 標匯流排上之 含此所接收之 結傳送此第一 流排上之第一 應此所接收之 第一及第二目標匯流排 令。 亦提供一種橋接於第_ 置,包括: 介面匯5019 ^ 3607-PF.ptd Page 21 is executed by the destination device: Include the write command for the backflow command-write command 'applicable to generate-network write addiction; block J into the command in this target channel transfer example 'This write is transmitted on this network. In the description of the invention (17), a target unit writes a main one and enters a bus root in parallel. There are buses and second sources in the sequence space. The first and the buses and the second and the second are installed. The data is sealed so far and the second entry order and ασ are early. The writing envelope of the data is transmitted according to the invention. The bus and the bus control control the execution of the target channel—and the communication. The target address is one or more. The main address packet of the second network transfer data packet that is issued with a second purpose command is installed according to other purposes according to the present invention. The peripheral part is suitable for the package and is one of the first and the second one. OK, the second position of this adapter is suitable for receiving sink processing and is set by the device first and the first, respectively, so that the order is set for transmission, which is more used for receiving. The preferred embodiment of the write command, the second target advection processing device includes:, which specifies this address range to be divided into this second order command, because Separate in the first row, and apply the two data packets to the first and the first, respectively, so that the main rule is passed through this embodiment of the bus, and the packets on the first bus are installed between the buses. The write request packet; and the write packet transmitted by this second bus is applicable to this number. It also provides a device that bridges between the buses of a bank, the common combination and the source bus of these processes. One address category and the first and second destinations within the first and second ranges of the first and second bus commands combined with at least one and the second destination on the set of source buses to generate packets; and another sequence with two destinations The sink address returns the received bus on the bus with the received node to transmit the first and second target bus orders received on the first bus. It also provides a bridge to the _, including: interface sink
486633486633
五、發明說明(18) 一目標通道轉接器,適用於在第一周邊零件介面匯法 排上之目標位址接收一周邊零件介面匯流排命今,1 〜 7 此命今 是藉由於第一周邊零件介面匯流排上之一來源裝置發中 此命令指示第二周邊零件介面匯流排上之一目 ^ μ ’ Μ我置實預 一周邊零件介面匯流排處理,且適周於產生包含此所接兄 之匯流棑命令之資料封包;以及 ‘ ^V. Description of the invention (18) A target channel adapter, suitable for receiving a peripheral component interface bus command at a target address on the first peripheral component interface bus, 1 to 7 This command is due to the first A source device on a peripheral part interface bus issued this command to instruct a second item on the second peripheral part interface bus ^ μ 'Μ I set the pre-processing of a peripheral part interface bus, and it is suitable to generate Data packet for receiving confluence order from brother; and '^
一網路轉接器,設定經由一序列連結傳送此資料封包 至此苐二周邊零件介面匯流排上之一主要位址,如此使得 於此主要位址回應此所接收之資料封包,依照周邊零件介 面順序規則經由此第二周邊零件介面匯流排至此目的裝置 傳送此匯流排命令。 在一較佳實施 一發出的匯流排命 其中此目標 目標單元, 之此發出的 此發出的資料封包 ,丨· H5 — 土要單兀, 進入的封 包,而 流排上 傳送之 匯流排上傳送 以 圖式之 為 明顯易 下配合圖式 簡單說明: 了讓本發明 懂’所附圖 令’此資料封包包括一發出的資料封 通道轉接器包括: 其適用於接收在此第一周邊零件介面匯 周邊零件介面匯流排命令且適用於產生 ;以及 其適用於接收來自於此第二匯流排上所 包且回應此進入的封包,適用於在此第 進入的周邊零件介面匯流排命令。 以及較佳實施例以說明本發明。A network adapter configured to send this data packet to a primary address on the second peripheral component interface bus through a serial link, so that this primary address responds to the received data packet in accordance with the peripheral component interface The order rule transmits the bus command through the bus of the second peripheral part interface to the destination device. In a preferred implementation, the bus sent out specifies the target unit, and the data packet sent out here, H5 — the single packet, the incoming packet, and the bus sent on the bus is sent on the bus. The figure is obvious and easy to match with the simple description: In order to make the present invention understand 'the attached figure', this data packet includes a data packet channel adapter including: it is suitable for receiving the first peripheral parts The interface bus peripheral part interface bus command is suitable for generating; and it is suitable for receiving packets from this second bus and responding to this entry, and is applicable to the peripheral part interface bus command entered here. And preferred embodiments to illustrate the invention.
^上述和其他目的、特徵、和優點能更 衣說明如下:^ The above and other purposes, features, and advantages can be explained as follows:
486633 五、發明說明(19) 第1圖係舉例說明在本發明之一較佳實施例中之一橋 接於多路的封包交換式網路上平行匯流排間之系統之方塊 圖。 第2圖係舉例說明在本發明之一較佳實施例中在第1圖 之系統中之一橋接裝置詳細構造之方塊圖。 第3圖係舉例說明在本發明之一較佳實施例中之在橋 接上實現一讀取處理之方法之流程圖。 第4圖係舉例說明在本發明之一較佳實施例中之經由 一封包交換式網路上傳輸一匯流排命令之方法之流程圖。486633 V. Description of the invention (19) Figure 1 is a block diagram illustrating a system bridged between parallel buses on a multi-channel packet-switched network in a preferred embodiment of the present invention. Fig. 2 is a block diagram illustrating the detailed construction of a bridge device in the system of Fig. 1 in a preferred embodiment of the present invention. Fig. 3 is a flowchart illustrating a method for implementing a reading process on a bridge in a preferred embodiment of the present invention. FIG. 4 is a flowchart illustrating a method for transmitting a bus command via a packet-switched network in a preferred embodiment of the present invention.
第5圖係舉例說明在本發明之一較佳實施例中之經由 一封包交換式網路上服務一所接收之匯流排讀取請求之方 法之流程圖。 第6圖係舉例說明在本發明之一較佳實施例中在第2圖 之橋接裝置之更詳細構造之方塊圖。 符號說明 2 0〜網路糸統; 28、32、38〜橋接裝置; 22、34、40〜周邊零件介面匯流排; 3 0〜無窮頻帶封包交換式網路; 26〜周邊及輸出/輸入(I/O)裝置; 36、42〜目標周邊裝置; 24〜中央處理機; 5 0〜目標通道轉接器; 5 2〜交換器;FIG. 5 is a flowchart illustrating a method for serving a received bus read request via a packet-switched network in a preferred embodiment of the present invention. Fig. 6 is a block diagram illustrating a more detailed construction of the bridging device of Fig. 2 in a preferred embodiment of the present invention. Explanation of symbols 2 0 ~ network system; 28, 32, 38 ~ bridge device; 22, 34, 40 ~ peripheral component interface bus; 3 0 ~ infinite band packet switching network; 26 ~ peripheral and output / input ( I / O) device; 36, 42 ~ target peripheral device; 24 ~ central processing unit; 50 ~ target channel adapter; 52 ~ switch;
5019-3607-PF.ptd 第24頁5019-3607-PF.ptd Page 24
^OOOJJ^ OOOJJ
54〜PCI目標單元(PCIT); 56〜PCI主控單元(pciM); 58、60〜緩衝儲存器; i3〇〜先進先出(FIFO)佇列; e〜寫入請求;134〜裁決器 幸父佳貫施例: 统20匕圖上舉例說明在本發明之-較佳實施例中之-系 广接於夕路的周邊零件介面(periph㈣i c⑽p〇_t54 ~ PCI target unit (PCIT); 56 ~ PCI master control unit (pciM); 58, 60 ~ buffer memory; i3〇 ~ first-in-first-out (FIFO) queue; e ~ write request; 134 ~ ruler Father Jiaguan Example: An example of the peripheral part interface (periph㈣i c⑽p〇_t) that is widely connected to Xilu in the present invention-the preferred embodiment-is illustrated on the system diagram.
士PCI)匯流排22、34、及40之方塊圖。各pci i 由橋接裝置28、32或38連接至一無窮頻帶 路:。1二IB)封包交換式網路30,各對橋接裝置及紹 橋接於士匯流排之間之一pci_t〇_pci(p2p)橋接 τπ以之較佳貫施例將參照PCI匯流排及IB網路,將可 =二解Ϊ發明之原理將應用於橋接於其他型式之平行匯访 排間’ f應用於遵守不同標準封包交換式網路上。(PCI) bus block diagram of buses 22, 34, and 40. Each pci i is connected to an infinite frequency band by a bridge device 28, 32 or 38. 1 2 IB) packet-switched network 30, each pair of bridge devices and one bridge between the buses pci_t0_pci (p2p) bridge τπ, a better implementation example will refer to the PCI bus and the IB network The principle of the invention can be applied to bridges of other types of parallel exchanges, and it is applied to packet-switched networks that comply with different standards.
於第1圖中所示之例子,匯流排2 2上之一主要裝置, 士口一中央處理機(cpu)24,要去讀來自於或寫至匯流排34 士之-目標周邊裝置36,主要裝置發出一適當PCI :令至位於PCI匯流排22之位址空間内之一位址,此位址 疋分配給橋接裝置28,其餘之PCI匯流排22位址空間一 是分配給匿流排22上之周邊及輸出/輸入(ί/〇)裝置26。又 接裝置28產生-基於CPU請求之16命令且經由網路3〇將/ 傳达至橋接裝置32,橋接裝置32解碼ίβ命令及產生適告、 PCI匯流排命令經由匯流排34傳送至周邊裝置”,周邊田裝In the example shown in Figure 1, one of the main devices on the bus 22, taxi-central processing unit (cpu) 24, is to read from or write to the bus 34 taxi-target peripheral device 36, The main device issues an appropriate PCI: order an address located in the address space of the PCI bus 22, this address is allocated to the bridge device 28, and the remaining PCI bus 22 address space is allocated to the hidden bus Peripheral and output / input (ί / 〇) device 26 on 22. Another device 28 generates-16 commands based on the CPU request and transmits / communicates to the bridge device 32 via the network 30. The bridge device 32 decodes the β command and generates a report. The PCI bus command is transmitted to the peripheral device via the bus 34. ", Field dress
486633 五、發明說明(21) 置回傳適當的回應(資料、一讀取命令之情況,一寫人 令之一確認)至橋接裝置36。橋接裝置36產生一庳15 f封包且經由網路30將回應封包回傳至橋接裝置28'择回 裝置28經由匯流排22將回應封包傳送至cpu。 巧接 依照PCI標準,匯流排2 2上之各裝置可具有多重 址"視窗”,或節區,於匯流排22上之各記憶體、結構的^ 址空間中分配給它。較佳為,3個位址空間之各個*-間中之此些視窗中之16個視窗是分配給橋接 二 可分配較多或較少視窗。此些節區之配置及定義之复:: 點是說明在上述專利申請標題”經由封包交換式模組之平 仃匯流排通訊",關於系統2〇之啟動及 邊ί置36之:位址,此位址是在分配給二置 ,、之位址視囪内。KCPU因此定址所有記憶體對 2匯流排34上之裝置之讀及寫命令至ρπ記憶體位址空 J :之橋接裝置28之適當記憶體視窗;所有結構之讀及寫 〒々至PCI結構位址空間中之橋接裝置28之適當結構視 窗二及所有I/O之讀及寫命令至PCI結構位址空間中之橋接 衣罝2f之適當結構視窗。可選用地,在分配給橋接裝置2 8 t視窗中,亦有結合經由網路30至橋接裝置32之通道之視 窗,用以定址匯流排40上之周邊裝置42,未顯示於圖式中 之附加的PC I匯流排。 分配給橋接裝置28之各位址視窗是結合一不同通道, 或在IB網路30中之工作佇列對(w〇rk Queue ,WQp), 如上述,在IB網路3〇中之各通道經由網路對應至一固定路486633 V. Description of the invention (21) Return the appropriate response (data, the condition of a read command, one of the writer's order) to the bridge device 36. The bridge device 36 generates a 15f packet and sends the response packet back to the bridge device 28 through the network 30. The selection device 28 sends the response packet to the CPU via the bus 22. Coincidentally, according to the PCI standard, each device on the bus 22 may have multiple addresses " windows ", or sections, allocated to it in the address space of each memory and structure on the bus 22. It is preferably , 16 of these windows in each of the 3 address spaces are allocated to the bridge 2. More or fewer windows can be allocated. The configuration and definition of these sections are duplicated: Point is description In the title of the above patent application "Platform Bus Communication via Packet Switching Module", regarding the start and side of System 20: 36, this address is assigned to Erzhi, Inside the viewing tunnel. The KCPU therefore addresses all memory read and write commands to the device on 2 bus 34 to ρπ memory address empty J: the appropriate memory window of bridge device 28; all structures read and write to the PCI structure address The appropriate structure window 2 of the bridge device 28 in the space and all I / O read and write commands to the appropriate structure window of the bridge clothes 2f in the PCI structure address space. Optionally, in the 2 8 t window allocated to the bridge device, there is also a window combined with the channel through the network 30 to the bridge device 32 to address the peripheral device 42 on the bus 40, which is not shown in the figure. Additional PC I bus. The address windows assigned to the bridging device 28 are combined with a different channel, or a work queue pair (work queue, WQp) in the IB network 30. As described above, each channel in the IB network 30 passes through Network maps to a fixed road
五、發明說明(22) 及服務層級,且封包之順庠 之所右抖’ + + 丨貞序疋、准持在一給定通道所攜帶 包之順序之類似方法是習知技術 之,、他型式網路中已知的。此通道 及寫請求至PCI匯流排34(彳_ Μ 4 、,'口果所有5貝 之一认定4八s /(隐肢、結構或丨/〇)位址空間中 在此:由橋接裝置32來接收’ τ序中它們是藉由橋接裝置28來傳送。周邊裝 置db之回應疋相同地僖回$括^ 返回至CPU 24。 橋接叙置32及在正確的順序中 f置2第8 2 之圖^舉播例說明在本發明之—較佳實施例中之橋接 二造之方塊圖°裝置32及38之結構亦如此圖 Ch不、、口 H。1置28包括一目標通道轉接器(Target 器5ΡγΓγ^、Γ ΚΑ)5!及一交換器52,目標通道轉接 二供六祕β 一笔仙·排22,交換器耦接至網路30。此目的之 又、疋°兄明在上述專利申請號碼60/ 1 52, 849及60/175 ,339 ’交換器52之設計是超出本專利申請範圍之外,然 3二!封包交換符合無窮頻帶規格,或至少具有在-通 =封包順序之特徵’將適用於實現交換器5 2之功 能0 TCA 50疋作為轉換PCI命令(或循環)進入ΙΒ封包,及 ^之亦然。TCA包括一PCI目標單元(pciT)54及一 ρ(:ι主控❶ =兀(PCIM)56,PCIT 54回應來自於ρπ匯流排μ上之執 二,匕們是藉由一匯流排主控,如cpu 24來初始化。特別 :PC 1 T由PC I匯流排接收讀及寫命令與產生適當I B讀及 寫知求封包以經由交換器52傳送。當由目標匯流排接收回V. Description of the invention (22) and service level, and the right way of the packet's right hand shake '+ + 丨 Zhen Xu, a similar method of holding the order of the packets carried in a given channel is a known technology, Known in other types of networks. This channel and the write request to the PCI bus 34 (彳 _Μ 4 ,, 'one of all 5 shells identified as 48 s / (hidden limb, structure or 丨 / 〇) address space here: by the bridge device In order to receive 32, they are transmitted by the bridge device 28. The response from the peripheral device db is similarly returned to $ 24 and returned to the CPU 24. The bridge is set to 32 and in the correct order, f is set to 2 and 8 Figure 2 shows an example of a block diagram of a bridge made of two in the preferred embodiment of the present invention. The structure of the devices 32 and 38 is also the same as shown in Figure Ch. Connector (Target device 5PγΓγ ^, Γ ΚΑ) 5! And a switch 52, the target channel is transferred to two for six secrets β a pen and row 22, the switch is coupled to the network 30. This purpose, ° Brother Ming in the above patent application numbers 60/1 52, 849 and 60/175, 339 'The design of the switch 52 is beyond the scope of this patent application, but 32! Packet exchange meets the infinite band specification, or at least -Pass = characteristics of packet sequence 'will be applicable to implement the function of switch 5 2 0 TCA 50 疋 as a conversion PCI command (or loop) to enter IB Package, and vice versa. The TCA includes a PCI target unit (pciT) 54 and a ρ (: ι master control unit = ((PCIM) 56, PCIT 54 responds to the second from the π bus μ. It is initialized by a bus master, such as CPU 24. In particular: PC 1 T receives read and write commands by PC I bus and generates appropriate IB read and write packets for transmission via switch 52. When transmitted by the target Bus receives back
486633 五、發明說明(23) 1 ί包UCIT 24接收此些封包及於pci匯流排22上產生 適*回應循環(回傳資料以回應—讀取請求或一寫入請求 一方面,PCiM 56是作為接收來自網路30之IB 二藤::Λ包,1 β讀及寫請求封包是藉由-遠端發源 & 主控裝置來傳送。PCIM 56轉換此些請求成 為匯流排22上之適當讀及寫命令,此例中是目標匯流排。 PCIM之後封存所產生之回應以傳回到發源匯流棑。 第3圖係舉例說明在本發明之一較佳實施例中之在ib 網路上實現一PC;[讀取處理之方法之流程圖。在一讀取浐 求步驟70 ’ CPU 2 4發出一讀取命令,其是指㈣^ 置36。如上述,CPU傳送請求至一位址,此位址是分配ς TCA 50之匯流排22之位址空間内之一適當視窗内之—位 址0486633 V. Description of the invention (23) 1 packet UCIT 24 receives these packets and generates a suitable response loop on the PCI bus 22 (returning data in response to a read request or a write request. On the one hand, PCiM 56 is In order to receive the IB Nito :: Λ packets from the network 30, 1 β read and write request packets are transmitted by the -remote source & master control device. PCIM 56 converts these requests to become appropriate on bus 22 Read and write commands, this example is the target bus. The response generated after PCIM is archived to return to the originating bus. Figure 3 illustrates the implementation on the ib network in a preferred embodiment of the present invention. A PC; [Flow chart of the method of reading processing. In a reading request step 70 ', the CPU 24 sends a reading command, which refers to the setting 36. As described above, the CPU sends a request to a bit address, This address is in an appropriate window within the address space of bus 22 allocated TCA 50—address 0
在一確認步驟72,PC IT 54利用一PCI”再試,,回應匯流 排22上之中央處理機(cpu) 24以回應讀取請求,通知Cpu請 求資料尚不可用,所以CPU應稍後再試此請求。如上述,^ ▲ CPU發出一宣告記憶體寫入(p〇sted memory write,pwm )命令,PC I T立即確認此命令,cpu必須繼續再試非宣告讀 及寫請求,直到收到來自於目標匯流排3 4之延遲回應為^ 。當它發出再試回應的同時,PC I T於一缓衝儲存器58中士己 錄此讀取請求並配置空間以接收預期來自於裝置3 6之讀取 回應資料。讀取請求是以充分的確認資訊記錄在緩衝错存 器中所以PCIT將可以聯繫讀取回應封包,讀取回應封包= CPU收到來自於裝置36之特殊讀取請求。 匕疋In a confirmation step 72, the PC IT 54 uses a PCI "to retry, and responds to the central processing unit (cpu) 24 on the bus 22 in response to the read request, informing the CPU that the requested data is not yet available, so the CPU should retry this later As mentioned above, ^ ▲ The CPU issues a declared memory write (pwm) command. PC IT immediately confirms this command. The CPU must continue to retry non-declared read and write requests until it receives a request from the target. The delayed response of bus 3 4 is ^. When it sends a retry response, PC IT records this read request in a buffer memory 58 and allocates space to receive the read response expected from device 36. Data. The read request is recorded in the buffer memory with sufficient confirmation information so PCIT will be able to contact the read response packet. The read response packet = the CPU received a special read request from device 36. Dagger
5019-3607-PF.ptd 第28頁 486633 五、發明說明(24) 如上述表1所示,CPU 24可傳送5種不同型式之pc I讀 取請求,在一封包傳送步驟74,依讀取請求之型式及位 址,PCIT產生一適當IB遠端直接記憶體存取(Rem〇te Direct Memory Access,RDMA)讀取請求封包,及將此封 包傳送至交換器52。PCIT在精確的順序中發出ίβ RDMA, 在此精確的順序中接收來自於匯流排22之對廡的括月宜八 令。而在PCU取命令下映射PCI位址至1定 虛擬位址(及邏輯位址),將對應的IB讀取請求 標匯流排34上之橋接裝置32及由那裡到周邊裝置36。^ PCI命令映射至IB請求及網路通道之其他觀點是說明在上 述專利申請標題|·經由封包交換式模組之平行匯流排通訊 列巴按叹步驟·υ,秸田偫得裝置2 RDMA讀取請求封包是藉由橋接裝置32來 : 目的中,雜然裝置32之其他設計亦可,二本貫施例 大體上是與裝置28 一致。(事實上,太 衣置32一之構 所提供之於PCI位址視窗及IB通道間之二j之較佳貫施你 士許在?匯流排上之不同型式的橋接'射之-優點是它 非橋接裝置所特定或私有的。再者,^封包中之資訊· 至任何Ιβ-應允的終止-點’如網路3〇,接裳置可傳送封 而不僅僅是其他橋接裝置。)在接收之—I/O控制器, =52傳送封包至此裝置之% ^上,裝置32之交 緩衝儲存器60中,t糾陌、六^ 其將此請求置於一 、 t到匯流排能夠服務此請求//於 486633 五、發明說明(25) 裝置32之PCIM 56映射IB封包之通道及虛擬位址至匯 流排34之PCI周邊裝置36之實體位址。依RDMA封包之通道 及資料長度’PCIM選擇PCI讀取命令之適當型式以傳谈至 周邊裝置,且接收符合PC I匯流排程序之請求資料,pC J M 產生一 IB讀取回應封包以傳回至橋接裝置28。在一回應傳 送步驟80,回應封包被提交至交換器52且藉由交換器52經 由網路3 0傳送。於服務緩衝儲存器6 〇中之下一讀取或寫入 請求前,P C I Μ傳送讀取回應封包以完成延遲讀取處理 (delayed read transaction,DRC),延遲寫入完成 (delayed write completion,DWC)確認是同樣地給定高 於新懸而未決的請求之優先權。 在一回應接收步驟8 2,當IB讀取回應封包回傳至橋接 裝置28時,交換器52將其發送至pc IT 54,PC IT 54緩衝儲 存此資料。PC IT將回應資訊與緩衝儲存器58中之懸而未決 的请求比較及再試來自緩衝儲存器之目前已完成之延遲讀 取請求(delayed read request,DRR)。在一資料傳送步 驟84 ’在CPU 24下一次再試此讀取請求時,pcn 54經由 匯流排22傳送所接收之資料至cp[J。當任何宣告記憶體寫 入(posted memory write,PMW)命令於 pci 匯流排 22 上發5019-3607-PF.ptd Page 28 486633 V. Description of the invention (24) As shown in Table 1 above, the CPU 24 can transmit 5 different types of PC I read requests. In step 74 of a packet transmission, according to the read The type and address of the request, the PCIT generates an appropriate IB Remote Direct Memory Access (RDMA) read request packet, and transmits the packet to the switch 52. The PCIT issues β RDMA in a precise sequence, in which it receives eight orders from the confrontation of the bus 22. Under the PCU fetch command, the PCI address is mapped to a fixed virtual address (and logical address), and the corresponding IB read request is marked to the bridge device 32 on the bus 34 and from there to the peripheral device 36. ^ The other point of view that the PCI command is mapped to the IB request and the network channel is to explain in the above patent application title | · Parallel bus communication via packet-switched module; The request packet is obtained by bridging the device 32. For the purpose, other designs of the heterogeneous device 32 are also possible. The second embodiment is generally consistent with the device 28. (In fact, the best implementation provided by the Taiyizhi 32i structure between the PCI address window and the IB channel is the best implementation of the different types of bridges on the bus. The advantage is- It is not specific or private to the bridging device. Furthermore, the information in the packet to any Iβ-accepted termination-points, such as the network 30, can be used to send packets, not just other bridging devices.) In the receiving-I / O controller, = 52 sends a packet to %% of this device, in the buffer memory 60 at the intersection of device 32, t correction, six ^ It places this request on one, t to the bus can Serving this request // on 486633 V. Description of the invention (25) The PCIM 56 of the device 32 maps the channel and virtual address of the IB packet to the physical address of the PCI peripheral device 36 of the bus 34. According to the channel and data length of the RDMA packet, the PCIM selects the appropriate type of the PCI read command to talk to the peripheral device, and receives the request data in accordance with the PC I bus process. The pC JM generates an IB read response packet to return to桥 装置 28。 The bridge device 28. In a response transmission step 80, the response packet is submitted to the switch 52 and transmitted by the switch 52 via the network 30. Before the next read or write request in the service buffer memory 60, the PCI M transmits a read response packet to complete a delayed read transaction (DRC), and a delayed write completion (DWC) ) Confirmation is equally given priority over newly outstanding requests. In a response receiving step 82, when the IB reads the response packet back to the bridge device 28, the switch 52 sends it to the pc IT 54, and the PC IT 54 buffers and stores this data. The PC IT compares the response information with the pending request in the buffer memory 58 and retries the currently completed delayed read request (DRR) from the buffer memory. In a data transfer step 84 ', when the CPU 24 next retries the read request, the pcn 54 transmits the received data via the bus 22 to cp [J. When any posted memory write (PMW) command is issued on the pci bus 22
出而回應資料是在缓衝儲存器中等待時,pcIT 54直到PMW 完成時才會試圖將資料放置在匯流排上,以保證能遵守 | pci處理順序規則。 弟4圖係舉例说明在本發明之一較佳實施例中之轉換 一 P C I匯流排命令成一 IB封包之方法之流程圖。此轉換是While the response data is waiting in the buffer memory, pcIT 54 will not attempt to place the data on the bus until the PMW is completed to ensure compliance with the pci processing sequence rules. Figure 4 is a flowchart illustrating a method for converting a PCI bus command into an IB packet in a preferred embodiment of the present invention. This conversion is
5019-3607-PF.ptd5019-3607-PF.ptd
486633 五、發明說明(26) p用二第】之步驟74中,其使得9種不同型式之 寫請胃求封包卩。表1被映射至1B網路上之適當讀及 包目交換模組來傳送,在封 訊協定雄晶之 颌i <回應,此封包型式是由結合IB通 u協疋堆宜之—延伸傳輸表頭Extended Transport486633 V. Description of the invention (26) Step 74 of the second application], which enables the writing of 9 different types, please ask the stomach to seal the bag. Table 1 is mapped to the appropriate reading and packet exchange module on the 1B network for transmission. In the message agreement, the male jaw i < responds. This packet type is combined with the IB communication protocol to extend the transmission. Header Extended Transport
Header,ΕΤΗ)來指定,讀及寫操作是由一遠端直接圮憒 = =ire:: M_y AcCesS,_)ΕΤΗ 來行;: 卢擬位址來Ρ二寫凊求之第一訊息包含一RDMA ΕΤΗ指定— f iUi:,一存取鍵(R-key)及資料緩衝儲存器之 (其可能接,A寫入封包)之負载。接收寫二 體回應一碟認封包,具有一讀認ETH(Ackn〇wiedge eth): ΑΕΤΗ亦呈現在接收讀取請求之一實體所回傳之讀取回 應封包之中。此讀取回應封包亦具有一含有所請求資料之 一負載。習知技術之技巧將辨識類似此些亦在封包交換式 網路内發生之其他技術已知之封包類型及操作。 在一循環接收步驟90,橋接裝置28之代17 54接收於 PC I匯流排上之一讀或寫命令。在一位址空間確定步驟 9 2,PC IT檢查3個PC I位址空間中之何者是被命令所定址: 記憶體、結構或I/O cPCIT確定⑺通道上之一對岸封包依 位址空間被傳送,因此,在一1/0封包產生步驟94,若此 位址是在I/O空間中,一RDMA讀或寫封包被傳輸在通道, 例如”上。此例中,資料緩衝儲存器之一長度將不大於Header, ΕΤΗ) to specify, read and write operations are performed directly by a remote end = = ire :: M_y AcCesS, _) ΕΤΗ ;: The first message requested by the Lu address is written to include two RDMA ΕΤΗ designation — f iUi :, an access key (R-key) and the data buffer memory (which may be connected, A write packet) load. The receiver writes a response to a disc acknowledgement packet, and has a read acknowledgement ETH (Acknowiedge eth): ΑΕΤΗ also appears in the read response packet returned by an entity receiving the read request. This read response packet also has a payload containing the requested data. Techniques of known techniques will identify packet types and operations similar to these other techniques known to also occur in packet switched networks. In a loop receiving step 90, the bridge device 28 instead of 17 54 receives a read or write command on the PC I bus. In the address space determination step 92, the PC IT checks which of the three PC I address spaces is addressed by the command: memory, structure, or I / O cPCIT determines one of the on-channel packets on the channel by address space It is transmitted, therefore, in a 1/0 packet generation step 94, if the address is in the I / O space, an RDMA read or write packet is transmitted on the channel, such as ". In this example, the data buffer storage One of the length will not be greater than
5019-3607-PF.ptd 第31頁 486633 五、發明說明(27) 32位元’符合PCI協定。(此通道數目及下面所引用之其他 通道數目是隨意選擇的以用來舉例。)在一結構封包產生 步驟96,另一方面,若此位址是在結構空間中,所對應 RDMA讀或寫封包被傳輸在通道” 上。此例中,資料緩衝 儲存為之長度同樣地將不大於4位元組,如位元組可用 (Byte Enable,BE)位元所指出之主要裝置(cpu 24)所寫 之位元,符合P C I協定。 在一記憶體封包選用步驟98,若代1匯流排命令位址 是在PCI匯流排記憶體空間中,所對應仙“讀或寫封包被 指定在通道” C”上傳送。]^封包之產生取決於它是否攜帶 讀或寫請求。如表1所示,有兩種型式之記憶體寫入處 理·寫入,及寫入而無效。在一無效步驟1〇〇,它是確定 是否目前循環是一寫入而無效循環。若如此的話, MWI設定步驟1〇2 , —專用的記憶體寫入而無效(Mem〇ry Wnte and Invalidate,MWI)位元是設定在 R])MA 寫入 之結構部分中。在一寫入封包傳送步驟1 〇4,以pC丨耷 命令指定之實際資料長度所給定之一資料 J入 包。對於記憶體及I/O寫入命令,輕私么你田 千街封 平又仏為使用一 I R值译h 包,其不明確指定匯流排34上之一 1寻达封 1立址。橋接裝w μ 映射所產生PCI命令至目的裝置36之一入人於衣置U之後 另一方面,結構寫入命令,較# 玎緒廿為。5019-3607-PF.ptd Page 31 486633 V. Description of the invention (27) 32-bit 'conforms to the PCI agreement. (The number of channels and the number of other channels referenced below are arbitrarily selected for example.) In a structured packet generation step 96, on the other hand, if the address is in the structure space, the corresponding RDMA read or write The packet is transmitted on the channel ". In this example, the length of the data buffer will be no more than 4 bytes, as the main device (cpu 24) indicated by the Byte Enable (BE) bit The written bit conforms to the PCI protocol. In a memory packet selection step 98, if the generation 1 bus command address is in the PCI bus memory space, the corresponding "read or write packet is specified on the channel" C ". ] ^ A packet is generated depending on whether it carries a read or write request. As shown in Table 1, there are two types of memory write processing and write, and write without effect. In an invalid step 100, it is determined whether the current cycle is a write and an invalid cycle. If so, the MWI setting step 102, the dedicated memory write and invalid (MWI) bit is set in the structure part of the R]) MA write. In a write packet transmission step 104, one of the data J given by the actual data length specified by the pC 丨 耷 command is packed into the packet. Regarding the memory and I / O write commands, you do n’t want to use a private packet to translate the H packet, which does not explicitly specify one of the buses 34 1 to find the address 1 to the address. The bridge device w μ maps the PCI command generated to one of the destination devices 36 after the user places it on the other hand. On the other hand, the structure write command is better than # 玎 绪 廿.
1土 马使用—IR 入封包且指定匯流排34上之要寫入資料之位KDMA寫 是’PCI寫入命令可被映射至ΙΒ寫入或ΙΒ傳址。另一選擇 於主要裝置24與目的裝置36如何石氣 、4包’取決 -互動。各例中之映射較佳1 Native use—IR enters the packet and specifies the bit of data to be written on the bus 34. KDMA write Yes' The PCI write command can be mapped to IB write or IB address. Another option depends on the interaction between the main device 24 and the destination device 36. Better mapping in each case
5019-3607-PF.ptd 第32頁 五、發明說明(28) 為結合所指定IB通道。 右一讀]^封勺 命令,一RDMa讀匕,廷步驟1 06,若遇到一pci記憶體讀取 封包中之資料=对包被傳送於通道C上。此例中,RDMA 決定。對於記^ ^是由PCI記憶體以讀取之型式及長度來 一快速緩衝儲讀取列,資料長度是由主要裝置24之下 於記憶體讀取多^之=所要讀取之記憶體長度來決定。對 所要讀取之快遠蜂二資料長度是由記憶體中之下一頁邊界 第5圖係舉;:說二倚存區之多列來給定。5019-3607-PF.ptd Page 32 V. Description of the Invention (28) The IB channel specified for the combination. Right reading] ^ Sealing command, an RDMa reading command, step 1 06, if a pci memory is encountered to read the data in the packet = the packet is transmitted on channel C. In this example, RDMA is determined. For the memory ^ ^, the PCI memory uses the read type and length to quickly store the read row. The data length is read by the main device 24 under the memory. ^ Of = the length of the memory to be read To decide. Yes The length of the data to be read is determined by the next page boundary in the memory.
P 一 IB RDMA讀取請求封f本發明之一較佳實施例中之轉換 之流程圖。此轉換4、包成為—PC1匯流排讀取命令之方法 更說明在上述專利第3圖之方法中之步驟78中,其 匯流排通訊,,。在一封3 ‘題”經由封包交換式模組之平行 由PCIM 56來接收。在$接收步驟1 10,讀取請求封包是藉 封包之IB通道。一;道決定步驟U2,PCIM檢查接收 上接收,PCIM發取步驟U4,若封包是在通道八 置。同樣地,在—結槿^取命令至代1匯流排上之適當裝 接收,PCIM發出—:構:取步驟11 6,若封包是在通道B上 產生在一同樣的方;胃取命令°1/〇及結構寫入命令是 若RDMA讀取請求县六、畜、苦 憶體讀取命令。在一Λ疋且在通逼c上接收,其對應至—記 封包之資料長度決定:二長度檢查步驟118,PCIM 56依ΙΒ 八yv λ. '' c I匯流排上發出何種形式之讀取 命令。在一讀取步驟12Q,了於 '〜靖取 發出-簡單的PCI記憶體續;於4:凡組’則 心,取命令。在一讀取列步驟1 2 2,P-IB RDMA read request encapsulation f Flow chart of conversion in a preferred embodiment of the present invention. This conversion 4. The packet becomes-the method of the PC1 bus read command. It is further explained in step 78 in the method of the above-mentioned patent 3, the bus communication. In a 3 'question', the packet is received by the PCIM 56 in parallel with the packet switching module. In the $ receiving step 1 10, the read request packet is the IB channel of the borrowed packet. First, the decision step U2, the PCIM checks the receiving When receiving, the PCIM sends step U4, if the packet is set on channel eight. Similarly, the -Make ^ fetch command to the appropriate device on the bus 1 to receive, the PCIM sends-: structure: take step 116, if the packet It is generated on the same side on channel B; the stomach fetch command ° 1 / 〇 and the structure write command are read commands if the RDMA read requests the county, animal, and Memories. Received on c, which corresponds to the data length determination of the packet: the second length check step 118, PCIM 56 according to IB eight yv λ. '' c I what kind of read command is issued on the bus. In a read step 12Q, I issued in '~ Jing fetch-simple PCI memory continued; in 4: where the group' is, take the command. Steps 1 2 2 in a read column,
5019-3607-PF.ptd 第33頁 486633 五、發明說明(29) 若資料長度是大於4位元組,但並不跨 之列邊界,則pc IM發出一記憶體讀取列可人决入速緩衝轉 列項取步驟124,若資料長度是大於4位元了二。在〜多 越一快速緩衝儲存區之列邊界,則pciM必;;取1買取資料跨 讀取多列命令。 屑發Μ 一記埯趲5019-3607-PF.ptd Page 33 486633 V. Description of the invention (29) If the data length is greater than 4 bytes, but does not cross the column boundary, pc IM issues a memory to read the column can be determined The cache transfer entry takes step 124 if the data length is greater than 4 bits. In ~ more than the column boundary of a fast buffer storage area, pciM must; take 1 to buy data across read multiple columns command. Dandruff
於通道C上之16讀取請求(未顯示在此圖杓’ΡΓΤ 56於PCI匯流排上發出適當記憶體寫入 2 PClM 之Mm立元被設定,且封包資料包括快速:衝=包中 對準之具有一位址之一整體數量之快速儲•子m之列、 則PCIM將發出一記憶體寫入而無效命令。存區之巧, 普通記憶體寫入命令。因此,所有不同型 ’則洁發出〜 寫入操作被映射至IB RDMA讀取及寫入請求封包,靖及 在目標匯流排轉換回到適當型式之pc !操作。、匕且之後 第6圖係舉例說明在本發明之一較佳實施例中之一 細之PCIS控單元(PCIM)56及其相關之緩衝儲存器6〇。= PCIM 56於IB網路30上接收任何延遲請求(DRR或dwr)日士每 其將此請求置於緩衝儲存器60中,較佳為置於一先 (FIFO)仔列130中。若此仵列溢位,PCIM較佳為通知正出 送之PCIT其已丟棄額外的RDMA請求封包,且pciT接著會 封包。 傳 另一方面,當PCIM 56接收一宣告寫入請求132時,Α 不會將此請求輸入至緩衝儲存器60中,而是讓它直接通過 以將其傳送至PC I匾流排。一裁決器1 34給定優先權至請求 1 3 2 ’此優先權南於所有等待在緩衝儲存器中之懸而未決16 read requests on channel C (not shown in this picture: 'ΡΓΤ 56 sends appropriate memory writes on the PCI bus 2 PClM Mm liters are set, and the packet information includes fast: punch = packet pair If there is a fast memory in one bit and one sub-m, the PCIM will issue a memory write and invalid command. The coincidence of the storage area is ordinary memory write command. Therefore, all different types' Then Jie issued ~ The write operation is mapped to the IB RDMA read and write request packet, and the target bus is converted back to the appropriate type of PC! Operation. After that, FIG. 6 illustrates an example in the present invention. A preferred embodiment of the PCIS control unit (PCIM) 56 and its associated buffer memory 60. = PCIM 56 receives any delay request (DRR or dwr) on the IB network 30 This request is placed in the buffer memory 60, preferably in a first (FIFO) queue 130. If this queue overflows, the PCIM preferably informs the sending PCIT that it has discarded additional RDMA request packets And pciT will then packetize. On the other hand, when PCIM 56 receives an announcement write When requesting 132, Α will not enter this request into buffer memory 60, but let it pass directly to transmit it to the PC I plaque stream. A arbiter 1 34 gives priority to request 1 3 2 ' This priority applies to all pending pending buffers
5019-3607-PF.ptd5019-3607-PF.ptd
486633 五、發明說明(30) 的請求之優先權。因此,當一PMW到達PCIM 56,其總是被 允許越過等待在緩衝儲存器中之懸而未決的⑽以&DWRs。 同樣地’若有任何未完成之PMWs等待在PCIM 56中時 ,DRCs及DRWs不被允許越過至了^ 5〇。然而,延遲完成封 包被允許越過先前-到達延遲請求封包。 總括來說,參考表列在發明背景之7個?(:1順序規則, I看到PCIM 56之操作,特別是鍰衝儲存i6〇中之佇列之 官理,保證本橋接器遵守規則5和6,即PMWs, DRCs及DWCs 2許超越DRRs及DWRS。再者,由於ρπτ 54及16網路⑽保 存經由PCi匯流排所接收之讀取及寫入命令之順 以 PMW將不會超越任何盆#刑彳 + n q Λ」7 他m處理’因此會遵守規則1、 瑕後,由於PCIT 54緩衝健存接收來自於目的橋接 =f之DRCs及DWCs,而直到任何#候的g 成後,才將對應之PCI匯流排上資 則4和7。因此系統2。符合-P2P橋接器之二:遵2 經由橋接於IB網路30所獲致之額外當 八有 任何熟習此技藝者,系統20之很明顯的對於 的情況下可以簡單的方式使用適法在有須要 網路、處理及順序規則來代換。 间一式之匯流排、 雖然本發明已以較佳實施 限定本發明,任何熟習此技蓺者7二 ,μ其並非用以 和範圍内,當可作些許之更ί與潤=不脫離本發明之精神 範圍當視後附之申請專利範 ^此本發明之保護 ㈤尸^界疋者為準。486633 V. Priority of the claim of invention description (30). Therefore, when a PMW arrives at PCIM 56, it is always allowed to go over the pending commands waiting in the buffer memory with & DWRs. Similarly, if there are any outstanding PMWs waiting in PCIM 56, DRCs and DRWs are not allowed to cross to ^ 50. However, delayed completion packets are allowed to go over previous-arrival delayed request packets. In a nutshell, the reference table is listed in 7 of the background of the invention? (: 1 sequence rule, I see the operation of PCIM 56, especially the official mechanism listed in the i60, and ensure that the bridge complies with rules 5 and 6, that is, PMWs, DRCs and DWCs 2 may exceed DRRs and DWRS. In addition, because ρπτ 54 and 16 networks save the read and write commands received via the PCi bus, PMW will not surpass any basin # 彳 彳 + nq Λ "7 other processing 'therefore Will abide by rule 1. After the defect, the PCIT 54 buffer memory receives DRCs and DWCs from the destination bridge = f, and until any # candidate g is completed, the corresponding PCI bus will be listed on the rules 4 and 7. Therefore System 2. Compliant -P2P Bridge Part 2: Compliance 2 Extra obtained by bridging to the IB network 30. When anyone is familiar with this skill, the system 20 is obviously suitable for situations where the proper method can be used Where there is a need for network, processing, and ordering rules to replace it. Although the present invention has been limited to the present invention with a better implementation, anyone skilled in this technology will not use it within the scope. When it can be done a little bit more, and it will not depart from the spirit of the present invention Attachment of the following claims and the protection scope of this present invention ^ v ^ dead whichever piece goods sector.
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TWI447578B (en) * | 2010-01-22 | 2014-08-01 | Synopsys Inc | Method and system for packet switch based logic replication |
US11765237B1 (en) | 2022-04-20 | 2023-09-19 | Mellanox Technologies, Ltd. | Session-based remote direct memory access |
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TWI447578B (en) * | 2010-01-22 | 2014-08-01 | Synopsys Inc | Method and system for packet switch based logic replication |
US9052357B2 (en) | 2010-01-22 | 2015-06-09 | Synopsys, Inc. | Packet switch based logic replication |
US11765237B1 (en) | 2022-04-20 | 2023-09-19 | Mellanox Technologies, Ltd. | Session-based remote direct memory access |
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