WO2024082944A1

WO2024082944A1 - Method and apparatus for data exchange between multiple processors, device, and storage medium

Info

Publication number: WO2024082944A1
Application number: PCT/CN2023/121778
Authority: WO
Inventors: 赵元; 马志超; 符云越
Original assignee: 山东云海国创云计算装备产业创新中心有限公司
Priority date: 2022-10-21
Filing date: 2023-09-26
Publication date: 2024-04-25
Also published as: CN115374046B; CN115374046A

Abstract

The present application relates to the technical field of processors, and discloses a method and apparatus for data exchange between multiple processors, a device, and a storage medium. The method comprises: controlling a shared buffer component of an access initiating processor to acquire access information from the access initiating processor, the access initiating processor being connected to the corresponding shared buffer component thereof by means of a peripheral component interconnect express interface; performing address remapping on the access information on the basis of a system address mapping table by using a switch remapping module so as to determine an address of an accessed processor, and establishing a data path between the access initiating processor and the accessed processor; and controlling the shared buffer component of the access initiating processor to perform data exchange with a shared buffer component of the accessed processor by means of the data path. The present application can avoid the delay caused by multiple interface conversion and forwarding operations in a traditional processor interconnection process, thereby improving the overall performance of the system.

Description

一种多处理器数据交互方法、装置、设备及存储介质A multi-processor data interaction method, device, equipment and storage medium

相关申请的交叉引用CROSS-REFERENCE TO RELATED APPLICATIONS

本申请要求于2022年10月21日提交中国专利局，申请号为202211290888.8，申请名称为“一种多处理器数据交互方法、装置、设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。This application claims priority to a Chinese patent application filed with the China Patent Office on October 21, 2022, with application number 202211290888.8 and application name “A multi-processor data interaction method, device, equipment and storage medium”, all contents of which are incorporated by reference in this application.

技术领域Technical Field

本申请涉及处理器技术领域，特别涉及一种多处理器数据交互方法、装置、设备及存储介质。The present application relates to the field of processor technology, and in particular to a multi-processor data interaction method, device, equipment and storage medium.

背景技术Background technique

随着多路处理器的应用越来越广泛，处理器之间的互联互通成为一个重要应用需求。当前，基于处理器的集群互联的实现一般基于标准以太网接口，通过***软件的任务调度用以实现各种***任务的执行。普通处理器互联的实现架构如图1所示，主要通过标准以太网经过多级网络交换机互联组成通常意义上的处理器集群，通过***软件的任务调度用以实现各种***任务的执行。手机***芯片的处理器互联，由于其***级芯片SOC(System On Chip)一般不具有标准以太网接口，往往是通过***组件互连快速接口PCIE(Peripheral Component Interconnect Express)接口或者USB接口外接扩展网络转换芯片，将其接口转为标准以太网接口之后，再通过网络交换机进行互联，形成与普通处理器通过以太网接口互联架构上一致的集群***，如图2所示。As the application of multi-way processors becomes more and more widespread, the interconnection between processors has become an important application requirement. At present, the implementation of processor-based cluster interconnection is generally based on the standard Ethernet interface, and the task scheduling of the system software is used to implement the execution of various system tasks. The implementation architecture of ordinary processor interconnection is shown in Figure 1. It is mainly connected through standard Ethernet through multi-level network switches to form a processor cluster in the usual sense, and the task scheduling of the system software is used to implement the execution of various system tasks. The processor interconnection of the mobile phone system chip, because its system-level chip SOC (System On Chip) generally does not have a standard Ethernet interface, is often connected through the peripheral component interconnection express interface PCIE (Peripheral Component Interconnect Express) interface or USB interface external expansion network conversion chip, after converting its interface to a standard Ethernet interface, and then interconnected through a network switch, forming a cluster system consistent with the architecture of ordinary processors interconnected through Ethernet interfaces, as shown in Figure 2.

图1实现架构对于采用服务器级别处理器芯片的通用的服务器而言，有足够多的网络接口可以接入各级以太网交换机，从而实现多机互联的集群。但是对于图2实现架构，由于本身采用的是低成本的手机SOC芯片进行集群的目的就是降低整个处理器集群的成本，这里对于每一个手机SOC芯片额外增加的网络接口适配转换芯片使得整个***的成本大幅度增加，从而失去了最初的降低整个处理器集群的成本的***设计目标。而且，通过接口转换需要进行跨多个不同接口的多级转发，手机SOC芯片之间互联的效率受到各接口的限制，通信和数据交互效率都会有显著降低。For a general server using server-level processor chips, the implementation architecture of Figure 1 has enough network interfaces to access various levels of Ethernet switches, thereby realizing a cluster of multiple machines. However, for the implementation architecture of Figure 2, since the purpose of clustering using low-cost mobile SOC chips is to reduce the cost of the entire processor cluster, the additional network interface adapter conversion chip for each mobile SOC chip greatly increases the cost of the entire system, thereby losing the original system design goal of reducing the cost of the entire processor cluster. Moreover, interface conversion requires multi-level forwarding across multiple different interfaces, and the efficiency of interconnection between mobile SOC chips is limited by each interface, which significantly reduces the efficiency of communication and data interaction.

发明内容Summary of the invention

有鉴于此，本申请的目的在于提供一种多处理器数据交互方法、装置、设备及存储介质，能够避免传统处理器互联过程中由于多次接口转换转发造成的延迟，从而提升***整体性能。其具体方案如下：In view of this, the purpose of this application is to provide a multi-processor data interaction method, device, equipment and storage medium, which can avoid the delay caused by multiple interface conversion and forwarding in the traditional processor interconnection process, thereby improving the overall performance of the system. The specific scheme is as follows:

本申请的第一方面提供了一种多处理器数据交互方法，包括：A first aspect of the present application provides a multi-processor data interaction method, comprising:

控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息；其中，访问发起处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接；The shared buffer component of the access initiating processor is controlled to obtain access information from the access initiating processor; wherein the access initiating processor and its corresponding shared buffer component are connected via a peripheral component interconnect fast interface;

利用交换重映射模块基于***地址映射表对访问信息进行地址重映射以确定出被访问处理器地址，并建立访问发起处理器与被访问处理器之间的数据通路；Using the exchange remapping module to perform address remapping on the access information based on the system address mapping table to determine the address of the accessed processor, and establish a data path between the access initiating processor and the accessed processor;

控制访问发起处理器的共享缓冲组件通过数据通路与被访问处理器的共享缓冲组件进行数据交互；其中，被访问处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。 The shared buffer component of the access initiating processor is controlled to perform data interaction with the shared buffer component of the accessed processor through a data path; wherein the accessed processor and its corresponding shared buffer component are connected through a peripheral component interconnect fast interface.

可选的，控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息，包括：Optionally, the shared buffer component controlling the access initiating processor obtains access information from the access initiating processor, including:

访问发起处理器的共享缓冲组件中的直接存储器访问控制器通过直接存储器访问方式从访问发起处理器获取访问信息，并将访问信息在访问发起处理器的共享缓冲组件中的缓存空间进行存储。The direct memory access controller in the shared buffer component of the access initiating processor obtains access information from the access initiating processor in a direct memory access manner, and stores the access information in a cache space in the shared buffer component of the access initiating processor.

可选的，利用交换重映射模块基于***地址映射表对访问信息进行地址重映射以确定出被访问处理器地址，包括：Optionally, using a switching remapping module to perform address remapping on the access information based on a system address mapping table to determine the address of the accessed processor includes:

访问发起处理器的共享缓冲组件中的缓存空间将存储的访问信息发送至交换重映射模块；Accessing the cache space in the shared buffer component of the initiating processor sends the stored access information to the switch remapping module;

交换重映射模块对访问信息进行解析的得到访问地址并根据***地址映射表将访问地址重映射为被访问处理器地址，以将访问信息发送至被访问处理器的共享缓冲组件中的直接存储器访问控制器。The exchange remapping module parses the access information to obtain the access address and remaps the access address to the accessed processor address according to the system address mapping table, so as to send the access information to the direct memory access controller in the shared buffer component of the accessed processor.

可选的，访问信息包括访问类型和访问数据量；其中，访问类型包括写数据和读数据中的至少一种，访问数据量为与写数据对应的写入数据量和与读数据对应的读取数据量；Optionally, the access information includes an access type and an access data volume; wherein the access type includes at least one of write data and read data, and the access data volume is a write data volume corresponding to the write data and a read data volume corresponding to the read data;

相应的，控制访问发起处理器的共享缓冲组件通过数据通路与被访问处理器的共享缓冲组件进行数据交互，包括：Accordingly, controlling the shared buffer component of the access initiating processor to perform data interaction with the shared buffer component of the accessed processor through the data path includes:

如果访问类型为写数据，则控制被访问处理器的共享缓冲组件通过数据通路从访问发起处理器的共享缓冲组件中读取第一任务数据，并将第一任务数据写入被访问处理器的内存空间；If the access type is writing data, controlling the shared buffer component of the accessed processor to read the first task data from the shared buffer component of the access initiating processor through the data path, and writing the first task data into the memory space of the accessed processor;

如果访问类型为读数据，则控制访问发起处理器的共享缓冲组件通过数据通路对被访问处理器的共享缓冲组件中读取第二任务数据，并将第二任务数据写入访问处理器的内存空间。If the access type is to read data, the shared buffer component of the access initiating processor is controlled to read the second task data from the shared buffer component of the accessed processor through a data path, and write the second task data into the memory space of the accessing processor.

可选的，交换重映射模块将访问信息发送至被访问处理器的共享缓冲组件中的直接存储器访问控制器之后，还包括：Optionally, after the exchange remapping module sends the access information to the direct memory access controller in the shared buffer component of the accessed processor, the method further includes:

如果访问类型为写数据，则被访问处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向被访问发起处理器发送写入请求，以便被访问处理器分配与写入数据量相适应的用于存储第一任务数据的内存空间。If the access type is write data, the direct memory access controller in the shared buffer component of the accessed processor sends a write request to the accessed initiating processor through the peripheral component interconnect fast interface, so that the accessed processor allocates memory space for storing the first task data corresponding to the amount of write data.

可选的，控制被访问处理器的共享缓冲组件通过数据通路从访问发起处理器的共享缓冲组件中读取第一任务数据之前，还包括：Optionally, before controlling the shared buffer component of the accessed processor to read the first task data from the shared buffer component of the access initiating processor through the data path, the method further includes:

访问发起处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向访问发起处理器发送第一读取请求，以便访问发起处理器根据第一读取请求返回第一任务数据并存储在访问发起处理器的共享缓冲组件中的缓存空间。The direct memory access controller in the shared buffer component of the access initiating processor sends a first read request to the access initiating processor through the peripheral component interconnect fast interface, so that the access initiating processor returns the first task data according to the first read request and stores it in the cache space in the shared buffer component of the access initiating processor.

可选的，控制被访问处理器的共享缓冲组件通过数据通路从访问发起处理器的共享缓冲组件中读取第一任务数据，并将第一任务数据写入被访问处理器的内存空间，包括：Optionally, controlling the shared buffer component of the accessed processor to read the first task data from the shared buffer component of the access initiating processor through a data path, and writing the first task data into the memory space of the accessed processor includes:

被访问处理器的共享缓冲组件中的直接存储器访问控制器从访问发起处理器的共享缓冲组件中的缓存空间读取第一任务数据，并通过***组件互联快速接口将第一任务数据写入被访问处理器的内存空间。The direct memory access controller in the shared buffer component of the accessed processor reads the first task data from the cache space in the shared buffer component of the access initiating processor, and writes the first task data into the memory space of the accessed processor through the peripheral component interconnect express interface.

可选的，控制访问发起处理器的共享缓冲组件通过数据通路对被访问处理器的共享缓冲组件中读取第二任务数据之前，还包括：Optionally, before controlling the shared buffer component of the access initiating processor to read the second task data from the shared buffer component of the accessed processor through the data path, the method further includes:

被访问处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向被访问发起处理器发送第二读取请求，以便被访问发起处理器根据第二读取请求返回第二任务数据并存储在被访问处理器的共享缓冲组件中的缓存空间。The direct memory access controller in the shared buffer component of the accessed processor sends a The accessed initiating processor sends a second read request, so that the accessed initiating processor returns the second task data according to the second read request and stores it in the cache space of the shared buffer component of the accessed processor.

可选的，控制访问发起处理器的共享缓冲组件通过数据通路对被访问处理器的共享缓冲组件中读取第二任务数据，并将第二任务数据写入访问处理器的内存空间，包括：Optionally, controlling the shared buffer component of the access initiating processor to read the second task data from the shared buffer component of the accessed processor through a data path, and writing the second task data into the memory space of the accessing processor includes:

访问发起处理器的共享缓冲组件中的直接存储器访问控制器从被访问处理器的共享缓冲组件中的缓存空间读取第二任务数据，并通过***组件互联快速接口将第二任务数据写入访问处理器的内存空间。The direct memory access controller in the shared buffer component of the access initiating processor reads the second task data from the cache space in the shared buffer component of the accessed processor, and writes the second task data into the memory space of the accessing processor through the peripheral component interconnect express interface.

可选的，控制处理器的共享缓冲组件读取任务数据之后，还包括：Optionally, after the shared buffer component of the control processor reads the task data, the method further includes:

被访问处理器的共享缓冲组件中的直接存储器访问控制器向交换重映射模块发送交互结束指令，以使交换重映射模块断开数据通路。The direct memory access controller in the shared buffer component of the accessed processor sends an interaction end instruction to the swap remapping module, so that the swap remapping module disconnects the data path.

可选的，将任务数据写入处理器的内存空间之后，还包括：Optionally, after writing the task data into the memory space of the processor, it also includes:

访问处理器的共享缓冲组件中的直接存储器访问控制器向访问处理器发送中断指令，以使访问处理器获取读取到内存空间中的数据；A direct memory access controller in a shared buffer component of the access processor sends an interrupt instruction to the access processor so that the access processor obtains the data read into the memory space;

被访问处理器的共享缓冲组件中的直接存储器访问控制器向被访问处理器发送中断指令，以使被访问处理器获取写入内存空间中的数据。The direct memory access controller in the shared buffer component of the accessed processor sends an interrupt instruction to the accessed processor, so that the accessed processor obtains the data written into the memory space.

可选的，访问发起处理器和被访问处理器为***级芯片集群中的任意两个处理器。Optionally, the access initiating processor and the accessed processor are any two processors in a system-on-chip cluster.

本申请的第二方面提供了一种多处理器数据交互装置，包括：A second aspect of the present application provides a multi-processor data interaction device, comprising:

访问触发模块，用于控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息；其中，访问发起处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接；An access trigger module is used to control the shared buffer component of the access initiating processor to obtain access information from the access initiating processor; wherein the access initiating processor and its corresponding shared buffer component are connected via a peripheral component interconnect fast interface;

通路建立模块，用于利用交换重映射模块基于***地址映射表对访问信息进行地址重映射以确定出被访问处理器地址，并建立访问发起处理器与被访问处理器之间的数据通路；A path establishing module, used for performing address remapping on access information based on a system address mapping table by using a switching remapping module to determine the address of the processor being accessed, and establishing a data path between the access initiating processor and the processor being accessed;

数据交互模块，用于控制访问发起处理器的共享缓冲组件通过数据通路与被访问处理器的共享缓冲组件进行数据交互；其中，被访问处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。The data interaction module is used to control the shared buffer component of the access initiating processor to perform data interaction with the shared buffer component of the accessed processor through a data path; wherein the accessed processor and its corresponding shared buffer component are connected through a peripheral component interconnect fast interface.

本申请的第三方面提供了一种电子设备，电子设备包括处理器和存储器；其中存储器用于存储计算机程序，计算机程序由处理器加载并执行以实现前述多处理器数据交互方法。A third aspect of the present application provides an electronic device, which includes a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the aforementioned multi-processor data interaction method.

本申请的第四方面提供了一种非易失性可读存储介质，非易失性可读存储介质中存储有计算机可执行指令，计算机可执行指令被处理器加载并执行时，实现前述多处理器数据交互方法。The fourth aspect of the present application provides a non-volatile readable storage medium, in which computer executable instructions are stored. When the computer executable instructions are loaded and executed by a processor, the aforementioned multi-processor data interaction method is implemented.

本申请中，先控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息；其中，访问发起处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接；然后利用交换重映射模块基于***地址映射表对访问信息进行地址重映射以确定出被访问处理器地址，并建立访问发起处理器与被访问处理器之间的数据通路；最后控制访问发起处理器的共享缓冲组件通过数据通路与被访问处理器的共享缓冲组件进行数据交互；其中，被访问处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。可见，本申请通过处理器自身的***组件互联快速接口连接共享缓冲组件，借助共享缓冲组件在处理器之间建立数据通路，处理器基于该数据通路进行数据交互，能够避免传统处理器互联过程中由于多次接口转换转发造成的延迟，从而提升***整体性能。 In the present application, the shared buffer component of the access initiating processor is first controlled to obtain access information from the access initiating processor; wherein the access initiating processor and its corresponding shared buffer component are connected through a peripheral component interconnect fast interface; then the exchange remapping module is used to perform address remapping of the access information based on the system address mapping table to determine the address of the accessed processor, and establish a data path between the access initiating processor and the accessed processor; finally, the shared buffer component of the access initiating processor is controlled to perform data interaction with the shared buffer component of the accessed processor through the data path; wherein the accessed processor and its corresponding shared buffer component are connected through a peripheral component interconnect fast interface. It can be seen that the present application connects the shared buffer component through the processor's own peripheral component interconnect fast interface, establishes a data path between the processors with the help of the shared buffer component, and the processors interact with each other based on the data path, which can avoid the delay caused by multiple interface conversion forwarding in the traditional processor interconnection process, thereby improving the overall performance of the system.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

图1为本申请提供的一种普通处理器互联的实现架构示例图；FIG1 is a diagram showing an example of an implementation architecture of a common processor interconnection provided by the present application;

图2为本申请提供的一种SOC处理器互联的实现架构示例图；FIG2 is a diagram showing an example of an implementation architecture of a SOC processor interconnection provided by the present application;

图3为本申请提供的一种多处理器数据交互方法流程图；FIG3 is a flow chart of a multi-processor data interaction method provided by the present application;

图4为本申请提供的一种具体多处理器数据交互的实现架构示例图；FIG4 is a diagram showing an example of a specific multi-processor data interaction implementation architecture provided by the present application;

图5为本申请提供的一种具体的***扩展内存映射表；FIG5 is a specific system extended memory mapping table provided by the present application;

图6为本申请提供的一种具体的多处理器数据交互方法流程图；FIG6 is a flowchart of a specific multi-processor data interaction method provided by the present application;

图7为本申请提供的一种具体的多处理器数据交互方法流程图；FIG7 is a flowchart of a specific multi-processor data interaction method provided by the present application;

图8为本申请提供的一种多处理器数据交互装置结构示意图；FIG8 is a schematic diagram of the structure of a multi-processor data interaction device provided by the present application;

图9为本申请提供的一种多处理器数据交互电子设备结构图。FIG9 is a structural diagram of a multi-processor data interaction electronic device provided by the present application.

具体实施方式Detailed ways

为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

现有的处理器互联实现架构以标准以太网接口为基础，但对于不具有以太网接口的处理器需要外接网络接口适配转换芯片才能够实现多处理器的网络集群。使得整个***的成本大幅度增加，从而失去了最初的降低整个处理器集群的成本的***设计目标。而且，通过接口转换需要进行跨多个不同接口的多级转发，互联的效率受到各接口的限制，通信和数据交互效率都会有显著降低。针对上述技术缺陷，本申请提供一种多处理器数据交互方案，通过处理器自身的***组件互联快速接口连接共享缓冲组件，借助共享缓冲组件在处理器之间建立数据通路，处理器基于该数据通路进行数据交互，能够避免传统处理器互联过程中由于多次接口转换转发造成的延迟，从而提升***整体性能。The existing processor interconnection implementation architecture is based on the standard Ethernet interface, but for processors that do not have an Ethernet interface, an external network interface adapter conversion chip is required to realize a multi-processor network cluster. This greatly increases the cost of the entire system, thereby losing the original system design goal of reducing the cost of the entire processor cluster. Moreover, interface conversion requires multi-level forwarding across multiple different interfaces, and the efficiency of interconnection is limited by each interface, and the efficiency of communication and data interaction will be significantly reduced. In response to the above-mentioned technical defects, the present application provides a multi-processor data interaction solution, which connects a shared buffer component through the processor's own peripheral component interconnection fast interface, establishes a data path between processors with the help of the shared buffer component, and the processors interact with data based on the data path, which can avoid the delay caused by multiple interface conversion forwarding in the traditional processor interconnection process, thereby improving the overall system performance.

图3为本申请实施例提供的一种多处理器数据交互方法流程图。参见图3所示，该多处理器数据交互方法包括：FIG3 is a flow chart of a multi-processor data interaction method provided by an embodiment of the present application. Referring to FIG3 , the multi-processor data interaction method includes:

S11：控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息；其中，访问发起处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。S11: controlling the shared buffer component of the access initiating processor to obtain access information from the access initiating processor; wherein the access initiating processor and its corresponding shared buffer component are connected via a peripheral component interconnect fast interface.

本实施例中，访问发起处理器作为请求发起方，被访问处理器作为被访问方，这里主要是内存访问也即内存共享。每个处理器对应一个共享缓冲组件，该共享缓冲组件用于辅助内存共享的实现。处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。***组件互联快速接口即PCIe接口。具体来说，访问发起处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接，被访问处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。In this embodiment, the access initiating processor acts as the request initiator, and the accessed processor acts as the accessed party. Here, it is mainly memory access, that is, memory sharing. Each processor corresponds to a shared buffer component, which is used to assist in the implementation of memory sharing. The processor and its corresponding shared buffer component are connected through a peripheral component interconnect express interface. The peripheral component interconnect express interface is a PCIe interface. Specifically, the access initiating processor and its corresponding shared buffer component are connected through a peripheral component interconnect express interface, and the accessed processor and its corresponding shared buffer component are connected through a peripheral component interconnect express interface.

进一步的，本实施中的共享缓冲组件包括直接存储器访问控制器DMA(Direct Memory Access)及缓存空间Buf。控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息的具体过程为：访问发起处理器的共享缓冲组件中的直接存储器访问控制器通过直接存储器访问方式从访问发起处理器获取访问信息，并将访问信息在访问发起处理器的共享缓冲组件中的缓存空间进行存储，交换重映射模块(switch remap module)与Buf连接，对应的***结构如图4所示。Furthermore, the shared buffer component in this embodiment includes a direct memory access controller DMA (Direct Memory Access) and a cache space Buf. The shared buffer component that controls the access initiating processor obtains the access from the access initiating processor. The specific process of information is as follows: the direct memory access controller in the shared buffer component of the access initiating processor obtains access information from the access initiating processor through direct memory access, and stores the access information in the cache space in the shared buffer component of the access initiating processor. The switch remap module is connected to Buf. The corresponding system structure is shown in Figure 4.

图4中，n个处理器器芯片分别通过PCIE的Root端口与共享缓冲组件相连接，由芯片中的DMA功能来实现数据从一个处理器内存到另一个处理器内存的搬移功能。共享缓冲组件中的DMA与对应的处理器通过处理器上的PCIE Root接口直接相连。从确定的某一个处理器的角度看，其他的处理器的内存都是自己的外接扩展内存。当一个处理器需要向其他处理器派发任务时，将任务数据通过对应连接的PCIE接口，经由共享缓冲组件传输到另一个处理器的内存，对应该内存的处理器从自身内容中获取任务数据进行处理，从而实现了共享内容任务数据处理的功能。具体的，EP0接口与处理器0相连接，负责传输处理器0中的数据，EP1接口与处理器1相连接，负责传输处理器1中的数据，依此类推，EPn接口与处理器n相连接，负责传输处理器n中的数据。DMA0～n分别作为读写处理器0～n内存中数据的引擎，通过各自连接的处理器0～n的PCIE的EP端口，发起符合PCIE协议标准的内存读写请求，实现到对应服务器主机内存的数据访问。从内存中获取的数据会缓存在对应的Buf0～n中。In Figure 4, n processor chips are connected to the shared buffer component through the root port of PCIE respectively, and the DMA function in the chip realizes the function of moving data from one processor memory to another processor memory. The DMA in the shared buffer component is directly connected to the corresponding processor through the PCIE root interface on the processor. From the perspective of a certain processor, the memory of other processors is its own external expansion memory. When a processor needs to dispatch tasks to other processors, the task data is transmitted to the memory of another processor through the corresponding connected PCIE interface and the shared buffer component. The processor corresponding to the memory obtains the task data from its own content for processing, thereby realizing the function of shared content task data processing. Specifically, the EP0 interface is connected to processor 0 and is responsible for transmitting data in processor 0. The EP1 interface is connected to processor 1 and is responsible for transmitting data in processor 1. Similarly, the EPn interface is connected to processor n and is responsible for transmitting data in processor n. DMA0~n respectively serve as engines for reading and writing data in the memory of processors 0~n. Through the EP ports of the PCIE of the connected processors 0~n, memory read and write requests that comply with the PCIE protocol standard are initiated to realize data access to the corresponding server host memory. The data obtained from the memory will be cached in the corresponding Buf0~n.

本实施例中，多处理器组成处理器集群，处理器可以为***级芯片SOC处理器，访问发起处理器和被访问处理器为***级芯片集群中的任意两个处理器。在SOC处理器集群架构下，本实施例主要基于SOC处理器的PCIE接口多根节点的互联实现数据交互。但是在某些情况下，可以不只是局限于在SOC处理器间实现互联，例如，在服务器***，桌面办公计算机***，多种不同架构的处理器***之间，都可以实现多个PCIE根节点的互联，从而实现处理器互联。In this embodiment, multiple processors form a processor cluster, the processor can be a system-on-chip SOC processor, and the access initiating processor and the accessed processor are any two processors in the system-on-chip cluster. Under the SOC processor cluster architecture, this embodiment mainly realizes data interaction based on the interconnection of multiple root nodes of the PCIE interface of the SOC processor. However, in some cases, it is not limited to realizing interconnection between SOC processors. For example, in server systems, desktop office computer systems, and processor systems with various different architectures, multiple PCIE root nodes can be interconnected to realize processor interconnection.

S12：利用交换重映射模块基于***地址映射表对访问信息进行地址重映射以确定出被访问处理器地址，并建立访问发起处理器与被访问处理器之间的数据通路。S12: using the exchange remapping module to perform address remapping on the access information based on the system address mapping table to determine the address of the accessed processor, and establishing a data path between the access initiating processor and the accessed processor.

本实施例中，利用交换重映射模块基于***地址映射表对访问信息进行地址重映射以确定出被访问处理器地址，并建立访问发起处理器与被访问处理器之间的数据通路。具体的，访问发起处理器的共享缓冲组件中的缓存空间将存储的访问信息发送至交换重映射模块；交换重映射模块对访问信息进行解析的得到访问地址并根据***地址映射表将访问地址重映射为被访问处理器地址，以将访问信息发送至被访问处理器的共享缓冲组件中的直接存储器访问控制器。In this embodiment, the exchange remapping module is used to perform address remapping on the access information based on the system address mapping table to determine the address of the accessed processor, and to establish a data path between the access initiating processor and the accessed processor. Specifically, the cache space in the shared buffer component of the access initiating processor sends the stored access information to the exchange remapping module; the exchange remapping module parses the access information to obtain the access address and remaps the access address to the accessed processor address according to the system address mapping table, so as to send the access information to the direct memory access controller in the shared buffer component of the accessed processor.

本实施例中，图5所示为***地址映射表示例，在***初始化的时候，***地址映射表可以被配置在DMA、Buf和switch map module中，在***运行过程中，可以根据需要进行动态调整。交换重映射模块根据如图5所示的***扩展内存映射表，在数据任务分发时的通过内存目标地址进行路由译码，建立从目标内存所在处理器接口到本地存储数据的缓存空间Buf的数据链路，再由对应DMA引擎发起请求，从Buf中读取数据，通过建立的数据链路，将数据写入目标内存中。In this embodiment, FIG5 shows an example of a system address mapping table. When the system is initialized, the system address mapping table can be configured in DMA, Buf and switch map module, and can be dynamically adjusted as needed during system operation. The switch remapping module performs routing decoding through the memory target address when distributing data tasks according to the system extended memory mapping table shown in FIG5, establishes a data link from the processor interface where the target memory is located to the cache space Buf for local data storage, and then initiates a request by the corresponding DMA engine to read data from Buf, and writes the data to the target memory through the established data link.

图5中，0～addr0-1为每个处理器的固有的属于本处理器的内存地址。这块地址是不能够进行跨处理器节点进行访问的，只有本处理器节点可以访问，作为节点***启动初始化完成***任务使用，其大小根据实际***应用而定。从addr0地址开始的内存可以为所有处理器节点共享使用：从addr0～addr1-1的地址是挂载在处理器0下面的内存，从addr1～addrn-1的地址是挂载在处理器1下面的内存，以此类推。每个处理器下面挂载的内存大小可以相同也可以不同，只要能把图5中的地址映射关系确定对应就可以。当某个处理器访问不属于自己处理器下面挂载的内存时，需要通过共享缓冲组件建立从发起访问的处理器到被访问内存的处理器之间的数据通路，然后才能进行内存数据的传输。需要注意，当某个处理器访问属于自己处理器下面挂载的内存时，不需要通过共享缓冲组件接口，直接通过本地处理器访问本地内存就行。In Figure 5, 0 to addr0-1 are the inherent memory addresses of each processor. This address block cannot be accessed across processor nodes. Only the processor node can access it. It is used as the node system startup initialization to complete the system task. Its size depends on the actual system application. The memory starting from the addr0 address can be shared by all processor nodes: the addresses from addr0 to addr1-1 are the memory mounted under processor 0, and the addresses from addr1 to addrn-1 are the memory mounted under processor 0. The address is the memory mounted under processor 1, and so on. The size of the memory mounted under each processor can be the same or different, as long as the address mapping relationship in Figure 5 can be determined to correspond. When a processor accesses the memory that is not mounted under its own processor, it is necessary to establish a data path from the processor initiating the access to the processor of the accessed memory through the shared buffer component before the memory data can be transmitted. It should be noted that when a processor accesses the memory mounted under its own processor, it does not need to go through the shared buffer component interface, but can directly access the local memory through the local processor.

S13：控制访问发起处理器的共享缓冲组件通过数据通路与被访问处理器的共享缓冲组件进行数据交互；其中，被访问处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。S13: Control the shared buffer component of the access initiating processor to perform data interaction with the shared buffer component of the accessed processor through a data path; wherein the accessed processor and its corresponding shared buffer component are connected through a peripheral component interconnect fast interface.

本实施例中，控制访问发起处理器的共享缓冲组件通过数据通路与被访问处理器的共享缓冲组件进行数据交互；其中，被访问处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。In this embodiment, the shared buffer component of the access initiating processor is controlled to exchange data with the shared buffer component of the accessed processor through a data path; wherein the accessed processor and its corresponding shared buffer component are connected through a peripheral component interconnect fast interface.

可以理解，上述访问信息包括访问类型和访问数据量；其中，访问类型包括写数据和读数据中的至少一种，访问数据量为与写数据对应的写入数据量和与读数据对应的读取数据量。如果访问类型为写数据，则控制被访问处理器的共享缓冲组件通过数据通路从访问发起处理器的共享缓冲组件中读取第一任务数据，并将第一任务数据写入被访问处理器的内存空间。如果访问类型为读数据，则控制访问发起处理器的共享缓冲组件通过数据通路对被访问处理器的共享缓冲组件中读取第二任务数据，并将第二任务数据写入访问处理器的内存空间。It can be understood that the above access information includes the access type and the access data volume; wherein the access type includes at least one of write data and read data, and the access data volume is the write data volume corresponding to the write data and the read data volume corresponding to the read data. If the access type is write data, the shared buffer component of the accessed processor is controlled to read the first task data from the shared buffer component of the access initiating processor through the data path, and write the first task data into the memory space of the accessed processor. If the access type is read data, the shared buffer component of the access initiating processor is controlled to read the second task data from the shared buffer component of the accessed processor through the data path, and write the second task data into the memory space of the accessing processor.

本实施例中，第一任务数据和第二任务数据只是为了区分写入的任务数据和读取的任务数据，第一任务数据和第二任务数据是与任务数据相关的数据，在写入时，写入的是任务，在读取时，读取的是任务执行的结果。也即，第一任务数据为任务，第二任务数据为任务执行结果。In this embodiment, the first task data and the second task data are only used to distinguish between the written task data and the read task data. The first task data and the second task data are data related to the task data. When writing, what is written is the task, and when reading, what is read is the result of the task execution. That is, the first task data is the task, and the second task data is the result of the task execution.

可见，本申请实施例先控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息；其中，访问发起处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接；然后利用交换重映射模块基于***地址映射表对访问信息进行地址重映射以确定出被访问处理器地址，并建立访问发起处理器与被访问处理器之间的数据通路；最后控制访问发起处理器的共享缓冲组件通过数据通路与被访问处理器的共享缓冲组件进行数据交互；其中，被访问处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。本申请实施例通过处理器自身的***组件互联快速接口连接共享缓冲组件，借助共享缓冲组件在处理器之间建立数据通路，处理器基于该数据通路进行数据交互，能够避免传统处理器互联过程中由于多次接口转换转发造成的延迟，从而提升***整体性能。It can be seen that the embodiment of the present application first controls the shared buffer component of the access initiating processor to obtain access information from the access initiating processor; wherein, the access initiating processor and its corresponding shared buffer component are connected through the peripheral component interconnect fast interface; then the exchange remapping module is used to perform address remapping of the access information based on the system address mapping table to determine the address of the accessed processor, and establish a data path between the access initiating processor and the accessed processor; finally, the shared buffer component of the access initiating processor is controlled to perform data interaction with the shared buffer component of the accessed processor through the data path; wherein, the accessed processor and its corresponding shared buffer component are connected through the peripheral component interconnect fast interface. The embodiment of the present application connects the shared buffer component through the processor's own peripheral component interconnect fast interface, establishes a data path between the processors with the help of the shared buffer component, and the processors interact data based on the data path, which can avoid the delay caused by multiple interface conversion forwarding in the traditional processor interconnection process, thereby improving the overall performance of the system.

图6为本申请实施例提供的一种具体的多处理器数据交互方法流程图。参见图6所示，该多处理器数据交互方法包括：FIG6 is a flowchart of a specific multi-processor data interaction method provided in an embodiment of the present application. Referring to FIG6 , the multi-processor data interaction method includes:

S21：控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息；其中，访问信息包括访问类型和访问数据量；访问类型包括写数据，访问数据量为与写数据对应的写入数据量。S21: controlling the shared buffer component of the access initiating processor to obtain access information from the access initiating processor; wherein the access information includes access type and access data volume; the access type includes write data, and the access data volume is the write data volume corresponding to the write data.

S22：访问发起处理器的共享缓冲组件中的缓存空间将存储的访问信息发送至交换重映射模块。 S22: The access initiator sends the stored access information to the switch remapping module by accessing the cache space in the shared buffer component of the processor.

S23：交换重映射模块对访问信息进行解析的得到访问地址并根据***地址映射表将访问地址重映射为被访问处理器地址，以将访问信息发送至被访问处理器的共享缓冲组件中的直接存储器访问控制器，并建立访问发起处理器与被访问处理器之间的数据通路。S23: The exchange remapping module parses the access information to obtain the access address and remaps the access address to the accessed processor address according to the system address mapping table, so as to send the access information to the direct memory access controller in the shared buffer component of the accessed processor and establish a data path between the access initiating processor and the accessed processor.

本实施例中，主要针对写数据过程进行说明，关于上述步骤S21至步骤S23的具体过程，可以参考前述实施例中公开的相应内容，在此不再进行赘述。以SOC0处理器写SOC1处理器内存空间为例对写数据过程进行具体说明：SOC0通过PCIE接口将要访问的内存地址信息放在真正的任务数据头部，首先写入Buf0中，Buf0对该信息通过图5的地址映射表进行解析，识别出需要访问的内存在SOC1上，并获取到要写入的数据空间的大小，将这些信息通过Switch Map Module发送到DMA1。In this embodiment, the data writing process is mainly described. For the specific process of the above steps S21 to S23, reference can be made to the corresponding content disclosed in the above embodiments, which will not be repeated here. Take the SOC0 processor writing the SOC1 processor memory space as an example to specifically describe the data writing process: SOC0 puts the memory address information to be accessed in the real task data header through the PCIE interface, and first writes it into Buf0. Buf0 parses the information through the address mapping table of Figure 5, recognizes that the memory to be accessed is on SOC1, and obtains the size of the data space to be written, and sends this information to DMA1 through the Switch Map Module.

S24：访问处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向被访问发起处理器发送写入请求，以便被访问处理器分配与写入数据量相适应的用于存储第一任务数据的内存空间。S24: The direct memory access controller in the shared buffer component of the accessing processor sends a write request to the accessed initiating processor through the PCI Express interface, so that the accessed processor allocates a memory space for storing the first task data that is adapted to the amount of write data.

本实施例中，访问处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向被访问发起处理器发送写入请求，以便被访问处理器分配与写入数据量相适应的用于存储第一任务数据的内存空间。也即DMA1通过PCIE接口向SOC1发起地址空间的写入数据请求，SOC1接收到请求后，分配对应的内存地址空间给DMA1使用。In this embodiment, the direct memory access controller in the shared buffer component of the access processor sends a write request to the accessed initiating processor through the peripheral component interconnect fast interface, so that the accessed processor allocates a memory space for storing the first task data that is suitable for the amount of write data. That is, DMA1 initiates a write data request of the address space to SOC1 through the PCIE interface, and after receiving the request, SOC1 allocates the corresponding memory address space to DMA1 for use.

S25：被访问发起处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向访问发起处理器发送第一读取请求，以便访问发起处理器根据第一读取请求返回第一任务数据并存储在访问发起处理器的共享缓冲组件中的缓存空间。S25: The direct memory access controller in the shared buffer component of the access initiating processor sends a first read request to the access initiating processor through the peripheral component interconnect fast interface, so that the access initiating processor returns the first task data according to the first read request and stores it in the cache space of the shared buffer component of the access initiating processor.

S26：控制被访问处理器的共享缓冲组件通过数据通路从访问发起处理器的共享缓冲组件中读取第一任务数据，并将第一任务数据写入被访问处理器的内存空间。S26: Control the shared buffer component of the accessed processor to read the first task data from the shared buffer component of the access initiating processor through the data path, and write the first task data into the memory space of the accessed processor.

本实施例中，被访问发起处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向访问发起处理器发送第一读取请求，以便访问发起处理器根据第一读取请求返回第一任务数据并存储在访问发起处理器的共享缓冲组件中的缓存空间。最后控制被访问处理器的共享缓冲组件通过数据通路从访问发起处理器的共享缓冲组件中读取第一任务数据，并将第一任务数据写入被访问处理器的内存空间。DMA1收到响应后，通过switch map module发起读取Buf0数据的请求，switch map module收到请求后，将该请求转发给Buf0，并建立起从Buf0到DMA1的数据通路。真正的通路其实是在这个阶段才完全建立起来，此时开始写入数据。In this embodiment, the direct memory access controller in the shared buffer component of the accessed initiating processor sends a first read request to the access initiating processor through the peripheral component interconnect fast interface, so that the access initiating processor returns the first task data according to the first read request and stores it in the cache space in the shared buffer component of the access initiating processor. Finally, the shared buffer component of the accessed processor is controlled to read the first task data from the shared buffer component of the access initiating processor through the data path, and write the first task data to the memory space of the accessed processor. After receiving the response, DMA1 initiates a request to read Buf0 data through the switch map module. After receiving the request, the switch map module forwards the request to Buf0 and establishes a data path from Buf0 to DMA1. The real path is actually fully established at this stage, and data writing begins at this time.

进一步的，本实施例会将写入数据进行分包以分段写入，对于每一个数据包，Buf0收到读请求后，一面通过switch map module中建立的数据通路将缓存的数据发送给DMA1，一面通过PCIE接口告知SOC0可以继续发送后续的任务数据到Buf0，Buf0通过自身缓存的多少对SOC0发送过来的数据速度进行流量控制。DMA1收到来自Buf0的数据后，通过PCIe接口发送该数据到SOC1的内存，并发送新的读请求到Buf0，读取新的数据并按照同样的操作写入SOC1的内存，直到完成整个任务数据的传输完成。Furthermore, this embodiment will packetize the write data to write in segments. For each data packet, after Buf0 receives the read request, it sends the cached data to DMA1 through the data path established in the switch map module, and informs SOC0 through the PCIE interface that it can continue to send subsequent task data to Buf0. Buf0 controls the flow rate of the data sent from SOC0 based on the amount of its own cache. After DMA1 receives the data from Buf0, it sends the data to the memory of SOC1 through the PCIe interface, and sends a new read request to Buf0, reads the new data and writes it to the memory of SOC1 according to the same operation until the transmission of the entire task data is completed.

传输完成后，被访问处理器的共享缓冲组件中的直接存储器访问控制器向交换重映射模块发送交互结束指令，以使交换重映射模块断开数据通路。同时被访问处理器的共享缓冲组件中的直接存储器访问控制器向被访问处理器发送中断指令，以使被访问处理器获取写入内存空间中的数据。DMA1发送传输结束信息给switch map module结束之前建立的数据通路，并发送中断给SOC1，告知数据传送完成，SOC1处理器可以从该内存中读取任务数据进行处理。After the transfer is completed, the direct memory access controller in the shared buffer component of the accessed processor sends an interaction end instruction to the switch remapping module to disconnect the data path. At the same time, the direct memory access controller in the shared buffer component of the accessed processor sends an interrupt instruction to the accessed processor to enable the accessed processor to obtain the data written into the memory space. DMA1 sends a transfer end message to the switch map module to end the previously established data path. And send an interrupt to SOC1 to inform that the data transfer is completed. The SOC1 processor can read the task data from the memory for processing.

图7为本申请实施例提供的一种具体的多处理器数据交互方法流程图。参见图7所示，该多处理器数据交互方法包括：FIG7 is a flowchart of a specific multi-processor data interaction method provided by an embodiment of the present application. Referring to FIG7 , the multi-processor data interaction method includes:

S31：控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息；其中，访问信息包括访问类型和访问数据量；访问类型包括读数据，访问数据量为与读数据对应的读取数据量。S31: controlling the shared buffer component of the access initiating processor to obtain access information from the access initiating processor; wherein the access information includes access type and access data volume; the access type includes read data, and the access data volume is the read data volume corresponding to the read data.

S32：访问发起处理器的共享缓冲组件中的缓存空间将存储的访问信息发送至交换重映射模块。S32: The access initiator sends the stored access information to the switch remapping module by accessing the cache space in the shared buffer component of the processor.

S33：交换重映射模块对访问信息进行解析的得到访问地址并根据***地址映射表将访问地址重映射为被访问处理器地址，以将访问信息发送至被访问处理器的共享缓冲组件中的直接存储器访问控制器，并建立访问发起处理器与被访问处理器之间的数据通路。S33: The exchange remapping module parses the access information to obtain the access address and remaps the access address to the accessed processor address according to the system address mapping table, so as to send the access information to the direct memory access controller in the shared buffer component of the accessed processor and establish a data path between the access initiating processor and the accessed processor.

本实施例中，主要针对读数据过程进行说明，关于上述步骤31至步骤S33的具体过程，可以参考前述实施例中公开的相应内容，在此不再进行赘述。以SOC0处理器写SOC1处理器内存空间为例对读数据过程进行具体说明：SOC0通过PCIE接口将要访问的内存地址信息发送到Buf0中，Buf0对该信息通过图5的地址映射表进行解析，识别出需要访问的内存在SOC1上，并获取到要读出的数据空间的大小，将这些信息通过switch map module，将Buf0中的信息发送到DMA1。In this embodiment, the data reading process is mainly described. For the specific process of the above steps 31 to S33, reference can be made to the corresponding content disclosed in the above embodiments, and no further description will be given here. Taking the SOC0 processor writing the SOC1 processor memory space as an example, the data reading process is specifically described: SOC0 sends the memory address information to be accessed to Buf0 through the PCIE interface, and Buf0 parses the information through the address mapping table of Figure 5, recognizes that the memory to be accessed is on SOC1, and obtains the size of the data space to be read, and sends the information in Buf0 to DMA1 through the switch map module.

S34：被访问处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向被访问发起处理器发送第二读取请求，以便被访问发起处理器根据第二读取请求返回第二任务数据并存储在被访问处理器的共享缓冲组件中的缓存空间。S34: The direct memory access controller in the shared buffer component of the accessed processor sends a second read request to the accessed initiating processor through the peripheral component interconnect fast interface, so that the accessed initiating processor returns the second task data according to the second read request and stores it in the cache space in the shared buffer component of the accessed processor.

S35：访问发起处理器的共享缓冲组件中的直接存储器访问控制器从被访问处理器的共享缓冲组件中的缓存空间读取第二任务数据，并通过***组件互联快速接口将第二任务数据写入访问处理器的内存空间。S35: The direct memory access controller in the shared buffer component of the access initiating processor reads the second task data from the cache space in the shared buffer component of the accessed processor, and writes the second task data into the memory space of the accessing processor through the PCI Express interface.

本实施例中，被访问处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向被访问发起处理器发送第二读取请求，以便被访问发起处理器根据第二读取请求返回第二任务数据并存储在被访问处理器的共享缓冲组件中的缓存空间。最后访问发起处理器的共享缓冲组件中的直接存储器访问控制器从被访问处理器的共享缓冲组件中的缓存空间读取第二任务数据，并通过***组件互联快速接口将第二任务数据写入访问处理器的内存空间。DMA1通过PCIE接口向SOC1发起地址空间的读数据请求，从SOC1的内存空间获得数据后，DMA1将数据缓存在Buf1中，并通过switch map moduleModule告知DMA0写入SOC1的数据请求，switch map module收到请求后，将该请求转发给DMA0，并建立起从Buf1到DMA0的数据通路。真正的通路其实是在这个阶段才完全建立起来，此时开始读取数据。In this embodiment, the direct memory access controller in the shared buffer component of the accessed processor sends a second read request to the accessed initiating processor through the peripheral component interconnect fast interface, so that the accessed initiating processor returns the second task data according to the second read request and stores it in the cache space in the shared buffer component of the accessed processor. Finally, the direct memory access controller in the shared buffer component of the accessing initiating processor reads the second task data from the cache space in the shared buffer component of the accessed processor, and writes the second task data to the memory space of the accessing processor through the peripheral component interconnect fast interface. DMA1 initiates a read data request of the address space to SOC1 through the PCIE interface. After obtaining the data from the memory space of SOC1, DMA1 caches the data in Buf1 and informs DMA0 of the data request to write SOC1 through the switch map moduleModule. After receiving the request, the switch map module forwards the request to DMA0 and establishes a data path from Buf1 to DMA0. The real path is actually fully established at this stage, and data reading begins at this time.

DMA0收到请求后，通过switch map module中建立的数据通路将缓存在Buf1的数据读出后，通过PCIE接口写入SOC0的内存。DMA1在Buf1数据被DMA0读出后，可以继续发送后续的读请求到SOC1内存，读取新的数据并按照同样的操作完成上面的过程，最终将所有数据写入到SOC0的内存中，直到完成整个任务数据的传输完成。After receiving the request, DMA0 reads the data cached in Buf1 through the data path established in the switch map module, and writes it to the memory of SOC0 through the PCIE interface. After the Buf1 data is read by DMA0, DMA1 can continue to send subsequent read requests to the SOC1 memory, read new data and complete the above process in the same way, and finally write all data to the memory of SOC0 until the entire task data transmission is completed.

同样的，传输完成后，被访问处理器的共享缓冲组件中的直接存储器访问控制器向交换重映射模块发送交互结束指令，以使交换重映射模块断开数据通路。同时访问处理器的共享缓冲组件中的直接存储器访问控制器向访问处理器发送中断指令，以使访问处理器获取读取到内存空间中的数据。DMA1发送传输结束信息给switch map module结束之前建立的数据通路，DMA0完成写入数据到SOC0内存后发送中断给SOC0，告知数据传送完成，SOC0处理器可以从该内存中读取任务数据的处理结果。Similarly, after the transmission is completed, the direct memory access controller in the shared buffer component of the accessed processor sends an interaction end instruction to the exchange remapping module to cause the exchange remapping module to disconnect the data path. The direct memory access controller in the buffer component sends an interrupt instruction to the access processor to enable the access processor to obtain the data read into the memory space. DMA1 sends a transfer end message to the switch map module to end the previously established data path. After DMA0 completes writing data to the SOC0 memory, it sends an interrupt to SOC0 to inform it that the data transfer is complete. The SOC0 processor can read the processing results of the task data from the memory.

不难理解，任意两个SOC处理器之间的数据交互与上面的例子类似，各个SOC之间的读写内存空间独立，互不干扰，从而可以实现读写数据全双工的并行交互。例如，SOC0可以向SOC1发送数据的同时，接收SOC1发送给SOC0的数据。It is not difficult to understand that the data interaction between any two SOC processors is similar to the above example. The read and write memory spaces between each SOC are independent and do not interfere with each other, so full-duplex parallel interaction of read and write data can be achieved. For example, SOC0 can send data to SOC1 while receiving data sent by SOC1 to SOC0.

综上，实施例二和实施例三示例的多SOC处理器的共享内存的快速数据交互方法，有助于利用基于ARM处理器的手机SOC处理器接口，直接实现多个SOC处理器的数据快速交互，从而能够在多个SOC处理器上快速进行任务派发，实现应用任务的平稳运行。在保持SOC处理器接口不变的情况下，能够同时兼容手机端和服务器端的使用，拓展了基于ARM处理器的手机SOC处理器应用场景，并能够与手机端SOC处理器的迭代速度相匹配，快速将基于ARM处理器的手机SOC处理器的服务器集群设备量产和市场化。In summary, the fast data interaction method of shared memory of multiple SOC processors in the examples of Embodiment 2 and Embodiment 3 helps to directly realize fast data interaction of multiple SOC processors by using the SOC processor interface of the mobile phone based on the ARM processor, so that tasks can be quickly dispatched on multiple SOC processors to achieve smooth operation of application tasks. While keeping the SOC processor interface unchanged, it can be compatible with the use of the mobile phone side and the server side at the same time, expand the application scenarios of the mobile phone SOC processor based on the ARM processor, and can match the iteration speed of the SOC processor on the mobile phone side, and quickly mass-produce and market the server cluster equipment of the mobile phone SOC processor based on the ARM processor.

参见图8所示，本申请实施例还相应公开了一种多处理器数据交互装置，包括：As shown in FIG8 , the embodiment of the present application further discloses a multi-processor data interaction device, including:

访问触发模块11，用于控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息；其中，访问发起处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接；An access trigger module 11 is used to control the shared buffer component of the access initiating processor to obtain access information from the access initiating processor; wherein the access initiating processor and its corresponding shared buffer component are connected via a peripheral component interconnect fast interface;

通路建立模块12，用于利用交换重映射模块基于***地址映射表对访问信息进行地址重映射以确定出被访问处理器地址，并建立访问发起处理器与被访问处理器之间的数据通路；A path establishing module 12, configured to use a switching remapping module to perform address remapping on access information based on a system address mapping table to determine an address of an accessed processor, and to establish a data path between an access initiating processor and an accessed processor;

数据交互模块13，用于控制访问发起处理器的共享缓冲组件通过数据通路与被访问处理器的共享缓冲组件进行数据交互；其中，被访问处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。The data interaction module 13 is used to control the shared buffer component of the access initiating processor to perform data interaction with the shared buffer component of the accessed processor through a data path; wherein the accessed processor and its corresponding shared buffer component are connected through a peripheral component interconnect fast interface.

在一些具体实施例中，访问触发模块11，具体用于访问发起处理器的共享缓冲组件中的直接存储器访问控制器通过直接存储器访问方式从访问发起处理器获取访问信息，并将访问信息在访问发起处理器的共享缓冲组件中的缓存空间进行存储。In some specific embodiments, the access trigger module 11 is specifically used to obtain access information from the access initiating processor through a direct memory access method by a direct memory access controller in a shared buffer component of the access initiating processor, and stores the access information in a cache space in the shared buffer component of the access initiating processor.

在一些具体实施例中，通路建立模块12，具体包括：In some specific embodiments, the path establishing module 12 specifically includes:

信息发送单元，用于访问发起处理器的共享缓冲组件中的缓存空间将存储的访问信息发送至交换重映射模块；An information sending unit, configured to access the cache space in the shared buffer component of the initiating processor and send the stored access information to the switch remapping module;

重映射单元，用于交换重映射模块对访问信息进行解析的得到访问地址并根据***地址映射表将访问地址重映射为被访问处理器地址，以将访问信息发送至被访问处理器的共享缓冲组件中的直接存储器访问控制器。A remapping unit is used to obtain an access address by parsing the access information with the exchange remapping module and remap the access address to the accessed processor address according to the system address mapping table, so as to send the access information to the shared cache of the accessed processor. Direct memory access controller in the buffer component.

在一些具体实施例中，多处理器数据交互装置中的访问信息包括访问类型和访问数据量；其中，访问类型包括写数据和读数据中的至少一种，访问数据量为与写数据对应的写入数据量和与读数据对应的读取数据量；In some specific embodiments, the access information in the multi-processor data interaction device includes an access type and an access data amount; wherein the access type includes at least one of write data and read data, and the access data amount is a write data amount corresponding to the write data and a read data amount corresponding to the read data;

相应的，数据交互模块13，具体包括：Correspondingly, the data interaction module 13 specifically includes:

写数据模块，用于如果访问类型为写数据，则控制被访问处理器的共享缓冲组件通过数据通路从访问发起处理器的共享缓冲组件中读取第一任务数据，并将第一任务数据写入被访问处理器的内存空间；a data writing module, configured to control the shared buffer component of the accessed processor to read the first task data from the shared buffer component of the access initiating processor through a data path if the access type is data writing, and write the first task data into the memory space of the accessed processor;

读数据模块，用于如果访问类型为读数据，则控制访问发起处理器的共享缓冲组件通过数据通路对被访问处理器的共享缓冲组件中读取第二任务数据，并将第二任务数据写入访问处理器的内存空间。The data reading module is used to control the shared buffer component of the access initiating processor to read the second task data from the shared buffer component of the accessed processor through the data path if the access type is read data, and write the second task data into the memory space of the accessing processor.

在一些具体实施例中，多处理器数据交互装置还包括：In some specific embodiments, the multi-processor data interaction device further includes:

内存分配模块，用于如果访问类型为写数据，则被访问处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向被访问发起处理器发送写入请求，以便被访问处理器分配与写入数据量相适应的用于存储第一任务数据的内存空间；a memory allocation module, configured to, if the access type is to write data, cause a direct memory access controller in a shared buffer component of the accessed processor to send a write request to the accessed initiating processor through a peripheral component interconnect fast interface, so that the accessed processor allocates a memory space for storing the first task data that is adapted to the amount of write data;

第一任务数据获取模块，用于访问发起处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向访问发起处理器发送第一读取请求，以便访问发起处理器根据第一读取请求返回第一任务数据并存储在访问发起处理器的共享缓冲组件中的缓存空间；A first task data acquisition module, configured to send a first read request to the access initiating processor via a peripheral component interconnect fast interface to enable the access initiating processor to return the first task data according to the first read request and store the first task data in a cache space in the shared buffer component of the access initiating processor;

第二任务数据获取模块，用于被访问处理器的共享缓冲组件中的直接存储器访问控制器通过***组件互联快速接口向被访问发起处理器发送第二读取请求，以便被访问发起处理器根据第二读取请求返回第二任务数据并存储在被访问处理器的共享缓冲组件中的缓存空间；A second task data acquisition module, used for a direct memory access controller in a shared buffer component of an accessed processor to send a second read request to an accessed initiating processor through a peripheral component interconnect fast interface, so that the accessed initiating processor returns the second task data according to the second read request and stores it in a cache space in the shared buffer component of the accessed processor;

通路断开模块，用于被访问处理器的共享缓冲组件中的直接存储器访问控制器向交换重映射模块发送交互结束指令，以使交换重映射模块断开数据通路；A path disconnection module is used for a direct memory access controller in a shared buffer component of an accessed processor to send an interaction end instruction to the exchange remapping module so that the exchange remapping module disconnects the data path;

第一中断指令发送模块，用于访问处理器的共享缓冲组件中的直接存储器访问控制器向访问处理器发送中断指令，以使访问处理器获取读取到内存空间中的数据；A first interrupt instruction sending module, configured to send an interrupt instruction to the access processor from a direct memory access controller in a shared buffer component of the access processor, so that the access processor acquires data read into the memory space;

第二中断指令发送模块，用于被访问处理器的共享缓冲组件中的直接存储器访问控制器向被访问处理器发送中断指令，以使被访问处理器获取写入内存空间中的数据。The second interrupt instruction sending module is used for the direct memory access controller in the shared buffer component of the accessed processor to send an interrupt instruction to the accessed processor, so that the accessed processor obtains the data written into the memory space.

在一些具体实施例中，写数据模块，具体用于被访问处理器的共享缓冲组件中的直接存储器访问控制器从访问发起处理器的共享缓冲组件中的缓存空间读取第一任务数据，并通过***组件互联快速接口将第一任务数据写入被访问处理器的内存空间。In some specific embodiments, a data write module, specifically a direct memory access controller in a shared buffer component of an accessed processor, reads first task data from a cache space in a shared buffer component of an access initiating processor, and writes the first task data into a memory space of the accessed processor through a peripheral component interconnect fast interface.

在一些具体实施例中，读数据模块，具体用于访问发起处理器的共享缓冲组件中的直接存储器访问控制器从被访问处理器的共享缓冲组件中的缓存空间读取第二任务数据，并通过***组件互联快速接口将第二任务数据写入访问处理器的内存空间。In some specific embodiments, the data reading module is specifically used to access the direct memory access controller in the shared buffer component of the initiating processor to read the second task data from the cache space in the shared buffer component of the accessed processor, and write the second task data to the memory space of the accessing processor through the peripheral component interconnect fast interface.

进一步的，本申请实施例还提供了一种电子设备。图9是根据一示例性实施例示出的电子设备20结构图，图中的内容不能认为是对本申请的使用范围的任何限制。Furthermore, an embodiment of the present application also provides an electronic device. Fig. 9 is a structural diagram of an electronic device 20 according to an exemplary embodiment, and the content in the diagram cannot be regarded as any limitation on the scope of application of the present application.

图9为本申请实施例提供的一种电子设备20的结构示意图。该电子设备20，具体可以包括：至少一个处理器21、至少一个存储器22、电源23、通信接口24、输入输出接口25和通信总线26。其中，存储器22用于存储计算机程序，计算机程序由处理器21加载并执行，以实现前述任一实施例公开的多处理器数据交互方法中的相关步骤。 FIG9 is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input/output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the multi-processor data interaction method disclosed in any of the aforementioned embodiments.

本实施例中，电源23用于为电子设备20上的各硬件设备提供工作电压；通信接口24能够为电子设备20创建与外界设备之间的数据传输通道，其所遵循的通信协议是能够适用于本申请技术方案的任意通信协议，在此不对其进行具体限定；输入输出接口25，用于获取外界输入数据或向外界输出数据，其具体的接口类型可以根据具体应用需要进行选取，在此不进行具体限定。In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

另外，存储器22作为资源存储的载体，可以是只读存储器、随机存储器、磁盘或者光盘等，其上所存储的资源可以包括操作***221、计算机程序222及数据223等，存储方式可以是短暂存储或者永久存储。In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

其中，操作***221用于管理与控制电子设备20上的各硬件设备以及计算机程序222，以实现处理器21对存储器22中海量数据223的运算与处理，其可以是Windows Server、Netware、Unix、Linux等。计算机程序222除了包括能够用于完成前述任一实施例公开的由电子设备20执行的多处理器数据交互方法的计算机程序之外，还可以进一步包括能够用于完成其他特定工作的计算机程序。数据223可以包括电子设备20收集到的访问信息等数据。The operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the massive data 223 in the memory 22 by the processor 21, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the multi-processor data interaction method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks. The data 223 can include data such as access information collected by the electronic device 20.

进一步的，本申请实施例还公开了一种存储介质，存储介质中存储有计算机程序，计算机程序被处理器加载并执行时，实现前述任一实施例公开的多处理器数据交互方法步骤。Furthermore, an embodiment of the present application also discloses a storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the steps of the multi-processor data interaction method disclosed in any of the aforementioned embodiments are implemented.

本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个…”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

以上对本申请所提供的多处理器数据交互方法、装置、设备及存储介质进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。 The multi-processor data interaction method, device, equipment and storage medium provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

一种多处理器数据交互方法，其特征在于，包括：A multi-processor data interaction method, characterized by comprising:

控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息；其中，访问发起处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接；The shared buffer component of the access initiating processor is controlled to obtain access information from the access initiating processor; wherein the access initiating processor and its corresponding shared buffer component are connected via a peripheral component interconnect fast interface;

利用交换重映射模块基于***地址映射表对所述访问信息进行地址重映射以确定出被访问处理器地址，并建立访问发起处理器与被访问处理器之间的数据通路；Using a switching remapping module to perform address remapping on the access information based on a system address mapping table to determine the address of the accessed processor, and to establish a data path between the access initiating processor and the accessed processor;

控制访问发起处理器的共享缓冲组件通过所述数据通路与被访问处理器的共享缓冲组件进行数据交互；其中，被访问处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。The shared buffer component of the access initiating processor is controlled to perform data interaction with the shared buffer component of the accessed processor through the data path; wherein the accessed processor and its corresponding shared buffer component are connected through a peripheral component interconnect fast interface.
根据权利要求1所述的多处理器数据交互方法，其特征在于，所述控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息，包括：The multi-processor data interaction method according to claim 1, characterized in that the shared buffer component controlling the access initiating processor obtains access information from the access initiating processor, comprising:

访问发起处理器的共享缓冲组件中的直接存储器访问控制器通过直接存储器访问方式从访问发起处理器获取所述访问信息，并将所述访问信息在访问发起处理器的共享缓冲组件中的缓存空间进行存储。The direct memory access controller in the shared buffer component of the access initiating processor obtains the access information from the access initiating processor in a direct memory access manner, and stores the access information in a cache space in the shared buffer component of the access initiating processor.
根据权利要求2所述的多处理器数据交互方法，其特征在于，所述利用交换重映射模块基于***地址映射表对所述访问信息进行地址重映射以确定出被访问处理器地址，包括：The multi-processor data interaction method according to claim 2 is characterized in that the use of the exchange remapping module to perform address remapping on the access information based on the system address mapping table to determine the address of the accessed processor comprises:

访问发起处理器的共享缓冲组件中的缓存空间将存储的所述访问信息发送至所述交换重映射模块；Accessing the cache space in the shared buffer component of the initiating processor to send the stored access information to the switch remapping module;

所述交换重映射模块对所述访问信息进行解析的得到访问地址并根据所述***地址映射表将所述访问地址重映射为被访问处理器地址，以将所述访问信息发送至被访问处理器的共享缓冲组件中的直接存储器访问控制器。The exchange remapping module parses the access information to obtain an access address and remaps the access address to an accessed processor address according to the system address mapping table, so as to send the access information to a direct memory access controller in a shared buffer component of the accessed processor.
根据权利要求3所述的多处理器数据交互方法，其特征在于，所述访问信息包括访问类型和访问数据量；其中，所述访问类型包括写数据和读数据中的至少一种，所述访问数据量为与写数据对应的写入数据量和与读数据对应的读取数据量；The multi-processor data interaction method according to claim 3, characterized in that the access information includes an access type and an access data amount; wherein the access type includes at least one of write data and read data, and the access data amount is a write data amount corresponding to the write data and a read data amount corresponding to the read data;

相应的，所述控制访问发起处理器的共享缓冲组件通过所述数据通路与被访问处理器的共享缓冲组件进行数据交互，包括：Correspondingly, the control accesses the shared buffer component of the initiating processor to perform data interaction with the shared buffer component of the accessed processor through the data path, including:

如果访问类型为写数据，则控制被访问处理器的共享缓冲组件通过所述数据通路从访问发起处理器的共享缓冲组件中读取第一任务数据，并将所述第一任务数据写入被访问处理器的内存空间；If the access type is writing data, controlling the shared buffer component of the accessed processor to read the first task data from the shared buffer component of the access initiating processor through the data path, and writing the first task data into the memory space of the accessed processor;

如果访问类型为读数据，则控制访问发起处理器的共享缓冲组件通过所述数据通路对被访问处理器的共享缓冲组件中读取第二任务数据，并将所述第二任务数据写入访问处理器的内存空间。If the access type is to read data, the shared buffer component of the access initiating processor is controlled to read the second task data from the shared buffer component of the accessed processor through the data path, and write the second task data into the memory space of the accessing processor.
根据权利要求4所述的多处理器数据交互方法，其特征在于，所述交换重映射模块将所述访问信息发送至被访问处理器的共享缓冲组件中的直接存储器访问控制器之后，还包括：The multi-processor data interaction method according to claim 4 is characterized in that after the exchange remapping module sends the access information to the direct memory access controller in the shared buffer component of the accessed processor, it also includes:

如果访问类型为写数据，则被访问处理器的共享缓冲组件中的直接存储器访问控制器通过所述***组件互联快速接口向被访问发起处理器发送写入请求，以便被访问处理器分配与写入数据量相适应的用于存储所述第一任务数据的内存空间。 If the access type is writing data, the direct memory access controller in the shared buffer component of the accessed processor sends a write request to the accessed initiating processor through the peripheral component interconnect fast interface, so that the accessed processor allocates memory space for storing the first task data corresponding to the amount of write data.
根据权利要求4所述的多处理器数据交互方法，其特征在于，所述控制被访问处理器的共享缓冲组件通过所述数据通路从访问发起处理器的共享缓冲组件中读取第一任务数据之前，还包括：The multi-processor data interaction method according to claim 4 is characterized in that before the shared buffer component of the accessed processor is controlled to read the first task data from the shared buffer component of the access initiating processor through the data path, it also includes:

访问发起处理器的共享缓冲组件中的直接存储器访问控制器通过所述***组件互联快速接口向访问发起处理器发送第一读取请求，以便访问发起处理器根据所述第一读取请求返回所述第一任务数据并存储在访问发起处理器的共享缓冲组件中的缓存空间。The direct memory access controller in the shared buffer component of the access initiating processor sends a first read request to the access initiating processor through the peripheral component interconnect fast interface, so that the access initiating processor returns the first task data according to the first read request and stores it in the cache space in the shared buffer component of the access initiating processor.
根据权利要求6所述的多处理器数据交互方法，其特征在于，所述控制被访问处理器的共享缓冲组件通过所述数据通路从访问发起处理器的共享缓冲组件中读取第一任务数据，并将所述第一任务数据写入被访问处理器的内存空间，包括：The multi-processor data interaction method according to claim 6 is characterized in that the shared buffer component controlling the accessed processor reads the first task data from the shared buffer component of the access initiating processor through the data path, and writes the first task data into the memory space of the accessed processor, comprising:

被访问处理器的共享缓冲组件中的直接存储器访问控制器从访问发起处理器的共享缓冲组件中的缓存空间读取所述第一任务数据，并通过所述***组件互联快速接口将所述第一任务数据写入被访问处理器的内存空间。The direct memory access controller in the shared buffer component of the accessed processor reads the first task data from the cache space in the shared buffer component of the access initiating processor, and writes the first task data into the memory space of the accessed processor through the peripheral component interconnect fast interface.
根据权利要求4所述的多处理器数据交互方法，其特征在于，所述控制访问发起处理器的共享缓冲组件通过所述数据通路对被访问处理器的共享缓冲组件中读取第二任务数据之前，还包括：The multi-processor data interaction method according to claim 4 is characterized in that before the shared buffer component of the access initiating processor is controlled to read the second task data from the shared buffer component of the accessed processor through the data path, it also includes:

被访问处理器的共享缓冲组件中的直接存储器访问控制器通过所述***组件互联快速接口向被访问发起处理器发送第二读取请求，以便被访问发起处理器根据所述第二读取请求返回所述第二任务数据并存储在被访问处理器的共享缓冲组件中的缓存空间。The direct memory access controller in the shared buffer component of the accessed processor sends a second read request to the accessed initiating processor through the peripheral component interconnect fast interface, so that the accessed initiating processor returns the second task data according to the second read request and stores it in the cache space in the shared buffer component of the accessed processor.
根据权利要求8所述的多处理器数据交互方法，其特征在于，所述控制访问发起处理器的共享缓冲组件通过所述数据通路对被访问处理器的共享缓冲组件中读取第二任务数据，并将所述第二任务数据写入访问处理器的内存空间，包括：The multi-processor data interaction method according to claim 8, characterized in that the shared buffer component of the access initiating processor is controlled to read the second task data from the shared buffer component of the accessed processor through the data path, and write the second task data into the memory space of the accessing processor, comprising:

访问发起处理器的共享缓冲组件中的直接存储器访问控制器从被访问处理器的共享缓冲组件中的缓存空间读取所述第二任务数据，并通过所述***组件互联快速接口将所述第二任务数据写入访问处理器的内存空间。The direct memory access controller in the shared buffer component of the access initiating processor reads the second task data from the cache space in the shared buffer component of the accessed processor, and writes the second task data into the memory space of the accessing processor through the peripheral component interconnect express interface.
根据权利要求4至9任一项所述的多处理器数据交互方法，其特征在于，控制处理器的共享缓冲组件读取任务数据之后，还包括：The multi-processor data interaction method according to any one of claims 4 to 9 is characterized in that after the shared buffer component of the control processor reads the task data, it also includes:

被访问处理器的共享缓冲组件中的直接存储器访问控制器向所述交换重映射模块发送交互结束指令，以使所述交换重映射模块断开所述数据通路。The direct memory access controller in the shared buffer component of the accessed processor sends an interaction end instruction to the exchange remapping module, so that the exchange remapping module disconnects the data path.
根据权利要求10所述的多处理器数据交互方法，其特征在于，将任务数据写入处理器的内存空间之后，还包括：The multi-processor data interaction method according to claim 10 is characterized in that after writing the task data into the memory space of the processor, it also includes:

访问处理器的共享缓冲组件中的直接存储器访问控制器向访问处理器发送中断指令，以使访问处理器获取读取到内存空间中的数据；A direct memory access controller in a shared buffer component of the access processor sends an interrupt instruction to the access processor so that the access processor acquires the data read into the memory space;

被访问处理器的共享缓冲组件中的直接存储器访问控制器向被访问处理器发送中断指令，以使被访问处理器获取写入内存空间中的数据。The direct memory access controller in the shared buffer component of the accessed processor sends an interrupt instruction to the accessed processor, so that the accessed processor obtains the data written into the memory space.
根据权利要求1至9任一项所述的多处理器数据交互方法，其特征在于，访问发起处理器和被访问处理器为***级芯片集群中的任意两个处理器。The multi-processor data interaction method according to any one of claims 1 to 9 is characterized in that the access initiating processor and the accessed processor are any two processors in a system-on-chip cluster.
根据权利要求3所述的多处理器数据交互方法，其特征在于，The multi-processor data interaction method according to claim 3 is characterized in that:

交换重映射模块根据***扩展内存映射表，在数据任务分发时通过内存目标地址进行路由译码，建立从目标内存所在处理器接口到本地存储数据的缓存空间的数据链路，再由对应直接存储器访问控制器引擎发起请求，从缓存空间中读取数据，通过建立的数据链路，将数据写入目标内存中。The exchange remapping module uses the system extended memory mapping table to perform routing decoding through the memory target address when distributing data tasks, establishes a data link from the processor interface where the target memory is located to the cache space where the local data is stored, and then the corresponding direct memory access controller engine initiates a request to read data from the cache space. According to the link, the data is written to the target memory.
根据权利要求4所述的多处理器数据交互方法，其特征在于，所述第一任务数据为任务，所述第二任务数据为任务执行结果。The multi-processor data interaction method according to claim 4 is characterized in that the first task data is a task, and the second task data is a task execution result.
根据权利要求4所述的多处理器数据交互方法，其特征在于，还包括：The multi-processor data interaction method according to claim 4, characterized in that it also includes:

在数据传输过程中，将写入数据进行分包以分段写入。During data transmission, the write data is packetized and written in segments.
根据权利要求4所述的多处理器数据交互方法，其特征在于，还包括：The multi-processor data interaction method according to claim 4, characterized in that it also includes:

在传输完成后，被访问处理器的共享缓冲组件中的直接存储器访问控制器向交换重映射模块发送交互结束指令，以使交换重映射模块断开数据通路。After the transmission is completed, the direct memory access controller in the shared buffer component of the accessed processor sends an interaction end instruction to the exchange remapping module, so that the exchange remapping module disconnects the data path.
根据权利要求4所述的多处理器数据交互方法，其特征在于，还包括：The multi-processor data interaction method according to claim 4, characterized in that it also includes:

在传输完成后，被访问处理器的共享缓冲组件中的直接存储器访问控制器向被访问处理器发送中断指令，以使被访问处理器获取写入内存空间中的数据。After the transmission is completed, the direct memory access controller in the shared buffer component of the accessed processor sends an interrupt instruction to the accessed processor, so that the accessed processor obtains the data written into the memory space.
一种多处理器数据交互装置，其特征在于，包括：A multi-processor data interaction device, characterized by comprising:

访问触发模块，用于控制访问发起处理器的共享缓冲组件从访问发起处理器获取访问信息；其中，访问发起处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接；An access trigger module is used to control the shared buffer component of the access initiating processor to obtain access information from the access initiating processor; wherein the access initiating processor and its corresponding shared buffer component are connected via a peripheral component interconnect fast interface;

通路建立模块，用于利用交换重映射模块基于***地址映射表对所述访问信息进行地址重映射以确定出被访问处理器地址，并建立访问发起处理器与被访问处理器之间的数据通路；A path establishing module, used for performing address remapping on the access information based on the system address mapping table by using the exchange remapping module to determine the address of the accessed processor, and establishing a data path between the access initiating processor and the accessed processor;

数据交互模块，用于控制访问发起处理器的共享缓冲组件通过所述数据通路与被访问处理器的共享缓冲组件进行数据交互；其中，被访问处理器与其对应的共享缓冲组件之间通过***组件互联快速接口进行连接。The data interaction module is used to control the shared buffer component of the access initiating processor to perform data interaction with the shared buffer component of the accessed processor through the data path; wherein the accessed processor and its corresponding shared buffer component are connected through a peripheral component interconnect fast interface.
一种电子设备，其特征在于，所述电子设备包括处理器和存储器；其中所述存储器用于存储计算机程序，所述计算机程序由所述处理器加载并执行以实现如权利要求1至17任一项所述的多处理器数据交互方法。An electronic device, characterized in that the electronic device includes a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the multi-processor data interaction method as described in any one of claims 1 to 17.
一种非易失性可读存储介质，其特征在于，用于存储计算机可执行指令，所述计算机可执行指令被处理器加载并执行时，实现如权利要求1至17任一项所述的多处理器数据交互方法。 A non-volatile readable storage medium, characterized in that it is used to store computer executable instructions, and when the computer executable instructions are loaded and executed by a processor, the multi-processor data interaction method as described in any one of claims 1 to 17 is implemented.