TW480599B - Manufacture method of disposable spacer reverse source/drain process - Google Patents

Abstract

This invention provides a manufacture method of disposable spacer reverse source/drain process to for a lightly doped drain (LDD) metal oxide semiconductor field effect transistor (MOSFET), which consists of following steps: forming a gate electrode on a semiconductor substrate; forming a disposable spacer on opposite side of the gate electrode; implanting a heavy dose impurity in the substrate to form a heavily doped region; removing the disposable spacer; and implanting a light dose impurity to complete the first-heavy-later-light ion implantation step, which is reverse from the conventional first-light-later-heavy process and thus is called reverse source/drain manufacture process. The advantage of the inventive method is to reduce greatly in transient enhanced diffusion and thus can be applied to the formation of extreme shallow junction for sub-micro MOS device.

Description

480599 五、發明說明（1) 【發明領域】 本發明係關於一種使用拋棄式間隙側壁之反向源極/ 汲極製程，尤其關於一種使用拋棄式間隙侧壁之反向源極 /沒極製程，用以製造次微米輕摻雜汲極（Lightly Doped Drain ’ LDD)金屬氧化物半導體場效電晶體 (Metal-Oxide-Semiconductor Field-Effect，M0SFET)於 一半導體基板上。 【發明背景】 在先進的半導體積體電路中，M0SFET被廣泛地應用於 各種不同之電子產品。舉例而言，今日的動態隨機存取記 憶體（Dynamic Random Access Memory，DRAM)之單元大多 由一 MOSFET與一電容所組成。隨著半導體技術之進步， M0SFET之尺寸大大降低至次微米數量級，以增加半導體記 憶體之積集度。換言之，在單一的半導體基板上可容納更 多個由MOSFET所組成之記憶體單元。此積集度之增加帶來 二項優點：量產率之提昇以及製造成本之減低。 然而，在次微米MOSFET中，仍有若干技術問題必須解 決。此類問題中之一即所謂的熱載子效應（h〇t carrier· ef feet)，下文中將說明此效應。由於尺寸降低，在 MOSFET中，介於源極與汲極區域間之載子通道被縮短。因 而，當由源極區域所供應之載子，在汲極區域附近受到夹 止（pinch-off)區域附近的高電場之突然加速時，具有極 高能量之載子會產生於通道中。由於具有極高能量，此類480599 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a reverse source / drain process using a disposable gap sidewall, and more particularly to a reverse source / stepless process using a disposable gap sidewall. For fabricating sub-micron lightly doped drain (LDD) metal-oxide semiconductor field-effect transistors (MOS-FETs) on a semiconductor substrate. [Background of the Invention] In advanced semiconductor integrated circuits, MOSFETs are widely used in various electronic products. For example, most units of today's Dynamic Random Access Memory (DRAM) are composed of a MOSFET and a capacitor. With the advancement of semiconductor technology, the size of MOSFETs has been greatly reduced to the order of sub-microns in order to increase the accumulation of semiconductor memories. In other words, more memory cells composed of MOSFETs can be accommodated on a single semiconductor substrate. This increase in the degree of accumulation brings two advantages: an increase in volume yield and a reduction in manufacturing costs. However, in sub-micron MOSFETs, there are still several technical issues that must be resolved. One such problem is the so-called hot carrier effect (effect carrier effect), which will be explained below. Due to the reduced size, the carrier channel between the source and drain regions is shortened in the MOSFET. Therefore, when carriers supplied from the source region are suddenly accelerated by a high electric field near the pinch-off region near the drain region, carriers with extremely high energy are generated in the channel. Due to its extremely high energy, this class

第4頁 480599 五、發明說明（2) 熱載子。熱載子有機會注入閘極電極中，而使 決熱⑽)Λ構之隱^已被發明作為解 ⑽瞻以；=法’將參照圖1U)至1⑴，詳細說明 中所干，Λ Λ 習知方法的剖面圖。如圖Ka) 上。L ? 膜12形成於一半導體基板10例如矽 石夕膜13與一蓋覆閘極氧化物膜Η分別形 成於閘極氧化物膜][2上。 、刀〜❿ 化物二广3:!^ ，蓋覆間極氧 化物膜12上，球以疋義一閘極電極13a於閘極氧 夂昭isnr ”極電極係受一氧化物膜143所覆蓋。 ^ j圖1(c)，使用磷離子之第一離子植入ιι〇施行於 右一 =之結構之整個表面上，該第一離子植入110具 區域ιΖ/。里與一低植入能量，以形成輕摻雜1^型源極/汲極 =圖1(d)，藉由習知的化學氣相沉積法（，一 J化石夕臈15沉積於圖1(〇所示之結構之整個表面 後，如圖Ke)中所示’藉由習知的反應性離子钱刻法 (RIE)，部分蝕刻氧化矽膜15與閘極氧化物膜丨〗 壁1 5a於閘極電極丨3a與氧化物膜丨4a之每一相對侧上。 繼之，參照圖1(f)，以間隙側壁15a作為遮罩，使用 國 第5頁Page 4 480599 V. Description of the invention (2) Hot carrier. The hot carriers have the opportunity to be injected into the gate electrode, so that the heat is determined. ⑽) The structure of ^ has been invented as a solution; = method will refer to Figures 1U) to 1⑴. In the detailed description, Λ Λ A cross-sectional view of a conventional method. (Figure Ka). The L? Film 12 is formed on a semiconductor substrate 10 such as a silica film 13 and a gate oxide film Η, respectively, on the gate oxide film] [2. The electrode is covered with a metal oxide film 3:! ^, And the interlayer oxide film 12 is covered, and the ball is covered with an oxide film 143 with a gate electrode 13a on the gate electrode. ^ j Figure 1 (c), the first ion implantation using phosphorus ions is performed on the entire surface of the first right structure, the first ion implantation in 110 areas and a low implantation energy In order to form a lightly doped 1 ^ -type source / drain = FIG. 1 (d), a conventional chemical vapor deposition method (a J-fossil evening 臈 15 is deposited on the structure shown in FIG. 1 (0) After the entire surface, as shown in FIG. Ke) ', the silicon oxide film 15 and the gate oxide film are partially etched by the conventional reactive ion etching (RIE) method. The wall 15a is at the gate electrode 3a. On each side opposite to the oxide film 4a. Next, referring to FIG. 1 (f), the gap side wall 15a is used as a mask, using the country page 5

=子之第二離子植入12G施行於圖1(e)所示之結構之整 =面上該第一離子植入120相較於第一離子植入u〇， 量與一較高植入能量。因此，形成具有較深 :面之重私雜N型源極/汲極區域1〇2，而完成習知的ldd NMOS。 圖1(f)中明白顯示，LDD隨⑽具有一自對準的輕摻雜 域1〇la，其形成於通道與重摻雜N型源極/汲極區 域102間/ ☆因為此輕摻雜N型區域1〇 u使汲極接面附近之電 位分佈變緩和’以降低電場，所以減輕前述由源極區域供 應之電子党到極高電場加速之問題。因此，藉由ldd結構 之使用，可減輕熱載子注入對次微米M〇SFET產生之$化 應。 ^ 雖然LDD結構對於降低電場十分有效，然而，習知的 製程仍有若干缺點。 /首先，在間隙側壁l5a形成之前，輕摻雜1^}型區域1〇】& 先形成，因此間隙侧壁丨5a形成期間所附帶之熱效應 (thermal budget)，對於輕摻雜N型區域1〇la造成不可忽 略之影響。換言之，由於在間隙侧壁之形成期間中， 雜質（在NMOS例子中即為磷離子）之暫態擴散增益 (Transient Enhanced Diffusi〇n，TED)效應，加速輕摻 雜N型區域l〇la朝垂直與水平兩方向擴展。 此外’用以形成輕摻雜N型區域1〇la之第一離子植入 110會k成缺，例如石夕間隙（interstitial)於半導體某 板中。此等缺陷將與雜質發生交互作用，導致雜質之土= The second ion implantation 12G is performed on the structure shown in Fig. 1 (e) = the surface of the first ion implantation 120 is higher than the first ion implantation u0, and the amount is a higher implantation energy. Therefore, a deep private N-type source / drain region 102 is formed, and the conventional ldd NMOS is completed. It is clearly shown in FIG. 1 (f) that the LDD has a self-aligned lightly doped domain 10a, which is formed between the channel and the heavily doped N-type source / drain region 102 / because of this light doping The hetero-N-type region 10u slows down the potential distribution near the drain junction to reduce the electric field, so the aforementioned problem of acceleration of the electron field supplied from the source region to a very high electric field is alleviated. Therefore, the use of the ldd structure can reduce the effect of hot carrier injection on submicron MOSFETs. ^ Although the LDD structure is very effective in reducing the electric field, the conventional process still has several disadvantages. / First, lightly doped 1 ^}-type region 10] is formed before the gap sidewall 15a is formed. Therefore, the thermal budget attached to the gap sidewall 5a during the formation of the light-doped N-type region 10la causes a non-negligible effect. In other words, the transient diffusion gain (TED) effect of impurities (phosphorus ions in the NMOS example) during the formation of the gap sidewall accelerates the lightly doped N-type region 10a toward Expand in both vertical and horizontal directions. In addition, the first ion implantation 110 used to form the lightly doped N-type region 10la will be deficient in k, for example, interstitial in a semiconductor plate. These defects will interact with impurities, leading to the soil of impurities

第6頁Page 6

辦w ϊ後，在間隙側壁15a形成之後，藉由第二離子插 >成之重摻雜N型源極/汲極區域丨02使更多的入 生’且更增強雜質之TED。 、句產 因而，習知製程難以達成可應用於次微米 接面。 b 1千之極淺 【發明概述】 有鑒於LDD MOSFET之習知製造方法的缺點， 二月之一目的在於，提供一種新穎製程，其中_ ，本 退火’以即時修補重劑量植入所產生 更進仃決連、熱 LDD雜質盥前诚址於技^ ^ &座玍之缺，猎以防止 …、引述缺陷發生父互作用所導致之TED。 劑量離：：之又一目的在於’提供-種新穎製程，1中重 質之TED，該咖係由重劑量植J 瓌^防止雜 成。 · 〜 Μ座生之知壞與缺陷所造 没極本：…種使用抛棄式間隙侧壁之反向源極/ 含下C驟:ί形成：·ΕΤ元件於-半導體基板上，包 化物膜於該半步驟第u-閘極氧After w is performed, after the formation of the gap sidewall 15a, the heavily doped N-type source / drain region by the second ion insertion > 02 is used to make more entrances ' and the TED of the impurities is more enhanced. Therefore, it is difficult for the conventional process to achieve submicron junctions. b Extremely shallow for one thousand [Summary of the invention] In view of the shortcomings of the conventional manufacturing method of LDD MOSFET, one of the objectives of February is to provide a novel process, in which _, this annealing 'immediately repairs the heavy dose implantation to produce more In order to prevent TED caused by parental interaction, the defect of thermal LDD impurities is located in the technology ^ ^ & seat, in order to prevent ..., cited defects. Dosage separation :: Another purpose is to provide a novel process, 1 heavy TED, this coffee line is prevented from mixing by heavy dose planting. · ~ M-thickness and defects caused by defects: ... a reverse source using a discontinuous gap sidewall / containing the following step C: formation: · ET device on-semiconductor substrate, clad film U-gate oxygen

第7頁 五、發明說明（5) :積；！！膜於該問極氧化物膜上；一光阻遮罩形成步 =由光微影印刷術以形成一圖案化光阻臈於該導 —閘極電極形成步驟，使用該圖案化光阻膜作、 餘刻該導電膜，以形成一閘極電極；一第二沉^ 用以沉積一絕緣膜於該閘極電極與該閘極氧=物ς 一一間隙壁形成步驟，用以部分蝕刻該絕緣膜，以带 =式間隙側壁於該閘極電極之每一相對側上；一重二 拎：域形成步驟’用以施行一第一離子植入，以形成―二 區域於該半導體基板内；一間隙壁移除步驟，用以 =邊間隙側壁；以及一輕摻雜區域形成步驟，用以施行— 一離子植入，以形成一輕摻雜區域於該半導體基板内。 【較佳實施例之詳細說明】 實施=將參照圖2(a)至2(h)，詳細說明依據本發明之較佳 如圖2(a)中所示，藉由習知的熱處理，一厚度約 9 mn之閘極氧化物膜21形成於一半導體基板2〇例如矽 22二藉由⑽法’ 一厚度約為100至150⑽之導電膜 Η如夕晶矽膜，形成於閘極氧化物膜以 。導電膜22得包含複數個疊製層，舉例而言應=一 矽層；一矽化鎢層，形成於該多晶矽層上；一氧化矽 ^ ^成於該石夕化鶴層上；以及一氮化矽層，形成於該氧 石曰上。隨後，藉由習知的光微影印刷術 (ph〇t〇lithography)，使圖案化光阻膜2〇()形成於該導體 480599Page 7 V. Description of the Invention (5): Product; !! Film on the interlayer oxide film; a photoresist mask forming step = photolithography to form a patterned photoresist in the conducting-gate electrode forming step, using the patterned photoresist film as 2. The conductive film is etched to form a gate electrode; a second electrode is used for depositing an insulating film on the gate electrode and the gate oxygen = a gap forming step for partially etching the gate electrode; An insulating film with a tape-type gap sidewall on each of the opposite sides of the gate electrode; a double layer: a field formation step 'for performing a first ion implantation to form two regions in the semiconductor substrate; A gap removing step is used to = an edge gap sidewall; and a lightly doped region forming step is performed to perform an ion implantation to form a lightly doped region in the semiconductor substrate. [Detailed description of the preferred embodiment] Implementation = The detailed description of the preferred embodiment according to the present invention is shown in FIG. 2 (a) with reference to FIGS. 2 (a) to 2 (h). A gate oxide film 21 having a thickness of about 9 mn is formed on a semiconductor substrate 20, such as silicon 22, and a conductive film having a thickness of about 100 to 150 Η, such as a crystalline silicon film, is formed on the gate oxide. Film with. The conductive film 22 may include a plurality of stacked layers, for example, a silicon layer; a tungsten silicide layer formed on the polycrystalline silicon layer; silicon oxide is formed on the stone chemical crane layer; and a nitrogen A silicon layer is formed on the oxygen stone. Subsequently, a patterned photoresist film 20 () is formed on the conductor by a conventional photolithography (ph〇lithography) 480599

膜22上。 參照圖2(b)，使用圖案化光阻膜2〇〇作為遮雙 =:刻：電膜22，“定義—閘極電極22a於閘極氧化=膜 社構持^敎得於習知的爐管（未圖示）中，料所形成之 、，、。構持、，加熱一段預疋的時間，以達成退火。 絕绫3圖VO ’精由CM法，一由例如氮化石夕所製成之 絕緣膜24，沉積於圖2(b)所示之結構之整個表面上。繼 =，如圖2(d)所示，藉由RIE法，部分蝕刻絕緣膜24，使 得絕緣膜24之一部份存留，以形成拋棄式間隙側壁24&於 閘極電極22a之每一相對側上。在本實施例中，拋棄式間 隙侧壁24a之橫向厚度203實質上位於20 ηιη至60 ηπΓ之範圍 内’最佳為40 nm。 、 參妝圖2 (e )，以閘極電極2 2 a與拋棄式間隙側壁2 4 a作 為遮罩，使用例如砷離子之第一離子植入2丨〇施行於圖 2 (d)所示之結構之整個表面上，以形成具有深接面之重摻 雜N型源極/汲極區域2〇2於半導體基板中。在本實施例 中’舉例而言，所施行之第一離子植入21 〇之劑量約為 lxlO15 至 5xl015(l/cm3)，且植入能量約為 30 至 60 keV。 參照圖2 ( f )，在第一離子植入21 〇後，藉由習知的蝕 刻方法，例如使用含H3P04之蝕刻溶液的濕式蝕刻法，移除 拋棄式間隙側壁24a。隨後，藉由快速熱退火（rtA)法，於 溫度約為9 5 0 °C至1 0 5 0 °C下，對所形成的結構持續退火約 1 〇至3 0秒。因而，消除第一離子植入21 〇所產生之損壞與 缺陷。On the film 22. Referring to FIG. 2 (b), a patterned photoresist film 2000 is used as a masking double =: engraved: electrical film 22, "definition-the gate electrode 22a is oxidized by the gate = film structure is obtained from the conventional In the furnace tube (not shown), the material formed by ,,,,,,,,,,,,,,,,,,,,,,,,,, and is heated for a predetermined period of time to achieve annealing. The completed insulating film 24 is deposited on the entire surface of the structure shown in FIG. 2 (b). Next, as shown in FIG. 2 (d), the insulating film 24 is partially etched by the RIE method to make the insulating film 24 A portion remains to form a disposable gap sidewall 24 & on each opposite side of the gate electrode 22a. In this embodiment, the lateral thickness 203 of the disposable gap sidewall 24a is substantially between 20 η and 60 ηπΓ The best range is 40 nm. (See Figure 2 (e), using the gate electrode 2 2 a and the discontinuous gap side wall 2 4 a as a mask, using a first ion implantation such as arsenic ions 2 丨〇Performed on the entire surface of the structure shown in Figure 2 (d) to form a heavily doped N-type source / drain region 200 with a deep junction in the semiconductor substrate In this embodiment, for example, the dose of the first ion implantation 21 is about lxlO15 to 5xl015 (l / cm3), and the implantation energy is about 30 to 60 keV. Refer to FIG. 2 (f ), After the first ion implantation 21 °, the disposable gap sidewall 24a is removed by a conventional etching method, such as a wet etching method using an etching solution containing H3P04. Subsequently, by rapid thermal annealing (rtA ) Method, the structure is continuously annealed for about 10 to 30 seconds at a temperature of about 950 ° C to 1050 ° C. Therefore, the damage caused by the first ion implantation 21 ° is eliminated. With defects.

480599 五、發明說明（7) " -- 然後，參照圖2(g)，以閘極電極22a作為遮罩，使用 例如磷離子之第二離子植入22〇施行於圖2(f)所示之結構 之整個表面上，以形成具有較淺接面之輕摻雜N型源極/汲 極區域202於半導體基板中。在本實施例中，舉例而言，/ 所施行之第二離子植入22〇之劑量約為〇i3至 3xl〇13(l/cm3)，且植入能量約為1〇至3〇 keV。 繼而，藉由RTA法，於溫度約為950 °C至1 050。(：下，對 圖2(g)所示之結構持續退火約1〇至3〇秒。因而，消除第二 離子植入220所產生之損壞與缺陷。最後，一隔絕膜μ沉一 積於整個表面上，而完成依據本發明之LDD m〇sfet，其具 有由輕摻雜區域20 1 a與重摻雜區域202a所構成的源極/汲、 與前述之習知製程相反 ——隹依據本發明之製程中，夢 :使用拋棄式間隙側壁24a，重劑量離子植入21; 劑量離子植入220,因此，本製程被稱為反向源2 汲極1程。所以，依據本發明之製程可防止ldd雜質之 係因LDD雜質與 =劑=子明之反向離子 之75：1)。 里削里離千植入期間所增強的雜質480599 V. Description of the invention (7) "-Then, referring to FIG. 2 (g), the gate electrode 22a is used as a mask, and a second ion implantation such as phosphorus ion 22 is performed in FIG. 2 (f). A lightly doped N-type source / drain region 202 having a shallower junction is formed on the entire surface of the structure shown in the semiconductor substrate. In this embodiment, for example, the dose of the second ion implantation 22 performed is about 0 3 to 3 × 10 13 (1 / cm 3), and the implantation energy is about 10 to 30 keV. Then, by the RTA method, the temperature is about 950 ° C to 1 050. (: Next, the structure shown in FIG. 2 (g) is continuously annealed for about 10 to 30 seconds. Therefore, the damage and defects generated by the second ion implantation 220 are eliminated. Finally, an insulation film μ is deposited on the On the entire surface, the LDD m0sfet according to the present invention is completed, which has a source / drain composed of a lightly doped region 20 1 a and a heavily doped region 202 a, which is the opposite of the conventional process described above— 隹 Basis In the process of the present invention, the dream: the use of disposable gap sidewalls 24a, heavy dose ion implantation 21; dose ion implantation 220, therefore, this process is called the reverse source 2 drain 1 pass. Therefore, according to the present invention The process can prevent the ldd impurities from 75: 1 due to the LDD impurities and the counter ion of the agent = Ziming. Impurities enhanced during ripping

480599 五、發明說明（8) 應注意者為：美國專利第5, 46 8, 665號中揭露另— 向源極/汲極製程。然而，此習知技術與本發明間存 干差異。茲說明如下： 右 (1)，在美國專利第5, 468, 665號中，必須形成_由> 化矽所製成之輔助層，隨後，選擇性蝕刻該輔助層乳 一輔助圖案。然而，依據本發明之製程不需該輔 ^ 而，本製程變得較簡單。 層因 一（2)在美國專利第5,468,665號中，閘極電極 係經由兩步驟蝕刻方完成。該兩步驟中之一用 輔助層與-暫時間隙侧壁作為遮罩而進行，另_ 用該輔助層作為遮罩而進行。然而，依據本發明之製程 中’僅使用一蝕刻步驟以形成閘極電極。 置於(】)知專利第5’468,665號中’LDD M0SFET係放 =約87〇。°之溫度下，退火約40分鐘， 之較高溫度下，進行約10至3。秒之較 Ϊ:方TA二提：較Λ的熱預算，有效減緩雜質朝垂直：水 β而，f本發明已參照附有圖示之用以形成NM0S元件之製 私而砰細說明，但本發明不限於NM〇s元 PM0S(P型_或⑽s(互補_ 而=應^於 明之製程用以製造PM0S元件時，舉例而1^，°虽依據本發 210係使·2作為雜質，且以劑量約為^1(^離子植入 480599 五、發明說明（9) 4xl015(l/cm3)與植入能量約為25至50keV而施行，然而第 二離子植入220則使用BF2作為雜質，且以劑量約為ΐχΐ 〇i3 至5x 1 013(1 / cm3)與植入能量約為1 〇至2〇keV施行之。 植入步驟， 益擴散（TED) 之極淺接面480599 V. Description of the invention (8) It should be noted that: US Patent No. 5, 46 8, 665 discloses another process to the source / drain. However, there are differences between this conventional technique and the present invention. The description is as follows: Right (1), in U.S. Patent No. 5,468,665, an auxiliary layer made of siliconized silicon must be formed, and then the auxiliary layer is selectively etched with an auxiliary pattern. However, the manufacturing process according to the present invention does not require this supplement, and the manufacturing process becomes simpler. Layer factor one (2) In U.S. Patent No. 5,468,665, the gate electrode is completed by a two-step etching process. One of the two steps is performed with the auxiliary layer and the temporary gap side wall as a mask, and the other is performed with the auxiliary layer as a mask. However, in the manufacturing process according to the present invention, only one etching step is used to form the gate electrode. The "LDD MOSFET" is placed in ()) known patent No. 5'468,665 = about 87. The annealing is performed at a temperature of about 40 minutes, and at a higher temperature, about 10 to 3 minutes. Second comparison: Fang TA Second mention: Compared with Λ's thermal budget, it effectively slows down the impurity vertical: water β And, f The present invention has been described in detail with reference to the system for forming NMOS devices with illustrations, but The present invention is not limited to the NMMOS element PMOS (P-type _ or ⑽s (complementary_) and = should be used in the manufacturing process of PM0S elements, for example, 1 ^, ° Although 2 is used as an impurity according to the 210 series of the hair, And the dose is about ^ 1 (^ ion implantation 480599 V. Description of the invention (9) 4xl015 (l / cm3) and implantation energy is about 25 to 50keV, but the second ion implantation 220 uses BF2 as an impurity , And the dose is about ΐχ〇 〇i3 to 5x 1013 (1 / cm3) and the implantation energy is about 10 to 20keV. The implantation step, the extremely shallow junction of the TED

綜上所述’本發明業已揭露一種使用拋棄式間隙側壁 之反向源極/汲極製程，用以形成一LDD M0SFET於一半導 體基板中。本發明採用拋棄式間隙側壁，以完成反向 娃入 趣， 丁 態増 元件 雖然本發明業已藉由較佳實施例作為例示加、 應了解者為：本發明不限於此被揭露的實施例。說明， 本發明意欲涵蓋對於熟習此項技藝之人士而言係』反地， =修改與相似配置。因此，申請專利範圍隻範園_的各 廣的詮釋，以包容所有此類修改與相似配置。〜根據最In summary, the present invention has disclosed a reverse source / drain process using a disposable gap sidewall to form an LDD MOSFET in a half-conductor substrate. The present invention uses a discontinuous gap sidewall to complete the reverse silicon-injection, Ding element. Although the present invention has been taken as an example of the preferred embodiment, it should be understood that the present invention is not limited to the disclosed embodiment. It is to be noted that the present invention is intended to cover modifications and similar configurations for those skilled in the art. Therefore, the scope of patent application is only a broad interpretation of Fanyuan_ to accommodate all such modifications and similar configurations. ~ According to the most

480599 圖式簡單說明 【圖示之簡單說明】 本發明之前述與其他目的、特徵、以及優點將因下文 中參照圖示之較佳實施例之詳細說明而更明顯，其中之圖 示為： 圖1(a)至1(f)係顯示製造LDD M0SFET之習知製程；以 及 圖2(a)至2(h)係顯示依據本發明之使用拋棄式間隙側 壁以製造LDD M0SFET之製程。480599 Brief description of the drawings [Simplified description of the drawings] The foregoing and other objects, features, and advantages of the present invention will be more apparent from the following detailed description of the preferred embodiments with reference to the drawings, in which the drawings are: 1 (a) to 1 (f) show a conventional process for manufacturing an LDD MOSFET; and FIGS. 2 (a) to 2 (h) show a process for manufacturing an LDD MOSFET using a disposable gap sidewall according to the present invention.

第13頁Page 13

Claims (1)

六、申請專利範圍 1 · 一種使用拋棄式間隙 形成一MOSFET元件於—’、、側壁之反向源極/汲極製程，用以 —閘極氧化物形導體基板上，包含下列步驟·· 該半導體基板之表面上^驟’用以形成一閘極氧化物膜於 一第一沉積步驟， 膜上； 用以沉積一導電膜於該閘極氧化物 一光阻遮罩形成+ — 案化光阻膜於該導電^上’藉由光微影印刷術以形成一圖 一閘極電極形虏+ 罩’蝕刻該導電膜，以妒：使用該圖案化光阻膜作為遮 -第二沉積ί驟：成一閑極電極； 該閘極氧化物膜上； 以沉積一絕緣膜於該閘極電極與 間隙壁形成步驟，用 -拋棄式間隙側壁於編 ==刻該絕緣膜’以形成 -.挟M r : 閘電極之每一相對側上； λ重払雜區域形成步驟，用以施行一第一離子祐 以形成一重摻雜區域於該半導體基板内； 壁移除步驟’用以移除該間隙側壁； -輕摻雜區域形成步驟，用以施行一第二離子： 以形成一輕摻雜區域於該半導體基板内。 入， 2.如申請專利範圍第1項之使用拋棄式間隙側壁 極/汲極製程，其中該導電膜係由多晶矽所製成。° ^ 3.如申請專利範圍第丨項之使用拋棄式間隙侧壁之反向 源6. Scope of patent application1. A reverse source / drain process using a discarded gap to form a MOSFET element on a side wall for a gate oxide-shaped conductor substrate, including the following steps: A step of forming a gate oxide film on the surface of the semiconductor substrate is used to form a first deposition step on the film; and a conductive film is deposited on the gate oxide to form a photoresist mask to form a light film. The resist film is formed on the conductive substrate by photolithography to form a picture, a gate electrode, and a mask. The conductive film is etched to envy: use the patterned photoresist film as a mask-second deposition. Step: forming a free electrode; on the gate oxide film; to deposit an insulating film on the gate electrode and the gap forming step, using a -disposable gap side wall to edit == engraved the insulating film to form-.挟 M r: on each opposite side of the gate electrode; λ heavily doped region forming step for performing a first ion to form a heavily doped region in the semiconductor substrate; wall removing step 'for removing The gap sidewalls;-lightly doped region formation Step, for the purposes of a second ion: to form a lightly doped region in the semiconductor substrate. 2. The process of using a disposable gap sidewall / drain electrode as described in item 1 of the patent application scope, wherein the conductive film is made of polycrystalline silicon. ° ^ 3. Inverse source using a discontinuous gap sidewall as described in item 丨 480599 六、申請專利範圍 極/汲極製程，其中該導 電膜係由複數個叠製層所組成 4.如申請專利範圍第3項之使用拋棄 極/汲極製程，其中該複數個疊製層、勺人.隙側壁之反向源 一多晶碎層； 一 ^化鎢層，形成於該多晶矽層上 一氧化矽層，形成於該矽化鎢^上 一氮化矽層，形成於該氧化矽層 以及 上 5.如申請專利範圍第〗項之使用拋極/汲極製程，JL中該举鏠茱式間隙側壁之反向源 八T这、、、邑緣膜係由氮化矽所製成。 6 ·如申請專利範圍第1項之ητη δ fin nm , 之板向屋痊釣為20 nro 至 6 0 nm 7極利；之壁使移，_壁之反向源 _4之姓刻溶液的濕絲刻法/步驟之施行係：使用含 8. 如申請專利範圍第丨項之使用拋 極/汲極製程’其中該M〇sm係—N型二謂。 9. 如申請專利範圍第8項之使用拋棄式間隙側壁之反向源 間隙側壁之反向源 第15頁 480599480599 6. Application for patent range pole / drain process, where the conductive film is composed of a plurality of stacked layers. 4. For the use of a discard / drain process in the scope of patent application item 3, where the multiple stacked layers The reverse source of the gap side wall is a polycrystalline fragment; a tungsten silicide layer is formed on the polycrystalline silicon layer; a silicon oxide layer is formed on the tungsten silicide; a silicon nitride layer is formed on the oxide; The silicon layer and the upper 5. If using the process of using the pole / drain process in the scope of the patent application, the reverse source of the dogwood-type gap side wall in JL is 8T. production. 6 · If ητη δ fin nm in the first item of the patent application, the plate is cured from 20 nro to 60 nm 7 very well; the wall is moved, _ the reverse source of the wall _4 is engraved with the solution Wet wire engraving method / step execution system: use the process of using the pole / drain process as described in item No. 丨 in the scope of the patent application, where the Mosm is an N-type two term. 9. For example, using the reverse source of the discarded gap side wall in the scope of patent application No. 8 The reverse source of the gap side wall Page 15 480599 之施行係：珅離子劑 入能量約為30至60 極/汲極製程，其中該第一離子植入 量約為 lxio15 至 5xl015(l/cm3)，且植 keV。 棄式間隙側壁之反向 入之施行係：磷離子 植入能量約為1 0至3 0 10·如申請專利範圍第9項之使用拋 源極/汲極製程，其中該第二離子植 劑量約為lxl〇i3 至3xl〇i3(1/cm3)，且 keV。 11 ·如申印專利範圍第1項之使用拋棄式間隙側壁之反向 源極/汲極製程，其中該M0SFET之一源極/汲極區域係由該 重摻雜區域與該輕摻雜區域所組成。 12·如申請專利範圍第1項之使用拋棄式間隙侧壁之反向 源極/汲極製程，介於該間隙壁移除步驟與該輕摻雜區域 形成步驟間，更包含一第一快速熱退火步驟，用以降低在 該半導體基板中之缺陷。 13·如申請專利範圍第1 2項之使用拋棄式間隙側壁之反向 源極/沒極製程，其中該第一快速熱退火步驟係於溫度約 為9 5 0 °C至1 〇 5 〇 °c下，持續進行約1 〇至3 〇秒。 14·如申請專利範圍第1項之使用拋棄式間隙側壁之反向 源極/沒極製程，在該輕摻雜區域形成步驟之後，更包含The implementation system is: the ion implantation energy is about 30 to 60 pole / drain process, wherein the first ion implantation amount is about lxio15 to 5xl015 (l / cm3), and keV is implanted. The implementation of the reverse entrance of the side wall of the discarded gap is: the energy of phosphorus ion implantation is about 10 to 3 0 10. For example, using the throw-source / drain process in the patent application No. 9, wherein the second ion implantation dose Approximately 1x10i3 to 3x10i3 (1 / cm3), and keV. 11 · The reverse source / drain process using a disposable gap sidewall as described in item 1 of the printed patent scope, wherein one of the source / drain regions of the MOSFET is composed of the heavily doped region and the lightly doped region Composed of. 12. If the reverse source / drain process using a discontinuous gap sidewall as described in item 1 of the patent application scope is between the step of removing the gap and the step of forming the lightly doped region, a first rapid A thermal annealing step is used to reduce defects in the semiconductor substrate. 13. The reverse source / non-polar process using a disposable gap sidewall as described in item 12 of the patent application scope, wherein the first rapid thermal annealing step is at a temperature of about 9 50 ° C to 105 ° Under c, continue for about 10 to 30 seconds. 14. If the reverse source / non-polar process using a discontinuous gap sidewall as described in item 1 of the scope of the patent application, after the lightly doped region forming step, it further includes 第16頁 480599 六、申請專利範圍 一第二快速熱退火步驟，用以降低在該半導體基板中之缺 陷。 1 5 ·如申請專利範圍第1 4項之使用拋棄式間隙側壁之反向 源極/，極製程，其中該第二快速熱退火步驟係於溫度約 為9 5 0 °C至1 0 5 0。(：下，持續進行約1 〇至3 〇秒。 16·如申請專利範圍第1項之使用拋棄式間隙側壁之反向 源極/汲極製程，其中該M〇SFET係一P MM〇SFET。 17.如申請專利範圍第16項之使用拋棄式間隙側壁之反向 源極/汲極製程，其中該第一離子植入之施行係：BF2離子 劑量約為lxl0i5至4xl〇15(1/cffl3)，且植入能量約為25至5〇 keV ° L如申請/利範圍第17項之使用抛棄式間隙侧壁之反向 =/沒極製程’其中該第二離子植入之施行係：BF2離子 ，置約為lxl(P至5xl(F(l/cm”，且植Λ能量約為1〇至2〇 keV 〇 19·如申請專利範圍第i項之使_棄“隙側壁之反向 源極/汲極製程，介於該閘極電極形成+ 止咖 Λ步驟與該第二沉積 内進行一預定時 步驟間，更包含一熱處理步驟，於一壚管 間之退火。Page 16 480599 VI. Scope of Patent Application A second rapid thermal annealing step is used to reduce defects in the semiconductor substrate. 1 5 · The reverse source / pole process using a discontinuous gap sidewall as described in item 14 of the scope of patent application, wherein the second rapid thermal annealing step is at a temperature of about 9 5 0 ° C to 1 0 5 0 . (:, Continue for about 10 to 30 seconds. 16. As in the application of the scope of patent application of the reverse source / drain process using a discontinuous gap sidewall, where the MOSFET is a P MM0SFET 17. The reverse source / drain process using a discontinuous gap sidewall as described in item 16 of the scope of patent application, wherein the implementation of the first ion implantation is: BF2 ion dose is about lxl0i5 to 4xlO15 (1 / cffl3), and the implantation energy is about 25 to 50 keV ° L. For example, the application of the reverse range of the use of a disposable gap side wall of the scope of item 17 = / non-polar process' where the implementation of the second ion implantation system : BF2 ions, set to about lxl (P to 5xl (F (l / cm "), and the energy of planting Λ is about 10 to 20keV. The reverse source / drain process is between the gate electrode formation + stopping step and a predetermined time step in the second deposition, and further includes a heat treatment step for annealing between a tube. Hi·,:Hi · ,: 第17頁 480599 六、申請專利範圍 2 0. 如申請專利範圍第1項之使用拋棄式間隙側壁之反向 源極/汲極製程，其中該M0SFET之尺寸係次微米數量級及 其以下。 1^1Page 17 480599 6. Scope of patent application 20. For example, the reverse source / drain process using a discarded gap sidewall as described in item 1 of the patent application scope, wherein the size of the MOSFET is on the order of sub-microns and below. 1 ^ 1