JPS6199376A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6199376A JPS6199376A JP22068184A JP22068184A JPS6199376A JP S6199376 A JPS6199376 A JP S6199376A JP 22068184 A JP22068184 A JP 22068184A JP 22068184 A JP22068184 A JP 22068184A JP S6199376 A JPS6199376 A JP S6199376A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- region
- semiconductor
- substrate
- element region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000009826 distribution Methods 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000002347 injection Methods 0.000 description 8
- 239000007924 injection Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〈発明の技術分野〉
本発明は半導体装置の製造方法、特にＭＯＳ型電界効果
トランジスタより成る集積回路の素子領域及び素子分離
領域の形成方法に関するものである０
〈発明の技術的背景とその問題点〉
従来より、高集積化に伴い、トランジスタの微細化が進
み、ソースドレイン耐圧（パンチスルー耐圧）の向上、
短チャンネル効果の抑制の為、チャンネルに深い注入を
行ったシ、基板濃度自体？上げたり、ウェルを形成した
りして対応している０したし、基板濃度を上げ几り、ウ
ェル乞形成したリスるとトランジスタのバンチスルー耐
圧は同上し短チャンネル効果も抑制され相補型Ｍ ＯＳ
（ＣＭＯＳ ） の場合、ラッチアップ強度も向上す
るが、プロセスが複雑になシ、又閾値の制御も困難にな
る。チャンネルへの深い注入もパンチスルー、短チャン
ネル効果には有効であるがラッチアップに対して効果が
ない。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for forming element regions and isolation regions of an integrated circuit comprising MOS field effect transistors. Technical Background and Problems> Traditionally, with the increase in integration, transistors have become smaller and the source-drain breakdown voltage (punch-through breakdown voltage) has improved,
In order to suppress the short channel effect, deep implantation was performed in the channel, and the substrate concentration itself? The transistor's bunch-through breakdown voltage is the same as above, the short channel effect is also suppressed, and complementary MOS is realized.
In the case of (CMOS), the latch-up strength is improved, but the process is complicated and the control of the threshold value is also difficult. Deep injection into the channel is effective for punch-through and short channel effects, but is not effective against latch-up.
一方、素子分離法としては、従来選択酸化法（ＬＯＧＯ
５）かよく用いられている。この方法は■ 素子分離耐
圧向上の為の注入（いわゆるチャンネルストッパー注入
）の際、耐酸化マスクとして用いる５１３Ｎ４膜？注入
のマスクとして用いることができる為、チャンネルスト
ッパーを自己整合的に注入でき、マスク合わせの必要が
な（、その余裕も必要な（なり、微細化に適している。On the other hand, as a device isolation method, the conventional selective oxidation method (LOGO
5) It is often used. This method is: ■ A 513N4 film is used as an oxidation-resistant mask during implantation to improve device isolation breakdown voltage (so-called channel stopper implantation). Since it can be used as a mask for implantation, the channel stopper can be implanted in a self-aligned manner, and there is no need for mask alignment (or allowance for mask alignment), making it suitable for miniaturization.
■ 素子分離部の厚い酸化膜の約１／２ がＳｉ基板中
に埋め込まれている為、平坦な分離形状が得られる。(2) Approximately 1/2 of the thick oxide film in the element isolation section is buried in the Si substrate, so a flat isolation shape can be obtained.
という長所があるが、熱酸化で厚い分離用酸化膜を形成
する為、第３図に示す様に耐酸化マスクである８１３Ｎ
４の下部Ｋまで横方向酸化が進み、いわゆるバーズビー
クが形成される。その為、素子領域のマスク寸法と最終
のできあかり寸法の差（第３図中のΔＷ）が大きく大集
積化の妨げとなっている。However, in order to form a thick isolation oxide film by thermal oxidation, the oxidation-resistant mask 813N is used as shown in Figure 3.
Lateral oxidation progresses to the lower part K of No. 4, forming a so-called bird's beak. Therefore, the difference between the mask dimension of the element region and the final finished dimension (ΔW in FIG. 3) is large, which hinders large-scale integration.
〈発明の目的〉
本発明は上記諸点に鑑みて成されたもので、素子領域の
マスク寸法と最終の出来上り寸法の差の小さい素子分離
領域と微細化に対応したＭ ＯＳ型電界効果トランジス
タの形［−可能にした半導体装置の製造方法全提供する
ことを目的さしたものである。<Object of the Invention> The present invention has been made in view of the above points, and provides an element isolation region with a small difference between the mask dimension of the element region and the final finished dimension, and a shape of a MOS field effect transistor that is compatible with miniaturization. [-] is intended to provide a complete method of manufacturing a semiconductor device that makes it possible.
〈発明の構成〉
上記目的全達成するため、本発明の半導体装置の製造方
法は、ＭＯＳ型電界効果トランジスタより成る集積回路
の素子分離に際し、半導体表面に素子分離用の厚い絶縁
膜を形成し、素子領域のみこの絶縁膜を除去し、その後
素子分離領域の半導体表面近傍で濃度分布のピークを持
つように、半導体基板と同−型の不純物全絶縁膜を通し
て高エネルギーで全面にイオン注入するように構成して
いる。<Structure of the Invention> In order to achieve all of the above objects, the method for manufacturing a semiconductor device of the present invention includes forming a thick insulating film for element isolation on the semiconductor surface when isolating elements of an integrated circuit made of MOS field effect transistors; This insulating film is removed only in the element region, and then impurities of the same type as the semiconductor substrate are ion-implanted to the entire surface at high energy through the entire insulating film so that the concentration distribution peaks near the semiconductor surface in the element isolation region. It consists of
〈発明の実施例〉
本発明の実施例に先立って、まず本発明の詳細な説明す
る。<Embodiments of the Invention> Prior to the embodiments of the present invention, the present invention will first be described in detail.
本発明は、表面から深い所に濃度分布全もつような高エ
ネルギーのイオン注入技術、及び導入された不純物が、
その後の熱処理により大きく拡散しないようなプロセス
の低温化の技術により成シ立っている。The present invention utilizes a high-energy ion implantation technique that has the entire concentration distribution deep from the surface, and that the introduced impurities
This is achieved through low-temperature process technology that prevents significant diffusion during subsequent heat treatment.
即ち、第１図に示すように、半導体基板１０１上に厚い
絶縁膜１０２全形成した後、素子領域となる半導体基板
を露出する為のエツチング窓１０３を、フォ） ＩＪソ
ゲラフイエ程で形成し、絶縁膜厚の約１／２ ’ｉ等
方性エツチング、残りｔ異方性エツチングを行なって、
素子領域の厚い絶縁膜を除去する。その後厚い絶縁膜を
有する素子分離部の半導体表面付近に濃度分布のピーク
？もつように高いエネルギーで基板と同−型のイオン注
入を行えば、厚い絶縁膜を有しない素子領域には半導体
基板中の深い所（はぼ絶縁膜の厚さに相描する深さ）に
濃度のピーク？もち、かつチャンネルの形成される表面
付近は基板濃度か保たれるような不純物分布１０４が得
られる。That is, as shown in FIG. 1, after a thick insulating film 102 is completely formed on a semiconductor substrate 101, an etching window 103 for exposing the semiconductor substrate that will become an element region is formed using an IJ soger etching process, and the insulating film is removed. Approximately 1/2 of the film thickness isotropically etched for i, and the rest is anisotropically etched,
Remove the thick insulating film in the element area. After that, the concentration distribution peaks near the semiconductor surface in the element isolation part with a thick insulating film? If ions of the same type as the substrate are implanted at a high energy level, the device region without a thick insulating film will be implanted deep within the semiconductor substrate (at a depth comparable to the thickness of the insulating film). Peak concentration? An impurity distribution 104 is obtained in which the substrate concentration is maintained near the surface where the channel is formed.
素子分離部の不純物は表面付近に濃度分布のピーク全も
つ為、チャンネルストッパーとして働き分離耐圧上向上
させ、素子部の不純物は、その後の熱処理により、多少
表面付近まで拡散するものの、閾値制御に影響を及す程
表面濃度は上がらず、パンチスルー耐圧全向上させるだ
けでなく、基板抵抗を下げＣＭＯＳの場合、ラッチアッ
プ強度を上げる役割を果たす。又、必要ならばチャンネ
ル注入と同時に、いわゆる従来通りの深いチャンネル注
入も併用すればよい。Since the impurities in the element isolation part have the peak of their concentration distribution near the surface, they act as a channel stopper and improve the isolation breakdown voltage. Although the impurities in the element part diffuse to some extent near the surface due to subsequent heat treatment, they do not affect threshold control. The surface concentration does not increase to the extent that it affects the temperature, and it not only improves the punch-through breakdown voltage, but also lowers the substrate resistance and, in the case of CMOS, plays a role in increasing the latch-up strength. Furthermore, if necessary, so-called conventional deep channel implantation may be used simultaneously with the channel implantation.
次に、本発明の半導体装置の製造方法をｎチャンネルＭ
Ｏ３）ランジスタに適用した場合を実施例に挙げて、＠
２図（ロ））〜（ｄ）の製造工程図に基づいて説明する
。Next, the method for manufacturing a semiconductor device according to the present invention will be described below.
O3) Give an example of the case where it is applied to a transistor, @
The explanation will be based on the manufacturing process diagrams in FIGS. 2(b) to 2(d).
［：Ｉ） ！ずＰ型シリコン基板ｌ上に熱酸化にニジ厚
さ約５００λの５ｉ０２膜２を形成した後、ＣＶＤ法Ｋ
Ｊ：り約５００人のボリンリコン膜３を堆積踵続いてＣ
ＶＤ法に工りＳ ｉＯ２膜４を約７０００人堆積する。[:I)! First, a 5i02 film 2 with a thickness of about 500λ was formed on a P-type silicon substrate by thermal oxidation, and then a CVD method was applied.
J: Deposit about 500 volinlicon films 3 followed by C.
Approximately 7,000 SiO2 films 4 are deposited using the VD method.
その後通常のフォトリングラフィにより、素子領域とな
る部分のフォトレジスト５をパターニングし、エツチン
グ窓６を開孔する。Thereafter, the photoresist 5 in a portion that will become the element region is patterned by ordinary photolithography, and an etching window 6 is opened.
（＠２図（ａ））
〔■〕次に、フォトレジスト５をマスクとしてウェット
エッチ又は等方性プラズマエッチにより、ＣＶＤ５ｉ０
２膜４を約４０００λエツチングし、側壁上部の角を取
り除き、引き続いて異方性エッチ、たとえばリアクティ
ブイオンエッチにｆり残、９４０００λ程のＣ）’ＤＳ
２０２膜を除去する。その時、ポリシリコン膜３はＳ
ｉｏ ２エツチングのストッパーとして働き、ＣＶＤ５
ｉ Ｏ２膜４堆積時のバラツキによるオーバーエッチ
を防ぐ他、リアクティブイオンエッチによるＳｉ基板１
への損傷全防止する。次いで薄いポリシリコン膜３をた
とえばプラズマエッチで除去する。（％２図（ｂ）ン
（ト）次にフォトレジスト５金除去しイオン注入により
ボロンｔ−３０，０ＫｅＶで３Ｘ１０ １／ｃｉ全面
注大して、Ｐ＋領域７全基板１中に形成する。（第２図
（Ｃ））
３３次に熱酸化膜２？ウエツトエツチで除去し、ゲート
酸化膜９を形成後従来のｎチャンネルポリシリコンゲー
トプロセスを用いて、所望のトランジスタ？製造した。(@Figure 2 (a)) [■] Next, using the photoresist 5 as a mask, wet etching or isotropic plasma etching is performed to remove CVD5i0
2 film 4 is etched to about 4000λ, the upper corner of the sidewall is removed, and then anisotropic etching, such as reactive ion etching, is performed to remove the remaining part, and C)'DS of about 94000λ is removed.
202 film is removed. At that time, the polysilicon film 3 is S
Works as a stopper for io2 etching, CVD5
i In addition to preventing over-etching due to variations in the deposition of the O2 film 4, it also prevents over-etching of the Si substrate 1 by reactive ion etching.
Totally prevent damage to the product. Next, the thin polysilicon film 3 is removed by, for example, plasma etching. (%2(b)) Next, the photoresist 5 is removed and 3×10 1/ci of boron is injected into the entire surface of the substrate 1 at t-30,0 KeV by ion implantation to form a P+ region 7 in the entire substrate 1. 2(C)) 33 Next, the thermal oxide film 2 was removed by wet etching, and after forming a gate oxide film 9, a desired transistor was manufactured using a conventional n-channel polysilicon gate process.
（第２図（ｄ） ）なお、第２図（ｄ）において、８は
チャンネル注入及び深いチャンネル注入層、９はゲート
酸化膜、１０はポリシリコンゲート電極、１１はソース
・ドレイン部（Ｎ＋部）、１２はＰＳＧ膜、１３猷を電
極である。(Fig. 2(d)) In Fig. 2(d), 8 is the channel injection layer and deep channel injection layer, 9 is the gate oxide film, 10 is the polysilicon gate electrode, and 11 is the source/drain part (N+ part). ), 12 is a PSG film, and 13 is an electrode.
〈発明の効果〉
以上のように本発明にＬれば、素子領域のマスク寸法と
最終のできあがり寸法の差の小さい素子分離分域全形成
することが出来るため、大集積化に適した製造方法全稈
ることが出来る。<Effects of the Invention> As described above, according to the present invention, it is possible to form the entire element isolation region with a small difference between the mask dimension of the element region and the final finished dimension, so that the manufacturing method is suitable for large scale integration. The entire culm can be produced.
第１図は本発明？用いた場合の素子分離形状全示す断面
図、第２図（ａ）乃至（ｄ）は本発明によるｎチャンネ
ル注入層）ランジスタの裂造工程金示す断面図、第３図
はＬＯＣＯ５法を用いた場合の素子分離形状金示す断面
図である。
ｌ・・・Ｐ型シリコン基板、２・・・熱酸化膜、３・・
・ポリシリコンＨ，４−ｃｖＤｓＥｏ２膜、５−・・フ
ォトレジスト、６・・・素子領域開孔部、７用ボロン注
入層。
８・・・チャンネル注入及び深いチャンネル注入層。
９・・・ゲート酸化膜、１０・・・ポリシリコン電極、
＋１・・・ソース・ドレイン部（Ｎ＋部）、＋２・・・
ＰＳＧ膜。
１３・・・Ａｔ電極。
代理人 弁理士 福 士 愛 彦 （他２名）第１図Is Figure 1 the invention? 2(a) to 2(d) are sectional views showing the fabrication process of the n-channel injection layer (n-channel injection layer) transistor according to the present invention; FIG. FIG. 3 is a cross-sectional view showing the element isolation shape in the case of FIG. l...P-type silicon substrate, 2...thermal oxide film, 3...
- Polysilicon H, 4-cvDsEo2 film, 5-...photoresist, 6... element region opening, boron injection layer for 7. 8... Channel injection and deep channel injection layer. 9... Gate oxide film, 10... Polysilicon electrode,
+1... Source/drain part (N+ part), +2...
PSG membrane. 13...At electrode. Agent Patent attorney Aihiko Fukushi (and 2 others) Figure 1
Claims (1)
素子分離に際し、 半導体表面に素子分離用の厚い絶縁膜を形成し、 素子領域のみ該絶縁膜を除去し、 その後素子分離領域の半導体表面近傍で濃度分布のピー
クをもつように、半導体基板と同一型の不純物を絶縁膜
を通して高エネルギーで全面にイオン注入する ことを特徴とする半導体装置の製造方法。 ２、前記素子領域の厚い絶縁膜を除去する工程は、マス
ク形成後に等方性エッチングにより該絶縁膜の約１／２
を除去し、残り１／２程を異方性エッチングで除去し、
素子分離用絶縁膜側壁上部の角を取り除くことを特徴と
する、特許請求の範囲第１項記載の半導体装置の製造方
法。 ３、前記素子分離用絶縁膜の形成は、半導体基板の熱酸
化膜を形成し、Ｓｉ＿３Ｎ＿４又はポリシリコンを堆積
した後、ＣＶＤ酸化膜を堆積した三層構造となしたこと
を特徴とする特許請求の範囲第１項記載の半導体装置の
製造方法。[Claims] 1. When isolating elements of an integrated circuit made of MOS field effect transistors, a thick insulating film for element isolation is formed on the semiconductor surface, the insulating film is removed only in the element region, and then the element isolation region is removed. 1. A method for manufacturing a semiconductor device, which comprises ion-implanting impurities of the same type as a semiconductor substrate over the entire surface at high energy through an insulating film so that the concentration distribution peaks near the semiconductor surface. 2. The step of removing the thick insulating film in the element region involves removing about 1/2 of the insulating film by isotropic etching after forming the mask.
, and the remaining 1/2 was removed by anisotropic etching.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising removing an upper corner of the side wall of the element isolation insulating film. 3. Formation of the element isolation insulating film has a three-layer structure in which a thermal oxide film is formed on the semiconductor substrate, Si_3N_4 or polysilicon is deposited, and then a CVD oxide film is deposited. A method for manufacturing a semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22068184A JPS6199376A (en) | 1984-10-19 | 1984-10-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22068184A JPS6199376A (en) | 1984-10-19 | 1984-10-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6199376A true JPS6199376A (en) | 1986-05-17 |
Family
ID=16754798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22068184A Pending JPS6199376A (en) | 1984-10-19 | 1984-10-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6199376A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152324A (en) * | 1991-11-26 | 1993-06-18 | Sharp Corp | Manufacture of semiconductor device |
| US6541825B2 (en) | 2000-10-04 | 2003-04-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same |
| US6648686B2 (en) | 2000-11-30 | 2003-11-18 | Shimano Inc. | Electrical connector |
| US6848930B2 (en) | 2003-01-15 | 2005-02-01 | Shimano, Inc. | Electrical connector with resilient retaining ring to restrict radial expansion |
-
1984
- 1984-10-19 JP JP22068184A patent/JPS6199376A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05152324A (en) * | 1991-11-26 | 1993-06-18 | Sharp Corp | Manufacture of semiconductor device |
| US6541825B2 (en) | 2000-10-04 | 2003-04-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same |
| US6841440B2 (en) | 2000-10-04 | 2005-01-11 | Renesas Technology Corp. | Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same |
| US6648686B2 (en) | 2000-11-30 | 2003-11-18 | Shimano Inc. | Electrical connector |
| US6848930B2 (en) | 2003-01-15 | 2005-02-01 | Shimano, Inc. | Electrical connector with resilient retaining ring to restrict radial expansion |
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