479407 經濟部智慧財產局員工消費合作社印製 6914twf.doc/006 A/ __B7 五、發明說明（f ) 發明背景 發明領域 本發明是有關於一種正反器，且特別是有關於一種高 速低設定時間電壓感測正反器。 相關技藝之說明 隨著數位系統之運作頻率的增加，其時序需求也跟著 增加。當電路中的整合度及元件數目增加以及其運作速度 增加時，必須消除任何多餘的延遲。 傳統的正反器一般具有相當長的時脈至輸出（dock-to-output，簡稱clk-to-Q)延遲。clk-to-Q延遲爲在時脈輸入啓 動一轉換時，資料輸出出現在Q輸出所需之時間。除了 clk-to-Q延遲之外，另一個關心的時序的問題是設定時間 (setup time) 〇 請參照第1圖，其繪示習知正反器之電路圖。該正反 器具有非常大的clk-to-Q延遲，如圖示上的121、131與141， 加上傳輸閘G2的延遲。如第1圖所繪示之習知正反器亦 必須忍受很大的設定時間（兩個反相器加上一個傳輸閘的 延遲）。 發明總結 爲了克服習知正反器缺點及不便，本發明提出一種高 速低設定時間之電壓感測正反器。 請參照第2圖，其繪示本發明之一實施例之高速低設 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線- 本紙張尺度適用中國國家標準（CNS)Al規格（2.10x297公釐） 479407 6914twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（2) 定時間之電壓感測正反器之電路圖。本發明之一實施例之 高速低設定時間之電壓感測正反器包括一主閂鎖及一僕問 鎖。該主閂鎖具有一資料輸入及一時脈輸入。該僕閂鎖接 受來自該主閂鎖的兩條信號線。當該時脈輸入爲低電位 時，至該僕閂鎖之該兩個輸入線被上拉至高電位。其將使 電晶體導190及200導通且使至該僕閂鎖之該些輸入預充 電。 當該時脈轉換至高電位時，該主閂鎖中之該上拉電晶 體關閉，使該僕閂鎖之該些輸入與該主閂鎖之該輸出分 隔。此時，假如IN爲高電位，則至該僕閂鎖之A輸入會 放電。假如IN爲低電位，則至該僕閂鎖之B輸入會放電。 在該僕閂鎖之該兩個輸入與該主閂鎖分隔之後’由於該兩 條輸入線未被拉高或拉低，所以在IN信號的任何改變都 會使至該僕閂鎖之該些輸入成爲浮動低電位。以此方式’ 至該僕閂鎖之該些輸入在每個時脈週期會被預充電及放 電。由此預充電可得到接近零的設定時間。· 特別參照第2圖的僕閂鎖5。因爲僕閂鎖的輸出Q及 QB具有對稱的上拉及下拉電路，所以在兩個輸出信號之 間沒有延遲誤差。此可以與第1圖的習知正反器的輸出Q 及輸出QB做比較。注意習知正反器的輸出Q必須經過額 外的反相器。此會造成兩個輪出之間的延遲以及導致較差 的設計。此爲本發明超越習知設計的一項優點。 當至僕閂鎖的兩個輸入A及B都爲高電位時’會使電 晶體190及200導通而電晶體130及160關閉。此允許電 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線 木紙張尺度適用中國國家標準（CNS)/U規格α]〇χ 297公釐） 479407 69l4twf.doc/OOi A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（> ) 晶體140及150維持其邏輯位準 定。 當時脈輸入轉變至高電位時 準，時脈信號的邊緣會引發輸入或輸入B放電。主閂鎖 的結構在時脈的每個轉變時，只允許輸入A或B中的一個 放電。因此，輸出Q及輸出QB爲互補邏輯位準。在上面 的情況中，假如輸入IN爲高電丨，則輸入A放電，使電 晶體130導通，以及使輸出Q被jt拉至邏輯高，而輸出qB 被下拉至邏輯低。假如輸入IN爲 使電晶體160導通，以及使輸出 輸出Q被下拉至邏輯低。 因爲至僕閂鎖的輸入在每個 以本發明之電壓感測正反器具有 非常低的設定時間。事實上，由於[主閂鎖及僕閂鎖的設計 其設定時間實際上是接近零的。 相對的，習知正反器具有非 包括三個反相器加上一個傳輸閘 器也要忍受由兩個反相器加上一 的設定時間。更進一步，習知正反器由於輸出Q必須經過 額外的反相器，藉以使輸出Q與輸出QB爲互補，故其在 輸出Q及輸出QB會產生延遲。 必須要瞭解，前面之一般4說明及後面的詳細說明皆 是範例性及解釋性的，以及用4做爲提供本發明之宣告之 更進一步之解釋。. 其保持Q及QB輸出穩 依據資料輸入IN的位 低電位，則輸入B放電， QB被上拉至邏輯高，而 時脈週期會被預充電，所 非常高的速度，以及具有 常大的clk-to-Q延遲，其 的延遲。此外，習知正反 個傳輸閘的延遲造成很大 (請先閱讀背面之注意事項再填寫本頁) ----II--訂--I----ί · ‘紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479407 6914twf.doc/006 A7 B7 五、發明說明（ 圖式之簡單 所附圖式，其爲用來提供本 及結合在及構成此說明書之一部 例以及與說明書一起用來解釋本 中·· 第1圖繪示習知正反器之電路 第2圖繪示本發明之一實施 壓感測正反器之電路圖。 說明 發明之更進一步之瞭解以 分，其繪示本發明之實施 發明之原理。在這些圖式 圖；以及 例之局速低設定時間之電 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製479407 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6914twf.doc / 006 A / __B7 V. Description of the Invention (f) Background of the Invention The present invention relates to a flip-flop, and in particular to a high-speed and low-set time Voltage sensing flip-flop. Explanation of related techniques As the operating frequency of digital systems increases, their timing requirements also increase. As the degree of integration and number of components in a circuit increases and its operating speed increases, any unnecessary delay must be eliminated. Traditional flip-flops generally have a fairly long clock-to-output (clk-to-Q) delay. clk-to-Q delay is the time required for the data output to appear at the Q output when a transition is initiated by the clock input. In addition to clk-to-Q delay, another concern with timing is setup time. Please refer to Figure 1 for a circuit diagram of a conventional flip-flop. The flip-flop has a very large clk-to-Q delay, such as 121, 131, and 141 on the figure, plus the delay of transmission gate G2. The conventional flip-flop shown in Figure 1 must also tolerate a large set time (two inverters plus a delay of a transmission gate). Summary of the Invention In order to overcome the disadvantages and inconveniences of conventional flip-flops, the present invention proposes a voltage sensing flip-flop with high speed and low set time. Please refer to Figure 2, which shows the high speed and low setting of an embodiment of the present invention (please read the precautions on the back before filling this page). -Line- This paper size applies the Chinese National Standard (CNS) Al specification (2.10x297mm) 479407 6914twf.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) Voltage at a fixed time Circuit diagram of sensing flip-flop. The voltage sensing flip-flop of high speed and low setting time according to an embodiment of the present invention includes a main latch and a slave latch. The main latch has a data input and a clock input. The slave latch accepts two signal lines from the main latch. When the clock input is low, the two input lines to the slave latch are pulled up to high. It will turn on transistors 190 and 200 and pre-charge the inputs to the slave latch. When the clock is switched to a high potential, the pull-up electrical crystal in the main latch is turned off, so that the inputs of the slave latch are separated from the output of the main latch. At this time, if IN is high, the A input to the slave latch will discharge. If IN is low, the B input to the slave latch will discharge. After the two inputs of the slave latch are separated from the main latch, 'because the two input lines are not pulled high or low, any change in the IN signal will cause the inputs to the slave latch. It becomes a floating low potential. In this way, the inputs to the slave latch are precharged and discharged at each clock cycle. As a result, the pre-charging can obtain a set time close to zero. · Special reference is made to the slave latch 5 in FIG. 2. Because the latched outputs Q and QB have symmetrical pull-up and pull-down circuits, there is no delay error between the two output signals. This can be compared with the output Q and output QB of the conventional flip-flop in Figure 1. Note that the output of the conventional flip-flop must pass through an additional inverter. This can cause delays between two rotations and lead to poor designs. This is an advantage of the invention over conventional designs. When both the inputs A and B to the slave latch are at a high potential ', transistors 190 and 200 are turned on and transistors 130 and 160 are turned off. This allows electricity (please read the precautions on the back before filling this page). -------- Order --------- Wire wood paper size applies to China National Standard (CNS) / U specifications α ] 〇χ 297 mm) 479407 69l4twf.doc / OOi A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (&); Crystals 140 and 150 maintain their logical level. When the clock input transitions to a high potential, the edge of the clock signal will cause the input or input B to discharge. The structure of the main latch allows each input A or B to discharge at each transition of the clock. Therefore, the output Q and the output QB are complementary logic levels. In the above case, if input IN is high, input A is discharged, transistor 130 is turned on, and output Q is pulled to logic high by jt, and output qB is pulled to logic low. Suppose the input IN is to turn on the transistor 160 and the output Q is pulled down to logic low. Because the input to the slave latch has a very low settling time for each voltage sensing flip-flop with the present invention. In fact, due to the design of the [master latch and the slave latch, the set time is practically zero. In contrast, the conventional flip-flop has three inverters plus one transmission gate, and it has to endure a set time of two inverters plus one. Furthermore, the conventional flip-flop has a delay in the output Q and the output QB because the output Q must pass through an additional inverter so that the output Q and the output QB are complementary. It must be understood that the foregoing general 4 description and the following detailed description are exemplary and explanatory, and 4 is used to provide a further explanation of the declaration of the present invention. It keeps the Q and QB output stable according to the data input IN bit low potential, then input B is discharged, QB is pulled up to logic high, and the clock cycle is precharged, which has a very high speed and has a very large clk-to-Q delay, its delay. In addition, it is known that the delay between the positive and negative transmission gates is very large (please read the precautions on the back before filling this page) ---- II--Order--I ---- ί '' The paper size is applicable to China Standard (CNS) A4 specification (210 X 297 mm) 479407 6914twf.doc / 006 A7 B7 V. Description of the invention (simple drawing, the drawing is used to provide the book, and to incorporate and constitute one of the specifications Examples and explanations are used together with the description to explain this ... Figure 1 shows a circuit of a conventional flip-flop. Figure 2 shows a circuit diagram of a pressure-sensing flip-flop implemented by one of the present invention. Understand the points, which show the principle of the invention. In these diagrams; and for example, the speed of the set time is low (please read the precautions on the back before filling this page). Staff of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Consumer Cooperatives
圖式中標示之簡單說明 IN輸入埠 Gl、G2傳輸閘 工1 1、1丨2、.〗21、、丨31與反相益 Q輸出堤 QB輸出埠 10主閂鎖 15僕閂鎖 20、30、40、50、60、70、农 80 電晶體 90反相器 100、110、120、130、及 14 150 、 160 、 170 、 180 、 190 、 200輸出Q 210輸出QB 電晶體 及200電晶體 裝--------訂---------· 木紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 479407 69l4twf.doc/〇〇6 五、發明說明（f) A7 B7 較佳實施例之說明 現在將要參照所附圖式繪示 較佳實施例。其中任何可能之處 之實例詳細說明本發明之 在圖式及說明中使用的 相同參考標號爲參考到相同或類似的元件 請參照第2圖，其繪示本發 明之一^實施例之局速低設 定時間之電壓感測正反器之電路圖 本發明之一實施例之高速低設定時間之電壓感測正反 器包括主閂鎖(Master Layer)10及僕閂鎖(Slave Layer)15 主閂鎖10具有輸入IN 105及時&輸入CLK。僕閂鎖15接 受來自主閂鎖10的兩條信號線 爲低電位時，到僕閂鎖15的兩$信號線，A及B，會被拉 高。其會使電晶體190及200導^以及對到僕閂鎖15的輸 入A及B預充電。 主閂鎖的電晶體80橋接輸1電晶體100及110。電晶 體80做爲等化器，用以等化IN 徑與INB 110信號上拉/下拉途徑 輸入100信號上拉/下拉途 之間之位準。 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線· 經濟部智慧財產局員工消費合作社印製 當時脈CLK轉變爲高電位時，主閂鎖10的上拉電晶 體20及50會關閉，其使僕閂鎖15的輸入A及B與主閂 鎖10的分隔。此時，假如IN 105爲高電位，則僕閂鎖15 的輸入A會放電。假如IN 105爲低電位，則僕閂鎖15的 輸入B會放電。在這僕閂鎖15的兩個輸入A及B與主閂 鎖10的分隔之後，IN信號105的任何改變會導致至僕閂 鎖15的輸入變爲浮動低電位，因爲該兩條線未被拉高或 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） 479407 6 9 14twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（έ ) 拉低。以此方式，至僕閂鎖15的輸入A及B在每個CLK 時脈週期都會預充電及放電。此預充電可以得到近乎零的 設定時間。 因爲主閂鎖10做爲電壓感測放大器，在感測期間只 有很短暫的不穩定狀態時間。然而’在達到穩定狀態後’ 在輸入IN 105或INB 110的任何改變對至僕閂鎖15的兩 個輸入A及B沒有任何影響。一旦達到穩定狀態’資料輸 入IN 105或資料輸入INB 110上的較高電壓位準將會決定 A及B的狀態。 請特別參照第2圖的僕閂鎖15。因爲僕閂鎖15的輸 出Q 210及QB 220具有對稱的上拉及下拉電路’其中在 輸出信號Q 210及QB 220之間沒有延遲誤差。此可以與 第1圖的習知正反器的輸出Q 1〇〇及輸出QB 110做比較。 注意習知正反器的輸出Q 100必須經過額外的反相器90 ° 此會造成兩個輪出Q 100及QB 110之間的延遲以及導致 較差的設計。由兩個輪出Q 及QB 11〇之間的延遲所 成的非對稱輸出係習知正反器的缺點’而消除了此種非對 稱係本發明超越習知設計的一項優點。 請再參照第2圖，當至僕閂鎖15的兩個輸入A及B 都爲高電位時，會使電晶體190及200導通以及電晶體130 及160關閉。此允許電晶體140及150維持其邏輯位準， 其保持Q 210及QB 220輸出穩定。 當時脈輸入CLK轉變至高電位時’依據資料輸入IN 的位準，時脈信號CLK的邊緣會引發輸入A或輸入B放 本紙張尺度適用中國國家標準（CNS)A‘l規格（210 X 297公# ) (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線· 479407 6914twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（q) 電。主閂鎖10的結構在時脈CLK的每個轉變時，只允許 輸入A或B中的一個放電。因此，輸出Q 210及輸出QB 220 爲互補邏輯位準。在上面的情況中，假如輸入IN 105爲高 電位，則輸入A放電，使電晶體130導通，以及使輸出Q 210 被上拉至邏輯高，而輸出QB 220被下拉至邏輯低。假如 輸入IN 105爲低電位，則輸入B放電，使電晶體160導通， 以及使輸出QB 220被上拉至邏輯高，而輸出Q 210被下 拉至邏輯低。 因爲至僕閂鎖15的輸入A及B在時脈信號CLK的每 個週期會被預充電，所以本發明之電壓感測正反器具有非 常高的速度，以及具有非常低的設定時間。事實上，由於 主閂鎖10及僕閂鎖15的設計，其設定時間實際上是接近 零的。 相對的，習知正反器具有非常大的clk-toQ延遲，其 包括四個反相器加上兩個傳輸閘的延遲。此外，習知正反 器也要忍受由兩個反相器加上一個傳輸閘的延遲造成很大 的設定時間。更進一步，習知正反器由於輸出Q必須經過 額外的反相器，藉以使輸出Q與輸出QB爲互補，故其在 輸出Q及輸出QB會產生延遲。 很明顯的，熟習此技藝者可以在不脫離本發明之精神 和範圍內，可以依照本發明之結構做不同的修飾及變化。 鑑於前面所述，本發明當涵蓋後附之申請專利範圍及其相 等之修飾及變化。 本紙張尺度適用中國國家標準（CNS)/V1規格（2.10 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ，裝---- 訂---------線·The brief description marked in the figure is the IN input ports G1, G2 transmission gates 1 1, 1 丨 2, 〖21 ,, 丨 31, and the reverse phase Q output bank QB output port 10 main latch 15 servant latch 20, 30, 40, 50, 60, 70, agricultural 80 transistor 90 inverter 100, 110, 120, 130, and 14 150, 160, 170, 180, 190, 200 output Q 210 output QB transistor and 200 transistor Installation -------- Order --------- · The size of wood paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 479407 69l4twf.doc / 〇〇6 V. Invention Explanation (f) Description of the preferred embodiment of A7 B7 The preferred embodiment will now be described with reference to the drawings. An example of any possible place details the same reference numerals used in the drawings and descriptions of the present invention for reference to the same or similar elements. Please refer to FIG. 2, which illustrates the speed of one embodiment of the present invention Circuit diagram of voltage sensing flip-flop with low setting time One embodiment of the present invention has a voltage sensing flip-flop with high setting and low setting time, which includes a master latch 10 and a slave layer 15 The lock 10 has an input IN 105 and an input CLK. When the slave latch 15 receives the two signal lines from the main latch 10 at a low potential, the two $ signal lines, A and B, to the slave latch 15 will be pulled high. It will pre-charge transistors 190 and 200 and input A and B to slave latch 15. The main latched transistor 80 bridges the one transistor 100 and 110. The transistor 80 is used as an equalizer to equalize the level between the IN path and the INB 110 signal pull-up / pull-down path. (Please read the precautions on the back before filling out this page) Loading -------- Order --------- Line · Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs At the potential, the pull-up transistors 20 and 50 of the main latch 10 are turned off, which separates the inputs A and B of the slave latch 15 from the main latch 10. At this time, if IN 105 is high, the input A of the slave latch 15 is discharged. If IN 105 is low, input B of slave latch 15 will discharge. After the two inputs A and B of the slave latch 15 are separated from the main latch 10, any change in the IN signal 105 will cause the input to the slave latch 15 to become a floating low potential because the two lines are not Raised or this paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 479407 6 9 14twf.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs low. In this way, the inputs A and B to the slave latch 15 are precharged and discharged every CLK clock cycle. This pre-charge can get almost zero set time. Because the main latch 10 acts as a voltage sense amplifier, there is only a short unstable state time during the sensing period. However, "after reaching a steady state" any change in input IN 105 or INB 110 has no effect on the two inputs A and B to the slave latch 15. Once the steady state is reached, the higher voltage level on data input IN 105 or data input INB 110 will determine the state of A and B. Please refer particularly to the latch 15 of FIG. 2. Since the outputs Q 210 and QB 220 of the slave latch 15 have symmetrical pull-up and pull-down circuits', there is no delay error between the output signals Q 210 and QB 220. This can be compared with the output Q 100 and output QB 110 of the conventional flip-flop in FIG. 1. Note that the output of the conventional flip-flop Q 100 must go through an additional inverter 90 °. This will cause a delay between the two round-out Q 100 and QB 110 and lead to a poor design. The asymmetric output is a disadvantage of the conventional flip-flop caused by the delay between the two round-out Q and QB 11o, and eliminates such an asymmetrical advantage of the present invention over the conventional design. Please refer to FIG. 2 again, when both inputs A and B to the slave latch 15 are high, transistors 190 and 200 are turned on and transistors 130 and 160 are turned off. This allows the transistors 140 and 150 to maintain their logic levels, which keeps the Q 210 and QB 220 outputs stable. When the clock input CLK transitions to a high level, 'depending on the level of the data input IN, the edge of the clock signal CLK will trigger the input A or input B. The paper size applies the Chinese National Standard (CNS) A'l specification (210 X 297 male) #) (Please read the precautions on the back before filling this page) -------- Order --------- line · 479 407 6914twf.doc / 006 A7 B7 Employees of Intellectual Property Bureau Printed by Consumer Cooperatives 5. Description of Invention (q) Electricity. The structure of the main latch 10 allows only one of the inputs A or B to discharge at each transition of the clock CLK. Therefore, output Q 210 and output QB 220 are complementary logic levels. In the above case, if the input IN 105 is high, the input A is discharged, the transistor 130 is turned on, and the output Q 210 is pulled up to a logic high, and the output QB 220 is pulled down to a logic low. If the input IN 105 is at a low level, the input B is discharged to turn on the transistor 160, and the output QB 220 is pulled up to a logic high and the output Q 210 is pulled down to a logic low. Because the inputs A and B to the slave latch 15 are precharged every cycle of the clock signal CLK, the voltage sensing flip-flop of the present invention has a very high speed and a very low set time. In fact, due to the design of the main latch 10 and the slave latch 15, the set time is practically close to zero. In contrast, the conventional flip-flop has a very large clk-toQ delay, which includes four inverters plus two transmission gate delays. In addition, the conventional flip-flop also suffers from a large set time caused by the delay of two inverters plus a transmission gate. Furthermore, the conventional flip-flop has a delay in the output Q and the output QB because the output Q must pass through an additional inverter to make the output Q and the output QB complementary. Obviously, those skilled in the art can make various modifications and changes according to the structure of the present invention without departing from the spirit and scope of the present invention. In view of the foregoing, the present invention should cover the scope of the appended patent application and its equivalent modifications and changes. This paper size applies to Chinese National Standard (CNS) / V1 specifications (2.10 X 297 mm) (Please read the precautions on the back before filling this page). ·