TW478115B - Method of manufacturing a flash EEPROM cell - Google Patents

Abstract

There is disclosed a method of manufacturing a flash EEPROM cell. It includes forming selectively a stack gate structure on a semiconductor substrate, performing first thermal treatment process and source ion implantation process to form an oxide film at the sidewalls of the stack gate structure and then implementing a second thermal treatment process, a source/drain ion implantation process and a third thermal treatment process. Therefore, the present invention can prevent bottom and upper oxide film in an ONO dielectric film from growing and can increase the effective channel length, thus improving reliability of a device.

Description

478115 經濟部智慧財產局員工消費合作社印製 A7 ------------- B7__ 五、發明説明（/ ) ^ —- 發明之背景： 發明之技術領域： 本發明係有·-種快閃電子式可抹除程式化唯讀記情 體之製程。尤指-種快閃電子式可抹除程式化唯讀記憶體: 製程，其可抑制氧化物_氮化物_氧化物（〇N〇)介電膜中的 氧化物膜成長，並可增加有效通道長度，以改良裝置的可靠 度；其巾該製程係藉域擇性地形成—堆翻極結構於一半 導體基板上，在第-道熱處理製程與第_道源極離子植入製 程進行後’形成間隔物於堆疊閘極結構的壁面上，以及接著 進打-道第二熱處理製程一道源極/汲極離子植人製程以及 一道第三熱處理製程。 習知先前技藝之說明： 第1圖表示一快閃電子式可抹除程式化唯讀記憶體 (EEPROM)記憶胞陣列的佈局，第2A圖至第2D圖為用於 說明製造慣用之快閃EEPROM記憶胞之穿經第1A圖之線段 A-A的裝置的橫剖面圖。 現在參考第1圖及第2A圖，藉由一裝置隔離遮罩1〇， 一裝置隔離膜被形成於一半導體基板1〇1上。其次，在一穿 隧氧化物膜102與一弟一多晶石夕膜1〇3依序被形成於整個結 構上之後，該第一多晶矽膜103與穿隧氧化物膜1〇2係藉由 使用一第一多晶矽遮罩20的光學微影製程而被刻晝。其次， 具有一 ΟΝΟΙ底層氧化物膜1〇4、一 0N02氮化物膜1〇5以 及一 0N03上層氧化物膜1〇6的介電膜被形成，一第二多晶 本紙張;？JL適用中國國家標準（CNS ) A4胁（210Χ'97公董) ----- (請先閱讀背面之注意事填寫本頁) .裝· 訂 .線 478115478115 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ------------- B7__ V. Description of the Invention (/) ^ --- Background of the Invention: Technical Field of the Invention: The present invention has: -A flash-type electronic process that can erase the stylized read-only memory. Especially-a flash electronic erasable stylized read-only memory: a process that can inhibit the growth of oxide films in oxide_nitride_oxide (〇N〇) dielectric films and can increase the effective The length of the channel is to improve the reliability of the device; the process is selectively formed by the field-stacking pole structure on a semiconductor substrate, after the first-channel heat treatment process and the first-channel source ion implantation process are performed 'A spacer is formed on the wall surface of the stacked gate structure, and then a second heat treatment process, a source / drain ion implantation process, and a third heat treatment process are performed. Description of the prior art: Figure 1 shows the layout of a flash electronic erasable stylized read-only memory (EEPROM) memory cell array, and Figures 2A to 2D are used to illustrate the conventional flash manufacturing. A cross-sectional view of the EEPROM memory cell passing through the line AA of FIG. 1A. Referring now to FIG. 1 and FIG. 2A, a device isolation film is formed on a semiconductor substrate 101 by a device isolation mask 10. Secondly, after a tunneling oxide film 102 and a polycrystalline stone film 103 are sequentially formed on the entire structure, the first polycrystalline silicon film 103 and the tunneling oxide film 102 are It is carved by an optical lithography process using a first polycrystalline silicon mask 20. Second, a dielectric film having a 100N bottom oxide film 104, a 0N02 nitride film 105, and a 0N03 upper oxide film 106 is formed, and a second polycrystalline paper; JL applies Chinese National Standard (CNS) A4 threat (210 × '97 public director) ----- (Please read the note on the back first and fill in this page). Binding · Ordering. Line 478115

經濟部智慧財產局員工消費合作社印製 =膜H)7與二金屬魏物媒依序被形成，其係接著被刻 旦而开j羊置祕魅細極被堆疊於射的堆疊閑極社 構。-浮置閘極係由一第—多晶稍1〇3所形成，而一測 開極則由一第二多晶石謂107與一石夕化鎮膜108所形成。其 次’為補償閘極的侧損傷，則進行一道再氧化製程。其次: 在:第-光__成於整個結構上之後，其係藉由使用一 ,自行對β蝴遮罩4G轉光與侧製料被刻晝。其次，一 第-記憶胞源極離子植人製程係使_第-光_圖案· 作為遮罩而被進行’以形成一個低濃度的源極接面⑽。該 第-記憶胞源極軒植人製程使聽濃度的碎或碟離子。 、見在多考第1 ®及第2A圖’在該第—光阻膜圖案1〇9 被移除後’進行—道記憶胞源極退火。藉由此製程，一個薄 的間隔物111被形躲該堆疊閘極結構的壁面上，而源極接 面110巾的離子被擴散，而使得源極接面110的深度更深。 此時’ 〇N01氧化物膜1〇4與⑽〇3氧化物膜1〇6的厚度因 該氧化製程而變厚。 上述的第一兄憶胞源極離子植入製程與記憶胞源極退火 製程被進行，以確保—均勻源極接_橫向深度。 敫個ϋΐ考第1圖及第2C圖’在—第二光阻膜被形成於 正、口 l·乂後’一第二光阻膜圖案112係藉由使用—自行 對背姓刻遮罩4Q的曝光與侧製麵被形成。為了以擴散法 形成連接個別記憶胞之源極接面11〇的一共用源極線，、一道 置於第1 ®之翻方向中之相鄰記聽間的裳置隔 離_自賴齊_齡被進行。再者’為了藉由在形成裝Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs = film H) 7 and the bimetallic Wei media were formed in order, which was then carved and opened. The sheep were placed in a secret stack.结构。 Structure. -The floating gate is formed by a first-polycrystal slightly 103, and a test-open electrode is formed by a second polycrystalline stone 107 and a Shixihua town film 108. Secondly, to compensate the side damage of the gate, a reoxidation process is performed. Second: After: The first-light __ is formed on the entire structure, it is used to automatically transform the β butterfly mask 4G to light and side materials by using one. Secondly, a first-memory cell source ion implantation process system uses _th-light_patterns as masks to form a low-concentration source junction. The first-memory cell source Xuan Xuan human implantation process makes hearing concentration of fragmented or dish ions. See Fig. 1 and Fig. 2A of Duokuo. After the first photoresist film pattern 109 is removed, the memory cell source annealing is performed. By this process, a thin spacer 111 is shaped to hide the wall surface of the stacked gate structure, and the ions of the source interface 110 are diffused, so that the depth of the source interface 110 is deeper. At this time, the thicknesses of the '〇N01 oxide film 104 and the ⑽03 oxide film 106 are thickened by the oxidation process. The above-mentioned first cell memory ion implantation process and memory cell source annealing process are performed to ensure-uniform source contact-lateral depth. Figure 1 and Figure 2C of a test: “in—the second photoresist film is formed at the front and the back of the mouth” —a second photoresist film pattern 112 is used by itself—engraving a mask on the back name 4Q exposure and side surface are formed. In order to form a common source line connecting the source junctions 11 of individual memory cells by the diffusion method, a segregation between adjacent recording and listening rooms placed in the first turning direction_ 自 赖 齐 _age Was carried out. Moreover, in order to

本紙張織用中國 五、發明説明（ J隔=置形成接面，而連接個別的源極接面， 弟一逼记憶胞源極離子植入制姑 極接面110。 植入衣滅進仃’而形成-高濃度源 且、極接面110的半導體基板仙被損傷， 且源極接面110亦被形成於均勻的縱深中。 产’藉由該第二道記憶胞源極離子植人製程，一低濃 ，源極接面的形狀⑻被推至低於閘極(b);又藉由該第二道記 低於其。 回，辰度源極接面的形狀(C)被形成 現在參考第i圖及第2D圖，一自行對齊_ (SAS)退 ^程被進彳T ’以活化高濃度㈣離子（作為鶴二道記憶 月巴源極離子植人材料），因而降低總記憶胞源極線的電阻率。 因此’該源極接面110的縱深由形狀W變為雜⑹。在一第 二光阻膜被職於整舰構上赠，—第三光晴ιΐ3係藉 由使用-祕遮罩轉光與細製程而被形成。使用第三光 阻膜圖f 113作為遮罩的雜質離子植入製程被進行，而形成 ，胞汲極接面114。其次，該第三光阻膜圖案113被移 除，而完成一快閃EEPROM記憶胞的製造。 、然而纟具有-欠四分之—微来之通道長度的記憶胞以上 述方法形成的狀況巾’當進行—用於製作高闊電壓狀態的程 式化作業、-用於用於製作低閥電壓狀態的抹除作業、一用 於私式化過度抹除之記憶胞的回復作業，以及一用於決定記 憶胞狀態為“Γ或‘‘〇，，的讀取作業時，下列問題將產生°。 首先’由於設計準則被降低至次四分之一微米的閘極長This paper is woven with Chinese V. Description of the invention (J septum = placement to form a junction, and the individual source junctions are connected. The younger one forces the memory cell source ion implantation to make the juncture junction 110. The implanted garment is destroyed. The formation of the high-concentration source and the semiconductor substrate of the electrode junction 110 is damaged, and the source junction 110 is also formed in a uniform depth. In the human process, the shape of a low-concentration source interface is pushed below the gate (b); and it is lowered by this second note. Back, the shape of the source interface (C) It is formed. Now referring to Figure i and Figure 2D, a self-alignment _ (SAS) regression process is carried out to T 'to activate high concentration of plutonium ions (as a source material for implantation of Heliang Memory Moonba source ions). Reduce the resistivity of the source line of the total memory cell. Therefore, 'the depth of the source junction 110 changes from a shape W to a hybrid. A second photoresist film is donated to the entire ship structure—the third light sunny ΐ3 It is formed by using a light-shielding mask to convert light and fine processes. The impurity ion implantation process using the third photoresist film f 113 as a mask is performed. The cell drain interface 114 is formed. Secondly, the third photoresist film pattern 113 is removed, and the manufacture of a flash EEPROM memory cell is completed. However, the channel length is-less than one-fourth-microseconds. The memory cell formed by the above method is used when performing-stylized operation for making a high and wide voltage state,-for erasing operation for making a low valve voltage state, and for over-erase of private type The memory cell recovery operation and a read operation to determine the state of the memory cell as "Γ or" 〇 ,, the following problems will occur. First, 'because the design criteria are reduced to the next quarter micron. Gate length

本紙張财賴家轉（CNS) (2lGx1297W (請先閲讀背面之注意事一^填寫本頁} -裝· 、11 線 經濟部智慧財產局員工消費合作社印製 A7五 、發明説明（ B7 = 0N01底層氧化物膜與該0N〇3上層氧化物膜將 胞源極退火製程而變厚，如第2B圖所示。、不 胎，姑—面上看似局部鳥嘴狀之酿的長紐拉長的記憶 广ΟΝΟΙ底層氧化物膜的橫剖面完全變為由邓埃至 、旱且口亥0Ν03上層氧化物膜的橫剖面完全變為由5〇埃 至120埃厚。在該狀況中，如第3圖所示，由於控制閑極鱼 =閘極之間的電容量Cg被降低’所以該閘極電容量輕^ =里 Cg/Ct (ct - Cg + Cd + Cs + Csub)被降低。因此，被 經濟部智慧財產局員工消費合作社印製 知加於控制閘極之偏壓的影響增加，而浮置閘極中的電位 vfg降低被減少。因此，該抹除作業（參閱第6圖中的數字工） 以及私式化與讀取作業（參閱第7圖中的數字幻皆被劣化。 因此所具有的缺點為一更高的偏壓必須被施加於該控制閑 極，以麵其。再者，由於該ΟΝΟ厚度增加的現象為為第 三次記憶胞源極退火製程期間的附加現象，所以該〇則底 層氧化物膜與0Ν03上層氧化物膜的厚度將基於取決於諸如 多晶矽中的摻雜程度的批次/晶圓/位置的變化、閘極定義製程 期間所產生之長度的變化、記憶麟極退火製雜間之氧化 作用的變化等，而有不同的增加。若該〇]^〇厚度不同，則 以區域或區塊膜除特性之觀點，具有相對薄厚度的記憶胞將 被快速抹除。另一方面，具有相對厚厚度的記憶胞將被緩慢 抹除，因此將明顯地加寬該記憶胞之閥電壓的分佈。在快速 抹除之被過度抹除的記憶胞中所具有的問題為，由於當程式 確認作業與讀取作業（施加沒極偏壓）進行時，位元線漏電 流明顯地增加，所以個別作業的效率被降低；而在緩慢抹除 ---------— 5____ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公董) ' 478115 A7This paper is based on a family transfer (CNS) (2lGx1297W (please read the note on the back first ^ fill out this page)-installed ·, 11 Printed by A11 of the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, V. Invention Description (B7 = 0N01 The bottom oxide film and the 0N03 upper oxide film are thickened by the cell source annealing process, as shown in Figure 2B. The long cross-section of the long memory oxide film on the bottom oxide film has completely changed from Dune to, and the cross-section of the upper oxide film on the film has completely changed from 50 Angstroms to 120 Angstroms thick. In this state, such as As shown in FIG. 3, since the capacitance Cg between the control idler and the gate is reduced, the gate capacitance is lighter, and the Cg / Ct (ct-Cg + Cd + Cs + Csub) is reduced. Therefore, the influence of the bias voltage applied to the control gate by the consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is increased, and the reduction of the potential vfg in the floating gate is reduced. Therefore, the erasing operation (see FIG. 6) Digital work) and privatization and reading operations (see the digital magic in Figure 7) Therefore, it has the disadvantage that a higher bias voltage must be applied to the control idler. In addition, since the ONO thickness increase phenomenon is an additional phenomenon during the third memory cell source annealing process. Therefore, the thickness of the bottom oxide film and the ON03 upper oxide film will be based on changes such as batch / wafer / position changes depending on the degree of doping in polycrystalline silicon, and changes in length generated during the gate definition process. , The change in the oxidation of the memory linji annealing system, and so on, there are different increases. If the thickness of 〇] ^ 〇 is different, from the perspective of the area or block film removal characteristics, the memory cell with a relatively thin thickness will It is quickly erased. On the other hand, a memory cell with a relatively thick thickness will be erased slowly, so the distribution of the valve voltage of the memory cell will be significantly widened. Among the memory cells that are quickly erased and over-erased The problem is that the bit line leakage current significantly increases when the program confirmation operation and the reading operation (applying the non-polar bias) are performed, so the efficiency of individual operations is reduced; ---------- 5____ erase this paper scale applicable Chinese National Standard (CNS) A4 size (210X297 public Dong) '478115 A7

(請先聞讀背面之注拳項寫本- 頁) -裝- 訂 478115 A7 --------B7 五、發明説明（L ) 於汲極開啟或汲極誘發阻障降低（DIBL)現象，可能會有更 夕的漏電流，其將造成程式化特性的劣化。因此，為了補償 其，幫浦電路必須足夠大，以增加電流。 經濟部智慧財產局員工消費合作社印製 第二，將產生汲極擾動的現象。該汲極擾動係為當進行 程式化作業或回復作業時，若一高的偏壓被施加於位元線， 則未被選擇之記憶胞的閥電壓將改變，如第二個狀況。就避 免漏電流的目的而言，由於汲極接面的直立深度必須為小 的，所以為確保有效通道長度，則必須形成薄的汲極接面。 在該狀況中，由於接面濃度增加且該接面中的空乏層寬度減 少，所以半導體基板與接面之間的能帶彎曲將增加，能帶對 忐帶的穿隧現象在一高偏壓施加於汲極之程式化作業與回復 作業中增加，且接面崩潰現象因其而增加。這二種現象明顯 地々加所產生之熱電洞的數量。在上述的二種作業模式中， 由於所形成的電場係由浮置閘極至沒極接面，所以熱電洞被 注入該浮置閘極以作為閘極電流（第8圖中的參考數字3)， 或者被捕捉於通道氧化物膜中，因而增加該浮置閘極的電 位。因此’如第8 ®中的參考數字！所示，當感測作業進行 時，因為在程式化狀態的記憶胞閥電壓被降低，所以該程式 化記憶胞未被辨別。再者，由於被捕捉的熱電洞具有有的有 效質量，所以其將造成穿隧氧化物膜中的氧化物膜崩潰，而 明顯地降低記憶胞的壽命。 第四，在自行對齊蝕刻製程期間，由於源極接面主動區 域中的半導體基板·幾乎為直立地產生，所崎記憶胞的 特性分佈被加寬，因為高濃度接面的形成對於損耗不同而有 本紙張尺度適用中國國家標準（CNS ) ( 2獻297公董(Please read the Notepad Box on the back-page first)-Binding-Book 478115 A7 -------- B7 V. Description of the Invention (L) Turn on the drain or the drain-induced barrier reduction (DIBL) Phenomenon, there may be more leakage current, which will cause the degradation of stylized characteristics. Therefore, to compensate for this, the pump circuit must be large enough to increase the current. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Second, there will be a phenomenon of drain disturbance. The drain perturbation is that if a high bias voltage is applied to the bit line when programming or restoring, the valve voltage of the unselected memory cell will change, as in the second case. For the purpose of avoiding leakage current, since the upright depth of the drain junction must be small, to ensure an effective channel length, a thin drain junction must be formed. In this situation, because the junction concentration increases and the width of the empty layer in the junction decreases, the band bending between the semiconductor substrate and the junction will increase, and the tunneling phenomenon of the band-to-band band is at a high bias voltage. Stylized operations and recovery operations applied to the drain are increased, and the interface collapse phenomenon is increased due to this. These two phenomena significantly increase the number of thermal holes generated. In the above two modes of operation, since the electric field formed is from the floating gate to the non-electrode junction, a thermal hole is injected into the floating gate as the gate current (reference numeral 3 in FIG. 8). ), Or is captured in the channel oxide film, thereby increasing the potential of the floating gate. So ’as the reference number in Section 8 ®! As shown, when the sensing operation is performed, because the voltage of the memory cell valve in the programmed state is lowered, the programmed memory cell is not identified. Furthermore, since the trapped thermal holes have an effective mass, they will cause the oxide film in the tunneling oxide film to collapse, and significantly reduce the life of the memory cell. Fourth, during the self-aligned etching process, since the semiconductor substrate in the active area of the source junction is almost upright, the characteristic distribution of the Sozaki memory cell is widened because the formation of a high-concentration junction is different for different losses. Have this paper size applicable to China National Standards (CNS) (2 Xian 297 directors

敏感地反應。 發明之簡要說明： _ = 本^明之—目的在於提供—種可解決上述問題之 快閃电子f可抹除程式化唯讀記憶體的製程。 二士、、±_成述目的’根據本發明之—種將快閃記憶胞程 :士構、ιφ Γΐ在於其包含的步驟有：形成—個堆疊閘極 構’其中—個牙隨氧化物膜、—個浮置閘極、—個介電膜 =個控制閘，被堆疊於一半導體基板的特定區域上，並接 乳化退火製程；藉由植入低濃度的雜f離子於 體基板的特定區域中，而形成一低濃度雜接面；形 ==___結_壁面上’進行—道記憶胞源極 :將;二=,一自行對齊源極綱遮罩_刻製程， 定區域侧；以及藉由植入高濃度雜 歧極接面，並接著進行-道自行對齊 源極退火製程。 圖式之簡要說明： 圖而在下列說明 本發明之前述特性與其他特徵將配合附 中被說明，其中： 弟1圖表示 ceeprom,.㈣0式可抹除程式化唯讀記憶體 CEEPR0M)記憶胞陣列的佈局。 圖至第2D圖為用於說明慣用之快閃卿腿記 隱胞的製裎的裝置的橫剖面圖。Respond sensitively. Brief description of the invention: _ = The purpose of the present invention is to provide a process for erasing the programmable read-only memory by a flash electron f which can solve the above problems. Two scholars, ± _ to achieve the stated purpose 'According to the present invention-a kind of flash memory cell: Shi structure, ιφ Γ ΐ lies in the steps it includes: forming a stacked gate structure' of which-a tooth with oxide Film, a floating gate electrode, a dielectric film = a control gate, are stacked on a specific area of a semiconductor substrate, and are connected to an emulsification annealing process; by implanting a low concentration of heterof ion into the body substrate, In a specific area, a low-concentration hybrid surface is formed; the shape == ___ knot_on the wall 'is performed—the channel memory cell source: will; the second =, a self-aligned source outline mask_engraving process, a fixed area Side; and by implanting a high-concentration heterojunction junction, and then performing a self-aligned source annealing process. Brief description of the drawings: The following characteristics and other features of the present invention will be described in the attached description in the following description, in which: Figure 1 represents ceeprom, .㈣0 type can erase the programmable read-only memory (CEEPR0M) memory cell array Layout. Figures 2 to 2D are cross-sectional views for explaining a conventional device for controlling a cymbal cell of a flash leg.

478115 A7 五、發明説明（》） ^ 3圖為一快閃EEPROM記憶胞陣列的示意圖式。 第4圖為用於說明各快閃EEPR〇M記憶胞端子與一浮置 間極之間的轉合電容量的記憶胞的示意圖。 第5A圖至第5D圖為用於說明根據本發明之快閃 EEPROMg己憶胞的製程的裝f的橫剖面圖。 第6圖為用於比較慣用及本發明之快閃EEPR〇M記憶胞 的抹除特性的圖式。 第7圖為用於比較慣用及本發明之快閃EEPR〇M記憶胞 的閘極電壓與汲極電流特性的圖式。 第8圖為用於比較慣用及本發明之快閃EEPR〇M記憶胞 的没極漏電極與閘極電流的圖式。 第9圖為用於比較慣用及本發明之快閃EEpR〇M記憶胞 之閥電壓基於被程式化記憶孢之汲極偏壓應力所產生的擾動 現象而被降低的現象的圖式。 (請先閲讀背面之注意事填寫本頁) .裝.478115 A7 V. Description of the Invention (") ^ 3 is a schematic diagram of a flash EEPROM memory cell array. Fig. 4 is a schematic diagram for explaining a memory cell with a switching capacitance between each flash EEPROM memory cell terminal and a floating electrode. 5A to 5D are cross-sectional views for explaining the process of the flash EEPROMg process according to the present invention. Fig. 6 is a diagram for comparing the erasing characteristics of the conventional flash EEPROM memory cell according to the present invention. Fig. 7 is a diagram for comparing the gate voltage and drain current characteristics of the conventional flash EEPROM memory cell according to the present invention. Fig. 8 is a diagram for comparing the electrodeless drain electrode and the gate current of the conventional flash EEPROM memory cell according to the present invention. Fig. 9 is a diagram for comparing the phenomenon in which the valve voltage of the flash EEPROM memory cell of the conventional and the present invention is reduced based on the perturbation phenomenon generated by the drain bias stress of the programmed memory spore. (Please read the notes on the back and fill in this page first).

，1T 經濟部智慧財產局員工消費合作社印製 圖號說明： 10-裝置隔離遮罩 20-第一多晶石夕遮罩 101- 半導體基板 102- 穿隧氧化物膜 103- 第一多晶矽膜 104- ONO1底層氧化物膜 105- ONO2氮化物膜 106- ONO3上層氧化物膜 k .m 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 478115 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（I ) 107- 第二多晶矽膜 108- 金屬矽化物膜 109- 第一光阻膜圖案 110- 低濃度的源極接面 111- 薄的間隔物 112- 第二光阻膜圖案 113- 第三光阻膜 114- 記憶胞汲極接面 201- 半導體基板 202- 穿隧氧化物膜 203- 第一多晶矽膜 204- ONO1底層氧化物膜 205- ONO2氮化物膜 206- ONO3上層氧化物膜 207- 第二多晶矽膜 208- 金屬矽化物膜 209- 第一光阻膜圖案 210- 低濃度的源極接面 211- 間隔物 212- 第二光阻膜圖案 213- 汲極接面 40-自行對齊#刻遮罩 (請先閲讀背面之注意事項寫本頁) -裝· -IQ- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 五、發明説明（（〇 ) 發明之詳細說明·· 本發月現在將|考附圖而以較佳實施例的方式詳細地說 明，其中相似的參考數字被使用代表相同或類似的部分。 第5A圖至第5D圖為用於說明根據本發明之快閃 EEPROM δ己憶胞的製程的裝置的橫剖面圖。根據本發明之快 閃EEPROM心隐胞的製程遵循帛i圖所示的佈局，其特徵在 於變成汲極接面的部分被改良為-源極/汲極接面。 現在參考第5A圖，_裝置隔離麟藉域置隔離遮罩 而被形成於-半導體基板2〇1 ±。其次，在一穿隧氧化物膜 =與-第-多晶频2G3依序被形成於整個結構上之後， ^ 一多晶石夕膜203與穿隧氧化物膜202係藉由使用一第一 多晶石夕遮罩的光學微影製細制4。其:欠，在包含有一 ΟΝΟΙ底層氧化物膜2〇4、一 〇N〇2氮化物膜2〇5以及一 0N03上層氧化物膜2Q6的一介電膜被形成彳 1，一第二多晶 矽膜207與一金屬石夕化物膜2〇8依序被形成。其:欠，其被刻 旦而幵>/成孚置閘極與控制閘極被堆疊於其中的堆疊閘極結 構。此時，該浮置閘極係由一第一多晶矽膜2〇3所形成，而 。亥拴制閘極則由一第二多晶矽膜2〇7與一矽化鎢膜2㈨所形 成。其次，為補償閘極的蝕刻損傷，則進行一道再氧化製程。 其次，在一第一光阻膜被形成於整個結構上之後，其係藉由 使用一自行對齊蝕刻遮罩40的曝光與蝕刻製程而被刻晝。其 次，一第一記憶胞源極離子植入製程係使用該第一光阻膜圖 案209作為遮罩而被進行，以形成一個低濃度的源極接面 210。此時，該第一記憶胞源極離子植入製程使用低濃度的砷 (請先閲讀背面之注意事項寫本頁} -裝- -訂 經濟部智慧財產局員工消費合作社印製 Η·/0丄丄二), 1T Printed drawing description by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs: 10-device isolation mask 20-first polycrystalline stone mask 101- semiconductor substrate 102- tunneling oxide film 103- first polycrystalline silicon Film 104- ONO1 bottom oxide film 105- ONO2 nitride film 106- ONO3 upper oxide film k .m This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) 478115 Employees ’Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed A7 B7 V. Description of the invention (I) 107- Second polycrystalline silicon film 108- Metal silicide film 109- First photoresist film pattern 110- Low-concentration source interface 111- Thin spacer 112- Second photoresist film pattern 113- Third photoresist film 114- Memory cell drain junction 201- Semiconductor substrate 202- Tunneling oxide film 203- First polycrystalline silicon film 204- ONO1 Underlayer oxide film 205- ONO2 Nitride film 206- ONO3 upper oxide film 207- Second polycrystalline silicon film 208- Metal silicide film 209- First photoresist film pattern 210- Low concentration source junction 211- Spacer 212- Second light Resist film pattern 213- Drain electrode interface 40- Self-aligning # Engraved mask (Please read the back first (Notes on this page) -Installation · -IQ- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 B7 V. Description of the invention ((〇) Detailed description of the invention The drawings will be described in detail in a preferred embodiment, in which similar reference numerals are used to represent the same or similar parts. Figures 5A to 5D are diagrams for explaining the flash EEPROM δ according to the present invention. A cross-sectional view of the device for the process of the self-memory cell. The process of the flash EEPROM heart cell according to the present invention follows the layout shown in Fig. I, which is characterized in that the portion that becomes the drain junction is improved to -source / Drain junction. Referring now to FIG. 5A, _device isolation is formed on a -semiconductor substrate by using an isolation mask. Secondly, a tunneling oxide film = and -the -polycrystalline frequency After 2G3 is sequentially formed on the entire structure, a polycrystalline silicon film 203 and a tunneling oxide film 202 are refined by optical lithography using a first polycrystalline silicon mask 4. It: However, in a layer containing a 100N bottom oxide film 204 and a 10N2 nitride film 2 A dielectric film of 5 and a 0N03 upper oxide film 2Q6 is formed. A second polycrystalline silicon film 207 and a metal oxide film 2008 are sequentially formed. It is: owed, it is carved And the stacked gate structure in which the Cheng gate and the control gate are stacked. At this time, the floating gate is formed by a first polycrystalline silicon film 203. The gate electrode is formed by a second polycrystalline silicon film 207 and a tungsten silicide film 2㈨. Secondly, in order to compensate the etching damage of the gate, a reoxidation process is performed. Secondly, after a first photoresist film is formed on the entire structure, it is etched by using an exposure and etching process using a self-aligned etching mask 40. Secondly, a first memory cell source ion implantation process is performed using the first photoresist film pattern 209 as a mask to form a low-concentration source interface 210. At this time, the first memory cell source ion implantation process uses a low concentration of arsenic (please read the precautions on the back to write this page first) (2)

或磷離子。 經濟部智慧財產局員工消費合作社印製 一個ίΐί考第5Β圖’在該第—光阻膜圖案209被移除後 :贿度為至5⑻埃的氧⑽戦於整個結構上。 二行一道間隔物崎程，而形成間隔物211於_ 職社。其:欠，妨—道城胞雜退火，箱 触210中的離子被擴散，而使得源極淑 ^*^更深。在該記11麵極退火製針，㈣間隔物 係作為-阻絕物，所以0Nm底層氧化物膜2Q4與〇N〇3 上層乳化物膜206㈣的程度因而被明顯地降低，不若慣用 者一般。 、 見在參考第5C目，在一第二光阻膜被形成於整個結構 上以後’-第二光阻膜_ 212係藉由使用一自行對齊侧 遮罩奶的曝光與侧製程而被形成。為了以擴散法形成連接 個別記憶胞之源極接面210的一共用源極線，一道用於移除 置於相鄰記憶胞間的裝置隔離膜的自行對齊侧製程被進 行。此日守’雖然源極接面210巾的半導體基板2〇1被損傷， 惟由於間隔物211被漸漸地損耗，所以接面21〇被損耗，以 使得其可具有緩合的梯度。 現在參考第5D圖’在該第二光阻膜2!2被移j^後，高 濃度的雜質離子被植入整個表面中，而形成一源極接面21〇 與一汲極接面2D。其次，若-自行對齊源極（SAS)退火 製程被進行’則該源極接面210與沒極接面213中的雜質離 子將被擴散進入半導體基板201，以使得源極接面21〇與汲 極接面213的區域變寬。Or phosphorus ions. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 5B. After the photo-resist film pattern 209 is removed, the bridging degree is 5 angstroms of oxygen on the entire structure. Two rows of spacers are formed, and spacers 211 are formed in _. Its: ow, may-anneal the Daocheng cell, the ions in the box contact 210 are diffused, which makes the source electrode ^ * ^ deeper. In this case, the needles are annealed and the ㈣ spacer is used as a -resistor. Therefore, the extent of the 0Nm bottom oxide film 2Q4 and the OONO3 upper emulsion film 206㈣ is significantly reduced, which is not as ordinary as that used by ordinary users. See the reference 5C, after a second photoresist film is formed on the entire structure, the second photoresist film _212 is formed by using a self-aligning side mask milk exposure and side process. . In order to form a common source line connecting the source junctions 210 of individual memory cells by a diffusion method, a self-aligned side process for removing a device isolation film placed between adjacent memory cells is performed. On this date, although the semiconductor substrate 201 of the source junction 210 is damaged, the spacer 211 is gradually lost, so the junction 21 is lost so that it can have a gentle gradient. Referring now to FIG. 5D, after the second photoresist film 2! 2 is shifted, a high concentration of impurity ions are implanted into the entire surface to form a source junction 21 and a drain junction 2D. . Secondly, if a self-aligned source (SAS) annealing process is performed, the impurity ions in the source interface 210 and the non-contact interface 213 will be diffused into the semiconductor substrate 201 so that the source interface 21 and the The area of the drain junction 213 becomes wider.

本紙張尺1適用中國國家標準（CNS) Α4· (21〇χ297公慶）This paper ruler 1 is applicable to Chinese National Standard (CNS) Α4 · (21〇χ297 公 庆)

478115 A7 ----------—_________ 五、發明説明（|>) 畐一快閃EEPROM以上述的方法製造時，下列的問題可 被解決。 經濟部智慧財產局員工消費合作社印製 如上所述，在記憶胞源極退火製程與SAS退火製程前形 成間隔物的狀況中，其可避免氧氣到達該〇N〇1底層氧化物 膜0N03上層氧化物膜，以及在其界面上的該第一與第二 多晶矽。在以本發明所製造的該快閃EEpR〇M記憶胞中，該 ΟΝΟΙ底層氧化物膜與〇N〇3上層氧化物膜的厚度係侧由 50埃增加至70埃。因此。該閘極耦合電容量數值明顯地增 加，且該閘極耦合電容量比例因而由〇45增加至〇6〇。這方 面可藉由比較抹除與讀取條件而被證實。如第6圖所示，在 抹除特性的狀況中，可見到相較於慣用的記憶胞，該經改良 的記憶胞的抹除速度進步約麵6。再者，第6圖表示該程 式化特性的差異，其中在經程式化記憶胞中的程式化速度可 月快，因為抹除特性的初始數值高於該經改良記憶胞的閥 電壓。因此，可見到該0N0厚度異變的降低，且該記憶胞 4寸f生刀佈因而變窄，因為該QN〇i底層氧化物膜與〇nq3上 層、氧化物膜的厚度增加被避免。第7圖為當一 〇 8v的汲極偏 壓被施加時，該Vg4d特性曲線的比較。其顯示當被抹除時， 該經改良的記憶胞在閘極偏壓區域中具有約1〇至2〇微安培 的增加輸出電流（其中讀取偏壓為“Γ )。在本發明中，基 於間隔物的存在，由於所形成的高濃度源極接面^開如^ 隔物的寬度，因而降低低濃度源極接面内推的現象。因此， 由於源極接面與浮置_重疊瓣低，所叫效通道長度被 增加。該結果明顯地表示於第9 ®中的汲極漏電流特性曲線 本紙張顧用中國國家標iT^NS) Α4· (21(^297公董） A7 — -------B7 五、發明説明（"） ~ —-- 2當經改良之記憶胞的漏電流特性曲線2與本發明的漏電 *寸性曲線1比較時，更可見到該記憶胞之特性曲線2的增 強 '中及極偏壓已經改良約J 〇至15V，以使得漏電流在 相_雜與雜之間錄。該縣意味著在相收極偏壓 条件下該、改良5己憶胞中之源極與沒極之間的漏電流被降 低。再者’由於存在有—記憶胞間隔物，所以該高濃度的沒 極接面以綱_的寬度隔轉在，並藉_第三記憶胞源 極退火製程而被内擴散往通道方向，因而與該浮置閘極重 疊。因此，軸辩㈣極與高濃歧極接面之_重疊與 慣用者相同，惟其因該高濃度汲極接面被擴散而有梯度，因 而增加空乏_寬度並降減帶彎曲。因此，在相同的没極 偏壓條件下，該能帶對能帶穿隨與接面崩潰電流係明顯地被 降低。此可由第8圖中的特性曲線i與2看見。因此，所產 生之熱電洞的數量係為該能帶對能帶穿隧與接面崩潰電流係 為所降低。目此，比較第8圖中之基於熱電洞注入所造成的 閘極電流3與4，當没極偏壓為4.7V時，該經改良記憶胞之 曲線4的閘極電流為1〇E13，而慣用記憶胞之曲線3的閘極 電流為10EH。由此，在經程式化之記憶胞中所示的汲極擾 動特性差異可被清楚地看見。參考第9圖中之該汲極擾動特 性曲線’可見到相較於該慣用的記憶胞，在該經改良之記憶 胞中的閥電壓偏移被降低15V。再者，由於被捕捉的熱電洞 數量降低，所以該穿隧氧化物膜的壽命明顯地增加。由於當 自行對齊源極蝕刻製程被進行時，所產生之半導體基的損 耗（第5C圖）具有一缓合的内凹曲線，因而產生該汲極接 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項寫本頁) •裝· 訂 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（1 + ) 面的/未度。因此，該記憶胞特性的均勻性可被增加。再者， 在進行自行㈣源極撤懷程後，進行該記憶胞源極級極離 子植入製& ’並接著進行SAS退火製程，目而將記憶胞源極 線中的坤離子活化，崎低其電阻率。因此，由於該記憶胞 源極/及極離子植入製程可被同時執行（省略第二道記憶胞源 極離子植人製程），所以其伽在於當執行光學微影製程時， 在一臨界製程中進行的該記憶胞汲極遮罩製程可以一非臨界 製程執行。 另一方面，在本發明的另一個實施例中，該間隔物係以 ^有-個氧化物膜與—個氮化物膜的雙重結構被形成。此 日二該氧化物麟作為該氮化物賴隔物的應力缓衝物。應 /主思地疋，該氮化物膜和氧化物膜的總厚度係與當該間隔物 以一單一的氧化物膜形成時的厚度相同。 如上所述，本發明具有下列效果·· 1·閘極電容量耦合比例可藉由避免〇N〇1底層氧化物 膜與ΟΝΟ3上層氧化物膜的厚度增加而被增加。因 此，該程式化與抹除速度可被改良，而記憶胞的電流 亦可被增加。 2_由於有效通道長度被增加，所以在程式化與回復作業 期間’未被選擇之記憶胞的源極與沒極之間的漏電流 可被降低。因此’程式傾速度與_的效率可被改 良’而幫浦電路的尺寸可被縮小。 3.由於在健_，該未被麵找憶朗源極與 没極之間的漏電流依據有效通道長度的增加而被降 478115 五 A7 、發明說明（ff) 低，所以讀取速度與感測邊際可被增加。 4·由於汲極接面被斜向地形成，所以在程式化與回復作 業期間所產生於未被獅之記憶胞巾的能帶對能帶 穿隧現象、没極接面崩潰現象等可被避免。因此，因 而產生的熱電洞數量可被降低，且藉由熱電洞注入浮 置閘極中引起之汲極擾動所造成之經程式化記憶胞 之閥電壓的降低程度可被減小，因此，由於被捕捉的 熱電洞數量可被降低，所以該穿隨氧化物膜的崩潰可 被避免，且其壽命可被增加。再者，由於在汲極接面 與基板間所1生的漏電流可被降低，所以該程式化與 回復特性可被改良。 5.當該自行對齊源極蝕刻製程被進行時，該源極接面的 損耗係以内凹狀產生。.因此，由於直立及水平深度可 被均勻地形成，所以該記憶胞的閥電壓與該記憶胞電 流的均勻性可被改良。 6，當進行光學微影製程時，其可以一非臨界製程進行， 而將该5己憶胞源極/>及極曝光’而非以一臨界製程而僅 將記憶胞汲極曝光。因此，製程困難度可被降低。 7.由於該漏電流與控制閘極偏壓可被降低，所以一種呈 有低功率、低電壓與高速度的裝置可被開發。 、 本發明已經參考有關一特定應用的一特定實施例做說 明。熟習本技藝並經本發明之教導的人士將瞭解落於其範脅 中的其他改良與應用。 所附申請專利範圍希冀涵蓋落於本發明之範疇中的任何 16 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐 ------·---- ----------------- (請先閱讀背面之注意事項再填寫本頁) ~ ' 478115 A7 B7 五、發明說明（A) 以及所有該應用 改良與實施例 (請先閱讀背面之注意事項再填寫本頁) 裝 鳜 經濟部智慧財產局員工消費合作社印製 17 Μ 公 97 2 X 10 2 一規 A4 ls)A N (C 準 標 國 國 中 用 適 度 尺 張 紙 本478115 A7 ----------——_________ V. Description of the Invention (| >) When a flash EEPROM is manufactured by the above method, the following problems can be solved. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, as described above, in the case where spacers are formed before the memory cell source annealing process and the SAS annealing process, it can prevent oxygen from reaching the 0N〇1 bottom oxide film 0N03 upper layer oxidation An object film, and the first and second polycrystalline silicon on its interface. In the flash ERepROM memory cell manufactured according to the present invention, the thickness of the ONO1 bottom oxide film and the ONO3 upper oxide film is increased from 50 angstroms to 70 angstroms. therefore. The value of the gate coupling capacitance increased significantly, and the ratio of the gate coupling capacitance increased from 045 to 060. This can be confirmed by comparing erase and read conditions. As shown in Fig. 6, in the state of the erasing characteristic, it can be seen that the erasing speed of the improved memory cell is improved by about 6 compared with the conventional memory cell. Furthermore, Fig. 6 shows the difference in the programming characteristics, in which the programming speed in the programmed memory cell can be faster, because the initial value of the erase characteristic is higher than the valve voltage of the modified memory cell. Therefore, it can be seen that the thickness variation of the 0N0 is reduced, and the 4 inch f-knives of the memory cell are narrowed because the thickness increase of the QNOi bottom oxide film and the Onq3 upper layer and oxide film is avoided. Fig. 7 is a comparison of the Vg4d characteristic curve when a 108V drain bias voltage is applied. It shows that the modified memory cell has an increased output current (where the read bias is "Γ) in the gate bias region of about 10 to 20 microamperes when erased. In the present invention, Based on the existence of the spacer, the formation of the high-concentration source junction is as wide as the width of the spacer, thereby reducing the phenomenon of inward push of the low-concentration source junction. Therefore, because the source junction overlaps with the floating junction The lobe is low, and the effective channel length is increased. This result is clearly shown in the characteristic curve of the drain leakage current in Section 9 ®. This paper uses the Chinese national standard iT ^ NS) Α4 · (21 (^ 297 公 董) A7 — ------- B7 V. Explanation of the invention ~ --- 2 When the leakage current characteristic curve 2 of the improved memory cell is compared with the leakage current characteristic curve 1 of the present invention, it is more visible The enhancement of the characteristic curve 2 of the memory cell's neutral pole bias has been improved by about J0 to 15V, so that the leakage current is recorded between the phase miscellaneous and the miscellaneous. The county means that the 5. The leakage current between the source electrode and the immortal electrode in the memory cell has been reduced. Furthermore, 'due to the existence of-the memory cell spacer Therefore, the high-density non-polar junction is separated by the width of the outline, and is diffused inward to the channel by the third memory cell source annealing process, so it overlaps with the floating gate. Therefore, the axis debate The overlap between the dipole and the high-density bipolar junction is the same as the conventional one, but it has a gradient because the high-concentration drain junction is diffused, thus increasing the width of the void and reducing the bending of the band. Therefore, at the same pole Under biased conditions, the band-to-band breakdown current at the junction is significantly reduced. This can be seen from the characteristic curves i and 2 in Fig. 8. Therefore, the number of thermal holes generated is The band-to-band tunneling and junction breakdown currents are reduced. For this reason, compare the gate currents 3 and 4 caused by thermal hole injection in Figure 8 when the non-pole bias is 4.7V. The gate current of curve 4 of the modified memory cell is 10E13, and the gate current of curve 3 of the conventional memory cell is 10EH. Therefore, the difference in the characteristics of the drain disturbance shown in the programmed memory cell is different. It can be clearly seen. Refer to the characteristic curve of the drain disturbance in Fig. 9 Compared to the conventional memory cell, the valve voltage offset in the modified memory cell is reduced by 15 V. Furthermore, the life of the tunneling oxide film is significantly reduced due to the reduced number of captured thermal holes. Increased. Because the self-aligned source etching process is performed, the semiconductor-based loss (Figure 5C) has a gentle concave curve, so the drain electrode is connected to the paper standard in accordance with Chinese national standards (CNS ) A4 specification (210X297 mm) (Please read the notes on the back to write this page first) • Binding and ordering printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (1 +) on the front / back. Therefore, the uniformity of the characteristics of the memory cell can be increased. Furthermore, after performing the self-pumping source removal process, the memory cell source-level polar ion implantation & 'and then the SAS annealing process are performed. The Kun ion in the source line of the memory cell is activated, and its resistivity is reduced. Therefore, since the memory cell source / and ion implantation process can be performed at the same time (the second memory cell source ion implantation process is omitted), the reason is that when the optical lithography process is performed, a critical process is performed. The memory cell drain mask process can be performed in a non-critical process. On the other hand, in another embodiment of the present invention, the spacer is formed in a double structure including an oxide film and a nitride film. Today, the oxide is used as a stress buffer for the nitride spacer. It should be noted that the total thickness of the nitride film and the oxide film is the same as the thickness when the spacer is formed as a single oxide film. As described above, the present invention has the following effects: 1. The gate capacitance coupling ratio can be increased by avoiding an increase in the thickness of the ONO1 bottom oxide film and ONO3 upper oxide film. Therefore, the programming and erasing speed can be improved, and the current of the memory cell can be increased. 2_ As the effective channel length is increased, the leakage current between the source and the non-selected memory cells during the stylization and recovery operations can be reduced. Therefore, the "program tilt speed and the efficiency of _ can be improved" and the size of the pump circuit can be reduced. 3. Due to Jian Jian, the leakage current between the source and the pole of the non-memory is reduced according to the increase of the effective channel length. 478115 Five A7, the description of the invention (ff) is low, so the reading speed and sensitivity The measurement margin can be increased. 4. Since the drain junction is formed obliquely, the band-to-band tunneling phenomenon of the lion's memory cell and the collapse of the non-polar junction during stylization and recovery operations can be avoided. avoid. Therefore, the number of thermal holes generated thereby can be reduced, and the degree of reduction in the valve voltage of the programmed memory cell caused by the drain disturbance caused by the injection of the thermal holes into the floating gate can be reduced. The number of trapped hot holes can be reduced, so the breakdown of the through oxide film can be avoided, and its lifetime can be increased. Furthermore, since the leakage current generated between the drain junction and the substrate can be reduced, the programming and recovery characteristics can be improved. 5. When the self-aligned source etching process is performed, the loss of the source junction is generated in a concave shape. Therefore, since the upright and horizontal depths can be formed uniformly, the uniformity of the valve voltage of the memory cell and the current of the memory cell can be improved. 6. When the optical lithography process is performed, it can be performed in a non-critical process, and the 5-cell memory source / > and pole exposure are exposed instead of a critical process and only the memory cell drain is exposed. Therefore, process difficulty can be reduced. 7. Since the leakage current and the control gate bias voltage can be reduced, a device with low power, low voltage, and high speed can be developed. The invention has been described with reference to a specific embodiment for a specific application. Those skilled in the art and taught by the present invention will appreciate other improvements and applications that fall into their scope. The scope of the attached patent application is intended to cover any of the 16 paper sizes falling within the scope of the present invention, which are applicable to the Chinese National Standard (CNS) A4 specification (21 × x297 mm) ----------- --- -------------- (Please read the notes on the back before filling out this page) ~ '478115 A7 B7 V. Description of the invention (A) and all the improvements and examples of this application (please first Read the precautions on the back and fill in this page.) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Printed 17 M. 97 2 X 10 2 A4 ls.

Claims (1)

甲請專利範圍 .-種快閃電子式可抹除 之 製程方法，包含下列步驟唯"挪體（咖0M) 形成一個堆疊閘極結構，复 個浮置閘極、一個介帝膜盥中個牙趣氧化物膜、一 體基板的特定區域上，祐接基 ^ Ml ^ 進行—道在氧化退火製程； 定區ίΓ 的雜f離子於該半導體基板的該特 疋£域中’而形成—低濃度源極接面； 形成間隔物於該堆疊閘極結構的壁面上 憶胞源極退火製程； 〜、尤 抑藉由使用一自行對齊源極麵遮罩的綱製程，而將 極區域中的該特定區域兹刻，·以及 2 藉由植入南濃度雜質離子而形成一源極與没極接 面，並接著進行一道自行對齊源極退火製程。 ^申請專利翻第1項所述之快閃電子式可抹除程式化唯 靖战體之製程方法，其中在一個氧化物膜被形成於該整 個結構上後，該_物係以毯覆式侧製㈣被形成。 經濟部智慧財4局具工消費合作社印製 3·如申請專利細第2顿狀快閃電子式可抹除程式化唯 讀記憶體之製程方法，其中所形成之該氧化物膜的厚度為 300 至 500 埃。 4·如申請專利範圍第1項所述之快閃電子式可抹除程式化唯 讀記憶體之製程方法，其中該間隔物係藉由毯覆式蝕刻製 程藉此一個氧化膜與一個氤化膜被依序形成於整個結構 上，而以具有一個氧化物膜與一個氤化物膜的雙重結構被 1 Q____ 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公f ) 478115 B8 C8 DS 丨六、申請專利範圍 形成。 I 5_如申請專利範圍第4項所述之快閃電子式可抹除程式化唯 | 讀記憶體之製程方法，其中該氧化物膜與該氮化物膜的厚 ! 度為3⑻至500埃。 經4-部智葸財.4局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公f 'A patent scope.-A flash electronic erasable manufacturing method, including the following steps: "Remove body (Ca 0M) to form a stacked gate structure, a plurality of floating gates, a membrane On a specific area of the dental oxide oxide film and the integrated substrate, the substrate ^ Ml ^ is carried out-in an oxidation annealing process; the hetero-ions in a specific region Γ are formed in the special region of the semiconductor substrate- Low-concentration source junctions; forming spacers on the walls of the stacked gate structure to recall the cell source annealing process; ~, especially by using a self-aligning source mask process, the This specific area is engraved, and 2 and 2 by implanting the impurity ions of the south concentration to form a source-animated interface, and then perform a self-aligned source annealing process. ^ The flash electronic erasable stylized Weijing warfare process method described in item 1 of the patent application, wherein after an oxide film is formed on the entire structure, the material is blanket-type Side restraints are formed. Printed by the Ministry of Economic Affairs, the 4th Bureau of Industrial Finance and the Consumer Cooperative. 3. If a patent application is made, the second flash-type flash-type electronic erasable stylized read-only memory is manufactured. The thickness of the oxide film formed is 300 to 500 Angstroms. 4. The flash electronic erasable stylized read-only memory process method as described in item 1 of the scope of the patent application, wherein the spacer is formed by a blanket etching process using an oxide film and a halogenated film. The film is sequentially formed on the entire structure, and is double-layered with an oxide film and a halide film. 1 Q____ This paper size applies to China National Standard (CNS) A4 (210X297 male f) 478115 B8 C8 DS 丨6. The scope of patent application is formed. I 5_ The flash electronic erasable stylized read-only memory method as described in item 4 of the scope of patent application, wherein the thickness of the oxide film and the nitride film is 3 to 500 angstroms. . Printed by Ministry of Intellectual Property, Department of Consumer Affairs Cooperatives of the 4th Bureau. This paper size is applicable to China National Standard (CNS) A4 specification (210X297 public f '