TW466538B

TW466538B - Non volatile semiconductor device and its manufacturing process

Info

Publication number: TW466538B
Application number: TW087120127A
Authority: TW
Inventors: Yukihiro Oya
Original assignee: Sanyo Electric Co
Priority date: 1998-03-17
Filing date: 1998-12-04
Publication date: 2001-12-01
Also published as: KR100276542B1; KR19990076551A

Abstract

There is discloses a nonvolatile semiconductor memory device. The memory device is provided to suppress the generation of mask misalignment between a mask for forming an isolation film and that for forming a floating gate, and comprises: an isolation film 2 formed on a semiconductor substrate of one conductivity type; a floating gate 34 which is formed in an active region isolated by said isolation film so as to be disposed in a gap between adjacent isolation films and have a sharp angle portion on the top; a tunnel oxide film which covers said floating gate 34; a control gate 36 formed on said tunnel oxide film so as to comprise a region which overlaps said floating gate 34; a drain region 37 and a source region 38 of an opposite conductivity type, formed in a surface of the semiconductor substrate 1 adjacent to said floating gate 34 and the control gate 36.

Description

五、發明說明u) [發明的技術領域] 本發明係有關’於矽基板上形成元件分離膜及形成於該元件分離膜以外的活性領域’且配上於鄰近元件分離膜狹縫間之浮置閘極（floating gate)，及具有；介由覆蓋該浮置閘極的隧道氧化膜重疊於該浮置閘極上，形成之控制閘極的非揮發性半導體記憶裝置及其製造方法。 [習用技術] 記憶胞由單一電晶體所成，且能以電刷消除的非揮發清半導體記憶裝置，尤其為可程式ROM(EEPROM): Electrically Erasble and Programmable ROM)中，具有浮置閘極與控制閘極的2重閘極構造的電晶體之各記憶胞形成者。如上述2重閘極構造的電晶體時，即可加速浮置閘極沒領域側產生的熱電子（h 〇 t e i e c t r ο η)注入浮置閘極’進行數據寫入。亦可以由F-N傳導（Fowler~Nordheim tunnel ling)，由浮置閘極將電荷抽向控制閘極，以實施數據清除。第8圖為具有浮置閘極之非揮發性半導體記憶裝置的記憶胞部分之平面圖。而第9圖即為圖中χ2 — χ2線的剖面圖。該圖中，係表示控制閘極與浮置閛極並排配置的*** 閘極（spl i t gat e)式構造。在P型石夕基板1表面領域，係以L0C0S(Local Oxidation of Silicon)法選擇性地形成較厚LOCOS氧化膜的複數個詩箋狀元件分離膜2，區劃為元件領域。矽基板1 上’介由氧化膜3A，在近鄰的元件分離膜2配置跨設的浮V. Description of the Invention u) [Technical Field of the Invention] The present invention relates to the formation of an element separation film on a silicon substrate and an active field formed outside the element separation film, and is provided with a float between slits of adjacent element separation films A floating gate, and a non-volatile semiconductor memory device that controls the gate formed by overlapping a tunnel oxide film covering the floating gate on the floating gate and a manufacturing method thereof. [Conventional technology] The memory cell is made of a single transistor and can be erased by a brush. A non-volatile semiconductor memory device, especially a programmable ROM (EEPROM): Electrically Erasble and Programmable ROM. It has a floating gate and Formation of each memory cell of a transistor that controls the double-gate structure of the gate. In the case of the transistor with the double-gate structure described above, the hot electrons (h o t e i e c t r ο η) generated in the floating gate without the field side can be accelerated and injected into the floating gate ′ for data writing. It can also be conducted by F-N (Fowler ~ Nordheim tunnel ling), and the floating gate draws charge to the control gate to implement data erasure. Fig. 8 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having a floating gate. Fig. 9 is a cross-sectional view taken along the line χ2-χ2 in the figure. This figure shows a split gate (spl i t gat e) structure in which the control gate and the floating pole are arranged side by side. In the surface area of the P-type Shixi substrate 1, a plurality of poem-like element separation films 2 which are formed with a thick LOCOS oxide film by the LOC0S (Local Oxidation of Silicon) method are selectively divided into element areas. On the silicon substrate 1, a floating electrode is disposed across the element separation film 2 via an oxide film 3A.

第4頁 466538 五、發明說明（2) 置閘極4。該浮置閘極4係於每1記憶胞單獨配置。浮置開極4上的選擇氧化膜5係以選擇氧化法，於浮置問極4中央部形成為一厚膜’且於浮置閘極4端部成銳角狀。由此，可於清除數據動作時’於浮置閘極4端部易以產生集中電場。、配置有複數個浮置閘極4的矽基板丨上，對應於浮置問極4的每列’介由與上述氧化膜3A成一髋化的隨道氧化膜 3，配置控制閘極6。該控制閘極6係將一部分重疊於浮置開極4上’其餘部分即介著氧化膜3A ’配置成為$接^矽基板1 °該浮置閘極4及控制閘極6係配置成各近鄰列相互為面對面的方式。於上述控制閘極6間的基板領域及浮置閘極4間的基板領域’形成N型汲領域7及源領域8。汲領域7係於控制$極 6間’由元件分離膜2圍繞而成各自獨立，源領域8即連續於控制閘極6延伸的方向。由該浮置閘極4、控制問極6 '、汲領域7及源領域8等構成記憶胞電晶體。然後，於上述控制閘極6上’介由氧化膜9，與控制聞極6以交叉方向配置鋁配線1 〇。該鋁配線丨〇係經由接I觸孔" 1 1連接於汲領域7。然後，以各控制閘極6為字（w〇rd)元線’與控制閘極6平行延伸的源領域8為源線。而以連乾在汲領域7的鋁配線1 〇為位元線。如上述2重閘極構造的記憶胞電晶體時，依所注入罕置閘極4的電荷量將使源及間的〇 n電阻值變動。因此以選擇性地於浮置閘極4注入電荷’以變動特定記憶胞電Page 4 466538 V. Description of the invention (2) Set gate 4. The floating gate 4 is configured separately for each memory cell. The selective oxide film 5 on the floating open electrode 4 is a selective oxidation method. A thick film is formed at the central portion of the floating question electrode 4 and an acute angle is formed at the end of the floating gate electrode 4. Therefore, it is easy to generate a concentrated electric field at the end of the floating gate 4 when the data is cleared. 2. On a silicon substrate with a plurality of floating gates 4, a corresponding gate electrode 6 is arranged on each of the columns of the floating gates 4 via the accompanying oxide film 3 which forms a hip with the oxide film 3A. The control gate 6 is partially superimposed on the floating open electrode 4 'the rest is via the oxide film 3A' and is configured as a silicon substrate 1 ° The floating gate 4 and the control gate 6 are arranged in each The neighbor columns are face to face with each other. An N-type drain region 7 and a source region 8 are formed in the substrate region between the control gates 6 and the substrate region between the floating gates 4 described above. The drain field 7 is connected to the control electrode 6 and is separated by the element separation membrane 2 and the source field 8 is continuous to the direction in which the control gate 6 extends. The floating gate electrode 4, the control gate electrode 6 ', the drain region 7 and the source region 8 constitute a memory cell transistor. Then, an aluminum wiring 10 is arranged on the control gate electrode 6 in an intersecting direction with the control electrode 6 via an oxide film 9. The aluminum wiring is connected to the drain region 7 via a contact hole "1 1". Then, a source field 8 extending in parallel with each control gate 6 is a source line 8 with each control gate 6 as a word line. The aluminum wiring 10 connected to the drain region 7 is a bit line. In the case of the memory cell transistor having the double-gate structure described above, depending on the amount of charge injected into the rare gate 4, the source and the on-resistance value will vary. Therefore, to selectively inject a charge ’to the floating gate 4 to change a specific memory cell

3 1.0 26 4 6 65 3 8 五、發明說明（3) 晶體的ON電阻值，由此，可對應於所生各記憶胞電晶體動作特性差別數據。於上述非揮發生半導體記憶裝置的數據寫入、消除及讀出各動作’係以下述方式進行。於寫入動作，使控制間極6的電位為2V、汲領域7的電位為0.5V、源領域8的高電位為1 2 V。因於源領域8施加高電位’於源領域8及浮置問極4間的偶聯比，使浮置閘極4的電位提升至9V左右，產生於 >及領域7附近的熱電子，即向浮置閘極4側加速，經氧化膜3A注入洋置閉極4 ’以進行數據的寫入。於消除動作，使汲領域7及源領域8的電位為0V、控制閘極6為14V。因此，儲存於浮置閘極4内的電荷（電子），由浮置閘極4角部的銳角部，以F-N傳導突破上述隧道氧化膜3放出於控制閘極6，使數據消除。又於讀出動作，使控制閘極6電位為4 V、汲領域7為 2 V、源領域8為0 V。此時，於浮置閘極4注入電荷（電子）> 即使浮置閘極4的電位降低，不能於浮置閘極4下方形成通道，故無汲電流流過。相反地，若於浮置閘極4無電荷（電子）注入，即因浮置閘極4的電位提高，於浮置閘極4下方形成通道而有汲電流流過。茲將上述非揮發性半導體記憶裝置的製造方法說明如下：又於第10至15圖中， (a)為平面圖、（b)為A-A剖面圖、（c)為β_Β剖面圖。第10圖中，於矽基板1上，以LOCOS法形成元件分離膜3 1.0 26 4 6 65 3 8 V. Description of the invention (3) The ON resistance value of the crystal can correspond to the difference data of the operating characteristics of the memory cell crystals. The data writing, erasing, and reading operations in the non-volatile semiconductor memory device are performed in the following manner. In the write operation, the potential of the control electrode 6 was 2V, the potential of the drain region 7 was 0.5V, and the high potential of the source region 8 was 12V. Due to the high potential applied to source area 8 ', the coupling ratio between source area 8 and floating interrogator 4 raises the potential of floating gate 4 to about 9V, which is generated by > and thermionic electrons near area 7, That is, the floating gate 4 is accelerated, and the closed gate 4 ′ is injected through the oxide film 3A to write data. For the erasing operation, the potentials of the drain region 7 and the source region 8 are set to 0V, and the control gate 6 is set to 14V. Therefore, the charges (electrons) stored in the floating gate 4 pass through the F-N conduction through the sharp corners of the floating gate 4 to break through the tunnel oxide film 3 and are placed on the control gate 6 to eliminate the data. In the read operation, the potential of the control gate 6 is 4 V, the drain region 7 is 2 V, and the source region 8 is 0 V. At this time, the charge (electrons) is injected into the floating gate 4 > Even if the potential of the floating gate 4 decreases, a channel cannot be formed under the floating gate 4, so no sink current flows. Conversely, if there is no charge (electron) injection into the floating gate 4, that is because the potential of the floating gate 4 increases, a channel is formed under the floating gate 4 and a sink current flows. The manufacturing method of the above-mentioned nonvolatile semiconductor memory device is described below: Also in Figs. 10 to 15, (a) is a plan view, (b) is an A-A cross-sectional view, and (c) is a β_B cross-sectional view. In FIG. 10, an element separation film is formed on the silicon substrate 1 by the LOCOS method.

第6頁 3 10 2 6 6， 466538 五、發明說明U) 2 ^即如第10圖（b)所示，於上述矽基板1上形成墊氧化 21、墊多晶矽膜22，以具有開口部的矽氮化膜23為遮罩、，定由選擇或氧化形成元件分離膜2。唯墊多晶政膜2 2不 ’ 為必須’可予以省略。其次，如第11圖，去除上述墊氧化膜21、墊多晶 22。嗎由塾氧化形成閘氧化棋形成具有開口部的矽 '氮再如第12圖，於石夕基板1上， 3A，再於其上形成多晶矽膜24後化膜25。復如第1 3圖所示，以上述矽氮化膜25為遮罩，選擇性地氧化上述多晶矽膜24，以形成選擇氧化膜5。之後’如第14圖所示’去除上述矽氮化膜25後，以弯擇氧化膜5為遮罩钱刻多晶石夕膜24形成浮置閘極4。又如第15圖所示，於全面形成隧道氧化膜3後，形成由多晶矽膜及鎢矽化物所成的導電膜，圖案化後形成控制問極6。唯上述控制閘極6得以由多晶矽膜所成的單層报成。於是’形成如第8及9圖所示的源領域8及汲領域9，以形成非揮發成半導體記憶裝置的記憶胞。 [發明所欲解決的間題] 然而，如第16圖（第15圖（b)的一部擴大圖）所示，在覆蓋載置於元件分離膜2端部的浮置閘極4之控制閘極6形成角狀尖端（參照第1 6圖所示點線内的A )，於該部分產生電場的集中，使浮置閘極4與控制閘極6間的耐壓降低，而Page 6 3 10 2 6 6, 466538 V. Description of the invention U) 2 ^ That is, as shown in FIG. 10 (b), a pad oxide 21 and a pad polycrystalline silicon film 22 are formed on the silicon substrate 1 to have an opening portion. The silicon nitride film 23 is a mask, and the element separation film 2 is formed by selection or oxidation. Only the polycrystalline silicon film 2 2 is not necessary and can be omitted. Next, as shown in FIG. 11, the pad oxide film 21 and the pad polycrystal 22 are removed. The gate oxide is formed by osmium oxidation. Silicon is formed with openings. As shown in FIG. 12, polycrystalline silicon film 24 is formed on the stone substrate 1 and 3A is formed thereon. As shown in FIG. 13, the polycrystalline silicon film 24 is selectively oxidized by using the silicon nitride film 25 as a mask to form a selective oxide film 5. Thereafter, after the silicon nitride film 25 is removed as shown in FIG. 14, the polysilicon film 24 is engraved with the selective oxide film 5 as a mask to form a floating gate 4. As shown in FIG. 15, after the tunnel oxide film 3 is completely formed, a conductive film composed of a polycrystalline silicon film and tungsten silicide is formed, and a control electrode 6 is formed after patterning. Only the above-mentioned control gate 6 can be reported in a single layer made of a polycrystalline silicon film. Then, a source region 8 and a drain region 9 as shown in Figs. 8 and 9 are formed to form a memory cell which is not volatile into a semiconductor memory device. [Intermediate problem to be solved by the invention] However, as shown in FIG. 16 (an enlarged view of FIG. 15 (b)), the control of the floating gate 4 placed on the end of the element separation membrane 2 is covered. The gate 6 forms an angular tip (refer to A in the dotted line shown in FIG. 16), and a concentration of an electric field is generated in this part, so that the withstand voltage between the floating gate 4 and the control gate 6 is reduced, and

^ 65 3 8 五、發明說明（5) 容易發生所謂逆随道效果（reverse tunnling)不良之問題。又因浮置閘極4與元件分離膜2間要求有較高的定位精度’即於元件分離瞑形成用遮罩與浮置閘極形成遮罩間的遮罩偏差發生，將使於元件分離膜上不能重叠浮置間極4 的端部，或重疊較淺（參照第1 7圖）。此時’若如上述讀出動作時，浮置閘極4為寫入狀態 (有電子蓄積之狀態）下’即使在通道領域無汲電流流通 (讀出電流），仍然壓浮置閘極4之端部不重疊於元件分離膜2上或重疊很淺之通道領域將如第17圖所示，由源領威8 有流向汲領域7侧的洩漏電流（參照圖中之1 l )，致產生判定為消除狀態之讀出不良之問題。為因應上述現象，若擴大浮置閘極4尺寸，即如第8 _ 所示，因該近鄰浮置閘極間的間隔狹窄，該浮置閘極有速接的問題發生。因此，本發明係以提供一種為抑制起因於元件分離膜形成用遮罩與浮置閘極形成用遮罩間的遮罩偏差之洩潙電流的產生’同時’亦為抑制逆隧道（reverse tunne 1 ing) 不良的發生之非揮發半導體記憶裝置，及其製造方法為目的。 [發明的實施形態] 兹就本發明之非揮發性半導體記憶裝置的製造方法之一實施形態’參照圖面說明如後；唯與習用構成為同樣的構成部分，僅附註同一符號，省略該說明。^ 65 3 8 V. Description of the invention (5) The problem of the so-called reverse tunnling is prone to occur. Also, due to the high positioning accuracy required between the floating gate 4 and the element separation film 2, that is, the mask deviation between the mask for forming element separation and the formation of the mask for floating gate occurs, which will cause the separation of the element. The membrane must not overlap the ends of the floating poles 4 or overlap lightly (see Figure 17). At this time, 'if the floating gate 4 is in the writing state (state with electron accumulation) during the reading operation as described above', the floating gate 4 is still depressed even if no sink current flows (reading current) in the channel area. The channel area where the end does not overlap the element separation membrane 2 or overlaps very shallowly, as shown in Fig. 17, there is a leakage current flowing from the source 8 to the drain area 7 (refer to 1 l in the figure). A problem arises in that the readout is judged to be in the erased state. In order to cope with the above-mentioned phenomenon, if the size of the floating gate 4 is enlarged, that is, as shown in FIG. 8 _, because the interval between the adjacent floating gates is narrow, the problem of quick connection of the floating gates occurs. Therefore, the present invention is to provide a method of suppressing the generation of leakage current caused by the mask deviation between the mask for element separation film formation and the mask for floating gate formation. 1 ing) Non-volatile semiconductor memory devices where defects occur, and methods of manufacturing the same. [Embodiment of the invention] An embodiment of the method for manufacturing a nonvolatile semiconductor memory device according to the present invention is described below with reference to the drawings; the same constituent parts are used for common structures, and only the same symbols are attached, and the description is omitted. .

第8頁 4 6 65 3 8 五 '發明說明（6) 第1圖為具有浮置閘極的非揮發性半導體記憶裝置的的記憶胞部分平面圖°圖_表示，控制閘極係與浮置閘極並列配置的***閘極構造。在P型矽基板1表面領域，係以LOCOS (Local Oxidation of Silicon)法選擇性地形成較厚LOCOS氧化膜的複數個詩箋狀元件分離膜2，區劃為元件領域。該元件分離領域的寬度dl約為0.5至1.5 ，其鄰接元件分離領域所挾持之活性領域的寬度<52即約為〇.5至1,5μιη。於矽基板1上’介著閘氧化膜31，在近鄰元件分離膜2的間隔内，配置膜厚約1 5 0 0 的浮置閘極3 4。該浮置閘極3 4係以每1記憶胞獨立方式配置。浮置閘極3 4上之選擇氧化膜 3 5，即以選擇氧化法，於浮置閘極3 4之中央部形成較厚部分’以形成浮置閘極34上部的尖銳角部。由此，使於數據消除動作時’於浮置閘極3 4端部易以產生電場集中。配置有複數個浮置閘極4的矽基板1上，對應於浮置閘極34的每列，介著與上述閘氧化膜31成一體化的隧道氧化膜33，配置控制閘極36。該控制閘極36係將一部分重疊於浮置閘極34上，其餘部分即介由隧道氧化膜33，配置成為連接於矽基板1。該浮置閘極34及控制閘極36係配置成各近鄰列相互為面對面的方式，於上述控制閘極36間的基板領域及浮置閘極34間的基板領域，形成Ν型汲領域37及源領域38。汲領域Page 8 4 6 65 3 8 5 'Description of the invention (6) Figure 1 is a plan view of a memory cell portion of a non-volatile semiconductor memory device with a floating gate. Figure _ shows the control gate system and the floating gate. Split gate structure with poles arranged in parallel. In the surface area of the P-type silicon substrate 1, a plurality of poem-like element separation films 2 which are formed with a thick LOCOS oxide film by the LOCOS (Local Oxidation of Silicon) method are selectively divided into element areas. The width dl of the element separation area is approximately 0.5 to 1.5, and the width of the active area held by the adjacent element separation area < 52 is approximately 0.5 to 1,5 μm. On the silicon substrate 1 ', a gate oxide film 31 is interposed, and a floating gate electrode 34 having a film thickness of about 15 0 0 is arranged in the interval between the neighboring element separation films 2. The floating gates 3 and 4 are arranged independently for each memory cell. The selective oxide film 35 on the floating gate 34 is a thicker portion formed at the center of the floating gate 34 by the selective oxidation method to form a sharp corner portion on the upper side of the floating gate 34. This makes it easier to generate electric field concentration at the ends of the floating gates 34 during the data erasing operation. A control gate 36 is disposed on the silicon substrate 1 on which the plurality of floating gates 4 are arranged, corresponding to each row of the floating gates 34, through a tunnel oxide film 33 integrated with the gate oxide film 31 described above. The control gate 36 is partially superimposed on the floating gate 34, and the rest is connected to the silicon substrate 1 through the tunnel oxide film 33. The floating gate 34 and the control gate 36 are arranged in such a manner that adjacent columns face each other. In the substrate area between the control gate 36 and the substrate area between the floating gate 34, an N-type drain area 37 is formed. And source area 38. Draw field

第9頁 65 3 8 五 '發明說明（7) - 閘極36、汲領域37及源領域38等構成記憶胞電晶體。 . 然後’於上述控制閘極36上，介由氧化膜3 9，與控制 3 6以交又方向配置鋁配線4 0。該鋁配線4 0係經由接觸孔4】連接於汲領域37。然後，以各控制閘極36為字（word)元線，與控制閘極3 6平行延伸的源領域3 8為源線。而以連接在汲領域37的鋁配線40為位元線。 ' 茲將上述非揮發性半導體裝置之記憶胞的製造方法說 - 明如下：於第3至7圖中，（a)為平面圖、（b)aA_A剖面圖' (c )為B-B剖面圖人首先，於第3圖中，於矽基板1上’以L〇c〇s法形成元 · 件分離膜2。即如第3圖（b)所示，於上述矽基板1上形成閘氧化膜31、多晶梦膜32 ’以具有開口部的>5夕氮化膜23為遮罩’由選擇性氧化形成元件分離膜2 於該製程，多晶石夕膜32由矽氮化膜23露出領域氧化成為元件分離膜2，覆蓋於石夕氮化膜23下’不為氧化而殘留的領域，即形成為浮置閘極3 4。因此’該元件分離膜2與浮置閘極34係連續的形成’其界面係以自行整合（self-aligned)完成。其次’如第4圖所示，形成上述矽氮化膜23上未圖示的光阻（photo-resist)膜後，以該光阻膜為遮罩，將鄰接元件分離膜2間隔位置的碎氣化摸2 3鞋刻，以形成開口部 2 3 A。該開口部2 3 A下面的多晶矽膜3 2即於後面製程成為浮置閑極3 4 □ 續之，如第5圖所示，以矽氧化膜23為遮罩，將上述開口部2 3 A下方的碎晶s夕膜3 2予以選擇性氧化，以形成選Page 9 65 3 8 5 'Explanation of the invention (7)-The gate 36, the drain field 37 and the source field 38 constitute a memory cell transistor. Then, on the control gate 36, an aluminum wiring 40 is arranged in an alternating direction with the control 36 through the oxide film 39. The aluminum wiring 40 is connected to the drain region 37 through the contact hole 4]. Then, each control gate 36 is a word line, and a source area 38 extending parallel to the control gate 36 is a source line. The aluminum wiring 40 connected to the drain region 37 is a bit line. 'The following describes the manufacturing method of the memory cell of the above non-volatile semiconductor device-as follows: In Figures 3 to 7, (a) is a plan view, (b) aA_A section view' (c) is a BB section view. As shown in FIG. 3, the element separation film 2 is formed on the silicon substrate 1 by the Locos method. That is, as shown in FIG. 3 (b), a gate oxide film 31 and a polycrystalline dream film 32 are formed on the above-mentioned silicon substrate 1 'with the > 5th nitride film 23 having an opening as a mask' by selective oxidation Forming the element separation film 2 In this process, the polycrystalline silicon film 32 is oxidized into the element separation film 2 from the exposed area of the silicon nitride film 23, covering the area that is not left for oxidation under the stone nitride film 23, that is, formed 4 for floating gates. Therefore, 'the element separation membrane 2 and the floating gate 34 are continuously formed', and the interface is completed by self-aligning. Next, as shown in FIG. 4, after a photo-resist film (not shown) on the silicon nitride film 23 is formed, the photoresist film is used as a mask, and the adjacent element separation film 2 is broken at a spaced position. Vapor touch 2 3 shoe engraved to form an opening 2 3 A. The polycrystalline silicon film 32 under the opening 2 3 A becomes a floating idler 3 4 in the subsequent process. Continued, as shown in FIG. 5, the silicon oxide film 23 is used as a mask to cover the opening 2 3 A. The lower broken crystal s film 3 2 is selectively oxidized to form a selective layer.

第10頁 3 1 p 26 6 · ~ 4S6538 五 '發明說明（8) 擇氧化膜35。再次，如第6圖，去除上述矽氮化膜23後，以選擇氧化膜35為遮罩，蝕刻多晶矽膜32，於上部形成具有尖銳角部的浮置閘極34。由此’可如第6圖（a)所示，得於鄰接元件分離膜2間隔内配置浮置閘極3 4。又如第7圖’於全面形成隧道氧化膜33後，形成由多晶石夕膜及鎢矽化膜所成的導電膜，圖案化後形成控制閘極 36。上述控制36可由多晶石夕膜的單層膜所成。於是’如第1及第2圖所示，形成源領域38及汲領域 3 7 ’以形成非揮發性半導體記憶裝置的記憶胞。如上述說明’本發明係將元件分離膜2形成用多晶矽膜32(相當於習用技術的墊多晶矽膜3)，於形成元件分離膜2後’不予去除’係由後製程作為浮置閘極34形成膜使用。故可較習用技術在其製造的製程上簡略化。亦如第1及第7圖等所示，因浮置閘極34與元件分離膜 2係以自己整合方式形成。不需如習用浮置閘極4與元件分離膜2間的高精度定位作業。得以解消由於洩漏電流流動的讀出不足之問題。又因’本發明的構造無如習用技術（如第16圖）將元件分離膜2端部搭載於浮置閘極4上的構造，故無覆蓋該浮置問極4之控制閘極6成角狀尖端，於該部分發生電場集中，致使浮置閘極4與控制閘極6間的耐壓降低，亦玎解消易以發生所謂逆隧道（reverse tunneling)不良之發生。復因兀件分離膜2端部不為搭載於浮置閘極4上的構造，故得以Page 10 3 1 p 26 6 · ~ 4S6538 Five 'Explanation of the invention (8) Selective oxide film 35. Again, as shown in FIG. 6, after removing the silicon nitride film 23, the polycrystalline silicon film 32 is etched with the selective oxide film 35 as a mask, and a floating gate 34 having a sharp corner is formed on the upper portion. Therefore, as shown in FIG. 6 (a), a floating gate electrode 34 can be arranged in the interval between the adjacent element separation membranes 2. As shown in FIG. 7 ′, after the tunnel oxide film 33 is completely formed, a conductive film made of a polycrystalline silicon film and a tungsten silicide film is formed, and the control gate 36 is formed after patterning. The control 36 described above may be formed by a single-layer film of a polycrystalline stone film. Then, as shown in Figs. 1 and 2, a source region 38 and a drain region 37 are formed to form a memory cell of a nonvolatile semiconductor memory device. As explained above, the present invention uses the polycrystalline silicon film 32 for forming the element separation film 2 (equivalent to the pad polycrystalline silicon film 3 of the conventional technology). After the element separation film 2 is formed, it is not removed. 34 is used for film formation. Therefore, the manufacturing process can be simplified compared to conventional techniques. As shown in Figs. 1 and 7 and the like, the floating gate 34 and the element separation membrane 2 are formed by their own integration. It is not necessary to use the high-precision positioning operation between the floating gate electrode 4 and the component separation film 2 as usual. This solves the problem of insufficient reading due to the leakage current flow. Also, because the structure of the present invention is inferior to conventional technology (such as FIG. 16), the structure in which the end of the element separation membrane 2 is mounted on the floating gate 4 is not covered by the control gate 60% of the floating interrogation electrode 4. At the angular tip, electric field concentration occurs in this part, resulting in a reduction in the withstand voltage between the floating gate 4 and the control gate 6, and it is easy to dissolve and cause the occurrence of so-called reverse tunneling defects. Because the end of the element separation membrane 2 is not a structure mounted on the floating gate 4, it can be obtained

第頁一 ,63 S 46 65 3 8 五、發明說明（9) 平坦化。又於本發明的一實施形態係於多晶矽膜32上形成選擇氡化膜3 5，再以該選擇氧化膜3 5為遮罩，蝕刻該多晶胡媒 32以形成浮置閘極34，唯本發明不限於此。亦可適用於通常形成多晶矽膜後，將該多晶矽膜以微影技術圖案化，構成具有浮置閘極構成之非揮發性半導體記憶裝置。又於本實施形態，係以多晶矽膜構成浮置閘極，但得以單晶矽膜、非晶矽膜或該等積層膜構成之。 [發明的效果] 如依本發明，係將元件分離膜形成用多晶矽膜，於元件分離膜形成後，不予以去除，於後面製程作為浮置閘極形成膜使用，故較習用技術得以簡化製造工程。又因浮置閘極與元件分離膜係以自行整合對準方式形成，故不需如習用技術，於浮置閘極及元件分離膜間的高精度定位作業’即可解消因洩漏電流流動所引起的讀出不良之問題。復因，本發明的構造無如習用技術，將元件分離膜端部搭載於浮置閘極上的構造。故無覆蓋該浮置閘極之控制問極成角狀尖端，於該部分發生電場集中，致使浮置間極與控制閘極6間的耐壓降低問題，可解消易以發生所謂逆陡道不良之發生。復因元件分離獏端部不為搭載於沣極上的構造，得以平坦化。、子置間 [圖面的簡單說明] 第1圖為表示本發明之非揮發半導體記憶裝置的記憶Page I, 63 S 46 65 3 8 V. Description of the invention (9) Flattening. According to another embodiment of the present invention, a selective siliconized film 35 is formed on the polycrystalline silicon film 32, and then the selective oxide film 35 is used as a mask to etch the polycrystalline silicon medium 32 to form a floating gate 34. The invention is not limited to this. It can also be used to form a non-volatile semiconductor memory device with a floating gate structure after patterning the polycrystalline silicon film by lithographic technology after the polycrystalline silicon film is usually formed. In this embodiment, the floating gate is formed by a polycrystalline silicon film, but it may be formed by a single crystal silicon film, an amorphous silicon film, or such a laminated film. [Effects of the Invention] According to the present invention, the polycrystalline silicon film for element separation film formation is not removed after the element separation film is formed, and it is used as a floating gate formation film in the later process, so the manufacturing can be simplified compared to conventional techniques. engineering. Because the floating gate and the element separation membrane are formed by self-integration and alignment, there is no need to use conventional techniques for high-precision positioning operations between the floating gate and the element separation membrane. Problems caused by poor readout. For another reason, the structure of the present invention is inferior to the conventional technique in that the end of the element separation membrane is mounted on a floating gate. Therefore, there is no angled tip of the control gate electrode covering the floating gate electrode, and electric field concentration occurs in this part, resulting in a reduction in the withstand voltage between the floating gate electrode and the control gate electrode 6, which can be easily eliminated to cause the so-called reverse steep track Bad things happen. The structure that separates the end of the multiplication element is not mounted on the pole, and is flattened. 、子置间 [Brief description of the drawing] Fig. 1 shows the memory of the non-volatile semiconductor memory device of the present invention.

4 6 65 3 8 五、發明說明（ίο) 胞構造的平面圖。第2圖為第1圖中，XI-XI線的剖面圖。第3圖為表示本發明之非揮發性半導體記憶裝置之製造方法的第1圖。第4圖為表示本發明之非揮發性半導體記憶裝置之製造方法的第2圖。第5圖為表示本發明之非揮發性半導體記憶裝置之製造方法的第3圖。第6圖為表示本發明之非揮發性半導體記憶裝置之製造方法的第4圖。第7圖為表示本發明之非揮發性半導體記憶裝置之製造方法的第5圖。第8圖為表示習用非揮發性半導體記憶裝置的記憶胞構造的平面圖。第9圖為第8圖中，X2-X2線的剖面圖。第10圖為表示習用非揮發性半導體記憶裝置之製造方法的第1圖= 第11圖為表示習用非揮發性半導體記憶裝置之製造方法的第2圖。第12圖為表示習用非揮發性半導體記憶裝置之製造方法的第3圖。第1 3圖為表示習用非揮發性半導體記憶裝置之製造方法的第4圖。第1 4圖為表示習用非揮發性半導體記憶裝置之製造方4 6 65 3 8 V. Description of the invention (ίο) Plan view of cell structure. Fig. 2 is a sectional view taken on line XI-XI in Fig. 1. Fig. 3 is a first view showing a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. Fig. 4 is a second view showing a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. Fig. 5 is a third view showing a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. Fig. 6 is a fourth view showing a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. Fig. 7 is a fifth view showing a method for manufacturing a nonvolatile semiconductor memory device according to the present invention. Fig. 8 is a plan view showing a memory cell structure of a conventional nonvolatile semiconductor memory device. Fig. 9 is a sectional view taken along line X2-X2 in Fig. 8. Fig. 10 is a first diagram showing a manufacturing method of a conventional non-volatile semiconductor memory device. Fig. 11 is a second diagram showing a manufacturing method of a conventional non-volatile semiconductor memory device. Fig. 12 is a third view showing a manufacturing method of a conventional nonvolatile semiconductor memory device. Fig. 13 is a fourth diagram showing a manufacturing method of a conventional nonvolatile semiconductor memory device. Figure 14 shows the manufacturing method of a conventional non-volatile semiconductor memory device.

第13頁 1 466538 五、發明說明（11) 法的第5圖。第1 5圖為表示習用非揮發性半導體記憶裝置之製造方法的第6圖。第1 6圖為說明習用問題的說明圖。第1 7圖為說明習用問題的說明圖。 [符號說明 ] 1 矽基板 2 元件分離膜 3 隧道氧化膜 4 浮置閘極 5 選擇氧化膜 6 控制閘極 7 汲領域 8 源領域 9 氧化膜 10 鋁配線 11 接觸孔 21 墊氧化膜 22 墊多晶矽膜 23 矽氮化膜 23A 開 π 部 24 多晶矽膜 25 矽氮化膜 31 閘氧化膜 32 多晶矽膜 \ 33 隧道氧化膜 34 浮置閘極 35 選擇氧化膜 36 控制閘極 37 汲領域 38 源領域 39 氧化膜 40 鋁配線 41 接觸孔Page 13 1 466538 V. Illustration 5 of the method of the invention (11). Fig. 15 is a diagram showing a conventional method for manufacturing a nonvolatile semiconductor memory device. Fig. 16 is an explanatory diagram for explaining a conventional problem. Fig. 17 is an explanatory diagram for explaining a conventional problem. [Symbol description] 1 Silicon substrate 2 Element separation film 3 Tunnel oxide film 4 Floating gate 5 Select oxide film 6 Control gate 7 Drain area 8 Source area 9 Oxide film 10 Aluminum wiring 11 Contact hole 21 Pad oxide film 22 Pad polycrystalline silicon Film 23 silicon nitride film 23A open π part 24 polycrystalline silicon film 25 silicon nitride film 31 gate oxide film 32 polycrystalline silicon film \ 33 tunnel oxide film 34 floating gate 35 selection oxide film 36 control gate 37 drain field 38 source field 39 Oxide film 40 Aluminum wiring 41 Contact hole

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Claims

-538 ——— 六、申請專利範圍 I —種非揮發性半導體記憶裝置具備：形成於一導電型矽基板上的元件分離膜；與上述元件分離膜端部一致，自行整合地形成於上述元件分離犋分離的活性領域内，且配置在鄰接元件分離膜狹縫間之浮動閘極；覆蓋上述浮置閘極的隧道氧化膜；介著上述隧道氧化膜，形成為於上述浮置閘極上具重疊領域的控制閘極，以及形成於鄰接上述浮置閘極，及上述控制閘極之上述半導體基板表面的逆導電型擴散領域者。 2·—種非揮發性半導體記憶裝置，具備：形成於一導電型矽基板上的元件分離膜；與上述元件分離膜端部一致，自行整合地形成於上述元件分離膜的活性領域内，且配置在鄰接元件分離膜狹缝間之上部，具有尖銳角部之浮置閘極；覆蓋上述浮置閉極的隧道氧化膜；介著上述隧道氧化膜，形成為於上述浮置閘極上具重疊領域的控制閛極，以及形成於鄰接上述浮置閘極，及上述半導體基板表面的逆導電型擴散領域者》 3 _ —種非揮發性半導體記憶裝置的製造方法，係具有：形成於一導電型矽基板上的元件分離膜；與上述元件分離膜端部一致，自行整合地形成於上述元件分離膜分離的活性領域内，且配置在鄰接元件分離膜狹縫間之浮置閘極；覆蓋上述浮置閘極的隧道氧化膜；-538 ——— VI. Patent Application Scope I — A non-volatile semiconductor memory device is provided with: an element separation film formed on a conductive silicon substrate; the end of the element separation film is consistent with the above, and it is formed on the above element by itself In the active field of separation and separation, a floating gate is arranged between the slits of the separation membranes of adjacent elements; a tunnel oxide film covering the floating gate; and the tunnel oxide film is formed on the floating gate through the tunnel oxide film. Control gates in overlapping areas, and reverse conduction type diffusion fields formed on the surface of the semiconductor substrate adjacent to the floating gate and the control gate. 2 · A non-volatile semiconductor memory device, comprising: an element separation membrane formed on a conductive silicon substrate; consistent with the end of the above-mentioned element separation membrane, formed in a self-integrated manner in the active area of the above-mentioned element separation membrane, and A floating gate electrode having an acute angle portion disposed above the slit between adjacent element separation films; a tunnel oxide film covering the floating closed electrode; formed through the tunnel oxide film to overlap the floating gate electrode Control electrodes in the field, and those formed in the field of reverse conductive diffusion adjacent to the floating gate and on the surface of the semiconductor substrate "3 _-A method for manufacturing a non-volatile semiconductor memory device, comprising: formed on a conductive Element separation membrane on a silicon substrate; consistent with the end of the above-mentioned element separation membrane, it is self-integrated and formed in the active area of the above-mentioned element separation membrane separation, and the floating gate is arranged between the slits of adjacent element separation membranes; covering The tunnel oxide film of the floating gate;

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介著上述随道氧# 、孔化犋，形成為於上述浮置閘極上具重且領域的控制閉極’以及，形成於鄰接上述浮置閘極及上述控制開極之上述半導體基板表面的逆導電型擴散領域之非揮發性半導體記憶裝置的製造方法，該製造方法之特徵為將上.述7C件分離膜及浮置閘極，以同一膜層形成者0 4，如申清專利範圍第3項的非揮發性半導體記憶裝置的製造方法’該記憶裝置製造方法中的上述同一膜層，係為多晶石夕膜’單晶矽膜，非晶矽膜或為這些膜之積層膜者。 5，一種非揮發性半導體記憶裝置的製造方法，係具有：形成於一導電型矽基板上的元件分離膜；與上述儿件分離膜端部一致’自行整合地形成於上述元件分離膜分離的活性領域内，且配置在鄰接元件分離狹缝間之浮置閘極；覆蓋上述浮置閘極的隧道氧化膜；介由上述隧道氧化膜，形成為於上述浮置閘極上具重疊領域的控制閘極，以及，形成於鄰接上述浮置^ ^上述控制閘極之上述半導體基板表面的逆導電^ 域之非揮發性半導體記憶裝置的製造方 1擴散領法，具襟：方去’此製造方後於上述矽基板上形成閘氧化膜及導曾於上述導電膜上形成具有第1開口部之石夕以該矽氮化膜為遮罩，以LOCOS法，此氮化膜將上述導電棋Via the above-mentioned oxygen channel # and the hole-shaped plutonium, formed as a heavy and field-controlled closed pole on the floating gate, and formed on the surface of the semiconductor substrate adjacent to the floating gate and the controlled open electrode. A method for manufacturing a non-volatile semiconductor memory device in the field of reverse conductivity type diffusion. The manufacturing method is characterized by the above-mentioned 7C separation membrane and floating gate, formed by the same film layer, as described in the patent scope. The third method of manufacturing a nonvolatile semiconductor memory device. The same film layer in the memory device manufacturing method is a polycrystalline silicon film, a single crystal silicon film, an amorphous silicon film, or a laminated film of these films. By. 5. A method for manufacturing a non-volatile semiconductor memory device, comprising: an element separation membrane formed on a conductive silicon substrate; and the same as the ends of the above-mentioned children's separation membrane; In the active area, a floating gate disposed between the separation slits of adjacent elements; a tunnel oxide film covering the floating gate; through the tunnel oxide film, formed to control the overlapping area on the floating gate Gate electrode, and a non-volatile semiconductor memory device formed on the surface of the semiconductor substrate adjacent to the above-mentioned floating gate ^ ^ control semiconductor gate in a non-volatile semiconductor memory device. After that, a gate oxide film is formed on the silicon substrate, and a stone having a first opening is formed on the conductive film. The silicon nitride film is used as a mask, and the nitride film is used to form the conductive film.

466538 六'申請專利範圍予以選擇性氧化，以形成元件分離膜的製程；於上述矽氮化膜形成光阻膜後，以該光阻膜作為遮罩，去除鄰接元件分離膜狹縫上的上述矽氮化膜，於該矽氮化膜形成第2開口部的製程；於去除上述光阻膜後，以上述矽氮化膜為遮罩，將上述第2開口部下方的導電膜予以選擇性氧化，在該導電膜上形成選擇氧化膜的製程；去除上述矽氮化膜後，以上述選擇氧化膜為遮罩，由異向性蝕刻法，在上述導電膜上部形成具有尖銳角部的浮置閘極的製程；以覆蓋上述浮置閘極及上述選擇氧化膜，形成隧道氧化膜的製程，以及介著上述隧道氧化膜於浮置閘極上形成具有重疊領域的控制閘極的製程者。 6.如申請專利範圍第5項的非揮發性半導體記憶裝置的製造方法，該製造方法中之上述導電膜，係為多晶矽膜、單晶矽膜、非晶矽膜或為該物之積層膜者。466538 Six 'patent application process for selective oxidation to form a device separation film; after the photoresist film is formed on the above silicon nitride film, the photoresist film is used as a mask to remove the above on the slits adjacent to the device separation film A silicon nitride film, a process for forming a second opening portion on the silicon nitride film; after removing the photoresist film, using the silicon nitride film as a mask, selectively selecting a conductive film under the second opening portion Oxidizing to form a selective oxide film on the conductive film; after removing the silicon nitride film, using the selective oxide film as a mask, an anisotropic etching method is used to form a floating layer with sharp corners on the conductive film; A process for setting a gate; a process for covering the floating gate and the selective oxide film to form a tunnel oxide film, and a process for forming a control gate with overlapping areas on the floating gate through the tunnel oxide film. 6. The method for manufacturing a non-volatile semiconductor memory device according to item 5 of the scope of patent application, wherein the conductive film in the manufacturing method is a polycrystalline silicon film, a single crystal silicon film, an amorphous silicon film, or a laminated film of the same By.

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