TW463270B - Electronic device without the requirement of bonding - Google Patents
Electronic device without the requirement of bonding Download PDFInfo
- Publication number
- TW463270B TW463270B TW89103996A TW89103996A TW463270B TW 463270 B TW463270 B TW 463270B TW 89103996 A TW89103996 A TW 89103996A TW 89103996 A TW89103996 A TW 89103996A TW 463270 B TW463270 B TW 463270B
- Authority
- TW
- Taiwan
- Prior art keywords
- line
- electrode
- crystal
- electronic device
- production
- Prior art date
Links
Landscapes
- Wire Bonding (AREA)
Abstract
Description
463270 五、發明說明(1) 《發明背景》 請參閱第一圖之(a )、第一圖之(b )所示,其係 為多晶粒模組封裝器件之結構示意圖,一般現在所有的封 裝(P a c k a g e )範疇皆可稱為"S I P 〃 (SIN GLE IN LINE PACKAGE),即單排直 插封裝,為封裝基片由電聯接之端子接頭齊平接線端之多 個接線端;其所佔用的封裝基片之使用面積非常龐大; 又,一般絕緣基ϋ必須利用一引線框架,來裝配到該封裝 基片上,故生產時所耗費的成本較高、時間較長,非常不 具經濟效益; 又,電子工程發展之初,一切製作過程,皆須經由人 手所做,然而,一些内部結構精密的電子零件,卻常因焊 接的時間過長,而導致整個零件於完成之初即以燒毀,也 因此,方有前人成功的開發出自動焊接裝置,該自動焊接 裝置包括了對於各個器件的封裝有不需壓焊、塑封成形、 及引線框架等優點,再加上各個電極同時形成聯接,不僅 有利於小型化,更可減輕產品重量、提升效能,並降低生 產成本,因該自動焊接裝置有上述種種優點,而被各高科 技類股應用於產品製造; 但是,以自動焊接裝置進行製造基板的工作,卻必須 於封裝前先行將零件於基板之上完成定位,如欲完成此一 動作,則必使用可透視之基板,或利用紅外線、顯微鏡之 類的光學設備達成目的;然而,採用如紅外線、顯微鏡等463270 V. Description of the invention (1) "Background of the invention" Please refer to the first diagram (a) and (b) of the first diagram, which are schematic diagrams of the structure of a multi-die module package device. The package (P ackage) category can be called " SIP 〃 (SIN GLE IN LINE PACKAGE), which is a single-row in-line package, which is a package of multiple terminals that are flush-connected to each other by terminal terminals that are electrically connected; The occupied area of the packaging substrate is very large. In addition, a general insulating substrate must be assembled to the packaging substrate by using a lead frame. Therefore, the cost of production is high, the time is long, and it is not economical. ; Also, at the beginning of the development of electronic engineering, all manufacturing processes must be done by human hands. However, some electronic components with precise internal structures are often burned because of the long welding time, which causes the entire part to be burned at the beginning. Therefore, Fang You's predecessors successfully developed an automatic welding device. The automatic welding device includes the package for each device without pressure welding, plastic molding, and lead frame. Points, coupled with the simultaneous formation of each electrode, not only facilitates miniaturization, but also reduces product weight, improves efficiency, and reduces production costs. Because this automatic welding device has the above-mentioned advantages, it is used by various high-tech stocks. Product manufacturing; however, to manufacture substrates with an automatic soldering device, you must complete the positioning of the parts on the substrate before packaging. If you want to complete this action, you must use a substrate that can see through, or use infrared, microscope Optical equipment such as
4 6 3 2 7 Ο 五、發明說明ί2) 光學設備進行對位,其所耗費對位技術所耗費之成本過高 ,造成在實際運用上俾不可行; 因此如何提供一種可解決上述問題之不需打線之電子 器件是為激發本案發明人之發明動機。 《發明目的》 有鑑於此,本案發明人乃以其本身所具備之技術、經 驗及專業素養,在多次之試作與改良,終使本發明得以誕 生,其目的是在於提供一種不需打線之電子器件,其主要 係為將電子元件或器件之接腳簡化時,同時設計標線,使 電極直接與印刷線路板進行接合封裝時,能正確無誤地安 裝於基片上所指定位置。 又,本發明完全不使用如紅外線、顯微鏡等高價位的 特殊設備; 另,本發明實現可以完全適應常規的配件製造工程, 且其所增加的成本微乎其微,幾乎可忽略不計;因此,本 發明可利用於打大哥大、攝影機、錄放影機、電腦等多種 類之電子產品。 《技術内容、特點及功效》 為使 貴審查委員方便了解本創作之内容,及所能達 成之功效、茲配合圖式列舉一具體實施例,詳細介紹說明 如下 : 圖號說明4 6 3 2 7 〇 V. Description of the invention 2) The alignment of optical equipment, the cost of the alignment technology is too high, making it practically impossible; therefore, how to provide a solution that can solve the above problems The electronic device to be wired is to motivate the inventor of the present invention. "Objective of the Invention" In view of this, the inventor of this case uses his own technology, experience, and professional qualities to make and improve the invention through several trials and improvements. The purpose of this invention is to provide an Electronic devices are mainly designed to simplify the pins of electronic components or devices, and at the same time design the marking lines so that when the electrodes are directly packaged with the printed circuit board, they can be accurately installed at the specified position on the substrate. In addition, the present invention does not use high-priced special equipment such as infrared rays and microscopes at all. In addition, the realization of the present invention can completely adapt to the conventional parts manufacturing process, and the added cost is negligible, which is almost negligible; therefore, the present invention can Used for playing various electronic products such as big brother, camera, video player, computer, etc. "Technical Content, Features and Effects" To make it easy for your reviewers to understand the content of this creation, and the effects that can be achieved, a specific embodiment is listed in conjunction with the drawings. The detailed description is as follows:
第5頁 463270 五、 發明說明(3) 1 •.晶粒 2 • ·電極 3 • •玻璃掩膜板 4 * *生產用之晶粒 5 • •分割線 6 ••印刷線路板 rj • •接線柱 8 • *定位點 1~I CM 一—i CO X X γ γ 線線線線 標標標標 明之 說圖 示 一 圖第 圖 意 示 面 剖 構 結 之 件 器 裝 封 組 模 粒 晶 多 係 圖 意 示 視 俯 構 結 之 件 器 裝 封 組 模 粒 晶 多 係 Ν)/ b /(\ 之 圖 - 第 圖圖 意意 示示 面視 剖仰 粒粒 晶晶 之之 明明 發發 本本 係係 \ly 、^V a b /(\ Γ\ 之之 圖圖 二二 第第Page 5 463270 V. Description of the invention (3) 1 • Die 2 • • Electrode 3 • • Glass mask 4 * * Die for production 5 • • Dividing line 6 • • Printed circuit board rj • • Wiring Column 8 • * Positioning point 1 ~ I CM a—i CO XX γ γ line line line line mark labeling indication icon picture one picture figure diagram surface plane structure assembly device packing group mold grain crystal multiple system The figure shows the structure of the packaging device of the top-down structure. The figure of the grain crystals is N) / b / (\-The figure shows the face of the hair crystals. \ ly and ^ V ab / (\ Γ \
_—< 蒼一 S 意 C示 〃 之 p \lry ο 1 「^ 圖s G 意4 A 示面K 視側C 俯單A 粒的P 晶粒 之晶E 明在N 發極I 本電L 係之 }明” C發I C本 之係E 圖圖 L 二三G 第第N_— <Cangyi S means C shows 〃 p \ lry ο 1 "^ Figure s G means 4 A shows surface K view side C down single A grain P crystal grains E Ming N N pole I L 系 的} 明 ”C issued IC books E diagram L two three G number N
第6頁 4 6 327 0 五、發明說明(4) 第四圖係本發明製作方法之示意圖。 第五圖係本發明之定位狀態圖。 第六圖係本發明之實施例。 第七圖係本發明之另一實施例。 粒拉 晶升 之提 明2 發極 本電 為之 係1 其粒 , 晶 示該 所將 3係 a 明 C發 之本 圖中 二其 第 , 閒圖 參意 請示 面 1MJ 咅Page 6 4 6 327 0 V. Description of the invention (4) The fourth diagram is a schematic diagram of the manufacturing method of the present invention. The fifth figure is a positioning state diagram of the present invention. The sixth diagram is an embodiment of the present invention. The seventh diagram is another embodiment of the present invention. The pull of the crystal and the rise of the crystal are shown in the figure. 2 The pole is the electric power. The grain is shown in the figure. The crystal shows the 3 series of the light in the picture. The second is the first in the picture.
Tt- 該晶 , 亥 41° 知在 得2 照極 對電 面 C表 (1 之粒 圖晶 二該 第示 與表 }線 b虛 C的 之中 圖 二 C 第ί 由之 並圖 ,二 高第 中 ~ 其,__一 ’ Υ 示線 所標 Λί/ ' C 2 (X 之~ 一畜一 ΊΧ 二 X 第線 第標 閱排 參編 再所 請方 ,上 置1 位粒 的晶 面該 背於 1位 粒該 X的 線面 標表 該1 ,粒 線晶 割該 分了 確位 正定 之的 2確 極正 電2 成Υ 形? 面 Τ—Ί 表Υ 1線 粒標。 晶、置 該CX1位 為X 2 2 、極 Υ 1 電 IX 粒Ε 晶Ν 在 >—_ 2 L 極 電Ν 之I 明 發Ε 本L 為G 係Ν 其I ,S 示C 所〃 圖Ρ 三I 第S 閱々 參面 請惻 η6- 的 線2 害X 分、 的 '—t 2 X 極線 電標 部用。 内採題 示,問 表知何 此可任 ,述生 圖上產 意由會 示,不 之2都 )Y 2 Ε ~ Y G 1 、 A Υ 1 K , Y C 1線 A X標 P為, 完晶後 片之, 兩用腳 用產刻 使生光 係該之 成又光 形,感 之3線 線板外 標膜紫 該掩於 中璃用 其玻使 ,之可 示確其 所準, 圖位布 四對條 第互光 閱相予 象\ 且面 請同兩 相4 全粒Tt- the crystal, oh 41 ° knows that there are 2 photoelectrodes on the surface of the C table (a grain diagram of the second crystal and the second line of the first and the table) line b virtual C of the second and the second from the figure, two Gao Dizhong ~ Its, __ 一 '示 indicates the line labeled Λί /' C 2 (X 之 ~ One animal, one Ί × 二 X line, the second line of the editorial parameters and then ask the party, on top of the 1 grain The line facing away from the 1 grain and the X line marks the 1 and the grain line cuts the 2 positive poles 2 which are positively positioned to form the shape? The surface T—Ί table 1 shows the mitochondrial mark. Crystal, set the CX1 position to X 2 2, pole Υ 1 electric IX grain Ε crystal N at >-2 L pole electric Ν I Mingfa EI This L is G series N and I, S shows C Please refer to the reference surface of the three-dimensional and three-dimensional reference points. Please use η6-'s line 2 to damage X points, and to use the '—t 2 X polar line electrical standard. For internal questions, ask the table to know how to do this. The production intention is indicated by the meeting, but not both) Y 2 Ε ~ YG 1, A Υ 1 K, YC 1 line AX marked P is, after the crystal is finished, the dual-use feet use the production engraving to make the light generation. It is also light-shaped, and the external standard film of the 3-wire wire board should be covered by Zhongli with its glass, May be shown by determining its registration, FIG four pairs of bits cloth reading light with respect to the cross-like \ and make surface 4 with two-phase full grain
第7頁 4 6 327 0 五、發明說明(5) 將該生產用之晶粗4之電 膜板3之間’採用兩面對 的位置,俾使該破璃掩膜 晶粒4上之電極正確對位 曝光,俾將該分割線5轉 經過顯影,烘培並進行刻 定的晶粒上方定位圖形, 請參閱第六圖所示, 晶粒部分的示意圖,其中 7 ,該矩形為定位點8 , 為與(請再參閱第五圖所 ’相互對準定位,以確保 刷線路板6所指定位置。 極面朝上,並***令土 μ , 玄兩片玻璃掩 =置,調整該生產用之晶粒4 板3上之分割線5與該生產用之 ,再從上下兩面同時進行紫外線 尸至該生產用之晶粒4上,最後 Ϊ J如第五圖所示)俾形成穩 進而使本發明得以完成。 其係為印刷線路板6中用於連接 數個黑點為與晶粒連接的接線柱 進而形成關鍵定位圖形,其作用 示)晶粒1上所形成的分割線5 該晶粒1能正確無誤地安裝於印 ,參閱第七圖所示,其係為各種可能的對位用圖形的 組合實施例’透過這些圖形可知,對位圖形還不只一種, ^過組合與基板配線的對應只要不會造成配線的混亂,俾 可對對位圖形進行任意變化組合;即使用同樣的晶粒構成 不同功能的多晶粒模組封裝器件的製作情況下,基板上的 配線有各種各樣的對應變化,然而本發明只要簡單地調整 基板上的關鍵對位圖形位置,俾可正確地形成晶粒與基板 的聯接。Page 7 4 6 327 0 V. Description of the invention (5) Use the two facing positions between the electric film plate 3 of the crystal grain 4 for production, and make the electrode on the glass mask grain 4 Correctly position the exposure, and then turn the dividing line 5 through development, bake, and engraving the positioning pattern above the grain. Refer to the sixth diagram, a schematic diagram of the grain part, of which 7, the rectangle is the positioning point 8. For mutual alignment with (Please refer to the fifth figure), to ensure that the designated position of the circuit board 6 is brushed. The pole is facing up, and the two glass masks are placed to adjust the production. The grains 4 used on the plate 3 and the production line, and then the ultraviolet ray from the upper and lower sides at the same time to the grains 4 for production, and finally (J as shown in the fifth figure), the formation is stable and further The present invention has been completed. It is used to connect a number of black dots in the printed circuit board 6 to connect the terminals connected to the crystal grains to form a key positioning pattern. Its function is shown.) The dividing line 5 formed on the crystal grain 1 can be correct. The ground is mounted on the printed board, as shown in the seventh figure, which is a combination of various possible alignment patterns. According to these graphs, it can be seen that there are more than one alignment patterns. As a result of wiring confusion, the alignment pattern can be arbitrarily changed and combined; that is, in the case of manufacturing a multi-die module package device with different functions using the same die, the wiring on the substrate has various corresponding changes. However, according to the present invention, as long as the position of the key alignment pattern on the substrate is simply adjusted, the connection between the die and the substrate can be correctly formed.
第8頁 4 6 327 0 五、發明說明(6) 為使本發明更加顯現出其進步性與實用性,茲將其優 點列舉如下: 1 、絕緣基片可不需要用到引線框架直接裝配到封裝 基片上,故使成本大幅下降、且重量減輕。 2 、與聯接的基板上的圖形配線變化具有極大的可適 應性。 3 、縮小體積之功效。 4 、極高的實用價值。 5 、降低製造成本。 6 、使本發明易於大量生產、生產周期縮短。 7 、具產業利用價值。 以上所述,僅係本發明之較佳實施例而已,舉凡利用 本發明上述之技術及方法所做之變化,均應包含於發明之 權利範圍。 綜上所述,本發明誠已符合發明專利之申請要件,爰 依法提出申請,祈請 鈞局審查委員明鑑,並賜予本創作Page 8 4 6 327 0 V. Description of the invention (6) In order to make the present invention show its progress and practicability, the advantages are listed as follows: 1. The insulating substrate can be directly assembled to the package without using a lead frame. On the substrate, the cost is greatly reduced, and the weight is reduced. 2. The pattern wiring on the connected substrate has great adaptability. 3, the effect of reducing volume. 4. High practical value. 5. Reduce manufacturing costs. 6. Make the invention easy for mass production and shorten the production cycle. 7. Industrial use value. The above descriptions are merely preferred embodiments of the present invention. For example, any changes made by using the above-mentioned technology and method of the present invention should be included in the scope of rights of the invention. To sum up, the present invention has already met the application requirements of the invention patent. 爰 Submit an application in accordance with the law, and ask the Commissioner of the Bureau of Examinations for a clear reference and give this creation
第9頁 463270Page 9 463270
第ίο頁Page ίο
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW89103996A TW463270B (en) | 2000-03-06 | 2000-03-06 | Electronic device without the requirement of bonding |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW89103996A TW463270B (en) | 2000-03-06 | 2000-03-06 | Electronic device without the requirement of bonding |
Publications (1)
Publication Number | Publication Date |
---|---|
TW463270B true TW463270B (en) | 2001-11-11 |
Family
ID=21658991
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW89103996A TW463270B (en) | 2000-03-06 | 2000-03-06 | Electronic device without the requirement of bonding |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW463270B (en) |
-
2000
- 2000-03-06 TW TW89103996A patent/TW463270B/en not_active IP Right Cessation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7071574B1 (en) | Semiconductor device and its wiring method | |
TWI270329B (en) | Method for fabricating conducting bump structures of circuit board | |
TWI240979B (en) | Bumping process | |
TWI314774B (en) | Semiconductor package and fabrication method thereof | |
TW538660B (en) | Method for making an electric circuit device | |
TW421980B (en) | Electronic component device, its manufacturing process, and collective circuits | |
TW200903588A (en) | Align mark, semiconductor chip including the same, semiconductor package including the chip and methods of fabricating the same | |
CN100468714C (en) | Substrate for forming semiconductor element and manufacturing method of the semiconductor element | |
CN108807446A (en) | A kind of encapsulating structure and packaging method of optical finger print chip | |
TW201001665A (en) | Circuit substrate having circuit wire formed of conductive polarization particles, method of manufacturing the circuit substrate and semiconductor package having the circuit wire | |
TW200411891A (en) | High density multi-chip module structure and manufacturing method thereof | |
TWI283056B (en) | Circuit board and package structure thereof | |
CN107403785A (en) | Electronic package and manufacturing method thereof | |
TW463270B (en) | Electronic device without the requirement of bonding | |
TWI251911B (en) | Test vehicle ball grid array package | |
TWI248653B (en) | Method of fabricating wafer level package | |
TWI307613B (en) | Circuit board formed conductor structure method for fabrication | |
CN104810339B (en) | Package substrate and method for fabricating the same, and semiconductor package and method for fabricating the same | |
TW201205721A (en) | Integrated circuit packaging system with rounded interconnect and method of manufacture thereof | |
TW201101446A (en) | Leadframe and method for manufacturing the same | |
CN104299959B (en) | A test structure for a flip chip, the flip chip and a manufacturing method thereof | |
TW200522329A (en) | Method of mounting wafer on printed wiring substrate | |
TW586195B (en) | Packaging method of semiconductor dies and the product | |
JP2004349611A (en) | Semiconductor substrate, method for manufacturing the semiconductor substrate and method for manufacturing semiconductor device | |
CN104112674B (en) | Method for manufacturing semiconductor package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GD4A | Issue of patent certificate for granted invention patent | ||
MM4A | Annulment or lapse of patent due to non-payment of fees |