TW201101446A - Leadframe and method for manufacturing the same - Google Patents

Leadframe and method for manufacturing the same Download PDF

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Publication number
TW201101446A
TW201101446A TW099117024A TW99117024A TW201101446A TW 201101446 A TW201101446 A TW 201101446A TW 099117024 A TW099117024 A TW 099117024A TW 99117024 A TW99117024 A TW 99117024A TW 201101446 A TW201101446 A TW 201101446A
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TW
Taiwan
Prior art keywords
lead frame
lead
semiconductor wafer
substrate
region
Prior art date
Application number
TW099117024A
Other languages
Chinese (zh)
Other versions
TWI419289B (en
Inventor
Sai-Ran Eom
Hyung-Eui Lee
Chung-Sik Park
Hyun-A Chun
Hye-Sun Yoon
Original Assignee
Lg Innotek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020090046267A external-priority patent/KR20100127924A/en
Priority claimed from KR1020090046397A external-priority patent/KR20100128004A/en
Application filed by Lg Innotek Co Ltd filed Critical Lg Innotek Co Ltd
Publication of TW201101446A publication Critical patent/TW201101446A/en
Application granted granted Critical
Publication of TWI419289B publication Critical patent/TWI419289B/en

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
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    • H01L23/49582—Metallic layers on lead frames
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
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  • Lead Frames For Integrated Circuits (AREA)

Abstract

Disclosed is a leadframe. The leadframe comprises a die pad part, at least one lead part, and at least one supporting part. A semiconductor chip is mounted on a first surface of the leadframe at the die pad. The at least one lead part electrically connects the semiconductor chip to at least one external circuit. The at least one supporting part is adjacent to a second surface opposited the first surface, includes an insulating material, and insulates the at least one lead part from each other.

Description

201101446 六、發明說明： 【發明所屬之技術領域】 本發明主張於2009年05月27日所申請之韓國專利申請 案號10-2009-0046397與2009年05月27日所申請之韓國專 利申請案號10-2009-0046267的優先權，此全文將併入本案以 作為參考。 本發明係有關於一種導線架及其製造方法，且特別是 有關於一種導線架及其製造方法能用以實現—精細圖案並 〇 減少厚度。 【先前技術】 一般而言，如圖1所示，一半導體晶片封裝200是利用對 於一導線架之一晶粒焊墊(diepad)上所安裝的一半導體晶片，執 行將該半導體晶片電性連接至該導線架的一打線結合(wk bonding)並使用一密封膠(seaiant)將所安裝的該半導體晶片進行 封裝。 Ο 因此’該導_具有將該半導體晶片封裝200之-内部連 接至-外部電路以及同時安裝該半導體晶片的功能。基於此目 的，導線架包含用於置放—半導體晶片的—晶粒焊塾部、利 用-導線(命)電性連接至半導體晶片之一導腳部21〇的一 内導腳，以及電性連接至一外部電路之導腳部21〇的一外 導腳。 如圖1所不，由於該導線架的該導腳部210為形成具 有-預定厚度的-導引腳結構，因而難以實現小型化、薄 3 201101446 型化與微形圖案（miCropattem)的構造。以及’由於將該半導體 晶片電性連接至該導腳部210的該内導腳之導線長度增 加’製造成本亦隨之增加。 【發明内容】 據此’本發明的實施例提供一種導線架及其製造方法 以形成一微形圖案並能減少導腳部之厚度。 在一實施例中，一導線架包含一晶粒焊墊（die pad part)、至少—導腳部以及至少—支揮部。—半導體晶片被 〇 安裝在該晶粒焊墊上該導線架的一第一表面上。該至少一 V腳。卩將§亥半導體晶片電性連接到至少一外部電路。該至 少一支撐部相鄰至與該第一表面相對的一第二表面，包含 一絕緣材料而使該至少一導腳部彼此相互絕緣。 每一該至少一導腳部可包含選自由銅(Cu)、鐵(Fe)及其 合金所組成之群組的至少一者。 該晶粒焊墊可包含一凹口（cavity)對應i安襄該半導體 ❹晶片的一區域。 每-該至少-導腳部可包含朝向該第—表面的水平 部’以及-垂直部從該第一表面延伸至該第二表面。該導 線架可包含至少-内導腳與至少一外導腳。該内導腳^形 成在該第-表面上的該水平部，以及該外導腳可形成在該 第二表面上的該垂直部。 該至少一内導腳的一寬唐可鲂κ 見沒·小於该至少一外導腳的 4 201101446 在該水平部中，置放有該至少一内導腳的一部份可比 未置放有該至少一内導腳的一部份較為凸出（protruded)。 至少一内導腳與該至少一外導腳包含選自由至少由鎳 (Ni)、鈀(Pd)、金(Au)、銀(Ag)、錫（Sn)、銅（Cu)、鉻(Cr)及 其合金所組成之群組的至少一材料。 該至少一支撐部可比該至少一外導腳較為凸出。 該至少一支撐部的一表面與該至少一外導腳的一表面 可定位在同一平面上。 〇 該導線架之一厚度：該至少一支撐部之一深度（depth) 的比例（ratio)可為 127:65 至 127:90。 在另一實施例中，一導線架包含一導線架基板以及至 少一支撐部。該導線架基板具有安裝半導體晶片於上方的一 第一表面，以及相對於該第一表面的一第二表面。在該導 線架基板中，定義出包含形成在該第二表面的至少一蝕刻 部（etchedportion)的一第一區域，以及除了該第一區域以外 Q 部份之一第二區域。該至少一支撐部形成在該第一區域的 該至少一蝕刻部中並包含一絕緣材料。該第二區域包含將 半導體晶片連接到至少一外部電路的至少一導腳部，以及 將半導體晶片安裝在上方的一晶粒焊墊。 在進一步的另一實施例中，用以製造一導線架的一方 法包含提供一導線架基板、形成至少一钱刻部以及形成至 少一支撐部。該導線架包含半導體晶片安裝在上方的一第 一表面，以及相對於(opposite to)該第一表面的一第二表 5 201101446 面。利用蚀刻該第二表面的一第一區域以形成該至少一餘 刻σ卩。利用填充絕緣材料在該至少一姓刻部中以形成該至 少一支撐部。 該導線架基板可包含一導電材料。除了該第一區域之 外的該第二區域可包含將半導體晶片連接到至少一外部電 路的至少一導腳部，以及半導體晶片安裝在上方的一晶粒 焊墊。 5亥方法可包含於提供該導線架基板與形成該至少一 〇#刻部之間’形成至少一内導腳與至少一外導腳電性連接 至該至少一導腳部。 形成該至少一内導腳與該至少一外導腳可包含形成 -光阻圖案在該導線架基板上，以及形成—金屬材料在該 光阻圖案的開口中。 开/成該至少一敍刻部可包含形成一光阻圖案在該導 線木基板上，以及藉由使用該光阻圖案作為一光罩（mask) 〇 以先（第一次)蝕刻該導線架基板的該第二表面。 於形成該至少一支撐部之後，該方法可包含再（第二次) 蝕刻該導線架基板的該第一表面以使該至少一導腳部彼此 相互絕緣。 在弟—次餘刻中，一凹口（cavity)可形成在該導線架基 板的該第一表面，而對應至安裝半導體晶片的位置。 該方去可包含在形成該至少一蝕刻部與形成該至少 一支撐部之間，移除該妹圖案。財法可包含於形成該 6 201101446 至少-支撐部後，第二次_該導線架基板的該第一表面 以減少該至少一導腳部的寬度與厚度並使該至少一導腳部 彼此相互絕緣。 在該第二次侧巾，可形成在該導線架基板的 S亥第一表面，而對應至文裝半導體晶片的位置。 根據本發明的實施例，利用使用一支撐部使該導腳部 絕緣的簡單程序’導腳部得以微形圖案來實現。 亦即，利用除了在一導電導線架基板的該支撐部之外 〇 的一區域作為一晶粒焊塾與該導腳部，比起利用一分開的 程序（separate process)形成該導腳部的例子，可簡化該程序 且一微形圖案得以實現。以及，該導線架的厚度得以減少。 此外，由於利用填充絕緣材料在該導線架基板的一蝕刻部 中以形成該至少一支撐部，該支撐部可使該導腳部絕緣以 及同時穩固地支撐該導線架基板。 此外’由於該導腳部的一内導腳被形成相鄰至一半導 Q 體晶片，連接該内導腳與該半導體晶片之一導線的該長度 可被減少。以及，由於該内導腳與該外導腳由包含至少一 柱體(column)的複數個柱體所形成的框架，因此高整合度是 可能的。 進一步地，於形成一蝕刻部的程序期間’由於蝕刻該 導線架基板的一頂部（upper portion)以形成安裝半導體晶 片的凹口，可減少已安裝半導體晶片之封裝(package)的厚 201101446 同時，導線架由一金屬材料所形成因而具有一卓越的 熱傳導性(thermal conductivity) 〇 【實施方式】 為讓本發明之上述目的、特徵和特點能更明顯易懂，茲 配合圖式將本發明相關實施例詳細說明如下。 於下文中，隨著圖2至圖49之參考，將說明本發明較佳 實施例。 ffi 2為根據本發明—實_之導線架的前視平面圖，圖3 〇為從圖2所示之導線架的後視平面圖，另外圖4為根據本發 明如圖2與圖3之第-實施例使用導線架之—半導體晶片^ 裝沿圖2中Ι-Γ線的剖視圖。 ，請參閱圖2至圖4，一導線架基板1〇包含安裝㈣响 半V體BB片120於上方的-晶粒焊墊(diepad卿)、將半 導體晶Μ 120 t性連接至一外部電路（未緣示）的導腳部 100，以及使導腳部100絕緣的一支撐部n〇。 ❹ 可將一内導腳122形成在導腳部10〇的一第一表面（於 下文中稱作為，，上表面，，），以及可將一外導腳124形成在導 腳部100的一第二表面（於下文中稱作為，，下表面”）。經由一 導線126將半導體晶片12〇連接至導腳部1〇〇的内導腳 122，以及利用導腳部1〇〇的外導腳124可連接至一外部電 路。此外，可進一步地提供用以將一接地電壓（gr〇und v〇kage) 供應至半導體晶片120的另一導腳121。然而，仍可能未形成 有導腳121。 201101446 請參閱圖4’包含導線架10的一半導體晶片封裝2〇可包 含e又置在導線架10之晶粒烊塾116上的半導體晶片12〇、將 半導體晶片120連接至導腳部1〇〇的導線126，以及密封導 線架10與半導體晶片120的一密封膠(sealant)i3〇。可使用一 壓模樹脂(mold resin)、環氧樹脂(EMC)或類似物當作密封膠 130。 現將更詳盡的說明根據此實施例的導線架1〇。 半導體晶片120被定位在導線架1〇的上表面上以及支 Ο 撐部11〇被定位在導線架ίο的下表面上。 在此實施例中，填充一絕緣材料在包含由蝕刻一導線 架基板（見圖14的150)所獲得之一蝕刻部112的一第一區 域中以形成支撐部112,以及除了第一區域之外的一第二 區域被當作晶粒焊墊116與導腳部1〇〇。因此，由於晶粒 焊塾116與導腳部1〇〇為相同導線架基板15〇的部分，晶 粒焊墊116與導腳部100可包含相同導電材料。於此，晶 〇粒焊墊U6與導腳部100可由具有導電性的一金屬材料所 形成，例如銅（Cu)、鐵(Fe)或銅與鐵的一合金。 導腳部100包含被朝勺導線架1〇之一上表面的一水平 部102’以及從上表面延伸至一下表面的一垂直部1〇4。内 導腳m形成在導腳部100的水平部1〇2,以及外導腳m 形成在導腳部100之垂直部的下表面。利用調整導腳部1〇〇 之水平部102的長度，具有不同尺寸的半導體晶片12〇可被 形成在具有相同尺寸的半導體晶片封裝中。 201101446 當從頂部俯視時’利用形成内導腳122其比外導腳124 更加相鄰至半導體晶片120 ’導線126之長度可被減少。導線 126之長度的減少可降低製造成本。外導聊124的寬度可被 形成而較大於内導腳122之寬度。 電性連接至導腳部100的内導腳122與外導腳124被 排列成至少一列（row)而可能的達成圖2所示如同在區域A 與區域B中之高度整合(high integration)。以一電子特性、導 線或外部電路的連接特性等考量而言，内導腳122與外導 〇 腳124可包含選自由鎳(Ni)、鈀(Pd)、金(Au)、銀(Ag)、錫 (Sn)、銅（Cu)、鉻(Cr)及其合金所組成之群組的至少一者。 支撐部110形成在這些導腳部1〇〇之間以使這些導腳 部彼此相互絕緣，以及支撐導線架10。可利用填充一絕緣 材料在蝕刻部112中以形成支撐部110。另可使用光防焊 (PSR)、樹脂包覆銅箱（RCC)、膠片（prepreg)、環氧樹脂等作 為絕緣材料。在此實施例中，支撐部11 〇與外導腳124被 ❹ 定位在同一平面上。 一凹口（cavity)106具有一深度，形成在對應安裝半導體 晶片120之一區域的晶粒焊墊116中。半導體晶片120*** 入(insert)與安裝(mount)牽涉其厚度，但由於凹口 ι〇6的深 度，故可減少半導體晶片封裝20的厚度。如此，晶粒焊墊116 的厚度可較小於導腳部100的垂直部1〇4。 根據此實施例在水平部1〇2中’形成有内導腳122的 一部份比起未形成有内導腳122的一部分較為凸出。亦 201101446201101446 VI. Description of the Invention: [Technical Field of the Invention] The present invention claims Korean Patent Application No. 10-2009-0046397 filed on May 27, 2009, and Korean Patent Application filed on May 27, 2009 The priority of the number 10-2009-0046267, the entire disclosure of which is hereby incorporated by reference. The present invention relates to a lead frame and a method of fabricating the same, and more particularly to a lead frame and a method of fabricating the same that can be used to achieve a fine pattern and reduce thickness. [Prior Art] Generally, as shown in FIG. 1, a semiconductor chip package 200 is electrically connected to a semiconductor wafer mounted on a die pad of a lead frame. The semiconductor wafer to be mounted is packaged by wk bonding to the lead frame and using a sealant. Therefore, the conductor has a function of internally connecting the semiconductor chip package 200 to an external circuit and simultaneously mounting the semiconductor wafer. For this purpose, the lead frame includes a die pad for placing a semiconductor wafer, an inner lead electrically connected to the pin 21 of the semiconductor wafer by a wire, and an electrical lead. An external lead connected to the pin portion 21 of an external circuit. As shown in Fig. 1, since the leg portion 210 of the lead frame is formed to have a - lead structure having a predetermined thickness, it is difficult to achieve a miniaturization, a thin pattern, and a miCropat. And the manufacturing cost of the wire length of the inner lead because the semiconductor wafer is electrically connected to the leg portion 210 increases. SUMMARY OF THE INVENTION Accordingly, embodiments of the present invention provide a lead frame and a method of fabricating the same to form a micro-pattern and reduce the thickness of the leg portion. In one embodiment, a leadframe includes a die pad part, at least a foot guide, and at least a branch. - a semiconductor wafer is mounted on the die pad on a first surface of the leadframe. The at least one V foot.电 Electrically connecting the CMOS semiconductor chip to at least one external circuit. The at least one support portion is adjacent to a second surface opposite the first surface and includes an insulating material to insulate the at least one leg portion from each other. Each of the at least one leg portion may comprise at least one selected from the group consisting of copper (Cu), iron (Fe), and alloys thereof. The die pad may include a cavity corresponding to an area of the semiconductor die. Each of the at least - foot portions may include a horizontal portion toward the first surface and - a vertical portion extending from the first surface to the second surface. The wire guide can include at least an inner guide pin and at least one outer guide pin. The inner guide leg ^ is formed on the horizontal portion on the first surface, and the vertical guide portion is formed on the second surface. a width of the at least one inner guide pin 见 见 · · · 小于 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 A portion of the at least one inner guide leg is more protruded. The at least one inner lead and the at least one outer lead comprise from at least nickel (Ni), palladium (Pd), gold (Au), silver (Ag), tin (Sn), copper (Cu), chromium (Cr) And at least one material of the group consisting of alloys thereof. The at least one support portion may protrude more than the at least one outer guide leg. A surface of the at least one support portion and a surface of the at least one outer guide leg may be positioned on the same plane.之一 One of the thickness of the lead frame: the ratio of the depth of one of the at least one support portion may be 127:65 to 127:90. In another embodiment, a leadframe includes a leadframe substrate and at least one support. The leadframe substrate has a first surface on which the semiconductor wafer is mounted, and a second surface opposite the first surface. In the lead frame substrate, a first region including at least one etched portion formed on the second surface, and a second region including a Q portion other than the first region are defined. The at least one support portion is formed in the at least one etched portion of the first region and includes an insulating material. The second region includes at least one leg portion connecting the semiconductor wafer to at least one external circuit, and a die pad for mounting the semiconductor wafer thereon. In still another embodiment, a method for fabricating a leadframe includes providing a leadframe substrate, forming at least one engraved portion, and forming at least one support portion. The leadframe includes a first surface on which the semiconductor wafer is mounted, and a second surface 5 201101446 opposite to the first surface. A first region of the second surface is etched to form the at least one σ 卩. A filler insulating material is used in the at least one surname to form the at least one support. The leadframe substrate can comprise a conductive material. The second region other than the first region may include at least one leg portion connecting the semiconductor wafer to at least one external circuit, and a die pad on which the semiconductor wafer is mounted. The method of 5th can include forming at least one inner lead between the lead frame substrate and the at least one engraved portion to electrically connect the at least one outer lead to the at least one lead. Forming the at least one inner lead and the at least one outer lead may include forming a photoresist pattern on the lead frame substrate, and forming a metal material in the opening of the photoresist pattern. Opening/forming the at least one scribe portion may include forming a photoresist pattern on the conductive wood substrate, and etching the lead frame first (by first) etching by using the photoresist pattern as a mask The second surface of the substrate. After forming the at least one support portion, the method can include re-etching the first surface of the leadframe substrate (second time) to insulate the at least one lead leg from each other. In the second time, a cavity may be formed on the first surface of the lead frame substrate, corresponding to the position at which the semiconductor wafer is mounted. The party can be included between forming the at least one etched portion and forming the at least one support portion to remove the sister pattern. The financial method may include forming the first surface of the lead frame substrate after forming the at least the support portion to reduce the width and thickness of the at least one lead portion and causing the at least one lead portion to mutually insulation. The second side scarf can be formed on the first surface of the lead frame substrate and corresponds to the position of the document semiconductor wafer. According to an embodiment of the present invention, a simple program 'footlet' that insulates the leg portion using a support portion is realized in a micro pattern. That is, using a region other than the support portion of a conductive lead frame substrate as a die bond and the leg portion, the guide leg portion is formed by using a separate process. For example, the program can be simplified and a micropattern can be implemented. And, the thickness of the lead frame is reduced. Further, since the at least one supporting portion is formed in an etched portion of the lead frame substrate by using a filling insulating material, the supporting portion can insulate the lead leg portion and at the same time stably support the lead frame substrate. Further, since an inner lead of the lead portion is formed adjacent to the one-half of the conductive body wafer, the length connecting the inner lead to one of the wires of the semiconductor wafer can be reduced. And, since the inner guide pin and the outer guide leg are formed by a frame formed of a plurality of cylinders including at least one column, high integration is possible. Further, during the process of forming an etched portion, the thickness of the mounted semiconductor wafer package can be reduced by etching an upper portion of the lead frame substrate to form a recess for mounting the semiconductor wafer. The lead frame is formed of a metal material and thus has an excellent thermal conductivity. [Embodiment] In order to make the above objects, features and features of the present invention more apparent, the present invention will be implemented in accordance with the drawings. The details are as follows. Hereinafter, preferred embodiments of the present invention will be described with reference to Figs. 2 to 49. Ffi 2 is a front plan view of a lead frame according to the present invention, FIG. 3 is a rear plan view of the lead frame shown in FIG. 2, and FIG. 4 is a view of FIG. 2 and FIG. 3 according to the present invention - The embodiment uses a lead frame - a semiconductor wafer is mounted along a Ι-Γ line in Fig. 2. Referring to FIG. 2 to FIG. 4, a lead frame substrate 1 〇 includes a die pad on which the (four) half V body BB piece 120 is mounted, and the semiconductor wafer 120 t is connected to an external circuit. The guide leg portion 100 (not shown) and a support portion n〇 that insulates the guide leg portion 100.一 An inner guide pin 122 may be formed on a first surface of the guide leg portion 10 (hereinafter referred to as an upper surface, and), and an outer guide pin 124 may be formed on the guide pin portion 100. a second surface (hereinafter referred to as a lower surface). The semiconductor wafer 12 is connected to the inner lead 122 of the lead portion 1 via a wire 126, and the outer guide of the lead portion 1 is used. The foot 124 can be connected to an external circuit. Further, another lead 121 for supplying a ground voltage to the semiconductor wafer 120 can be further provided. However, the lead pin may still not be formed. 121. 201101446 Please refer to FIG. 4's a semiconductor wafer package 2 including a lead frame 10, which may include a semiconductor wafer 12 disposed on the die 烊塾 116 of the lead frame 10, and connecting the semiconductor wafer 120 to the lead portion 1〇〇 of the wire 126, and a sealant 10 and a sealant of the semiconductor wafer 120. A mold resin, epoxy resin (EMC) or the like can be used as the sealant. 130. The lead frame 1 according to this embodiment will now be described in more detail. The semiconductor wafer 120 is positioned on the upper surface of the lead frame 1 and the support portion 11 is positioned on the lower surface of the lead frame. In this embodiment, an insulating material is filled in by etching a lead frame. A substrate (see 150 of FIG. 14) is obtained in a first region of the etched portion 112 to form the support portion 112, and a second region other than the first region is used as the die pad 116 and the lead pin Therefore, since the die pad 116 and the leg portion 1 are the same portion of the lead frame substrate 15, the die pad 116 and the leg portion 100 may comprise the same conductive material. The solder pad U6 and the leg portion 100 may be formed of a metal material having conductivity, such as copper (Cu), iron (Fe) or an alloy of copper and iron. The leg portion 100 includes a lead frame 1 a horizontal portion 102' of the upper surface of the crucible and a vertical portion 1〇4 extending from the upper surface to the lower surface. The inner guide leg m is formed at the horizontal portion 1〇2 of the leg portion 100, and the outer guide leg m is formed On the lower surface of the vertical portion of the leg portion 100. The length of the horizontal portion 102 of the adjusting leg portion 1 is used. Semiconductor wafers 12 having different sizes can be formed in a semiconductor wafer package having the same size. 201101446 When viewed from the top, 'using the inner via 122 to be more adjacent to the outer wafer 124 to the semiconductor wafer 120' The length of the 126 can be reduced. The reduction in the length of the wire 126 can reduce the manufacturing cost. The width of the external guide 124 can be formed to be larger than the width of the inner guide pin 122. The inner guide pin 122 is electrically connected to the guide pin 100. The outer guide legs 124 are arranged in at least one row and the possible achievement is as shown in FIG. 2 as high integration in the regions A and B. The inner lead 122 and the outer lead 124 may be selected from nickel (Ni), palladium (Pd), gold (Au), silver (Ag) in terms of an electronic characteristic, a connection characteristic of a wire or an external circuit, and the like. At least one of the group consisting of tin (Sn), copper (Cu), chromium (Cr), and alloys thereof. A support portion 110 is formed between the leg portions 1A to insulate the leg portions from each other and to support the lead frame 10. The insulating portion 112 may be filled in the etching portion 112 to form the support portion 110. A light solder resist (PSR), a resin coated copper box (RCC), a film (prepreg), an epoxy resin, or the like can be used as the insulating material. In this embodiment, the support portion 11 and the outer guide pins 124 are positioned on the same plane by the crucible. A cavity 106 has a depth formed in a die pad 116 corresponding to a region of the semiconductor wafer 120. The insertion and mounting of the semiconductor wafer 120 involves its thickness, but due to the depth of the recess 〇6, the thickness of the semiconductor wafer package 20 can be reduced. As such, the thickness of the die pad 116 can be smaller than the vertical portion 1〇4 of the leg portion 100. According to this embodiment, a portion in which the inner guide pin 122 is formed in the horizontal portion 1A is more convex than a portion in which the inner guide pin 122 is not formed. Also 201101446

下方之水平部102的厚度T1係較厚 !部分之水平部102的厚度Τ2。如此， 之半導體晶片封裝20的厚度。 ' 士日 延弋由於在該製造方法中，位置不在内導腳122下方 之=份的水平部102與垂直部104的厚度與寬度被減少 了，縫著圖5至圖10，將更詳盡地說明該製造方法。利用 製方法所製造之導線架1 〇的案例中，導腳部1 〇〇可形 成較精細圖案，且可薄化具有導線架10的半導體晶片封裝 Ο 20。 圖5至圖16為製造如圖4所示之導線架與半導體晶片 封裝之方法的剖視圖。 如圖5所示，提供由金屬所製成之一導線架基板15〇。 於此，導線架基板150可由一導電材料所形成，例如銅、 鐵以及其合金。導線架基板150可具有介於丨至1〇密耳 (mil)(l密耳=1/1〇〇〇吋)之範圍的厚度，最好在】至5密耳。 Ο 如圖6所示’塗佈一光阻140在導線架基板15〇之一 上表面與一下表面上，且隨後藉由使用光罩17〇與172來 圖形化。利用該圖形化，形成如圖7中所示之第一光阻圖 案 142a 與 142b。 具體地’如圖5所示’將光阻140形成在導線架15〇 的上表面與下表面上。於此，可使用一液態光阻(LpR>、一 乾膜光阻(DFE)或其類似物以形成光阻140。在導線架基板 15〇之上表面與下表面使用光罩170與172以執行一光微 11 201101446 影製程以曝光與顯影光阻140。 每一光罩170與172包含一不透明區域，該不透明區 域具有形成在一石英基板的一光遮蔽層，以及僅由談石英 基板所組成的一透明區域。圖Π與圖18為圖6程序中所 使用之光罩的平面圖。為了簡易區別，不通明區域Sl在圖 17與圖18中以黑色作表示。The thickness T1 of the lower horizontal portion 102 is thicker, and the thickness of the horizontal portion 102 of the portion is Τ2. As such, the thickness of the semiconductor wafer package 20 is. 'In the manufacturing method, the thickness and width of the horizontal portion 102 and the vertical portion 104 of the portion below the inner guide leg 122 are reduced, and the sewing of FIGS. 5 to 10 will be more detailed. The manufacturing method will be described. In the case of the lead frame 1 manufactured by the manufacturing method, the leg portion 1 can be formed into a finer pattern, and the semiconductor chip package 20 having the lead frame 10 can be thinned. 5 through 16 are cross-sectional views showing a method of manufacturing a lead frame and a semiconductor wafer package as shown in Fig. 4. As shown in FIG. 5, a lead frame substrate 15 made of metal is provided. Here, the lead frame substrate 150 may be formed of a conductive material such as copper, iron, and alloys thereof. The leadframe substrate 150 can have a thickness ranging from 丨 to 1 mil (l mil = 1/1 〇〇〇吋), preferably from 5 mils.涂布 As shown in Fig. 6, a photoresist 140 is coated on the upper surface and the lower surface of one of the lead frame substrates 15 and then patterned by using the masks 17 and 172. With this patterning, first photoresist patterns 142a and 142b as shown in Fig. 7 are formed. Specifically, the photoresist 140 is formed on the upper surface and the lower surface of the lead frame 15A as shown in Fig. 5. Here, a liquid photoresist (LpR), a dry film photoresist (DFE) or the like may be used to form the photoresist 140. The masks 170 and 172 are used on the upper and lower surfaces of the lead frame substrate 15 to perform A light micro 11 201101446 shadow process to expose and develop the photoresist 140. Each of the masks 170 and 172 includes an opaque region having a light shielding layer formed on a quartz substrate, and consisting only of a quartz substrate A transparent area. Figure 18 and Figure 18 are plan views of the reticle used in the procedure of Figure 6. For ease of distinction, the non-clear area S1 is shown in black in Figures 17 and 18.

在導線架基板150上方之光罩170的透明區域s2被定 位在對應至如圖17中所示一導腳121與—内導卿I〕]被形 成的部份，以及於該曝光程序期間傳送紫外光。於顯影程 序期間移除對應至透明區域S2之部份的光阻14〇，因而形 成如圖7中所示之一第一光阻圖案142a。 位於導線架基板150下方之光罩172的透明區域被定 位在對應至如圖18中所示形成有一外導腳124之部份，以 及於曝光程序期間傳送紫外光。於顯影程序期間移除對靡 於透明區域S2之部份的光阻140 ’因而形成如圖7中所示 之一第一光阻圖案142b。 然而，本實施例並非用以限定本發明。亦即，彳艮明顯 的，可使用未暴露在紫外光下而被移除之部份的光阻。 之後，如圖8中所示，一導腳121、一内導腳122以 及一外導腳124被各別地形成具有第一光阻圖案142之導 線架基板150的上表面與下表面上。可利用電鍍一金屬材 料在第一光阻圖案142之開口中形成導腳12卜内導腳122 以及外導腳124。可使用鎳(Ni)、鈀(Pd)、金(Au)、銀(Ag)、 12 201101446 錫（Sn)、銅（Cu)、鉻(Cr)，以及其合金作為該金屬材料。 然此實施例包含導腳121的導線架，但亦可能未形戍有 腳121 。 導 之後，如圖9中所示，將一光阻140a塗佈在導線架基 板150之上表面與下表面上，之後使用定位在導線架基板 150上方與下方之光罩174與176而被圖樣化。利用該圖 樣化’开> 成如圖中所示的一第二光阻圖案144a、144b。 具體地’將光阻14〇a形成在導線架基板15〇的上表面 〇 與下表面上。藉由使用光罩174與176的一光微影製程曝 光與顯影位於導線架基板150之上表面與下表面上的光阻 140a。 圖19為圖9程序中所使用之光罩174的一平面圖並定 位在導線架基板150上方。為了簡易區別，圖19中以黑色 表示一透明區域S2。 ‘線架基板150上方的光罩174具有一透明區域S2， Q 透明區域S2定位在對應於導腳121與導腳部122之間以及 這些導腳部122之間的一導腳間對應部（見圖1〇與圖u的 wl) ’以及在對應至凹口（見圖4之106)的一凹口對應部 W3 °於該曝光程序期間透明區域S2傳送紫外光。於該顯 影程序完成後，形成一第二光阻圖案144a在對應至不透明 區域S1的一區域，如圖1〇中所示。 導線架基板150下方之光罩176具有如圖18中所示相 同於光軍174的形狀。亦即，透明區域S2被定位在形成該 13 201101446 蝕刻部的一蝕刻對應部（見圖1〇與圖u的W2)，以及於該 曝光程序期間傳送紫外光。於該顯影程序完成後，利用該 曝光程序’形成一第二光阻圖案144b在除了該蝕刻對應部 W2之外的一區域，如圖中所示。 然而’本實施例並非用以限定本發明。亦即，很明顯 的’可使用未暴露在紫外光下而被移除之部份的光阻。 之後，如圖11中所示’藉由使用分別形成在導線架基 板150的上表面與下表面上的光阻圖案M4a、14朴執行一 Ο 第一次蝕刻程序。請參照圖11中所示一虛線部份表示一相 鄰的部份。 具體地，藉由使用第二光阻圖案144a作為一光罩以部 分地蝕刻導腳間對應部W1與凹口對應部W3。藉由使用第 一光阻圖案144b作為一光罩以钱刻導線架基板bo的下表 面的一厚度以形成蝕刻部112。較佳地，當導線架基板150 為5 mil (=127 μιη)厚，蝕刻部112可具有65至90 μιη(微米） Q 的一深度。於此，蝕刻部112可具有70至90 μιη(微米）的 一深度。 亦即，導線架基板150(或導線架10)之厚度：餘刻部 112 之深度（depth)的一比例（ratio)可為 127:65 至 127:90。或 者，導線架基板150(或導線架10)之厚度：蝕刻部112之深 度的比例可為127:70至127:90。然而’本實施例並非用以 限定本發明。 之後，如圖12中所示，移除餘留在導線架基板15〇之 14 201101446 上表面與下表面上的第二光阻圖案144a、144b。 之後，如圖13中所示，將一絕緣材料填充在餘刻部 112中以形成—切部11G。可㈣光焊阻(PSR)、樹脂包 覆銅^ (RCC)、膠片（卿吻、環氧樹脂(卬㈣等作為絕緣 材料。 可運用不同的方法，填充絕緣材料在似彳部112 中以形成支擔部11〇。如一範例，在將光焊阻作為絕緣材 料的例子中，於光烊阻被沈積後，可利用曝光與顯影將位 〇於除了_部外之區域上的光焊阻移除。在樹脂包覆銅 箔、膠片或環氧樹脂作為絕緣材料的例子中，如圖2〇中所 示壓合(press)—絕緣材料u〇a在導線架基板15〇的下表面 上，而後研磨（polish)絕緣材料110a以暴露外導腳124，藉 此形成支撐部110，如圖21中所示。 如圖14中所示，除了形成導腳121與内導腳122的區 域外’第二次(secondly)餘刻導線架基板15〇的上表面。藉 ❹由第二次蝕刻，進一步地蝕刻凹口對應部W3以形成具有 一預定深度的一凹口 106。導腳間對應部wi被蝕刻至形成 支撐部110的部份’因而使得導腳121與内導腳122彼此 相互絕緣且使得這些内導腳122彼此相互絕緣。以及，在 未形成導腳121與内導腳丨22之導腳部1〇〇的區域可被蝕 刻以減少導腳部100的寬度與厚度（更精確地說，其中一些 的該水平部102與該垂直部1〇4)。 亦即，在此實施例中’於移除第二光阻圖案l44a、144b 15 201101446 以及形成支撐部110的步驟後，執行第二次（secondly)蝕刻 導線架基板150以電性絕緣這些導腳部100。因此，可進 一步地減少這些導腳部100的寬度與厚度。據此，可達成 一較精細圖案。 如一範例，當該導線架基板150被形成5密耳(mil)的 厚度時，在圖11之該第一次蝕刻期間，導線架基板15〇的 上表面被部份地餘刻30微米（μιη)以及導線架基板150的下 表面被部份地#刻65微米（μιη)，藉此能夠組成該支撐部 Ο 110。之後，在如圖14中所示的第二次餘刻程序中，導線 架基板150的上表面可以被進一步地蝕刻30微米（μιη)。據 此’在未形成有導腳121與内導腳122的部份中，水平部 102可被形成為具有大約30微米（μιη)之厚度的一薄層。 如上所描述，隨著圖5至圖14所示的程序，可形成該 導線架10。圖15與16為說明使用該導線架1〇之該半導 體晶片封裝的剖視圖。 ^ 如圖15中所示，將半導體晶片120安裝在凹口 ι〇6 中，而後使用導線126將半導體晶片120與内導腳122， 以及半導體晶片120與導腳121電性連接。此時，藉由使 用黏膠(glue)可將半導體晶片120結合(bonded)在凹口 1 〇6 中。 之後，如圖16中所示，藉由利用一密封膠130將半導 體晶片120與導線126密封以形成半導體晶片封裝20。該 密封膠130可由包含一壓模樹脂(mold resin)、一環氧樹脂 16 201101446 (EMC)等的一材料所組成。 於下文中，將更詳盡地說明根據一第二實施例包含一 導線架的一半導體晶片封裝及其製造方法。為了簡易說 明，將省去相同以及類似那些該第一實施例之構造的描述 並僅描述不同的構造。相同或類似的參考數字代表整個相 同的元件。 圖22為根據本發明如圖2與圖3之一第二實施使用該 導線架之一半導體晶片封裝沿圖2中Ι-Γ線的剖視圖。 Ο 請參閱圖22，在此實施例中，相較於一外導腳124， 一支撐部110係為凸出的(protruded)。藉由凸出該支樓部 110，當連接一外部電路至外導腳124時，該凸出的支撐部 110具有一校準元件的功用。以及，利用於一第二次蝕刻 程序可防止一導腳121與一内導腳122受損的製造方法形 成此一結構。因此，根據此實施例，可防止導腳121與内 導腳122的損害。 q 於下文中，於圖22中所示說明用以製造一導線架與一 半導體封裝的方法將隨圖23至圖36進行說明。圖23至圖 36為說明用以製造圖22中所示之該導線架與該半導體晶 片封裝之方法一範例的剖視圖。 如圖23中所示，提供由金屬所製成的一導線架基板 150。 之後，如圖24中所示，將一光阻140塗佈在導線架基 板150之一上表面與一下表面上，且隨後藉由使用光罩170 17 201101446 與172而使導線架基板150被圖形化。利用該圖形化，形 成如圖25中所示之第一光阻圖案142a與142b。 之後，如圖26中所示，將一導腳121與一内導腳122 形成在導線架150的上表面上，以及將一外導腳124形成 在導線架150的下表面上。 之後’如圖27中所示，將一光阻140a塗佈在導線架 基板150之上表面與下表面上，而後藉由使用光罩174與 176而使導線架基板15〇被圖形化以形成如圖28中所示之 〇 一苐一光阻圖案144a、144b。 之後，如圖29中所示’藉由使用分別形成在導線架基 板150的上表面與下表面上的光阻圖案M4a、144b執行一 第一次敍刻程序。利用該第一次蝕刻程序，導線架基板15〇 之上表面的一凹口對應部W3被部份地蝕刻，且一導腳間 對應部wi也被部份地蝕刻。以及，將一蝕刻部U2形成 在導線架基板150之下表面的一蝕刻對應部W2。 〇 之後，如圖30中所示，將一絕緣材料填充在餘刻部 U2中以形成-支撐部11〇。可運用不同的方法，利用填充 絕緣材料在餘刻部112中以形成支撐部11〇。如一範例，在 將光焊阻作為絕緣材料的例子中，於該光焊阻被沈積後， y利用曝光與顯影將位於除了該關部以外之區域上的光 焊阻移除。在樹脂包覆銅落、膠片或環氧樹脂作為絕緣材 料的例子中’如圖35中所示壓合(press)-絕緣材料u〇a 在‘線架基板15〇的下表面上’而後研磨㈣咖絕緣材料 18 201101446 110a以暴露外導腳124 ’藉此形成支撐部no，如圖％中 所示。 之後，如圖31中所示，執行使用形成在導線架基板 150之上表面上的第二光阻圖案作為光罩的一第二次蝕刻 程序。利用第二次蝕刻，蝕刻導線架基板150之上表面。 據此，進一步地独刻凹口對應部W3以形成具有一預定深 度的一凹口 106。導腳間對應部W1被蝕刻至形成支撐部 110的部份，因而使得導腳121與内導腳122彼此相互絕 Ο 緣且使得這些内導腳122彼此相互絕緣。 之後，如圖32中所示，移除餘留在導線架基板150之 上表面與下表面上的第二光阻圖案144a、144b以形成一導 線架10。 此第二實施例與第一實施例之不同處在於：在第二實 施例中，在導線架基板150之第二次蝕刻程序（圖31)之後 移除第二光阻圖案144a、144b，但是在第一實施例中，是 ❹在導線架基板15〇之第二次蝕刻程序（圖14)之前移除第二 光阻圖案144a、144b。於此，由於在支撐部11〇形成後移 除第一光阻圖案144a、144b，相較於外導腳124，支撐部 11〇係為凸出的(pr〇truded)。在帛二實施例巾由於第二次 、d耘序在第—光阻圖案144a覆蓋導腳121與内導腳以2 、中所執行，於該第二次餘刻程序期間可防止導腳 121與内導腳⑵受到損壞。 後執行如圖33與圖34中所示的程序以形成一半 19 201101446 導體晶片封裝2G。亦即，如圖33中所示，將半導體晶片 120女裝在凹口 106中，而後使用一導線126將半導體晶 片120與導腳121，以及半導體晶片12〇與内導腳122電 性連接。之後，如圖34中所示，藉由利用一密封膠13〇將 導線架H)、半導體晶片120與導線126 一起密封以形成半 導體晶片封裝20。 於下文中，將隨著圖37至圖49所示說明根據一第二 實施例用以製造-導線架與一半導體晶片封裝之一方法的 〇另-範例。Η 37至圖49為根據本發明一第二實施例說明 用以製造-半導體晶片封裳一方法之另一範例的剖視圖。 如圖37中所示，提供由金屬所製成的一導線架基板 150 ° 如圖38中所示，將一光阻14〇塗佈在導線架基板15〇 之一上表面與一下表面上，且隨後藉由使用光罩17〇與172 而使導線架基板150被圖形化。利用該圖形化，形成如圖 ❹ 39中所示之一第一光阻圖案142。 如圖40中所示，將一導腳121與一内導腳122形成在 導線架150的上表面上，以及將一外導腳124形成在導線 架150的下表面上。 之後，如圖41中所示’將一光阻140b塗佈在導線架 基板150之上表面與下表面上，而後藉由使用光罩丨74與 176而使導線架基板150被圖案化以形成如圖42中所示之 一第二光阻圖案144b、144c。在此實施例中，以一乾膜光 20 201101446 阻(DFR)作為光阻140b。於此，可將該乾膜光阻形成為包含 一光敏材料層242與堆疊在光敏材料層242上之一保護祺 240的一堆疊結構。 、 〇 ❹ 請參閱圖42，於移除保護膜24〇的一狀態中使用位於 導線架基板150之上表面上的第二光阻圖案14如，以及於 移除保護膜24〇的-狀態中使用位於導線架基板15〇之下 表面上的光阻圖案144b。位於導線架基板15G上表面上之 第二光關案144e的光敏材料層242包含與紫外光作 的一圖案⑽，以及不與紫外光作反應的-圖案242b。… 如圖43中所$，藉由利用位於導線架基板⑼之下 L 上的第二光阻圖案_作為一光罩，第一次姓刻導線架 之下表面’以形成一蝕刻部112。本實施例與前 架基板= ㈣程序綱未_導線 成支=中所示’填充-絕緣材料在一中以形 的伴ir/Jzr，移除位於導線架基板-上表面上方 扪侏邊膜240而後顯影光 留下不與紫外弁你 ；e 242。利用該顯影，僅 ' 乍反應的圖案242b。 如圖46中所千，4丨 導腳間對應部W1蝕刻至該支 作為-光罩的〜第/用不與紫外光作反應的圖案2桃 表面。利用該第Sr程序敍刻導線架基板150之上 形成-凹口 106。以及序’餘刻—凹口對應部W3，以 21 201101446 撐部no，使得_ 121與内導腳122彼此相互絕緣且使 得這些内導腳122彼此相互絕緣。 如圖47中所示，移除餘留在導線架基板15〇之上表面 與下表面上而不與紫外光作反應的第二光阻圖案M4b與 圖案242b，稭此形成一導線架1 〇。 如圖48與圖49中所示，安裝一半導體晶片12〇而後 利用一導線26結合。之後，藉由利用一密封膠別將半導 體晶片120密封以形成該半導體晶片封裝2〇。 〇 綜上所述，乃僅記载本發明為呈現解決問題所採用的 技術手¥又之較佳實施方式或實施例而已，並非用來限定本 發明專利實施之範圍。即凡與本發明專利申請範圍文義相 符，或依本發明專利範圍所做的均等變化與修飾，皆為本 發明專利範圍所涵蓋。 【圖式簡單說明】 ◎圖1為一相關半導體晶片封裝技術的一透視圖； 圖2為根據本發明一實施例之導線架的前視平面圖； 圖3為從圖2所示之該導線架的後視平面圖； 圖4為根據本發明如圖2與圖3之第一實施例使用該導線 架之一半導體晶片封裝沿圖2中Ι-Γ線的剖視圖； 圖5至圖16為製造如圖4所示之該導線架與該半導體晶片 封裝之方法的剖視圖； 圖17與圖18為圖6程序中所使用之光罩的平面圖； 圖19為圖9程序中所使用之光罩的平面圖； 22 201101446 圖20與圖21為根據本發明一實施例用以製造一支撐部之方 法的剖視圖； 圖22為根據本發明如圖2與圖3之一第二實施使用該導線 架之一半導體晶片封裝沿圖2中Ι-Γ線的剖視圖； 圖23至圖34為製造如圖22中該導線架與該半導體晶片封 裝之方法之剖視圖； 圖35與圖36為製造支撐部之方法的剖視圖；以及 圖37至圖49為根據本發明一第二實施例說明用以製造一 〇 半導體晶片封裝之方法的另一範例剖視圖。 【主要元件符號說明】 200 半導體晶片封裝 210 導腳部 10 導線架 100 導腳部 102 水平部 104 垂直部 106 凹口 110 支撐部 110a 絕緣材料 112 蝕刻部 116 晶粒焊塾 120 半導體晶片 121 導腳 23 201101446 122 内導腳 124 外導腳 126 導線 130 密封膠 140, 140a,140b 光阻 142a,142b 第一光阻圖案 144a,144b,144c 第二光阻圖案 150 導線架基板 〇 170,172,174,176 光罩 20 半導體晶片封裝 240 保護膜 242 敏材料層 242a, 242b 圖案 A,B 區域 SI 不透明區域 O S2 透明區域 T1,T2 厚度 W1 導腳間對應部 W2 1虫刻對應部 W3 凹口對應部 24The transparent region s2 of the reticle 170 above the lead frame substrate 150 is positioned to correspond to a portion formed by a lead 121 and an inner guide I] as shown in FIG. 17, and transmitted during the exposure process. Ultraviolet light. The photoresist 14 对应 corresponding to a portion of the transparent region S2 is removed during the developing process, thereby forming a first photoresist pattern 142a as shown in FIG. The transparent region of the mask 172 under the leadframe substrate 150 is positioned to correspond to the portion of the outer guide 124 formed as shown in Figure 18, and to deliver ultraviolet light during the exposure process. The photoresist 140' that is removed from the portion of the transparent region S2 during the developing process thus forms a first photoresist pattern 142b as shown in FIG. However, this embodiment is not intended to limit the invention. That is, it is obvious that the photoresist which is removed without being exposed to ultraviolet light can be used. Thereafter, as shown in FIG. 8, a lead 121, an inner lead 122, and an outer lead 124 are individually formed on the upper and lower surfaces of the bobbin substrate 150 having the first photoresist pattern 142. The guide pin 12 inner guide pin 122 and the outer guide pin 124 may be formed in the opening of the first photoresist pattern 142 by electroplating a metal material. Nickel (Ni), palladium (Pd), gold (Au), silver (Ag), 12 201101446 tin (Sn), copper (Cu), chromium (Cr), and alloys thereof can be used as the metal material. However, this embodiment includes a lead frame for the guide pin 121, but may also have no foot 121. After the guiding, as shown in FIG. 9, a photoresist 140a is coated on the upper surface and the lower surface of the lead frame substrate 150, and then patterned using the masks 174 and 176 positioned above and below the lead frame substrate 150. Chemical. A second photoresist pattern 144a, 144b as shown in the figure is formed by the patterning. Specifically, the photoresist 14A is formed on the upper surface 〇 and the lower surface of the lead frame substrate 15A. The photoresist 140a on the upper and lower surfaces of the lead frame substrate 150 is exposed and developed by a photolithography process using the masks 174 and 176. Figure 19 is a plan view of the reticle 174 used in the procedure of Figure 9 and positioned over the leadframe substrate 150. For the sake of easy distinction, a transparent area S2 is indicated by black in Fig. 19. The reticle 174 above the bobbin substrate 150 has a transparent region S2 positioned at a corresponding portion between the lead pin 121 and the leg portion 122 and between the leg portions 122 ( See Fig. 1A and Fig. u's wl)' and a notch corresponding portion W3 corresponding to the notch (see Fig. 4, 106) to transmit ultraviolet light during the exposure process. After the development process is completed, a second photoresist pattern 144a is formed in an area corresponding to the opaque area S1, as shown in FIG. The reticle 176 below the lead frame substrate 150 has the same shape as the light 174 as shown in FIG. That is, the transparent region S2 is positioned at an etched portion (see Fig. 1A and W2 of Fig. u) which forms the etched portion of the 13201101446, and transmits ultraviolet light during the exposure process. After the development process is completed, a second photoresist pattern 144b is formed by the exposure process to an area other than the etching corresponding portion W2 as shown in the drawing. However, the present embodiment is not intended to limit the invention. That is, it is apparent that the photoresist which is removed without being exposed to ultraviolet light can be used. Thereafter, a first etching process is performed by using the photoresist patterns M4a, 14 respectively formed on the upper and lower surfaces of the lead frame substrate 150 as shown in Fig. 11. Referring to a broken line portion shown in Fig. 11, an adjacent portion is shown. Specifically, the inter-foot-to-foot corresponding portion W1 and the notch-corresponding portion W3 are partially etched by using the second photoresist pattern 144a as a mask. The etching portion 112 is formed by using the first photoresist pattern 144b as a mask to etch a thickness of the lower surface of the lead frame substrate bo. Preferably, when the lead frame substrate 150 is 5 mils (= 127 μm) thick, the etched portion 112 may have a depth of 65 to 90 μm (micrometers) Q. Here, the etched portion 112 may have a depth of 70 to 90 μm (micrometers). That is, the thickness of the lead frame substrate 150 (or the lead frame 10): a ratio of the depth of the residual portion 112 may be 127:65 to 127:90. Alternatively, the thickness of the lead frame substrate 150 (or the lead frame 10): the ratio of the depth of the etched portion 112 may be 127:70 to 127:90. However, the present embodiment is not intended to limit the invention. Thereafter, as shown in FIG. 12, the second photoresist patterns 144a, 144b remaining on the upper and lower surfaces of the lead frame substrate 15 201101446 are removed. Thereafter, as shown in Fig. 13, an insulating material is filled in the residual portion 112 to form a cut portion 11G. (4) Photo-resistance (PSR), resin-coated copper (RCC), film (clear kiss, epoxy (卬), etc.) as an insulating material. Different methods can be used to fill the insulating material in the like portion 112. The support portion 11 is formed. As an example, in the example of using the solder resist as an insulating material, after the photoresist is deposited, exposure and development can be used to locate the solder resist on the region other than the portion. In the example of resin-coated copper foil, film or epoxy resin as an insulating material, as shown in FIG. 2A, a press-insulating material u〇a is on the lower surface of the lead frame substrate 15A. Then, the insulating material 110a is polished to expose the outer lead 124, thereby forming the support portion 110 as shown in Fig. 21. As shown in Fig. 14, except for the area where the lead pin 121 and the inner lead 122 are formed 'Secondly remnant engraved on the upper surface of the lead frame substrate 15'. By the second etching, the notch corresponding portion W3 is further etched to form a notch 106 having a predetermined depth. The portion wi is etched to form a portion of the support portion 110, thus causing the guide pin 121 and the inner guide The insulators 122 are insulated from each other and the inner guide pins 122 are insulated from each other. Also, the region where the lead pins 121 and the guide pin portions 1 of the inner guide fins 22 are not formed may be etched to reduce the width of the leg portions 100 and Thickness (more precisely, some of the horizontal portion 102 and the vertical portion 1〇4). That is, in this embodiment, 'the second photoresist pattern l44a, 144b 15 201101446 is removed and the support portion 110 is formed. After the step, the lead frame substrate 150 is etched to electrically insulate the lead portions 100. Therefore, the width and thickness of the lead portions 100 can be further reduced. As an example, when the leadframe substrate 150 is formed to a thickness of 5 mils, during the first etch of FIG. 11, the upper surface of the leadframe substrate 15 is partially engraved by 30 micrometers. (μιη) and the lower surface of the lead frame substrate 150 are partially engraved by 65 μm, whereby the support portion 110 can be formed. Thereafter, in the second remnant program as shown in FIG. The upper surface of the lead frame substrate 150 can be further The ground is etched by 30 micrometers. Thus, in the portion where the lead pin 121 and the inner lead 122 are not formed, the horizontal portion 102 can be formed as a thin layer having a thickness of about 30 μm. As described, the lead frame 10 can be formed with the procedures shown in Figures 5 through 14. Figures 15 and 16 are cross-sectional views illustrating the semiconductor wafer package using the lead frame 1. As shown in Figure 15, The semiconductor wafer 120 is mounted in the recess ι6, and then the semiconductor wafer 120 and the inner lead 122, and the semiconductor wafer 120 and the lead 121 are electrically connected using the wires 126. At this time, the semiconductor wafer 120 can be bonded in the recess 1 〇 6 by using a glue. Thereafter, as shown in Fig. 16, the semiconductor wafer package 20 is formed by sealing the semiconductor wafer 120 and the wires 126 with a sealant 130. The sealant 130 may be composed of a material comprising a mold resin, an epoxy resin 16 201101446 (EMC), and the like. Hereinafter, a semiconductor wafer package including a lead frame and a method of fabricating the same according to a second embodiment will be explained in more detail. For the sake of simplicity, the description of the same and similar configurations of the first embodiment will be omitted and only different configurations will be described. The same or similar reference numerals represent the entire same elements. Figure 22 is a cross-sectional view of the semiconductor wafer package of the lead frame of Figure 2 and Figure 3 taken along the Ι-Γ line of Figure 2 in accordance with the second embodiment of the present invention. Referring to Figure 22, in this embodiment, a support portion 110 is protruded as compared to an outer guide leg 124. By projecting the branch portion 110, the raised support portion 110 has the function of a calibration element when an external circuit is connected to the outer guide leg 124. And, a manufacturing method for preventing damage of a lead pin 121 and an inner lead pin 122 by a second etching process forms the structure. Therefore, according to this embodiment, damage of the lead pin 121 and the inner guide pin 122 can be prevented. q Hereinafter, a method for manufacturing a lead frame and a semiconductor package illustrated in Fig. 22 will be described with reference to Figs. 23 to 36. 23 to 36 are cross-sectional views illustrating an example of a method for manufacturing the lead frame and the semiconductor wafer package shown in Fig. 22. As shown in Fig. 23, a lead frame substrate 150 made of metal is provided. Thereafter, as shown in FIG. 24, a photoresist 140 is coated on the upper surface and the lower surface of one of the lead frame substrates 150, and then the lead frame substrate 150 is patterned by using the masks 170 17 201101446 and 172. Chemical. With this patterning, the first photoresist patterns 142a and 142b as shown in Fig. 25 are formed. Thereafter, as shown in Fig. 26, a lead pin 121 and an inner lead 122 are formed on the upper surface of the lead frame 150, and an outer lead 124 is formed on the lower surface of the lead frame 150. Thereafter, as shown in FIG. 27, a photoresist 140a is coated on the upper surface and the lower surface of the lead frame substrate 150, and then the lead frame substrate 15 is patterned by using the masks 174 and 176 to form The photoresist patterns 144a, 144b are as shown in FIG. Thereafter, as shown in Fig. 29, a first characterization process is performed by using the photoresist patterns M4a, 144b respectively formed on the upper and lower surfaces of the lead frame substrate 150. With this first etching process, a notch corresponding portion W3 on the upper surface of the lead frame substrate 15A is partially etched, and a corresponding portion wi between the leads is also partially etched. And, an etching portion U2 is formed on an etching corresponding portion W2 on the lower surface of the lead frame substrate 150. Then, as shown in Fig. 30, an insulating material is filled in the residual portion U2 to form a - support portion 11A. Different methods can be employed to form the support portion 11 in the residual portion 112 by filling the insulating material. As an example, in the case where the solder resist is used as the insulating material, after the solder resist is deposited, y is removed by exposure and development to remove the solder resist located on the region other than the gate. In the case of a resin-coated copper drop, film or epoxy resin as an insulating material, 'press-insulating material u〇a on the lower surface of the bobbin substrate 15' as shown in FIG. 35 and then grinding (4) Coffee Insulation Material 18 201101446 110a to expose the outer guide leg 124' thereby forming the support portion no, as shown in the figure %. Thereafter, as shown in Fig. 31, a second etching process using the second photoresist pattern formed on the upper surface of the lead frame substrate 150 as a photomask is performed. The upper surface of the lead frame substrate 150 is etched by the second etching. According to this, the notch corresponding portion W3 is further singulated to form a notch 106 having a predetermined depth. The inter-foot-to-foot correspondence portion W1 is etched to a portion where the support portion 110 is formed, thereby causing the guide pin 121 and the inner guide pin 122 to be mutually insulated from each other and to insulate the inner guide pins 122 from each other. Thereafter, as shown in Fig. 32, the second photoresist patterns 144a, 144b remaining on the upper and lower surfaces of the lead frame substrate 150 are removed to form a lead frame 10. This second embodiment differs from the first embodiment in that, in the second embodiment, the second photoresist patterns 144a, 144b are removed after the second etching process (FIG. 31) of the lead frame substrate 150, but In the first embodiment, the second photoresist patterns 144a, 144b are removed before the second etching process (Fig. 14) of the lead frame substrate 15A. Here, since the first photoresist patterns 144a, 144b are removed after the support portion 11 is formed, the support portion 11 is convex (p〇truded) compared to the outer guide pins 124. In the second embodiment, since the second time, the d-step is performed in the first photoresist pattern 144a covering the lead 121 and the inner lead in 2, the lead 121 can be prevented during the second remnant procedure. Damaged with the inner guide foot (2). The procedure shown in FIGS. 33 and 34 is then performed to form a half 19 201101446 conductor chip package 2G. That is, as shown in Fig. 33, the semiconductor wafer 120 is placed in the recess 106, and then the semiconductor wafer 120 and the lead 121, and the semiconductor wafer 12 and the inner lead 122 are electrically connected using a wire 126. Thereafter, as shown in Fig. 34, the lead frame H), the semiconductor wafer 120 and the wires 126 are sealed together by using a sealant 13 to form a semiconductor chip package 20. Hereinafter, a further example of a method for manufacturing a lead frame and a semiconductor chip package according to a second embodiment will be described with reference to Figs. 37 to 49. 37 to 49 are cross-sectional views showing another example of a method for fabricating a semiconductor wafer package in accordance with a second embodiment of the present invention. As shown in FIG. 37, a lead frame substrate 150° made of metal is provided. As shown in FIG. 38, a photoresist 14 is coated on the upper surface and the lower surface of the lead frame substrate 15 The leadframe substrate 150 is then patterned by using the masks 17 and 172. With this patterning, one of the first photoresist patterns 142 as shown in Fig. 39 is formed. As shown in Fig. 40, a lead pin 121 and an inner lead 122 are formed on the upper surface of the lead frame 150, and an outer lead 124 is formed on the lower surface of the lead frame 150. Thereafter, as shown in FIG. 41, a photoresist 140b is coated on the upper surface and the lower surface of the lead frame substrate 150, and then the lead frame substrate 150 is patterned by using the masks 74 and 176 to form. One of the second photoresist patterns 144b, 144c is shown in FIG. In this embodiment, a dry film light 20 201101446 resistance (DFR) is used as the photoresist 140b. Here, the dry film photoresist can be formed into a stacked structure including a photosensitive material layer 242 and a protective crucible 240 stacked on the photosensitive material layer 242. Referring to FIG. 42, the second photoresist pattern 14 on the upper surface of the lead frame substrate 150 is used in a state in which the protective film 24 is removed, and in the state in which the protective film 24 is removed. A photoresist pattern 144b on the lower surface of the lead frame substrate 15 is used. The photosensitive material layer 242 of the second photo-cut 144e on the upper surface of the lead frame substrate 15G contains a pattern (10) with ultraviolet light and a pattern 242b which does not react with ultraviolet light. As shown in Fig. 43, by using the second photoresist pattern _ located under the lead frame substrate (9) as a reticle, the lower surface of the lead frame is first engraved to form an etched portion 112. This embodiment and the front frame substrate = (4) program outline = wire bundle = the 'filler-insulation material' in the shape of a pair of ir/Jzr, removed on the lead frame substrate - above the upper edge film 240 and then the developed light leaves you with no UV rays; e 242. With this development, only the pattern 242b of the reaction is '乍. As shown in Fig. 46, the corresponding portion W1 between the four guide pins is etched to the surface of the pattern 2, which is used as a mask, and the surface of the pattern 2 which does not react with ultraviolet light. The -Sr groove 106 is formed on the lead frame substrate 150 by the Sr program. And the suffix - the recess corresponding portion W3, with the 21 201101446 struts no, such that the _ 121 and the inner guide pins 122 are insulated from each other and the inner guide pins 122 are insulated from each other. As shown in FIG. 47, the second photoresist pattern M4b and the pattern 242b remaining on the upper surface and the lower surface of the lead frame substrate 15 without reacting with ultraviolet light are removed, thereby forming a lead frame 1 . As shown in Fig. 48 and Fig. 49, a semiconductor wafer 12 is mounted and then bonded by a wire 26. Thereafter, the semiconductor wafer package 120 is formed by sealing the semiconductor wafer 120 with a sealant. In view of the above, it is merely described that the present invention is intended to provide a solution to the problem, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made in accordance with the scope of the patent application of the present invention or the scope of the invention are covered by the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a related semiconductor chip package technology; FIG. 2 is a front plan view of a lead frame according to an embodiment of the present invention; FIG. 3 is a lead frame shown in FIG. Figure 4 is a cross-sectional view of the semiconductor wafer package of the lead frame of Figure 2 and Figure 3 taken along the Ι-Γ line of Figure 2 in accordance with the first embodiment of Figures 2 and 3; Figure 5 through Figure 16 are fabricated as Figure 4 is a cross-sectional view of the reticle used in the procedure of Figure 6; Figure 17 is a plan view of the reticle used in the procedure of Figure 9; 22 201101446 FIG. 20 and FIG. 21 are cross-sectional views showing a method of fabricating a support portion according to an embodiment of the present invention; FIG. 22 is a view showing a semiconductor of the lead frame used in a second embodiment of FIGS. 2 and 3 according to the present invention; A cross-sectional view of the wafer package taken along line Ι-Γ in FIG. 2; FIGS. 23 to 34 are cross-sectional views showing a method of manufacturing the lead frame and the semiconductor wafer package as in FIG. 22; FIGS. 35 and 36 are cross-sectional views showing a method of manufacturing the support portion. And Figures 37 to 49 are according to the present invention A second embodiment illustrates another example for a method for producing a semiconductor chip package ten of the cross-sectional view. [Main component symbol description] 200 semiconductor chip package 210 lead leg portion 10 lead frame 100 lead leg portion 102 horizontal portion 104 vertical portion 106 notch 110 support portion 110a insulating material 112 etching portion 116 die pad 120 semiconductor wafer 121 pin 23 201101446 122 Inner guide pin 124 External guide pin 126 Conductor 140 Sealant 140, 140a, 140b Photoresist 142a, 142b First photoresist pattern 144a, 144b, 144c Second photoresist pattern 150 Lead frame substrate 〇170, 172, 174, 176 Photomask 20 Semiconductor Wafer package 240 protective film 242 sensitive material layer 242a, 242b pattern A, B region SI opaque region O S2 transparent region T1, T2 thickness W1 guide portion between the legs W2 1 insect corresponding portion W3 notch corresponding portion 24

Claims (1)

201101446 七、申請專利範圍： 1. 一種導線架，包含： BB粒¥墊$ —半導體晶片安裝在該導線架之一 第一表面上之處； 至少-導腳部’將該半導體晶片電性連接到至少一 外部電路；以及 至少-支撐部’相鄰至與該第一表面相對的一第二 表面，該至少—切部包含―絕緣材料而使該至少-導 Ο 腳部彼此相互絕緣。 2. 如申請專利範圍第1項所述之導線架，其巾每—該至少 一導腳部包含選自由銅（Cu)、鐵㈣及其合金所組成之群 組的至少一者。 3. 如申請專利範圍第！項所述之導線架，其中該晶粒焊塾 包含一凹口（cavity)對應至安裝該半導體晶片的一區域。 4. 如申请專利範圍第1項所述之導線架，其中每一該至少 〇 一導腳部包含朝向該第一表面的一水平部，以及一垂直 部從該第-表面延伸至該第二表面，以及其中該導線架 包含呈少-内導腳與至少―外導腳，且其中該内導腳形 成在該第一表面上的該水平部，以及該外導腳形成在該 第二表面上的該垂直部。 5. 如申請專利範圍第4項所述之導線架，其中該至少一内 導腳的一寬度較小於該至少一外導腳的—寬度。 6·如申請專利範圍第4項所述之導線架，其中在該水平部 25 201101446 中，置放有該至少一内導腳的一部份比未置放有該至少 一内導腳的一部份較為凸出（protmded)。 7. 如申請專利範圍第4項所述之導線架，其中該至少一内 導腳與該至少一外導腳包含選自由至少由鎳（Ni)、鈀 (Pd)、金(Au)、銀(Ag)、錫（Sn)、銅（Cu)、鉻(Cr)及其合金 所組成之群組的至少一材料。 8. 如申請專利範圍第5項所述之導線架，其中該至少一支 撐部比該至少一外導腳較為凸出。 9·如申請專利範圍第5項所述之導線架，其中該至少一支 撐部的一表面與該至少一外導腳的一表面定位在同一平 面上。 10. 如申請專利範圍第i項所述之導線架，其中該導線架之 厚度.該至少一支撐部之一深度的比例為至 127:90。 11. 一種導線架，包含： D -導線架基板，具有—半導體晶片被安裝於上方的 一第一表面，以及相對該第一表面的一第二表面，其中 定義出-第-區域包含形成在該第二表面的至少一餘 刻部’以及除了該第-區域以外部份之一第二區域；以 及 至少-支撐部，形成在該第—區域的該至少一敍刻 部中並包含一絕緣材料，其令，該第二區域包含將該半 導體晶片連接到至少-外部電路的至少一導腳部，以及 26 201101446 該半導體晶片被安裝在上方的一晶粒焊墊。 12. —種用以製造導線架的方法，包含： 提供一導線架基板包含一半導體晶片被安裝在上方 的一第一表面，以及相對該第一表面的一第二表面； 利用钱刻該導線架基板形成至少一飯刻部在該第二 表面之一第一區域；以及 利用填充一絕緣材料在該至少一姓刻部中以形成至 少一支撐部。 13. 如申睛專利範圍第12項所述之用以製造導線架的方 法，其中该導線架基板包含一導電材料，以及除了該第 區域之外的一第二區域，該第二區域包含將該半導體 B曰片連接到至少一外部電路的至少一導腳部以及安裝 該半導體晶片在上方的一晶粒焊藝。 ’如申4專利範圍第13項所述之用以製造導線架的方 更包3於提供一導線架基板與形成至少一钱刻部的 〇 <間形成至少-内導腳與至少—外導腳電性連接至該 至少一導腳部。 15’如申請專利範圍第14項所述之用以製造導線架的方 其中忒至少一内導腳與該至少一外導腳的形成包 含： 形成一光阻圖案在該導線架基板上；以及 16形成一金屬材料在該光阻圖案的多個開口中。 申明專利範圍第13項所述之用以製造導線架的方 27 201101446 法，其甲該至少一餘刻部的形成包含： 形成一光阻圖案在該導線架基板上；以及 藉由使用該絲圖案作為—光相第_讀刻該導線 架基板的該第二表面。 17.如申請專·圍第16項所述之心製造導線架的方 法’其中於形成該至少—支撐部之後，該方法包含第二 人韻刻。亥導線架基板的該第一表面以使該至少一導卿 部彼此相互絕緣。 〇 18.如巾Μ專利範圍第17項所述之用以製造導線架的方 法’其中找第二次㈣中，—凹σ形成在該導線架基 板的該第一表面，而對應至安裝該半導體晶片的一位 置。 如申明專利範圍第16項所述之用以製造導線架的方 去其中δ亥方法包含在形成該至少一餘刻部與形成該至 少—支撐部之間移除該光阻圖案，以及在形成該至少一 ° 支撐部之後，第二次蝕刻該導線架基板的該第一表面以 減V β亥至少一導腳部的寬度與厚度並使該至少一導腳 部彼此相互絕緣。 2〇·如申請專利範圍第19項所述之用以製造導線架的方 法，其中在該第二次蝕刻中，一凹口形成在該導線架基 板的該第一表面，而對應至安裝該半導體晶片的一位 置。 28201101446 VII. Patent application scope: 1. A lead frame comprising: BB particles ¥ pads - where a semiconductor wafer is mounted on a first surface of the lead frame; at least - a lead portion ' electrically connecting the semiconductor wafer And to at least one external circuit; and at least the support portion is adjacent to a second surface opposite the first surface, the at least-cut portion comprising an "insulation material" to insulate the at least - guide leg portions from each other. 2. The lead frame of claim 1, wherein each of the at least one leg portion comprises at least one selected from the group consisting of copper (Cu), iron (tetra), and alloys thereof. 3. If you apply for a patent scope! The lead frame of the item, wherein the die pad comprises a cavity corresponding to an area in which the semiconductor wafer is mounted. 4. The lead frame of claim 1, wherein each of the at least one guide leg portion includes a horizontal portion facing the first surface, and a vertical portion extends from the first surface to the second portion a surface, and wherein the leadframe includes the horizontal portion having a small-inner guide and at least an outer guide, and wherein the inner guide is formed on the first surface, and the outer guide is formed on the second surface The vertical portion above. 5. The lead frame of claim 4, wherein a width of the at least one inner lead is smaller than a width of the at least one outer lead. 6. The lead frame of claim 4, wherein in the horizontal portion 25 201101446, a portion of the at least one inner guide pin is placed than a portion in which the at least one inner guide pin is not placed The part is more protmded. 7. The lead frame of claim 4, wherein the at least one inner lead and the at least one outer lead comprise from at least nickel (Ni), palladium (Pd), gold (Au), silver At least one material of the group consisting of (Ag), tin (Sn), copper (Cu), chromium (Cr), and alloys thereof. 8. The lead frame of claim 5, wherein the at least one support portion protrudes more than the at least one outer guide leg. 9. The lead frame of claim 5, wherein a surface of the at least one support portion is positioned on a same plane as a surface of the at least one outer guide leg. 10. The lead frame of claim i, wherein the thickness of the lead frame is a depth of one of the at least one support portion to 127:90. 11. A leadframe comprising: a D-lead carrier substrate having a first surface on which a semiconductor wafer is mounted, and a second surface opposite the first surface, wherein the -first region is defined to be formed At least one residual portion of the second surface and a second region other than the first region; and at least a support portion formed in the at least one cutout portion of the first region and including an insulation The material, wherein the second region comprises at least one leg portion connecting the semiconductor wafer to at least an external circuit, and 26 201101446 the semiconductor wafer is mounted on a die pad above. 12. A method for manufacturing a leadframe, comprising: providing a leadframe substrate comprising a first surface on which a semiconductor wafer is mounted, and a second surface opposite the first surface; The shelf substrate forms at least one rice portion in a first region of the second surface; and forms at least one support portion by filling an insulating material in the at least one surname portion. 13. The method for manufacturing a lead frame according to claim 12, wherein the lead frame substrate comprises a conductive material, and a second region other than the first region, the second region includes The semiconductor B-chip is connected to at least one lead portion of at least one external circuit and a die bonding technique on which the semiconductor wafer is mounted. The method for manufacturing a lead frame as described in claim 13 of claim 4 is to provide a lead frame substrate and a 〇 forming at least one of the nicks < forming at least an inner guide pin and at least The lead pin is electrically connected to the at least one lead leg. The method for manufacturing a lead frame according to claim 14, wherein the forming of the at least one inner lead and the at least one outer lead comprises: forming a photoresist pattern on the lead frame substrate; 16 forms a metal material in the plurality of openings of the photoresist pattern. A method of manufacturing a lead frame according to claim 13 of the invention, wherein the forming of the at least one portion includes: forming a photoresist pattern on the lead frame substrate; and using the wire The pattern acts as the optical phase to read the second surface of the leadframe substrate. 17. The method of manufacturing a lead frame as claimed in claim 16 wherein the method comprises a second person after forming the at least the support portion. The first surface of the lead frame substrate is insulated such that the at least one guide portion is insulated from each other. 〇18. The method for manufacturing a lead frame according to claim 17, wherein in the second (four), a concave σ is formed on the first surface of the lead frame substrate, and corresponding to mounting A location of a semiconductor wafer. The method for manufacturing a lead frame according to claim 16, wherein the method includes removing the photoresist pattern between forming the at least one residual portion and forming the at least one support portion, and forming After the at least one-degree support portion, the first surface of the lead frame substrate is etched a second time to reduce the width and thickness of at least one of the lead portions and to insulate the at least one lead portion from each other. The method for manufacturing a lead frame according to claim 19, wherein in the second etching, a notch is formed on the first surface of the lead frame substrate, and corresponding to mounting A location of a semiconductor wafer. 28
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US8557638B2 (en) * 2011-05-05 2013-10-15 Stats Chippac Ltd. Integrated circuit packaging system with pad connection and method of manufacture thereof
JP2016009746A (en) * 2014-06-24 2016-01-18 凸版印刷株式会社 Lead frame substrate with resin and manufacturing method for the same

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CN106981470A (en) * 2015-10-23 2017-07-25 新光电气工业株式会社 Lead frame and its manufacture method

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