4 62115 6483twf.doc/008 A7 _____B7_ 五、發明說明（I ) 本發明是有關於一種自行對準金屬矽化物（Self-Aligned Silicide, Salicide)的製作方法，且特別是有關於一 種降低片電阻（Sheet Resistance)及接觸電阻（Contact Resistance)之自行對準金屬矽化物的製作方法。 隨著半導體元件積集度增加，元件中之圖案與線寬亦 逐漸縮小，導致元件中之閘極與導線的接觸電阻增高，產 生較長的電阻-電容延遲(RC Delay)，影響元件操作速度。 由於金屬砂化物之電阻較多晶砂(Polysilicon)低，且其熱穩 定性也比一般內連線材料(例如鋁）高，因此爲了降低汲極 (Drain)與源極（Source)的片電阻（Sheet Resistance)，並確保 金屬與半導體兀件之間淺接面(Shallow Junction)的完整， 可在閘極與源極/汲極和金屬連線的連接介面形成金屬矽化 物’以降低閘極與源極/汲極和金屬連線之間的電阻。傳統 方法是在含矽材料層上形成金屬層，經熱製程使覆蓋於含 砂材料層上的金屬與矽反應形成金屬矽化物；或是直接在 含矽材料層上覆蓋金屬矽化物。目前在半導體元件製程 中’廣泛被採用的則是自行對準金屬矽化物之製程。 自行對準金屬矽化物的形成方式，是先在半導體晶片 上形成金屬層，最常使用的金屬材料是鈦。然後將晶片送 進高溫環境中，使覆蓋於閘極和源極/汲極上方之金屬層， S爲與矽接觸而在高溫下反應產生金屬矽化物。並且在高 溫環境下使其結構產生相轉變，以形成電阻値較低的金屬 砂化物。在晶片其他部分上，由於金屬層並未與矽接觸， 雖然經過高溫處理，也不會產生金屬矽化物。因爲在形成 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公嫠〉 {請先閲讀背面之注意事項再填寫本頁> :裝 > ^-nJa 線- 經濟部智慧財產局員工消费合作社印製 462115 6483twf.doc/008 五、發明說明（π) 金屬砂化物時’不必經過微影（Photolithography)製程的步 驟，所以這種金屬矽化物稱爲自行對準金屬矽化物。 <請先閱讀背面之注#^項再填窝本頁) 請參照第1A圖至第1B圖，其繪示依照習知之自行對 準金屬矽化物製作方法的剖面示意圖。如第1A圖所示， 在半導體基底100上依序形成一閘氧化層1〇1與一多晶矽 層102，再定義形成一閘極1〇3，其次於閘極103之側壁製 作間隙壁（Spacer)104,並對基底1〇〇進行離子植入（l〇n Implantation)，在閘極1(B兩側形成源極/汲極區〇接著 於基底100之上，使用磁控直流濺鍍（DC Magnetron Sputtering)形成鈦金屬層108，以覆蓋閘極103、間隙壁104 和源極/汲極區106。 其次請參照第1B圖，對第1A圖中表面覆有鈦金屬層 108之基底100加熱，進行快速加熱製程（Rapid Thermai Processing，RTP) ’使位於閘極中多晶矽層i〇2以及源極/汲 極區106上方之鈦金屬層108與矽產生反應，形成材質爲 C-49相矽化鈦(Τβΐ2)的自行對準金屬矽化物11〇。再將未 參與矽化反應或反應後剩餘的鈦金屬層移除，完成自行對 準金屬矽化物110之製作。 經濟部智慧財產局員工消費合作社印製 然而隨著元件尺寸的日漸縮小，金屬矽化物的成長會 因金屬矽化物與複晶矽接觸的應力（stress)太大，或是成核 位置(.nucleation site)太少，造成TiSix的比例有變，導致 金屬矽化物薄膜品質不佳，形成島狀（island)的金屬矽化物 層’因此粗糙的金屬矽化物層致使阻値上升，而影響閘極 操作的效能。 4 本^>張尺度適用中國國家標準（CNS)A4規格ΰΐΟ X 297公爱) d 621 1 5 6483twf.doc/008 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（巧） 有鑑於此’本發明之目的在提供一種自行對準金屬矽 化物之製造方法’可加強熱穩定度，避免因線寬縮小而使 元件品質降低的現象發生，以便更有利於元件尺寸的減小 或元件間距離的縮短，以及提供較佳之電性操作。 根據本發明之上述及其他目的，提出一種自行對準金 屬矽化物的製作方法’首先提供基底，於基底上依序形成 一閘氧化層與一多晶矽層。再定義該多晶矽層和該閘氧化 層以形成閘極結構，於閘極結構之側壁製作間隙壁，並在 基底中形成源極/汲極區。然後進行一間隙壁蝕刻步驟，使 間隙壁之寬度減少。接著在基底上沈積金屬層，再進行熱 處理，因爲較窄的間隙壁，而可以在源極/集極區上形成較 寬、品質較佳的自行對準金屬矽化物以降低電阻、_高半 導體元件之效能。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1B圖繪示習知自行對準金屬矽化物製作 方法的剖面示意圖；以及 第2A圖至第2H圖繪示依照本發明之較佳實施例，一 種自行對準金屬矽化物的製作方法，其製作流程之剖面示 意圖。 圖式之標記說明： 100、200 :基底 5 ^紙張尺度適用中®國家標準（CNS)A4規格（210 X ?97公釐） _ !·ι·!ΐ—·! - I I l· I I I 訂 <請先閱讀背面之注$項再填寫本頁> b2 1 1 5 6483twf.doc/008 A7 _B7_ 五、發明說明) 101、201、201a :閘氧化層 102 ' 202、202a :多晶砂層 103、 203 :閘極結構 (請先閲讀背面之注意事項再填窵本頁) 104、 204 ' 204a :間隙壁 205 :絕緣層 106、206a、206b :源極/汲極區 108、208 :金屬層 110、210、210a :自行對準金屬矽化物 實施例 第2A圖至第2H圖，其繪示依照本發明之較佳實施例 的一種自行對準金屬矽化物製作方法之剖面流程示意圖。 請參照第2A圖，首先提供半導體基底200，並於基底 200上依序形成一閘氧化層201與一多晶矽層202。其中形 成多晶砂層202之方法包括化學氣相沈積法(Chemical Vapor Deposition, CVD)。 經濟部智慧財產局員工消費合作社印製 其次請參照第2B圖，定義第2A圖中位於基底200上 之閘氧化層201和多晶矽層202，以形成閘極結構203。其 中閘極結構203包括閘氧化層201a與多晶矽層202a，而 定義形成閘極結構203之步驟則包括微影、蝕刻等。以閘 極結構203爲罩幕，對基底200進行離子植入，將低摻雜 劑量之雜質植入基底200中，形成輕摻雜源極/汲極區 206a。 再請參照第2C圖，在基底200上形成絕緣層205，以 覆蓋輕摻雜源極/汲極區206a和閘極結構203。其中形成 6 本紙張尺度適用尹國國家標準（CNS)A4規格（2】0 X 297公芨） 4 621 1 5 6483twf.doc/008 A7 B74 62115 6483twf.doc / 008 A7 _____B7_ 5. Description of the Invention (I) The present invention relates to a method for making self-aligned silicide (Salicide), and in particular to a method for reducing sheet resistance ( Sheet resistance) and contact resistance (self-aligned metal silicide) manufacturing method. As the accumulation of semiconductor elements increases, the patterns and line widths in the elements also gradually decrease, causing the contact resistance between the gate and the wires in the element to increase, resulting in a longer resistance-capacitance delay (RC Delay), which affects the operation speed of the element . Because metal sand has more resistance than polysilicon, and its thermal stability is higher than that of general interconnect materials (such as aluminum), in order to reduce the sheet resistance of the drain and source (Sheet Resistance) and ensure the integrity of the Shallow Junction between the metal and the semiconductor element. A metal silicide can be formed at the connection interface between the gate and the source / drain and the metal connection to reduce the gate. Resistance to source / drain and metal wiring. The traditional method is to form a metal layer on the silicon-containing material layer, and react the metal covering the sand-containing material layer with silicon to form a metal silicide through a thermal process; or directly cover the silicon-containing material layer with a metal silicide. At present, the process of self-aligning metal silicide is widely used in semiconductor device process. Self-aligned metal silicide is formed by first forming a metal layer on a semiconductor wafer. The most commonly used metal material is titanium. The wafer is then placed in a high-temperature environment, so that the metal layer covering the gate and source / drain electrodes, S is in contact with silicon and reacts at high temperature to generate metal silicide. And in the high temperature environment, its structure undergoes phase transformation to form metal sands with lower resistance. On other parts of the chip, since the metal layer is not in contact with silicon, no metal silicide is generated even after high temperature processing. Because in the formation of 3 paper standards, the Chinese National Standard (CNS) A4 specification (210 x 297 cm) is applied {Please read the precautions on the back before filling out this page >: packing > ^ -nJa line-Ministry of Economics Intellectual Property Printed by the Bureau ’s Consumer Cooperatives 462115 6483twf.doc / 008 V. Description of the invention (π) Metal sands do not need to go through the steps of the photolithography process, so this metal silicide is called self-aligned metal silicide. (Please read Note # ^ on the back before filling in this page) Please refer to Figures 1A to 1B, which are schematic cross-sectional views showing the method of self-aligning metal silicide according to the conventional method. As shown in FIG. 1A, a gate oxide layer 101 and a polycrystalline silicon layer 102 are sequentially formed on the semiconductor substrate 100, and then a gate electrode 103 is defined, followed by a spacer (Spacer) ) 104, and perform ion implantation on the substrate 100, forming a source / drain region on both sides of the gate 1 (B), and then on the substrate 100, using magnetron DC sputtering ( DC Magnetron Sputtering) to form a titanium metal layer 108 to cover the gate 103, the spacer 104, and the source / drain region 106. Next, referring to FIG. 1B, the substrate 100 with the titanium metal layer 108 on its surface in FIG. 1A Heating, performing rapid heating process (Rapid Thermai Processing, RTP) 'The titanium metal layer 108 located above the polycrystalline silicon layer i02 in the gate and the source / drain region 106 reacts with silicon to form a C-49 phase material. Self-aligned metal silicide 11 of titanium silicide (Tβ 对准 2). Then remove the remaining titanium metal layer that did not participate in the silicidation reaction or reaction to complete the self-aligned metal silicide 110 production. Consumption by staff of the Intellectual Property Bureau of the Ministry of Economic Affairs Co-operative printing however with increasing component size Shrinking, the growth of the metal silicide will be due to the stress of the metal silicide in contact with the polycrystalline silicon is too large, or too few nucleation sites (.nucleation site), resulting in a change in the ratio of TiSix, resulting in metal silicide film Poor quality, forming an island-like metal silicide layer '. Therefore, the rough metal silicide layer causes the resistance to rise, which affects the performance of the gate operation. 4 This ^ > Zhang scale is applicable to Chinese National Standards (CNS) A4 specifications (ΰΐ〇 X 297 public love) d 621 1 5 6483twf.doc / 008 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 V. Description of the invention The manufacturing method of silicide can enhance the thermal stability, avoid the phenomenon of reducing the quality of the device due to the reduction of the line width, so as to be more conducive to reducing the size of the device or the distance between the devices, and to provide better electrical operation. According to the above and other objects of the present invention, a method for manufacturing a self-aligned metal silicide is provided. First, a substrate is provided, and a gate oxide layer and a polycrystalline silicon layer are sequentially formed on the substrate. The polycrystalline silicon layer and the gate oxide layer are further defined to form a gate structure. A spacer wall is formed on a side wall of the gate structure, and a source / drain region is formed in the substrate. Then, a spacer etching step is performed to reduce the width of the spacer. Then deposit a metal layer on the substrate, and then perform heat treatment. Because of the narrow gap wall, a wider and better quality self-aligned metal silicide can be formed on the source / collector region to reduce resistance and high semiconductor Component performance. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A to FIG. 1B shows a schematic cross-sectional view of a conventional self-aligned metal silicide manufacturing method; and FIGS. 2A to 2H show a self-aligned metal silicide manufacturing method according to a preferred embodiment of the present invention. Schematic cross-section of the production process. Explanation of drawing symbols: 100, 200: 5 substrates ^ Applicable to Chinese Standards (CNS) A4 (210 X? 97 mm) _! · Ι ·! Ϊ́— ·!-II l · III Order < Please read the note on the back before filling in this page> b2 1 1 5 6483twf.doc / 008 A7 _B7_ V. Description of the invention 101, 201, 201a: Gate oxide layer 102 '202, 202a: Polycrystalline sand layer 103 , 203: Gate structure (please read the notes on the back before filling this page) 104, 204 '204a: Spacer 205: Insulation layers 106, 206a, 206b: Source / drain regions 108, 208: Metal layer 110, 210, and 210a: Figures 2A to 2H of the self-aligned metal silicide embodiment, which are schematic cross-sectional flow diagrams of a method for manufacturing a self-aligned metal silicide according to a preferred embodiment of the present invention. Referring to FIG. 2A, a semiconductor substrate 200 is first provided, and a gate oxide layer 201 and a polycrystalline silicon layer 202 are sequentially formed on the substrate 200. The method for forming the polycrystalline sand layer 202 includes a chemical vapor deposition method (Chemical Vapor Deposition, CVD). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Please refer to FIG. 2B to define the gate oxide layer 201 and the polycrystalline silicon layer 202 on the substrate 200 in FIG. 2A to form the gate structure 203. The gate structure 203 includes a gate oxide layer 201a and a polycrystalline silicon layer 202a, and the steps for defining the gate structure 203 include lithography, etching, and the like. With the gate structure 203 as a mask, ion implantation is performed on the substrate 200, and impurities with a low doping dose are implanted into the substrate 200 to form a lightly doped source / drain region 206a. Referring to FIG. 2C again, an insulating layer 205 is formed on the substrate 200 to cover the lightly doped source / drain regions 206a and the gate structure 203. Among them, 6 paper standards are applicable to Yin National Standard (CNS) A4 specifications (2) 0 X 297 cm. 4 621 1 5 6483twf.doc / 008 A7 B7
經濟部智慧財產局員工消費合作社印W 五、發明說明（ζ ) 絕緣層205之材質包括氧化矽或氮化矽，其中氧化矽例如 爲四乙基-鄰-砂酸酯（Tetra-Ethyl-Ortho-Silicate，TEOS)，形 成之方法則包括化學氣相沈積法等，例如是低壓化學氣相 沈積法(LPCVD)。 請參照第2D圖，移除第2C圖中部份之絕緣層205， 在閘極結構203側壁形成間隙壁204,並曝罐出多晶矽層 202a及部份基底200。其中間隙壁204之厚度約在500A 至2000A之間，而移除部份絕緣層之方法包括非等向性蝕 刻法，採用回蝕刻(Etching Back)方式進行。然後以閘極結 構203與間隙壁204爲罩幕，對基底200植入高摻雜劑量 之雜質，以形成重摻雜源極/汲極區206b，並由輕摻雜源 極/汲極區206a和重摻雜源極/汲極區206b共同組成源極/ 汲極區206。在本發明之另一實施例中，也可以等到較窄 的間隙壁204a形成之後，利用閘極結構203與較窄的間隙 壁204a爲罩幕，對基底200植入高摻雜劑量之雜質，以形 成重摻雜源極/汲極區（未圖示）。 接著請參照第2E圖，進行一間隙壁蝕刻步驟，移除 一部分的間隙壁204，使間隙壁204之寬度減少，而變爲 較窄的間隙壁204a。其中較窄的間隙壁204a之厚度約在 10A至1000A之間，而部分移除間隙壁204之方法包括濕 式蝕刻法等，例如是使用熱磷酸溶液以濕式浸漬方式，移 除材質爲氮化矽之間隙壁204 ;或是乾式蝕刻法，例如反 應性離子蝕刻法(RIE)。藉由減少間隙壁204之寬度，可在 閲 讀 背 項 再 填 寫 本 頁 裝 I I 訂 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） 4 62115 6483twf.doc/008 A7 經濟部智慧財產局具工消费合作社印製 五、發明說明（& ) _ 後續製程中形成於源極/集極區206上形成較寬較厚的自行 對準金屬矽化物210。 然後請參照第2F圖’形成一金 屬層208覆蓋於在源極/汲極區206、間隙壁2〇4a及多晶矽 層202a上。其中形成該金屬層208之材質包括鈦、鈷等’ 而形成方法包括濺鍍法，例如磁控直流濺鍍。 請參照第2G圖，進行一熱處理步驟，使第2F圖中之 金屬層208與所覆蓋之源極/汲極區206和多晶矽層202a 的矽產生矽化反應，分別在源極/汲極區206及多晶矽層 202a表面形成自行對準金屬矽化物210。其中該熱處理步 驟包括快速加熱製程，溫度設定約爲攝氏500-800度，而 形成之自行對準金屬矽化物220的材質包括矽化鈦或矽化 鈷等，例如是C-49相矽化鈦。 再請參照第2H圖，將未參與矽化反應或反應後剩餘 的金屬層208移除，以曝露出自行對準金屬矽化物210及 間隙壁204a。移除未反應之金屬層的方法包括溼式蝕刻。 然後進行第二熱處理步驟，使位於源極/汲極區206及多晶 矽層202a表面的自行對準金屬矽化物210緻密化，以獲得 所需之低電阻自行對準金屬矽化物210a。其中第二熱處埋 步驟包括快速加熱製程，溫度設定約爲攝氏6〇0_9〇〇度， 可以使原先自行對準金屬矽化物中電阻率約爲60至9〇微 歐姆-公分之C-49相矽化鈦轉變爲電阻率約爲5至30微歐 姆-公分之C-54相矽化鈦。 由上述本發明之較佳實施例可知，本發明的一個蔞要 特徵是在形成自行對準金屬矽化物前，進行一間隙壁軸刻 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 297公釐） <請先閱讀背面之注意ί項再填寫本頁> 裝 訂_· -線 462115 6483twf.doc/008 A7 B7 五、發明說明o ) 步驟，使間隙壁之寬度減少。接著在基底上沈積金屬層， 再進行熱處理，因爲較窄的間隙壁，而可以在源極/集極區 上形成較厚、品質較佳的自行對準金屬矽化物以降低電 阻'提高半導體元件之良率。 綜上所述，本發明因爲間隙壁之寬度較窄，故形成自 行對準金屬矽化物時，可以在源極/汲極形成較_寬且較均勻 之金屬矽化物，因此可以擴大熱處理步驟之製程容許範圍 (如回火溫度及時間等），對自行對準金屬矽化物之形成有 所助益，並可提高自行對準金屬矽化物的品質以及半導體 元件良率。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 n n n ki · n ϋ n K n ϋ n · ----線〆 (請先閲讀背*之注$項再填寓本頁} 經濟部智慧財產局員Η消費合作社印製 9 本紙張尺度適用t國國家標準（CNS)A4規格<210 X 297公釐）Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (ζ) The material of the insulating layer 205 includes silicon oxide or silicon nitride, where the silicon oxide is, for example, Tetra-Ethyl-Ortho -Silicate (TEOS). The formation method includes chemical vapor deposition, for example, low pressure chemical vapor deposition (LPCVD). Referring to FIG. 2D, a part of the insulating layer 205 in FIG. 2C is removed, a spacer wall 204 is formed on the sidewall of the gate structure 203, and a polycrystalline silicon layer 202a and a part of the substrate 200 are exposed. The thickness of the spacer 204 is between 500A and 2000A, and the method of removing a part of the insulating layer includes an anisotropic etching method, which is performed by an etch back method. Then, using the gate structure 203 and the spacer 204 as a mask, a high doping dose of impurities is implanted into the substrate 200 to form a heavily doped source / drain region 206b, and a lightly doped source / drain region is formed. 206a and the heavily doped source / drain region 206b together form the source / drain region 206. In another embodiment of the present invention, the gate structure 203 and the narrow gap wall 204a may be used as a mask after the narrow gap wall 204a is formed, and a high doping dose of impurities is implanted into the substrate 200. To form a heavily doped source / drain region (not shown). Next, referring to FIG. 2E, a spacer etching step is performed to remove a part of the spacer 204, so that the width of the spacer 204 is reduced to become a narrower spacer 204a. The thickness of the narrower spacer wall 204a is between 10A and 1000A, and the method of partially removing the spacer wall 204 includes wet etching. For example, the wet phosphoric acid solution is used to remove the material by nitrogen. Silicon spacers 204; or dry etching, such as reactive ion etching (RIE). By reducing the width of the gap 204, you can fill in the back page after reading the second page. The size of the paper is applicable to the national standard (CNS) A4 specification (210 X 297 mm) 4 62115 6483twf.doc / 008 A7 Economy Printed by the Ministry of Intellectual Property Bureau ’s Industrial and Consumer Cooperatives V. & Description of Invention _ In the subsequent process, a wider and thicker self-aligned metal silicide 210 is formed on the source / collector region 206. Then, referring to FIG. 2F ', a metal layer 208 is formed to cover the source / drain region 206, the spacer 204a, and the polycrystalline silicon layer 202a. The material for forming the metal layer 208 includes titanium, cobalt, and the like, and the forming method includes a sputtering method, such as magnetron DC sputtering. Referring to FIG. 2G, a heat treatment step is performed, so that the metal layer 208 in FIG. 2F generates silicidation reaction with the silicon of the covered source / drain region 206 and the polycrystalline silicon layer 202a, respectively in the source / drain region 206. A self-aligned metal silicide 210 is formed on the surface of the polycrystalline silicon layer 202a. The heat treatment step includes a rapid heating process, and the temperature is set to about 500-800 degrees Celsius. The material of the self-aligned metal silicide 220 formed includes titanium silicide or cobalt silicide, such as C-49 phase titanium silicide. Referring to FIG. 2H again, the metal layer 208 that is not involved in the silicidation reaction or after the reaction is removed to expose the self-aligned metal silicide 210 and the spacer 204a. The method of removing the unreacted metal layer includes wet etching. A second heat treatment step is then performed to densify the self-aligned metal silicide 210 on the surface of the source / drain region 206 and the polycrystalline silicon layer 202a to obtain the required low-resistance self-aligned metal silicide 210a. The second thermal embedding step includes a rapid heating process. The temperature is set to about 6,000-900 degrees Celsius, which allows the original self-alignment of the resistivity in the metal silicide to be about 60 to 90 microohm-cm-C-49. The phase titanium silicide is transformed into a C-54 phase titanium silicide having a resistivity of about 5 to 30 microohm-cm. It can be known from the above-mentioned preferred embodiments of the present invention that one of the main features of the present invention is to perform a spacer wall engraving before forming a self-aligned metal silicide. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 297 mm) < Please read the note on the back before filling this page > Binding _ · -line 462115 6483twf.doc / 008 A7 B7 V. Description of the invention o) steps to reduce the width of the gap wall. Next, a metal layer is deposited on the substrate and then heat-treated. Due to the narrow gap wall, a thicker and better-quality self-aligned metal silicide can be formed on the source / collector region to reduce the resistance and improve the semiconductor element. The yield. In summary, the present invention has a narrow width of the barrier wall, so when forming a self-aligned metal silicide, a wider and more uniform metal silicide can be formed at the source / drain, so the heat treatment step can be expanded. Process tolerances (such as tempering temperature and time) are beneficial to the formation of self-aligned metal silicide, and can improve the quality of self-aligned metal silicide and the yield of semiconductor components. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. nnn ki · n ϋ n K n ϋ n · ---- line 〆 (Please read the note of the back * before filling in this page} Printed by a member of the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 9 This paper is applicable to t countries National Standard (CNS) A4 Specification < 210 X 297 mm)