經濟部智慧財產局員工消費合作社印製 本發明是有關於一種半導體圖案化的方法，且特別 是有關於一種同時於對準標記之晶方(Die)與其他晶方上形 成圖案的方法。 微影（Photolithography)，是製造半導體元件成敗與 否的關鍵步驟，故而在半導體製程中，其佔著舉足.輕重的 地位。以一般製作元件的製程爲例，通常一個產品依其複 雜性的不同，所需要的微影、曝光步驟，約在1〇至18次 左右。爲使光罩的圖案能正確地轉移到晶'片£，通常，半 導體製作的過程中，在每一次執行光阻的曝光之前，必須 做好各層之間的對準，以避免不當的圖案轉移，而導致整 個晶片報廢的情況發生。 在傳統的曝光製程中，係在欲形成半導體元件之晶圓 上形成與光罩相對應的對準標記（Alignment Mark)來達到 對準的目的。爲了避免對準標記在製程中遭受破壞，通常 對準標記的周圍並不會形成圖案，然而，在製程上卻衍生 其他的問題，例如是在形成淺溝渠隔離結構時，對準標記 周圍的空礦區在施行化學機械硏磨製程之後會面臨氧化層 的殘餘等問題。 以下將以淺溝渠隔離結構的製造方法作爲說明。第1A 圖至第1C圖是習知一種淺溝渠隔離結構之製造流程的剖 面圖。 請參照第1A圖，典型的方法係在已形成有對準標記 102的基底100上形成一層罩幕層104，再於罩幕層1〇4上 形成一層圖案化的光阳層106，並藉其圖案化置墓曆104。 3 (請先閱讀背面之注意事項再填寫本頁) ’袭 ϋ n n ----訂---------难， ;3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 459298 A7 B7 6050twf2/002 五、發明說明（7) 接著’以光1層106與罩幕層104爲餓刻罩幕，蝕去部分 的基底100，以在基底100中形成溝渠108。 (請先閱讀背面之注意事項再填寫本頁) 其後’請參照第1B圖，去除光阻層1〇6並在基底100 上形成一層氧化矽層110’以覆蓋罩幕層104,並將溝渠108 塡滿》 之後，請參照第1C圖’以罩幕層104作爲硏磨終止層， 利用化學機械硏磨法去除多餘的氧化矽層110，留下溝渠 106之中的氧化矽層110a。最後再將罩幕層1〇4去除。 由於晶片上溝渠的密度不一，且在晶片上包括許多未 形成隔離結構的空曠區，例如是對準標記102周圍的空礦 區，因此，上述習知方法在硏磨去除罩幕層104表面上的 氧化層110時，位於空曠區112上的氧化層110會因爲化 學機械硏磨法其硏磨的特性而留在空曠區112上，而形成 殘留的氧化層ll〇b。 習知一種爲了改善氧化層殘留於空曠區的方法，係在 基底100的空曠區112中形成虛擬的隔離區，以使化學機 械硏磨製程具有均勻性，其製造的流程如第2A圖至第2D 圖所示。 經濟部智慧財產局員工消費合作社印製 請參照第2A圖，典型的作法係在用以定義隔離區之光 阻層106中，同時經由曝光製程，使曝光之處形成隔離區 圖案114與虛擬隔離區的圖案116。 請參照第2B圖，以顯影製程將光阻層106遭受曝光之 處去除，以使留下的光阻層106具有溝渠圖案114與虛擬 隔離區的圖案。之後，以光阻層106爲罩幕’蝕刻罩幕 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 6〇5〇4>f§C^2 9 8 A7 ________ B7 五、發明說明（>) 層104與基底100’以形成隔離區之溝渠1〇8與虛擬隔離區 之虛擬溝渠118。 請參照第2C圖，之後’將光阻層106去除，再於基底 100上形成一層氧化層110，以覆蓋罩幕層104並且將溝渠 108與虛擬溝渠118塡滿β 請參照第2D圖，以化學機械硏磨製程將罩幕層1〇4上 所覆蓋的氧化層110去除。 最後將罩幕層104去除，以在基底1〇〇中形成隔離區 110a與虛擬隔離區ll〇C。 上述在基底中形成虛擬隔離區的方法，係在同一層光 阻層106中，形成溝渠圖案114與虛擬隔離區的圖案116， 如第2A圖所示。其在進行曝光製程時，係將第4圖所示之 光罩400上的圖案逐一轉移至第3圖所示之晶片100上的 每一個曝光區塊120，使基底（晶片）100上的光阻層106形 成溝渠圖案1 Η之後，再將光罩400的圖案轉移至對準標 記102其周圍的空曠區112上，方能在同一層光阻層110 中形成虛擬溝渠圖案116。 請參照第3圖，由於晶片上形成對準標記102之區塊 122的大小，與每一次曝光製程的曝光區塊120的大小並不 相同，因此，進行虛擬隔離區圖案116的曝光製程時，係 將第4圖之光罩400上鍍有鉻膜402的一邊角（例如是左上 邊角）404對準對準標記區塊122的一邊角（例如是左上邊 角）130，並且利用曝光機台中用以遮蔽光罩的不透光葉片 (Blade)300來遮蔽光罩400上對應於對準標記102以及部分 5 (猜先閲讀背面之注意事項再填寫本頁) 裝----訂.！------線一' 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 459298 6050twf2/002 A7 B7 五、發明說明（y) 的對準標記區塊122之處，使曝光的光線可以透過光罩400 上的鉻膜402以及機台的不透光葉片300的遮蔽作用，使 曝光光線僅能通過一特定區域，進而使光罩400上其一邊 角404的溝渠圖案順利轉移至區塊122其邊角130之上。 而對準標記區塊Π2其其他邊角上的光阻層106,則須再以 同樣的方法，方能形成虛擬隔離圖案116。 以上述方法必須經由多次的曝光製程，方能在對準標 記區塊122上的光阻層106形成虛擬隔離區圖案116,其方 法不但費時、降低機台的產能(Throughput)而且會增加機台 其不透光葉片的損耗，因此，上述的方法亦會造成製造成 本的增加。 此外，爲了減少對準標記區塊122上之光阻層106形 成虛擬隔離區圖案116所需的曝光次數，通常，對準標記 102係形成在對準標記區塊122緊鄰另一晶方的一邊，如第 3_圖之放大圖所示者，而不會形成在對準標記122的中心之 處。然而，依此方法卻會使得後續的硏磨製程影響對準標 記102其周邊的晶片。 本發明提供一種半導體圖案化的方法，可以同時於對 準標記之晶方與其他晶方上形成圖案。 本發明提供一種半導體圖案化的方法，可以快速地完 成晶片的曝光製程。 本發明提供一種半導體圖案化的方法，可以將對準標 記配置於對準標記區塊的中心之處，以減少對準標記對周 邊晶片的影響。 6 本紙張尺度適@國家標準（CNS)A4規格（210 X 297公爱） <請先閲讀背面之注意事項再填寫本頁) 裝--------訂---------線 經濟部智慧財產局員工消費合作社印製 45929 8 6050twf2/002 A7 _____B7____ 五、發明說明（t ) 本發明提供一種半導體圖案化的方法，可以降低半導 體的製造成本。 本發明提供一種淺溝渠隔離結構的製造方法，可以在 進行化學機械硏磨製程時提供均勻的硏磨速率。 本發明提出一種半導體元件的製造方法，此方法係將 晶片區分爲數個第一曝光區塊與數個第二曝光區塊，並在 第一曝光區塊的其中一個晶方中形成對準標記之後，在晶 片上形成一層待圖案化層，然後，在待欄案化層上形成一 層負光阻，再進行第一曝光製程，以逐一在第一曝光區塊 與第二曝光區塊上的負光阻中形成數個第一受曝光區與數 個未遭受曝光區，接著，再進行第二曝光製程，以在對準 標記之上方所覆蓋的負光阻形成第二受曝光區，而此第二 受曝光區與對準標記上方之第一受曝光區及未遭受曝光區 重疊並涵蓋對準標記之區域，之後，進行一顯影步驟，以 去除未受曝光區之負光阻，裸露出待圖案化層，再以負光 阻爲罩幕，去除負光阻所裸露之待圖案化層，以使待圖案 化層圖案化，最後，再去除負光阻。 本發明提出一種淺溝渠隔離結構的製造方法，此方法 係提供一基底，此基底具有複數個晶方，且此基底區分爲 數個第一曝光區塊與數個第二曝光區塊，接著，在第一曝 光區塊中的其中一個晶方形成對準標記。然後，在基底上 形成一層罩幕層，再於罩幕層上形成一層負光阻層。之後， 進行第一曝光製程，逐一在第一曝光區塊與第二曝光區塊 上的負光阻層中形成數個第一受曝光區與數個未遭受曝光 7 (請先閱讀背面之注i項再填寫本頁) -裝 ''5·· 4. 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐） 459298 6050twf2/002 pj _B7_ 五、發明說明（6) 區，其中未遭受曝光區具有數個溝渠圖案。然後，進行第 二曝光製程，於對準標記之上方所覆蓋的負光阻層形成一 第二受曝光區，其中，第二受曝光區與對準標記上方之第 一受曝光區及未遭受曝光區之溝渠圖案重疊並涵蓋對準標 記之區域。之後，進行一顯影步驟，去除未受曝光區之負 光阻層，使負光阻層形成溝渠圖案，其中，溝渠圖案裸露 出罩幕層，之後，以負光阻層爲罩幕，去除負光阻層所裸 露之罩幕層，以使罩幕層形成溝渠圖案。其後，去除負光 阻層，再以罩幕層爲罩幕，去除罩幕層之溝渠圖案所裸露 之部分基底，以在第一曝光區塊與第二曝光區塊之晶方中 形成數個溝渠，然後，在晶片上形成一層絕緣層，以覆蓋 罩幕層，並塡滿溝渠，再以化學機械硏磨製程去除罩幕層 上所覆蓋之絕緣層，最後，將罩幕層去除，使留在第二曝 光區塊其溝渠之中的絕緣層形成一隔離區，而留在第一曝 光區塊其溝渠之中的絕緣層則做爲一虛擬隔離區。 依照本發明實施例所述，上述具有對準標記的第一曝 光區塊的大小與其他之第二曝光區塊的大小相同，因此， 在進行上述曝光製程時，僅需以步進機同時依序進行曝光 製程，即可在具有對準標記的第一曝光區塊中曝出預定的 圖案。換言之，此方法僅需以一次的曝光製程即可以完成 具有對準標記之第一曝光區塊的曝光製程，相較於習知需 以多次方能完成之方法，本發爲一種較爲快速，且是一種 可以增加產能，可以降低機台不透光葉片損耗，降低製造 成本的方法。 8 (請先閲讀背面之注意事項再填寫本頁) ' n n n -i-r-ejI I n n n n 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 459298 6050twf2/002 A7 B7 五、發明說明（ο ) 此外，本發明在基底上所形成的負光阻層，可以利用 光罩上淸除區周緣的鉻膜對準對準標記區的周緣’使光線 可以通過淸除區，而使其圖案轉移至晶片’以在對準標記 之上形成受曝光區。由於受曝光區的位置與大小係由光罩 的鉻膜遮蔽層所決定，而並非是由步進機其機台中用以遮 蔽光罩的不透光的葉片來定義，因此可以避免繞射現象的 發生，使光罩上淸除區的圖案正確轉移至光阻層上。 而且，本發明在對準標記周緣形成虛擬的隔離區，使 對準標記所屬之第一曝光區塊的溝渠密度與其他之第二曝 光區塊的溝渠密度相當，因此，使後續化學機械硏磨製程 可以提供均勻的硏磨速率。 另，本發明之方法中，不論對準標記是位在晶片的中 心之處或是位在緊靠於鄰近晶方得一邊，均只需要一次的 曝光製程即可以在對準標記周緣形成虛擬的隔離區圖案， 因此，本發明可以使對準標記的位置配置於晶方的中心之 處，而不需緊靠鄰近的晶方，以降低對準標記對周邊晶片 的影響。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1C圖是習知一種淺溝渠隔離結構之製造 流程的剖面圖。 第2A圖至第2D圖爲習知另一種淺溝渠隔離結構之製 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） <請先閲績背面之注$項再填寫本頁)The present invention relates to a method for patterning a semiconductor, and more particularly to a method for forming a pattern on a die (alignment mark) and other crystals at the same time. Photolithography (Photolithography) is a key step in the success or failure of manufacturing semiconductor components, so it plays an important role in the semiconductor manufacturing process. Taking the manufacturing process of general components as an example, usually a product needs about 10 to 18 times of lithography and exposure steps depending on its complexity. In order for the mask pattern to be correctly transferred to the wafer, usually, during the semiconductor manufacturing process, before each photoresist exposure is performed, the layers must be aligned to avoid improper pattern transfer. , Which leads to the entire wafer scrapped. In the traditional exposure process, an alignment mark corresponding to a photomask is formed on a wafer on which a semiconductor element is to be formed to achieve the purpose of alignment. In order to avoid damage to the alignment mark during the process, usually no pattern is formed around the alignment mark. However, other problems arise in the process, such as the formation of a shallow trench isolation structure. After the chemical mechanical honing process is carried out in the mining area, there will be problems such as residual oxide layers. In the following, the manufacturing method of the shallow trench isolation structure will be explained. Figures 1A to 1C are cross-sectional views of a conventional manufacturing process for a shallow trench isolation structure. Referring to FIG. 1A, a typical method is to form a mask layer 104 on the substrate 100 on which the alignment mark 102 has been formed, and then form a patterned light-emitting layer 106 on the mask layer 104, and borrow Its patterned tomb calendar 104. 3 (Please read the precautions on the back before filling out this page) '' ϋ 订 订 ---- ---- ，; 难 难 难 难 3 3 3 3 This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) 459298 A7 B7 6050twf2 / 002 V. Description of the invention (7) Next, the mask is engraved with the light 1 layer 106 and the mask layer 104 as a hungry part, and a part of the substrate 100 is etched to form a trench in the substrate 100 108. (Please read the precautions on the back before filling in this page.) Then 'Please refer to Figure 1B, remove the photoresist layer 106 and form a silicon oxide layer 110 on the substrate 100' to cover the mask layer 104, and After the trench 108 is full, please refer to FIG. 1C, using the mask layer 104 as a honing termination layer, and removing the excess silicon oxide layer 110 by a chemical mechanical honing method, leaving a silicon oxide layer 110a in the trench 106. Finally, the cover layer 104 is removed. Because the density of the trenches on the wafer is different, and there are many open areas on the wafer where no isolation structure is formed, such as the empty mining area around the alignment mark 102, the conventional method described above removes the surface of the mask layer 104 by honing. When the oxidized layer 110 is formed, the oxidized layer 110 located on the open area 112 will remain on the open area 112 due to the honing characteristics of the chemical mechanical honing method, thereby forming a residual oxide layer 110b. A method is known to improve the oxide layer remaining in the open area. A virtual isolation area is formed in the open area 112 of the substrate 100 to make the chemical mechanical honing process uniform. The manufacturing process is as shown in FIG. 2A to FIG. 2D illustration. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 2A. The typical method is to use a photoresist layer 106 to define the isolation area. At the same time, the exposure area is formed into an isolation area pattern 114 and virtual isolation through the exposure process. District's pattern 116. Referring to FIG. 2B, the exposed portion of the photoresist layer 106 is removed by a developing process, so that the remaining photoresist layer 106 has a trench pattern 114 and a pattern of a virtual isolation region. After that, the photoresist layer 106 is used as the mask. The etching mask 4 is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 6〇5〇4 > f§C ^ 2 9 8 A7 ________ B7 5. Description of the invention (>) The layer 104 and the substrate 100 'form a trench 108 of an isolation region and a virtual trench 118 of a virtual isolation region. Please refer to FIG. 2C, and then “remove the photoresist layer 106, and then form an oxide layer 110 on the substrate 100 to cover the mask layer 104 and fill the trench 108 and the virtual trench 118. β Please refer to FIG. 2D, The chemical mechanical honing process removes the oxide layer 110 covered on the mask layer 104. Finally, the mask layer 104 is removed to form an isolation region 110a and a dummy isolation region 110C in the substrate 100. The method for forming a dummy isolation region in the substrate described above is to form a trench pattern 114 and a pattern 116 of a dummy isolation region in the same layer of the photoresist layer 106, as shown in FIG. 2A. During the exposure process, the pattern on the photomask 400 shown in FIG. 4 is transferred to each of the exposure blocks 120 on the wafer 100 shown in FIG. 3 one by one, so that the light on the substrate (wafer) 100 is lightened. After the trench layer 106 is formed in the resist layer 106, the pattern of the photomask 400 is transferred to the open area 112 around the alignment mark 102 to form a dummy trench pattern 116 in the same photoresist layer 110. Please refer to FIG. 3, since the size of the block 122 forming the alignment mark 102 on the wafer is not the same as the size of the exposure block 120 of each exposure process, therefore, when performing the exposure process of the virtual isolation region pattern 116, The corner (for example, the upper left corner) 404 of the chrome plate 402 on the photomask 400 in FIG. 4 is aligned with the corner (for example, the upper left corner) 130 of the alignment mark block 122, and an exposure machine is used. The opaque Blade 300 in Taichung used to cover the photomask to cover the mask 400 corresponding to the alignment mark 102 and part 5 (guess first read the precautions on the back before filling this page). !! ------ Line 1 'Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs' Consumer Cooperatives This paper is printed in accordance with Chinese National Standards < CNS) A4 (210 X 297 mm) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs' Consumer Cooperatives 459298 6050twf2 / 002 A7 B7 V. Description of the invention (y) The alignment mark block 122 allows the exposed light to pass through the chrome film 402 on the reticle 400 and the shielding effect of the opaque blade 300 of the machine, so that The exposure light can only pass through a specific area, so that the trench pattern of the corner 404 on the photomask 400 can be smoothly transferred to the corner 130 of the block 122. For the photoresist layer 106 on the other corners of the alignment mark block Π2, the same method can be used to form the virtual isolation pattern 116. The above method must pass multiple exposure processes to form a virtual isolation region pattern 116 on the photoresist layer 106 on the alignment mark block 122. This method is not only time-consuming, reduces the throughput of the machine, but also increases the machine. Since the opaque leaves are lost, the method described above will also increase the manufacturing cost. In addition, in order to reduce the number of exposures required for the photoresist layer 106 on the alignment mark block 122 to form the dummy isolation region pattern 116, generally, the alignment mark 102 is formed on the side of the alignment mark block 122 next to the other crystal. As shown in the enlarged view of FIG. 3_, it is not formed at the center of the alignment mark 122. However, according to this method, the subsequent honing process will affect the wafers around the alignment mark 102. The invention provides a method for patterning a semiconductor, which can simultaneously form a pattern on a crystal cube of an alignment mark and another crystal cube. The invention provides a method for patterning a semiconductor, which can quickly complete a wafer exposure process. The invention provides a semiconductor patterning method, which can arrange an alignment mark at the center of an alignment mark block to reduce the influence of the alignment mark on the peripheral wafer. 6 This paper is suitable for @National Standard (CNS) A4 specification (210 X 297 public love) < Please read the precautions on the back before filling this page) --- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 45929 8 6050twf2 / 002 A7 _____B7____ V. Description of the Invention (t) The present invention provides a method for patterning a semiconductor, which can reduce the manufacturing cost of the semiconductor. The invention provides a method for manufacturing a shallow trench isolation structure, which can provide a uniform honing rate during a chemical mechanical honing process. The invention provides a method for manufacturing a semiconductor device. This method divides a wafer into a plurality of first exposure blocks and a plurality of second exposure blocks, and forms an alignment mark in one of the cubes of the first exposure block. After that, a layer to be patterned is formed on the wafer, and then a negative photoresist is formed on the layer to be patterned, and then a first exposure process is performed to sequentially place the first and second exposure blocks on the first exposure block and the second exposure block. A plurality of first exposed areas and a plurality of unexposed areas are formed in the negative photoresist. Then, a second exposure process is performed to form a second exposed area over the negative photoresist covered by the alignment mark. This second exposed area overlaps with the first exposed area above the alignment mark and the area not exposed to the exposure mark and covers the area of the alignment mark. Then, a developing step is performed to remove the negative photoresist of the unexposed area and expose it. After the layer to be patterned is taken out, the negative photoresist is used as a mask to remove the bare patterned layer exposed by the negative photoresist to pattern the layer to be patterned. Finally, the negative photoresist is removed. The invention provides a method for manufacturing a shallow trench isolation structure. This method provides a substrate having a plurality of crystal cubes, and the substrate is divided into a plurality of first exposure blocks and a plurality of second exposure blocks. Then, An alignment mark is formed on one of the cubes in the first exposure block. Then, a mask layer is formed on the substrate, and a negative photoresist layer is formed on the mask layer. After that, a first exposure process is performed to form several first exposed areas and several unexposed ones in the negative photoresist layer on the first exposure block and the second exposure block one by one (please read the note on the back first) Please fill in this page again for item i)-Install "5 ..." 4. This paper size applies to China National Standard (CNS) A4 (210x 297 mm) 459298 6050twf2 / 002 pj _B7_ V. Description of Invention (6) Area, where The unexposed area has several trench patterns. Then, a second exposure process is performed to form a second exposed area on the negative photoresist layer covered above the alignment mark, wherein the second exposed area and the first exposed area above the alignment mark are not affected. The trench pattern of the exposed area overlaps and covers the area of the alignment mark. Then, a developing step is performed to remove the negative photoresist layer in the unexposed area, so that the negative photoresist layer forms a trench pattern, wherein the trench pattern is exposed to expose the mask layer, and then the negative photoresist layer is used as the mask to remove the negative The cover screen layer exposed by the photoresist layer makes the cover screen layer form a trench pattern. After that, the negative photoresist layer is removed, and then the mask layer is used as a mask, and a part of the substrate exposed by the trench pattern of the mask layer is removed to form a number of crystals in the first exposure block and the second exposure block. A trench, and then an insulating layer is formed on the wafer to cover the cover layer, and the trench is filled, and then the insulating layer covered by the cover layer is removed by a chemical mechanical honing process. Finally, the cover layer is removed. The insulating layer remaining in the trench of the second exposure block forms an isolation region, and the insulating layer remaining in the trench of the first exposure block is used as a virtual isolation region. According to the embodiment of the present invention, the size of the first exposure block with the alignment mark is the same as that of other second exposure blocks. Therefore, when performing the exposure process, only a stepper is required to simultaneously By sequentially performing an exposure process, a predetermined pattern is exposed in a first exposure block having an alignment mark. In other words, this method requires only one exposure process to complete the exposure process of the first exposure block with the alignment mark. Compared to the conventional method, which can be completed multiple times, this method is a faster method. It is a method that can increase production capacity, reduce the loss of opaque blades of the machine, and reduce manufacturing costs. 8 (Please read the precautions on the back before filling out this page) 'nnn -ir-ejI I nnnn Printed on the paper by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 459298 6050twf2 / 002 A7 B7 V. Description of the invention (ο) In addition, the negative photoresist layer formed on the substrate of the present invention can be used to remove chromium on the periphery of the area by using a photomask. The film aligns the periphery of the alignment mark area 'allows light to pass through the erasure area and transfers its pattern to the wafer' to form an exposed area above the alignment mark. Since the position and size of the exposed area is determined by the chrome masking layer of the photomask, rather than being defined by the opaque leaves of the stepper to shield the photomask, diffraction phenomena can be avoided Occurs, the pattern of the erasure area on the photomask is correctly transferred to the photoresist layer. In addition, the present invention forms a virtual isolation region on the periphery of the alignment mark, so that the trench density of the first exposure block to which the alignment mark belongs is equivalent to the trench density of the other second exposure blocks. Therefore, subsequent chemical mechanical honing The process can provide a uniform honing rate. In addition, in the method of the present invention, no matter whether the alignment mark is located at the center of the wafer or on the side close to the adjacent crystal, only one exposure process is required to form a dummy on the periphery of the alignment mark. The pattern of the isolation region. Therefore, the present invention can arrange the position of the alignment mark at the center of the crystal cube without having to be close to the adjacent crystal cube, so as to reduce the influence of the alignment mark on the peripheral wafer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A FIG. 1 to FIG. 1C are cross-sectional views of a manufacturing process of a conventional shallow trench isolation structure. Figures 2A to 2D are known for another shallow trench isolation structure. 9 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) < Please read the note in the back of the performance first (Fill in this page)
f · I I I------------I 經濟部智慧財產局員工消費合作社印製 五、發明說明（3) 造流程的剖面圖。 第3圖是第2A圖至第2D圖之晶片的示意圖° 第4圖是習知一種用以定義第2A圖之隔離區之光罩的 示意圖。 第5A圖至第5H圖係依照本發明所繪示之一種淺溝渠 陽離結構的製造方法。 第6圖是本發明第5A圖至第5H圖之晶片的示意圖。 第7圖本發明是一種用以定義第5A圖之隔離區之光罩 的示意圖。 第8A圖至第8B圖係依照本發明所繪示之另一種淺溝 渠隔離結構的製造方法。 標記之簡單說明： 100、500 :基底 102、502 :對準標記 104 ' 504 :罩幕層 106、506、522 :光阻層 108、514、514a ' 514b、514c :溝渠 110、110a、110b :氧化矽層 :虛擬隔離區 112 :空曠區 114 :溝渠圖案 U6 :虛擬隔離區的圖案 118 :虛擬溝渠 U0 :曝光區塊 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填窝本頁) Μ--------tr---------線、 459298 6050twf2/002 A7 B7 -— — ~~ - — 五、發明說明（5) 130 ' 404 : —邊角 122 :對準標記區塊 300 :不透光葉片 400、700 :光罩 402 :鉻膜 508、512 :受曝光區 510 :未遭受曝光區 516 ' 516a、516b ' 516c :絕緣層 524 :開口圖案 600:晶方 602 ' 604 :曝光區塊 600a、600b :晶片 702 :淸除區 實施例 在以下的實施例係以淺溝渠結構的製造方法說明本發 明之一種同時在對準標記之晶方與其他晶方上形成圖案的 方法，然而在實際的應用上並不限定於此。 第5A圖至第5H圖係依照本發明所繪示之一種淺溝渠 隔離結構的製造方法。 經濟部智慧財產局員工消費合作社印製 請參照第5A圖，本發明之淺溝渠隔離區的製造方法係 提供一基底500 ’此基底500如第6圖所示，其具有數個晶 方600 ’晶方600可區分爲數個第一曝光區塊（Shoot)602與 數個第二曝光區塊6〇4。接著，在第一曝光區塊602中的其 中—個晶方600a形成對準標記502，第一曝光區塊602中 未形成對準標記5〇2的晶方則標示爲600b。較佳的第一曝 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ά5929 8 6050twf2/002 五、發明說明（丨Ο 光區塊6〇2與第二曝光區塊604係具有相同大小者。較佳 的對準標記5〇2係形成於第一曝光區塊602其晶方600&的 中心之處。 (請先閱讀背面之#1$項再填窝本頁} 接者’ ira繼繪參照桌5Α圖，在基底500上形成一層罩 幕層504 ’再於罩幕層504上形成一層光阻層506 '罩幕層 5〇4例如是先以熱氧化法在基底500上形成一層墊氧化 層’再以化學氣相沉積法在墊氧化層上形成一層氮化矽 層。光阻層506例如是負光阻層，其材質在照光之後，可 以使光阻層5〇6的分子產生鏈結(Crosslink)反應，或使光阻 層506在照光之處在顯影之後可以留下來，而未照光之處 在顯影之後可以去除。 之後，請參照第5B圖與第7圖，進行曝光製程，將第 7圖所示之光罩700上的圖案，逐一轉移至第一曝光區塊 6〇2與第二曝光區塊604的光阻層506中，以在光阻層506 中形成數個受曝光區508與數個未遭受曝光區510,其中未 遭受曝光區510具有預定形成之隔離區圖案。 經濟部智慧財產局員工消費合作社印製 値得一提的是，本發明具有對準標記502的曝光區塊 602其大小與曝光區塊604的大小相同，因此，在進行上述 曝光製程時，僅需以步進機同時依序在曝光區塊602與曝 光區塊604上的光阻層506之中形成受曝光區508與未遭 受曝光區510。換言之，本發明之對準標記區502僅佔用晶 片中的一個晶方600a，如第6圖所不，而此晶方6〇〇a所屬 的曝光區塊602在進行上述曝光製程時，可以以相同於其 他曝光區塊(曝光區塊604)的曝光方式同時進行曝光製 本紙張尺度適用中國國家標準（CNS)A4規格（210 297公釐> A7 B7 45929 8 6050twf2/002 五、發明說明（丨I ) 程，即可以在曝光區塊602中具有對準標記502之晶方600a 以及其他晶方600b之中曝出預定的圖案，而不需以習知的 方法另外對對準標記區所屬之晶方進行繁複的曝光製程。 請參照第5C圖與第6圖，進行另一曝光製程，以在對 準標記502其上方所覆蓋的光阻層506形成一受曝光區 512，其中，受曝光區512與對準標記502上方之受曝光區 5〇8及未遭受曝光區510之溝渠圖案重疊’並且涵蓋晶片上 形成有對準標記502之區域。較佳的受曝光區512係將光 罩700上淸除區702周緣的鉻膜遮蔽層對準對準標記區502 的周緣，以使光線通過淸除區702,而使其圖案轉移至晶片 方所覆蓋的光阻層506上，以形成受曝光區512。 請參照第5D圖，進行一顯影製程，以將光阻層5〇6中 具有隔離區圖案之未遭受曝光區510去除，裸露出部分的 罩幕層504。此時，所留下之受曝光區5M_與受曝光區512 的光阻層506係具有預定形成之溝渠圖案。 請»Μ參照第5^_圖，以光阻層506爲罩幕，蝕刻光阻 層506所裸露的罩幕層504,以使預定形成之溝渠圖案由光 阻層506轉移至罩幕層504。由於光阻層506的受曝光區 512在顯影製程之後可以保留下來，因此，在進行上述罩幕 層5〇4之蝕刻製程之後，對準標記上仍留有罩幕靥 5〇4 ’使對準標記5〇2在後續的蝕刻製程中不會遭受蝕 程的破壞。 / # 證·參照第5Ε圖，之後去除光阳層506’再以罩幕層5〇4 爲罩幕’利用蝕刻法，例如是反應性離子鈾刻法，去除罩 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝ill丨丨—訂· -----1丨_線，- 經濟部智慧財產局員工消費合作社印製 A7 B7 ^59298 6050twf2/002 玉·、發明說明（丨2) 幕層504所裸露的基底500,以在基底500中形成溝渠514。 依照溝渠514所在的位置，溝區5丨4可以區分爲溝渠5〗4a、 溝渠514b與溝渠514c，其中溝渠5I4a係形成於曝光區塊 604之基底500之中，係用以形成元件的隔離區；溝渠514b 係形成於曝光區塊602中不具有對準標記502之晶方 600b，係用以形成元件的隔離區；溝渠514c係形成於曝光 區塊602中、晶方600a其對準標記502周緣的空礦區者， 係用以在後續硏磨製程中，增加硏磨均勻度之用。 請參照第5F圖，接著，在基底500上形成一層絕緣層 516，以覆蓋罩幕層5〇4，並塡滿溝渠514a/b/c〇絕緣層516 之材質例如爲氧化矽，其形成的方法例如爲次常壓化學氣 相沈積法(SACVD)或高密度電漿化學氣相沈積法 (HDPCVD)，較佳的是以臭氧與四乙氧基矽烷（TEOS)爲 反應氣體源，利用次常壓化學氣相沉積法所形成之氧化 矽。較佳的作法在形成氧化矽材質之絕緣層516之後，在 高溫下，比如在約爲l〇〇〇°C的溫度條件，進行熱製程約 10〜30分鐘，以使絕緣層516密實化。 當形成絕緣層516之後，在絕緣層516上形成一層光 阻層522,此光阻層522在對準標記502上具有一開口圖案 524 ’裸露出位於對準標記5〇2上方之絕緣層516。具有開 口圖案524之光阻層522的形成方法，例如是在基底上形 成一層正型光阻層之後，利用第7圖之光罩700上淸除區 702周圍的鉻膜遮蔽層對準對準標記502的周緣，使光線通 過淸除區7〇2’進而使得淸除區702的圖案轉移至正型光阻 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) '乾-! — —丨訂·---- !線{ 經濟部智慧財產局員工消費合作社印製 459298 6050twf2/002 a7 _____B7 _ 五、發明說明（G) 層，然後，經由顯影製程，即可在絕緣層516上形成具有 開口圖案524的光阻層522。之後，以光阻層522爲罩幕， 以蝕刻法去除對準標記502上所覆蓋之絕緣層516,以裸露 出對準標記502上的罩幕層504。當光阳曆522去除之後， 其後續之製程則是以硏磨製程去除罩幕層504上的絕緣層 5 16 〇 値得一提的是，若是溝渠(預定形成之隔離區）其彼此之 間具有較大的空礦區者，如第8A圖標記520所示者，則在 絕緣層516上形成光阻層522的同時，可以經由曝光製程， 使空曠區520上之光阻層522曝光，再將光罩上之淸除區 的圖案轉移至光阻層，然後經由顯影製程，以使所留下的 光阻層522不僅裸露出對準標記502上之絕緣層516,亦裸 露出空曠區520上之絕緣層516。之後，再以光阻層522 爲罩幕，去除未被光阻層522覆蓋的絕緣層516，以裸露出 對準標記502以及空曠區520上之罩幕層504,其結 8Β圖所示° 請參照第5G圖，當光阻層522去除之後，再以化學機 械硏磨法，硏磨去除罩幕層504上所覆蓋的絕緣層516 ’以 留下溝渠514a之中的絕緣層516a、溝渠514b之中的絕緣 層516b以及溝渠514c之中的絕緣層516c，其中’絕緣層 516a與絕緣層516b係作爲元件隔離區；絕緣層516c則爲 虛擬隔離區。 由於曝光區塊602的大小與曝光區塊604的大小相 同，且其二者之基底500中所形成的溝渠514c、514b與 15 (請先閱讀背面之注意事項再填寫本頁) 裝 ----訂.--------線. 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（β) 514a，係以相同的光罩700(第7圖）所定義者，因此，曝光 區塊602之中的溝渠密度與曝光區塊604之中的溝渠密度 相近。所以，在以化學機械硏磨製程去除罩幕層504上所 覆蓋的絕緣層516時，具有良好的硏磨均勻度，並不會有 絕緣層516殘留於罩幕層504的問題。 請參照第5H圖，去除罩幕層504，以留下溝渠514a 之中的絕緣層516a、溝渠514b之中的絕緣層516b以及溝 渠514c之中的絕緣層516c。去除罩幕層504的方法包括濕 式蝕刻法。當罩幕層504係由墊氧化層與氮化矽層所構成 時，可以先以熱磷酸去除氮化矽層，再以氫氟酸去除墊氧 化層。 綜合以上所述，本發明至少具有下列優點： 1-本發明在基底上所形成的負光阻層，可以利用光罩上 淸除區周緣的鉻膜對準對準標記區的周緣，使光線可以通 過淸除區，而使其圖案轉移至晶片，以在對準標記之上形 成受曝光區。由於受曝光區的位置與大小係由光罩的鉻膜 遮蔽層所決定，而並非是由步進機其機台中用以遮蔽光罩 的不透光的葉片來定義，因此可以避免繞射現象的發生， 使光罩上淸除區的圖案正確轉移至光阻層上。 2.本發明具有對準標記的曝光區塊的大小與其他之曝 光區塊的大小相同，因此，在進行上述曝光製程時，僅需 以步進機同時依序進行曝光製程，即可在具有對準標記的 曝光區塊中曝出預定的圖案。換言之，此方法僅需以一次 的曝光製程即可以完成具有對準標記之曝光區塊的曝光製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1*..---;--------裝--------訂---------線，V (猜先閱讀背面之注意事項再填寫本頁) A7 B7 459298 6050twf2/002 五、發明說明（丨Γ) 程，相較於習知需以多次方能完成之方法，本發爲一種較 爲快速，且是一種可以增加產能，可以降低機台不透光葉 片損耗，降低製造成本的方法。 3. 本發明在對準標記周緣形成虛擬的隔離區，使對準標 記所屬之曝光區塊的溝渠密度與其他之曝光區塊的溝渠密 度相當，因此，使後續化學機械硏磨製程可以提供均勻的 硏磨速率。 4. 本發明之方法中，不論對準標記是位在晶片的中心之 處或是位在緊靠於鄰近晶方的一邊，均只需要一次的曝光 製程即可以在對準標記周緣形成虛擬的隔離區圖案，因 此’本發明可以使對準標記的位置配置於晶方的中心之 處，而不需緊靠鄰近的晶方，以降低對準標記對周邊晶片 的影響。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明’任何熟習此技藝者，在不脫離本發明之精 神和範圍內’當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 裝 tr---------線 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格（21〇 x 297公釐）f · I I I ------------ I Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (3) A cross-sectional view of the manufacturing process. Fig. 3 is a schematic diagram of the wafers of Figs. 2A to 2D. Fig. 4 is a schematic diagram of a conventional photomask used to define the isolation region of Fig. 2A. 5A to 5H illustrate a method for manufacturing a shallow trench canonization structure according to the present invention. Fig. 6 is a schematic diagram of the wafers of Figs. 5A to 5H of the present invention. Fig. 7 The present invention is a schematic diagram of a photomask used to define the isolation area of Fig. 5A. 8A to 8B illustrate another method for manufacturing a shallow trench isolation structure according to the present invention. Brief description of the marks: 100, 500: substrate 102, 502: alignment marks 104 '504: mask layer 106, 506, 522: photoresist layer 108, 514, 514a' 514b, 514c: trenches 110, 110a, 110b: Silicon oxide layer: virtual isolation area 112: open area 114: ditch pattern U6: virtual isolation area pattern 118: virtual ditch U0: exposed block 10 This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) ) (Please read the precautions on the back before filling in this page) Μ -------- tr --------- line, 459298 6050twf2 / 002 A7 B7-— — ~~-— 5 Description of the invention (5) 130 '404:-Corner 122: Alignment mark block 300: Opaque blade 400, 700: Photomask 402: Chrome film 508, 512: Exposed area 510: Unexposed area 516 '' 516a, 516b '' 516c: Insulating layer 524: Opening pattern 600: Cube 602 '' 604: Exposed block 600a, 600b: Wafer 702: Erased area Example In the following embodiments, a manufacturing method of a shallow trench structure is explained A method for forming a pattern on a crystal cube of an alignment mark and other crystal cubes at the same time in the present invention is not limited in practical application herein. 5A to 5H illustrate a method for manufacturing a shallow trench isolation structure according to the present invention. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to FIG. 5A. The manufacturing method of the shallow trench isolation zone of the present invention is to provide a substrate 500 'as shown in FIG. 6, which has several crystal cubes 600' The Cube 600 can be divided into several first exposure blocks (Shoot) 602 and several second exposure blocks 604. Next, an alignment mark 502 is formed in one of the cubes 600a in the first exposure block 602, and a cube without the alignment mark 502 in the first exposure block 602 is labeled 600b. The better first exposure size of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ά5929 8 6050twf2 / 002 5. Description of the invention (丨 〇 Light block 602 and second exposure block 604 Those with the same size. The better alignment mark 502 is formed at the center of the cube 600 & of the first exposure block 602. (Please read the # 1 $ item on the back before filling the nest page} Next, ira continues to refer to the table 5A, and forms a mask layer 504 on the substrate 500. Then, a photoresist layer 506 is formed on the mask layer 504. The mask layer 504 is, for example, firstly thermally oxidized. A pad oxide layer is formed on the substrate 500, and then a silicon nitride layer is formed on the pad oxide layer by a chemical vapor deposition method. The photoresist layer 506 is, for example, a negative photoresist layer, and the material can make the photoresist layer after being irradiated with light. The molecule of 50 has a Crosslink reaction, or the photoresist layer 506 can be left after being developed after being irradiated, and can be removed after being developed after being irradiated. Please refer to FIG. 5B and FIG. Figure 7, the exposure process is performed, and the pattern on the mask 700 shown in Figure 7 is transferred one by one In the photoresist layer 506 of the first exposure block 602 and the second exposure block 604, a plurality of exposed regions 508 and a plurality of unexposed regions 510 are formed in the photoresist layer 506, of which the unexposed regions are not exposed. 510 has a predetermined pattern of the isolation zone. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. It is noted that the exposure block 602 with the alignment mark 502 of the present invention has the same size as the exposure block 604, so When performing the above-mentioned exposure process, it is only necessary to use a stepper to sequentially form the exposed area 508 and the unexposed area 510 in the photoresist layer 506 on the exposure block 602 and the exposure block 604 at the same time. In other words, this The alignment mark area 502 of the invention only occupies one crystal 600a in the wafer, as shown in FIG. 6, and the exposure block 602 to which this crystal 600a belongs can be the same as the other during the above-mentioned exposure process. The exposure method of the exposure block (exposure block 604) is performed at the same time. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 297 mm > A7 B7 45929 8 6050twf2 / 002. 5. Description of the invention (丨 I) Process , Which can be exposed in block 6 The predetermined pattern is exposed in the crystal cubes 600a and the other crystal cubes 600b with the alignment mark 502 in 02, without the need to perform a complicated exposure process on the crystal cubes to which the alignment mark area belongs by a conventional method. Please refer to 5C and 6, another exposure process is performed to form an exposed area 512 on the photoresist layer 506 overlying the alignment mark 502. The exposed area 512 and the exposure area above the alignment mark 502 are exposed. The trench pattern of the exposed region 508 and the unexposed region 510 overlap 'and covers an area where the alignment mark 502 is formed on the wafer. The preferred exposed area 512 is to align the chrome masking layer on the periphery of the erasure area 702 on the photomask 700 with the periphery of the alignment mark area 502 so that light passes through the erasure area 702 and its pattern is transferred to the wafer side. The covered photoresist layer 506 forms an exposed area 512. Referring to FIG. 5D, a development process is performed to remove the unexposed area 510 with the isolation region pattern in the photoresist layer 506, and to expose the mask layer 504 in an exposed portion. At this time, the photoresist layer 506 of the exposed area 5M_ and the exposed area 512 has a predetermined trench pattern. Please refer to FIG. 5 ^ _. Using the photoresist layer 506 as a mask, the exposed mask layer 504 exposed by the photoresist layer 506 is etched to transfer the predetermined trench pattern from the photoresist layer 506 to the mask layer 504. . Since the exposed area 512 of the photoresist layer 506 can be retained after the development process, after the above-mentioned etching process of the mask layer 504 is performed, a mask 504 is left on the alignment mark. The quasi-marker 502 will not be damaged by the etching process in the subsequent etching process. / # Certificate · Refer to Figure 5E, and then remove the solar layer 506 'and then use the mask layer 504 as the mask'. Use an etching method, such as reactive ion engraving, to remove the mask. 13 This paper is applicable to China. Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling out this page) Assembling 丨 丨 —Order · ----- 1 丨 _line,-Staff of Intellectual Property Bureau, Ministry of Economic Affairs The consumer cooperative prints A7 B7 ^ 59298 6050twf2 / 002 jade, description of the invention (丨 2) the substrate 500 exposed by the curtain layer 504 to form a trench 514 in the substrate 500. According to the location of the trench 514, the trench area 5 丨 4 can be divided into trench 5 4a, trench 514b, and trench 514c. The trench 5I4a is formed in the substrate 500 of the exposed block 604, and is used to form an isolation area for components. The trench 514b is formed in the cube 600b without the alignment mark 502 in the exposure block 602, and is used to form an isolation region of the element; the trench 514c is formed in the exposure block 602, and the alignment mark 502 on the cube 600a is formed Peripheral empty mines are used to increase the uniformity of honing in the subsequent honing process. Please refer to FIG. 5F. Next, an insulating layer 516 is formed on the substrate 500 to cover the cover layer 504 and fill the trench 514a / b / c. The material of the insulating layer 516 is, for example, silicon oxide. The method is, for example, sub-atmospheric pressure chemical vapor deposition (SACVD) or high-density plasma chemical vapor deposition (HDPCVD). Preferably, ozone and tetraethoxysilane (TEOS) are used as reaction gas sources. Silicon oxide formed by atmospheric pressure chemical vapor deposition. After forming the insulating layer 516 made of silicon oxide, a preferable method is to perform a thermal process for about 10 to 30 minutes at a high temperature, for example, at a temperature of about 1000 ° C, so as to make the insulating layer 516 dense. After the insulating layer 516 is formed, a photoresist layer 522 is formed on the insulating layer 516. The photoresist layer 522 has an opening pattern 524 on the alignment mark 502. The insulation layer 516 is exposed above the alignment mark 502. . The method of forming the photoresist layer 522 with the opening pattern 524 is, for example, after forming a positive photoresist layer on the substrate, using a chromium film shielding layer around the erasure area 702 on the photomask 700 in FIG. 7 The periphery of the mark 502 allows light to pass through the erasing area 702 ′, thereby shifting the pattern of the erasing area 702 to a positive photoresist. This paper is in accordance with China National Standard (CNS) A4 (210 X 297 mm) (Please Please read the precautions on the back before filling this page) 'Stem-! — — 丨 order · ----! Line {printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 459298 6050twf2 / 002 a7 _____B7 _ V. Description of the invention (G ) Layer, and then, through a development process, a photoresist layer 522 having an opening pattern 524 can be formed on the insulating layer 516. After that, the photoresist layer 522 is used as a mask, and the insulating layer 516 covered on the alignment mark 502 is removed by etching to expose the mask layer 504 on the alignment mark 502. After the Guangyin calendar 522 is removed, the subsequent process is to remove the insulating layer 5 16 〇 on the mask layer 504 by a honing process. It is mentioned that if a trench (a predetermined isolation area) has each other For a large empty mining area, as shown in FIG. 8A, reference numeral 520, while forming a photoresist layer 522 on the insulating layer 516, the photoresist layer 522 on the open area 520 can be exposed through an exposure process, and then The pattern of the erasure area on the photomask is transferred to the photoresist layer, and then the development process is performed so that the remaining photoresist layer 522 not only exposes the insulating layer 516 on the alignment mark 502, but also exposes the open area 520. The insulation layer 516. After that, the photoresist layer 522 is used as a mask, and the insulating layer 516 not covered by the photoresist layer 522 is removed to expose the alignment mark 502 and the mask layer 504 on the open area 520, as shown in FIG. 8B. Please refer to FIG. 5G. After the photoresist layer 522 is removed, the insulating layer 516 'over the mask layer 504 is removed by honing by chemical mechanical honing to leave the insulating layer 516a and the trench in the trench 514a. The insulating layer 516b in 514b and the insulating layer 516c in the trench 514c, wherein the 'insulating layer 516a and the insulating layer 516b are used as element isolation regions; the insulating layer 516c is a virtual isolation region. Because the size of the exposed block 602 is the same as the size of the exposed block 604, and the trenches 514c, 514b, and 15 formed in the substrate 500 of the two (please read the precautions on the back before filling this page). -Order .-------- line. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs' Consumer Cooperatives. This paper is printed in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm). Print B7 V. Description of the invention (β) 514a, which is defined by the same mask 700 (Figure 7). Therefore, the density of the trenches in the exposed block 602 is similar to the density of the trenches in the exposed block 604. . Therefore, when the insulating layer 516 covered on the mask layer 504 is removed by a chemical mechanical honing process, the uniformity of the honing is good, and there is no problem that the insulating layer 516 remains on the mask layer 504. Referring to FIG. 5H, the mask layer 504 is removed to leave the insulating layer 516a in the trench 514a, the insulating layer 516b in the trench 514b, and the insulating layer 516c in the trench 514c. The method of removing the mask layer 504 includes a wet etching method. When the mask layer 504 is composed of a pad oxide layer and a silicon nitride layer, the silicon nitride layer may be removed with hot phosphoric acid first, and then the pad oxide layer may be removed with hydrofluoric acid. To sum up, the present invention has at least the following advantages: 1- The negative photoresist layer formed on the substrate of the present invention can use the chromium film on the periphery of the erasure area on the photomask to align the periphery of the alignment mark area to make light The pattern can be transferred to the wafer by erasing the area to form an exposed area above the alignment mark. Since the position and size of the exposed area is determined by the chrome masking layer of the photomask, rather than being defined by the opaque leaves of the stepper to shield the photomask, diffraction phenomena can be avoided Occurs, the pattern of the erasure area on the photomask is correctly transferred to the photoresist layer. 2. The size of the exposed block with the alignment mark of the present invention is the same as that of other exposed blocks. Therefore, when performing the above-mentioned exposure process, it is only necessary to perform the exposure process sequentially with a stepper at the same time. A predetermined pattern is exposed in the exposure block of the alignment mark. In other words, this method requires only one exposure process to complete the exposure format of the exposure block with the alignment mark. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 1 * ..--- ; -------- install -------- order --------- line, V (guess first read the notes on the back before filling in this page) A7 B7 459298 6050twf2 / 002 Fifth, the invention description (丨 Γ) process, compared to the conventional method that can be completed multiple times, this hair is a relatively fast, and it can increase the production capacity, can reduce the machine's opaque blade loss, Ways to reduce manufacturing costs. 3. The invention forms a virtual isolation area around the alignment mark, so that the trench density of the exposed block to which the alignment mark belongs is equivalent to the trench density of other exposed blocks, so that the subsequent chemical mechanical honing process can provide uniformity. Honing rate. 4. In the method of the present invention, regardless of whether the alignment mark is located at the center of the wafer or immediately adjacent to the side of the crystal cube, only a single exposure process is required to form a dummy on the periphery of the alignment mark. The pattern of the isolation region, therefore, the present invention can arrange the position of the alignment mark at the center of the crystal cube without having to be close to the adjacent crystal cube to reduce the influence of the alignment mark on the peripheral wafer. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page) Loading tr --------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with the Chinese National Standard (CNS) A4 specification (21〇 x 297 mm)