TW454322B - Embedded ball-grid array package structure having tape automated bonding tape - Google Patents

Embedded ball-grid array package structure having tape automated bonding tape Download PDF

Info

Publication number
TW454322B
TW454322B TW089100696A TW89100696A TW454322B TW 454322 B TW454322 B TW 454322B TW 089100696 A TW089100696 A TW 089100696A TW 89100696 A TW89100696 A TW 89100696A TW 454322 B TW454322 B TW 454322B
Authority
TW
Taiwan
Prior art keywords
tape
substrate
grid array
array package
package structure
Prior art date
Application number
TW089100696A
Other languages
Chinese (zh)
Inventor
Geng-Shin Shen
Original Assignee
Chipmos Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc filed Critical Chipmos Technologies Inc
Priority to TW089100696A priority Critical patent/TW454322B/en
Application granted granted Critical
Publication of TW454322B publication Critical patent/TW454322B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

An chip-embedded ball-grid array package structure is disclosed, which mainly comprises a substrate, a tape automated bonding (TAB) tape, and a semiconductor chip. The front side of the substrate has a concave portion to accommodate the semiconductor chip. The semiconductor chip has plural chip pads. The TAB tape electrically connects the plural chip pads to the plural substrate pads on the front side of the substrate. There are plural solder balls on the back side of the substrate, each solder ball is electrically connected to the corresponding substrate pad.

Description

454322 片队入式球格陣列封裝構造，其包含至少兩半導體 曰曰片，其中該每一半導體晶片係為彼此直列。 5依申叫專利範圍第1項之具有膠捲式自動黏著膠帶之 2片嵌入式球格陣列封裝構造，其包含至少兩半導體 晶片’其中該每一半導體晶片係為並列。 6種球格陣列封裝基板，其具有正面以及背面，該基 板之正面設有一凹部用以容置半導體晶片，該基板之 正面σ又有複數個基板銲墊，該基板之背面設有複數個 錫球用以與外界電性溝通，該每一個錫球係分別電性 連接至相對應的基板銲墊。 7、依申請專利範圍第6項之球袼陣列封裝基板，其中該 基板之凹部係設有一晶片承座用以承載半導體晶片。 第13頁454322 chip-type ball grid array package structure, which includes at least two semiconductor chips, wherein each of the semiconductor wafers is aligned with each other. 5 According to claim 1, the two-piece embedded ball grid array package structure with a film-type automatic adhesive tape includes the at least two semiconductor wafers', wherein each of the semiconductor wafers is juxtaposed. Six kinds of ball grid array package substrates, which have a front surface and a back surface. The front surface of the substrate is provided with a recess for accommodating semiconductor wafers. The balls are used for electrical communication with the outside world, and each solder ball is electrically connected to a corresponding substrate pad. 7. The ball grid array package substrate according to item 6 of the patent application scope, wherein a recess of the substrate is provided with a wafer holder for carrying a semiconductor wafer. Page 13

TW089100696A 2000-01-17 2000-01-17 Embedded ball-grid array package structure having tape automated bonding tape TW454322B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW089100696A TW454322B (en) 2000-01-17 2000-01-17 Embedded ball-grid array package structure having tape automated bonding tape

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW089100696A TW454322B (en) 2000-01-17 2000-01-17 Embedded ball-grid array package structure having tape automated bonding tape

Publications (1)

Publication Number Publication Date
TW454322B true TW454322B (en) 2001-09-11

Family

ID=21658506

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089100696A TW454322B (en) 2000-01-17 2000-01-17 Embedded ball-grid array package structure having tape automated bonding tape

Country Status (1)

Country Link
TW (1) TW454322B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8237249B2 (en) 2009-03-27 2012-08-07 Chipmos Technologies Inc. Stacked multichip package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8237249B2 (en) 2009-03-27 2012-08-07 Chipmos Technologies Inc. Stacked multichip package

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