TW444259B - Fabricating process of thin ball grid array substrate - Google Patents

Abstract

This invention is about the fabricating process of thin ball grid array substrate. In this invention, a thin copper surface layer is first sputtered on a polyimide film and is followed by electroplating a thicker copper layer on the copper surface layer. After that, the thicker copper layer is covered with a photosensitive coating, which is then separated by an appropriately treated mask (having the disposed circuit track) so as to be irradiated and underexposed. Therefore, the corresponding position on the photosensitive coating layer with respect to the circuit track of mask is etched away so as to form a circuit track of photosensitive coating that is recessed to copper layer. The manner of electroplating is used to make the thickness of copper circuit track become thicker. Substrate that is not protected by the bottom photosensitive coating is etched away. Metal material (such as lead tin alloy 63Sn/37Pb) is electroplated inside the recessed track of the front photosensitive coating. After removing the photosensitive coating and etching away the excess copper route, the process is completed.

Description

4442 5 9 五、發明說明（1) 發明領域： 本發明係一種薄型球柵陣列（Thin Ball Grid Array，TBGA)基板（Substrate)製程（Pr〇cess)，主要係 克服習知薄型球栅陣列基板以電解電鍍方式鍍高電路線之 製程會將電鍍線路留在基板，造成基板電氣特性不良的缺 失’進而開發的一種既可採用電鍍方式可鍍高電路線厚度 之優點’卻又不會將該電鍍線留在基板的製程。 習知技藝： 一般的可持式行動電子電器設備講究輕、薄、艘積小 等特性’故多採用薄型球栅陣列基板作為應用母板，而該 習知的薄型球栅陣列基板的電路佈局的製程，一般採電解 電錢與無電鍍（即化學電鍍）法，以下將電解電鍍製程示意 如下（請參照第la〜Ik圖所示）： 製程a:使用聚醯亞銨η薄膜層（p〇iyimide film)作 為載體1。 製程b:在該聚醯亞銨11薄膜層上先濺鍍出一層薄銅 12 » 製程c:於載體1薄銅12層表面上再電鍍出一層相對較 厚之銅層1 3。 製程d:在載體1最上層與最下層塗佈適當厚度之整片 積層感光塗料14層。 製程e:在頂層上方與底層下方分別設置一光罩15’ 該光罩15上具有可透光之電路線路軌跡151，4442 5 9 V. Description of the invention (1) Field of the invention: The present invention is a thin ball grid array (TBGA) substrate (Prcess) process, mainly to overcome the conventional thin ball grid array substrate The process of plating high circuit lines by electrolytic plating will leave the plated circuits on the substrate, resulting in the lack of poor electrical characteristics of the substrate. 'Furthermore, it has developed an advantage that can use the plating method to plate high circuit lines.' The plating line remains on the substrate. Know-how: General portable mobile electronic and electrical equipment pays attention to characteristics such as lightness, thinness, and small size. Therefore, a thin ball grid array substrate is often used as an application motherboard, and the circuit layout of the conventional thin ball grid array substrate is widely used. The process is generally based on electrolytic electricity and electroless plating (ie, electroless plating). The electrolytic plating process is shown below (see Figures 1 to Ik): Process a: Use polyimide η thin film layer (p (Iyimide film) as the carrier 1. Process b: Sputter a thin layer of copper 12 on the polyfluorene ammonium 11 film layer. »Process c: Electroplating a relatively thick copper layer 13 on the surface of the thin layer 12 of the carrier 1 copper. Process d: Apply the entire layer of 14 layers of laminated photosensitive paint to the upper and lower layers of the carrier 1 with an appropriate thickness. Process e: A photomask 15 ’is provided above the top layer and below the bottom layer. The photomask 15 has a light-transmitting circuit track 151,

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並予以曝光處理。 製程f:經曝光處理後顯影，俾在積層感光塗料14層 上相對於電路線路軌跡151的位置被去除，其 餘部份留下，使在積層感光塗料層上形成凹 入之電路線路執跡圖β 製程g:在表面鑛銅16’使該凹入之電路線路軌跡底 面的銅層13上再鑛出一層銅16，使與積層感 光塗料14層同高。 製程h:於底層施以蚀刻作業，使在製程f顯影去除 的電路線路軌跡的位置的聚醯亞錢Η薄媒層 被吃去。 製程i:以藥劑洗去積層的感光塗料14層。 製程j:去除表面之銅層13多餘的部份，僅保留電路 線19及其電鍍線17(請參照第ΐκ圖所示）》 製程k:利用電鍍線17接引電鍍設備的正負極來進行 電鍍作業’使各電路線19表層鍍上鎳、金等 金屬電鍍層1 8。 上述電解電鍍製法雖可鍍出較厚的電路厚度、且可選 擇較多種類的金屬來鍍在銅線路上’但此法會留下電鍍 線，造成高速信號傳送時產生傳送延遲、雜訊、信號能量 衰減，電氣特性不佳；另一種製法為無電鍍（化學電鍍）製 法僅能在現有的電路線上再覆以鎳（Ni)、金（Au)及錫（sn) 等金屬，且其鍍層厚度有所限制’但最大的優點即是在基 板上無電鍍線’有較佳之電路特性；而尚無任何一種製程And be exposed. Process f: After exposure processing, the photoresist is removed from the layer 14 of the laminated photosensitive paint with respect to the circuit track 151, and the rest is left, so that a concave circuit trace is formed on the laminated photosensitive paint layer. β process g: a layer of copper 16 is mined on the copper layer 13 on the bottom surface of the copper circuit 16 ′ on the surface of the concave circuit track to make it the same height as the layer 14 of the laminated photosensitive paint. Process h: An etching operation is performed on the bottom layer, so that the polysilicon thin dielectric layer at the position of the circuit traces removed by the process f development is eaten. Process i: Wash away the 14 layers of the photosensitive coating with a chemical agent. Process j: Remove the excess part of the copper layer 13 on the surface, leaving only the circuit wire 19 and its plating line 17 (see Figure 所示 κ). Process k: Use the plating line 17 to lead the positive and negative electrodes of the plating equipment to perform Electroplating operation 'coats each circuit line 19 with a metal plating layer 18 such as nickel or gold. Although the above electrolytic plating method can plate a thicker circuit thickness, and can choose more kinds of metals to be plated on copper lines', this method will leave plating lines, causing transmission delays, noise, The signal energy is attenuated and the electrical characteristics are not good. Another method is electroless plating (chemical plating). The existing circuit wires can only be covered with metals such as nickel (Ni), gold (Au), and tin (sn). The thickness is limited, but the biggest advantage is that there is no electroplated wire on the substrate. It has better circuit characteristics; there is no one process

4442 5 9 五、發明說明（3) 即可維持電解電鍍製法之可得到較厚的電路電鍍層之優 點，又可消除該電鍍線來獲得效佳電氣特性的製程法。 本發明之揭露，可提供前揭兩種製程優點之獲得，即 既可採用更多電鍍種類的金屬來電鍍，又可鍍出較厚的電 路，且又不會留下電鍍線在基板上的製程。 為使本發明之上述目的得以實現，並可更清楚瞭解其 使用的結構原理，茲配合簡單圖式說明如后： 具體實施例： 本發明主要係一種薄型球柵陣列（TBGA)基板 (Substrate)製程，係可克服目前習知薄型球柵陣列基板 製程之無法僅顧「無電鍍」與「電解電鍍」優點，進而開 發的一種既可採用電鍍方式可鍍高電路線厚度之優點，卻 又不會將該電鍍線留在基板的製程。 請配合參照第2a圖〜第2k圖所示並對應以下之a〜t 各製程，首先： 製程a:使用聚醜亞銨21薄膜層（poiyimide fiini)作為恭 體2。 Ά 製程b:為能該聚醯亞銨21薄膜層上長出銅層23，故先在 該聚醯亞銨21薄膜層上濺鍍出一層薄鋼22。 製程c:於整個載體2薄銅層22表面上鍍出一層相對較 厚之銅層2 3，以作為後續電鍍的媒介。 製程d:在整體載體2的最上層與最下層塗佈適當厚度之 片的上、下積層感光塗料24、25層。4442 5 9 V. Description of the invention (3) A process method that can maintain the advantages of obtaining a thicker circuit plating layer by electrolytic plating, and eliminate the plating line to obtain effective electrical characteristics. The disclosure of the present invention can provide the advantages of the two processes of pre-exposure, that is, both more plating types of metal can be used for plating, and thicker circuits can be plated without leaving the plating lines on the substrate. Process. In order to achieve the above-mentioned object of the present invention, and to better understand the structural principle used by it, the following is described with a simple diagram: Specific embodiments: The present invention is mainly a thin ball grid array (TBGA) substrate (Substrate) The manufacturing process can overcome the current conventional thin ball grid array substrate manufacturing process, which cannot only consider the advantages of "electroless plating" and "electrolytic plating", and then develops an advantage that can use the plating method to plate high circuit line thickness without This plating line is left on the substrate process. Please refer to Figures 2a to 2k and refer to the following a to t processes. First: Process a: Use polyimide 21 film layer (poiyimide fiini) as the body 2. Ά Process b: In order to grow a copper layer 23 on the polyfluorene ammonium 21 film layer, a thin steel layer 22 is sputtered on the polyfluorene ammonium 21 film layer. Process c: A relatively thick copper layer 23 is plated on the entire surface of the thin copper layer 22 of the carrier 2 as a medium for subsequent electroplating. Process d: The upper and lower layers of the monolithic carrier 2 are coated with 24 and 25 layers of photosensitive paint on the upper and lower layers of an appropriate thickness.

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五、發明說明（4) :在頂層上方與底層下方分別設置一光罩26，該光 罩26上具有可透光之電路線路轨跡261，並予以曝 光（exposure)處理 ° 製程f:經曝光處理後顯影，俾在上、下積層感光塗料24 、25層上相對於電路線路配置軌跡261的位置處被 去除，其餘部份留下，使在上、下積層感光塗料 24層上形成凹入之電路線路軌跡241、251配置圖 JW -to · g •在载艘2表面锻銅27’使該ej入之電路線路轨跡 241底下的銅層23上再鍍出一層銅27，其高度與上 積層感光塗料24層略低。 製程h :於載體2底層施以蝕刻（etching)作業，去除的底 面的凹入之電路線路執跡251，即不被積層感光塗 料25覆蓋的聚醢亞銨丨丨薄膜層處被吃去。 製程i .在該載體复表面之銅27上即（凹入之電路線路軌跡 241的位置處）以連接焊料的金屬材料29(如錫鉛合 金63Sn/37Pb)電鍍，使其鍍出的高度和該上積層 感光塗料24同高。 製程j:以藥劑洗去殘餘的上積層的感光塗料24層及下積 層的感光塗料25層》 製程k:蝕刻去除表面之銅層23多餘的部份，僅保留電路 線3(如第2K圖所示）及連接烊料的金屬材料29。 據此，在本發明製程完成後，可直接在連接焊料的金 屬材料29上植上錫球應用。因此不須留下為在電路線3上V. Description of the invention (4): A photomask 26 is provided above the top layer and below the bottom layer, and the photomask 26 has a light-transmitting circuit trace 261, and is exposed (exposure). Process f: After exposure Developed after processing, the radon was removed from the upper and lower layers of photosensitive paint 24 and 25 relative to the circuit line configuration track 261, and the rest was left, so that recesses were formed on the upper and lower layers of photosensitive paint 24. Circuit diagram 241,251 of the circuit layout JW -to · g • Copper 27 on the surface of the carrier 2 is forged with copper 27 ', and the copper layer 23 under the circuit trace 241 of the ej is plated with a layer of copper 27, the height and The upper 24 layers of photosensitive paint are slightly lower. Process h: An etching operation is performed on the bottom layer of the carrier 2 to remove the recessed circuit trace 251 on the bottom surface, that is, the polyimide film not covered by the laminated photosensitive coating 25 is eaten. Process i. Electroplating on the copper 27 of the carrier complex surface (ie, at the position of the recessed circuit trace 241) with a metal material 29 (such as tin-lead alloy 63Sn / 37Pb) connected to the solder, The upper build-up photosensitive paint 24 has the same height. Process j: The remaining upper layer of photosensitive paint 24 and the lower layer of photosensitive paint 25 are washed away with a chemical. Process k: Etching removes the excess part of the copper layer 23 on the surface, leaving only the circuit line 3 (as shown in Figure 2K (Shown) and the metal material 29 to which the material is connected. Accordingly, after the process of the present invention is completed, a solder ball can be directly applied on the metal material 29 connected to the solder. So there is no need to stay on circuit line 3

4442 5 9 五、發明說明（5) 鍍鎳、金時所必需如習用電鍍線17情形，而本發明在銅層 23電鍍銅27(製程g)時所用的電鍍線（圖中未示出）亦已在 製程k時連同銅層23被蝕刻去除，因此，本發明可應用電 鍍製法使該電路線3獲得一較佳之厚度，且可以去除造成 電氣特性差之電鍍線，實為克服習知製程缺失之好方法。 雖然本發明以一較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可作各種更動與潤飾，因此本發明之保護 範圍應同時參酌後附之申請專利範圍所界定者。4442 5 9 V. Description of the invention (5) The nickel plating and gold plating must be used as the conventional plating line 17, and the present invention is used when the copper layer 23 is electroplated with copper 27 (process g) (not shown in the figure). It has also been removed by etching with the copper layer 23 during the process k. Therefore, the present invention can apply the electroplating method to obtain a better thickness of the circuit line 3, and can remove the electroplated line that causes poor electrical characteristics, which overcomes the conventional process Missing good way. Although the present invention is disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. The scope of protection shall also refer to those defined in the appended patent application scope.

第10頁 ο 9 圖式簡單說明 第la〜lk圖係習知TBG Α基板之電解電鍍製程示意圖。 第1K圖係第1 f圖之立體示意圖。 第2a〜2k圖係本發明之TBG A基板製程示意圖。 第2K圖係第圖之立體示意圖。 各圖式所用符號說明： 1. 載體 1 1.聚醯亞銨 12.銅 1 3.銅層 1 4.積層感光塗料 15.光罩 1 5 1.電路線路軌跡 1 6，銅 1 7.電鍍線 18.鎳、金等金屬電鍍層 1 9.電路線 2. 載體 21. 聚醯亞銨 22. 銅 23. 銅層 24. 上積層感光塗料 241.凹入之電路線路軌跡 25. 下積層感光塗料 251.四入之電路線路軌跡Page 10 ο 9 Brief Description of Drawings Figures la ~ lk are schematic diagrams of the electrolytic plating process of the conventional TBG Α substrate. Figure 1K is a schematic perspective view of Figure 1f. Figures 2a to 2k are schematic diagrams of the TBG A substrate manufacturing process of the present invention. Figure 2K is a schematic perspective view of the second figure. Explanation of symbols used in each drawing: 1. Carrier 1 1. Polyammonium cyanide 12. Copper 1 3. Copper layer 1 4. Laminated photosensitive paint 15. Photomask 1 5 1. Circuit trace 1 6 and copper 1 7. Plating Line 18. Nickel, gold and other metal plating layer 1 9. Circuit wire 2. Carrier 21. Polyammonium polyimide 22. Copper 23. Copper layer 24. Upper layer of photosensitive coating 241. Recessed circuit track 25. Lower layer of photosensitive Paint 251. Four-entry circuit track

第11頁 4 圖式簡單說明 26.光罩 2 6 1.電路線路執跡 2 7 ‘銅 29.連接焊料的金屬材料 3.電路線Page 11 4 Schematic description 26. Mask 2 6 1. Circuit track 2 7 ‘Copper 29. Metal material for solder connection 3. Circuit wire

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Claims (1)

4442 5 六、申請專利範圍 一種薄型球柵陣列基板製程，係可以將基板電路鍍一 較佳厚度、並可將基板上的電鍍線去除的製程；其製程如 下： 製程a:使用聚醯亞銨薄膜層作為载體； 製程b:在聚醯亞銨薄膜層上濺鍍出一層薄銅； 製程c:於載體薄銅層表面上快閃鍍出一層相對較厚之銅 層； 製程d:在載體的上層與下層塗佈適當厚度之整片的上、 下積層感光塗料層； 製程e:在頂層上方與底層下方分別設置一光罩，該光 罩上具有可透光之電路線路轨跡，並予以曝光處 理； 製程f:經曝光處理後顯影，俾在上、下積層感光塗料層 上相對於電路線路配置軌跡的位置處被去除，其 餘部份留下，使在上、下積層感光塗料層上形成 凹入之電路線路軌跡配置圖； 製程g:在載體表面鍍銅，使該凹入之電路線路軌跡底下 的銅層上再鍍出一層銅，其高度與上積層感光塗 料層略低； 製程h:於載體底層施以蝕刻作業，去除的底面的凹入之 電路線路軌跡，即不被積層感光塗料覆蓋的聚醯 亞銨薄膜層處被吃去； 製程i:在該載體表面之銅上即（凹入之電路線路軌跡的位 置處）以連接焊料的金屬材料電鍍，使其鍍出的高4442 5 VI. Scope of patent application A thin ball grid array substrate manufacturing process is a process that can plate the substrate circuit to a better thickness and remove the plating lines on the substrate; the process is as follows: Process a: using polyammonium The thin film layer is used as a carrier; Process b: Sputtering a thin copper layer on the polyfluorene ammonium film layer; Process c: Quickly plating a relatively thick copper layer on the surface of the thin copper layer of the carrier; Process d: In The upper and lower layers of the carrier are coated with the entire thickness of the upper and lower layers of the photosensitive coating layer. Process e: a photomask is provided above the top layer and below the bottom layer, and the photomask has light-transmitting circuit traces. And exposure processing; process f: after exposure processing, development, the photoresist is removed on the upper and lower layers of the photosensitive paint layer with respect to the position of the circuit circuit configuration track, and the rest is left, so that the upper and lower layers of the photosensitive paint are laminated A recessed circuit trace configuration diagram is formed on the layer; process g: copper is plated on the surface of the carrier, and a copper layer is plated on the copper layer under the recessed circuit trace, the height of which is sensitive to the upper layer The material layer is slightly lower. Process h: the bottom of the carrier is subjected to an etching operation, and the concave circuit traces of the bottom surface that are removed, that is, the polyimide film layer not covered by the laminated photosensitive coating is eaten; process i: at The copper on the surface of the carrier (that is, the position of the recessed circuit trace) is plated with a metal material connected to the solder, so that 第13頁 4442 5 9 六、申請專利範圍 度和該上積層感光塗料同高； 製程j:以藥劑洗去殘餘的上積層的感光塗料層及下積層 的感光塗料層； 製程k:蝕刻去除表面之電路線其餘部份，僅保留電路線 及連接焊料的金屬材料。Page 13 4442 5 9 6. The scope of the patent application is the same as that of the upper layer of the photosensitive coating; Process j: the remaining upper layer of the photosensitive coating layer and the lower layer of the photosensitive coating layer are washed away with a chemical agent; the process k: etching removes the surface For the rest of the circuit line, only the circuit line and the metallic material connected to the solder remain. 第14頁Page 14