1、4429 0 9 _ · 五、發明說明（l) 本發明是有關於半導體積體電路（integrated ccircuit)的製程，特別是有關於以銅金屬製作鑲嵌式内 連線構造（dual damascene interconnect)的改良製程， 其利用多一次的銅金屬沈積步驟（c〇ppei· deposition)以 及化學機械研磨步锁（chemical mechanical polishing; CMP)以達到銅金屬内連線表面平坦化的目的。 不論何種電子元件均少不了用來傳輸電訊的金屬導 線’半導體積體電路元件亦然，各個元件必藉由適當的内 連線當作電性連接’方得以發揮所欲達成之功能。在今曰 多層内連線製程中，除了製作各層導線圖案之外，更須藉 助接觸孔（con tact via)構成，以作為元件接觸區與導線 之間或是多層導線之間的聯繫通道。尤其是當線寬曰益縮 小時，有一種稱為鑲嵌式内連線的構造被廣為應用。 以下即利用第1 A〜1 D圖，以說明習知技術形成銅金屬 鑲嵌式内連線的製造流程。 首先，請參照第1A圖’其顯示形成有絕緣層1 2的半導 體基底10，其上方可以形成任何所需的半導體元件，此處 為了簡化起見，僅以一平整的基底1〇表示之。絕緣層12具 有包含内連線溝槽（trench) 1 6與接觸孔14的鑲嵌式開口 DO ° 接著’請參照第1B圖’在上述銅金屬镶傲式開口])〇的 側壁（s i d e wa 11 )以及底部（b 〇 11 〇m )形成一阻絕層 (barrier layer) 18，用以防止銅金屬的擴散 (diffusion) 〇1. 4429 0 9 _ · V. Description of the invention (l) The present invention relates to the process of integrated ccircuit, and in particular to the production of dual damascene interconnects made of copper metal. The improved process uses an additional copper metal deposition step (coppei · deposition) and chemical mechanical polishing (CMP) to achieve the purpose of planarizing the surface of the copper metal interconnects. No matter what kind of electronic component is indispensable, the metal wire used for transmitting telecommunications is also a semiconductor integrated circuit component, and each component must perform its desired function by using appropriate interconnects as electrical connections. In today's multi-layer interconnection process, in addition to making each layer of wire pattern, it is also necessary to use contact holes (con tact via) to form the contact channel between the component contact area and the wire or between the multi-layer wire. Especially when the line width is reduced, a structure called a mosaic interconnect is widely used. The following is the use of Figures 1 A to 1 D to illustrate the manufacturing process of forming copper metal inlaid interconnects using conventional techniques. First, please refer to FIG. 1A, which shows a semiconductor substrate 10 having an insulating layer 12 formed thereon, and any desired semiconductor element can be formed thereon. Here, for simplicity, it is represented by a flat substrate 10 only. The insulating layer 12 has a mosaic opening DO including an interconnect trench (trench) 16 and a contact hole 14. Then, “Please refer to FIG. 1B” in the above copper metal mosaic opening]] (a side wall 11). ) And bottom (b 〇11 〇m) to form a barrier layer 18, to prevent diffusion of copper metal (diffusion).
第4頁 • Γ 4429 0 9 五、發明說明（2) 然後’請參照第1 C圖’利用填溝能力（g a p f丨1 1丨n g ) 佳的沈積方法全面性地形成銅金屬層2 0。 接著’請參照第1D圖，利用化學機械研磨法 層2 0進行平坦化製程，直到露出絕緣層丨2表面為止_S金屬 下位於鑲嵌式開口 D0之銅金屬2Oa。 ’以留 由於化學機械研磨時之銅研漿（copper sll卜 、 後續清洗溶液的作用，使得上述銅金屬2 〇 a表面^ ^及 或是凹陷處。 +損傷 如此的凹陷處或是受損不僅會影響其導電性，β 甚至會造成斷路的問題。 嚴重時 有鑑於此，本發明的目的在於提供一種銅. 内連線的製造方法，以消除銅内連線因研磨處理或 ^式 洗溶液蝕刻所造成的凹陷或損傷。 3後續清 根據上述目的，本發明提供一種銅金屬鎮嵌式 的製造方法，適用於半導體基底，上述方法包内連線 驟：在上述半導體基底上方形成一絕緣層，上述絕^步 有包含内連線溝槽與接觸孔的鑲嵌式開口；沈積、一、第層具 金屬層，上述第1銅金屬層填入上述鑲嵌式開D内，1麵 延伸於上述絕緣層表面；施以化學機械研磨法，、且 於上述鑲嵌式開口内的第1銅金屬，上述鑲嵌式開口 Γ位 第1銅金屬表面具有凹陷處；沈積一第2銅金屬層，、内的 上述凹陷處；施以化學機械研磨法以得到表面平填入 屬鑲嵌式内連線。 —的銅金 上述鋼金屬鑲嵌式内連線的製造方法，其中 絕緣層 係Page 4 • Γ 4429 0 9 V. Description of the invention (2) Then ‘please refer to FIG. 1C’ to form a copper metal layer 20 using the trench filling ability (g a p f 丨 1 1 丨 n g). Next, please refer to FIG. 1D, and use a chemical mechanical polishing method to planarize the layer 20 until the surface of the insulating layer 丨 2 is exposed. The copper metal 2Oa located under the mosaic opening D0 under the metal. 'Ire due to the effect of copper slurries (copper sll and subsequent cleaning solutions during chemical mechanical polishing), the surface of the above copper metal 20a and or depressions. + Damage to such depressions or damage not only Will affect its conductivity, β may even cause the problem of disconnection. In serious cases, in view of this, the purpose of the present invention is to provide a method of manufacturing copper. Interconnects to eliminate copper interconnects due to grinding or cleaning solution Depression or damage caused by etching. 3 Subsequent cleaning According to the above purpose, the present invention provides a copper metal embedded manufacturing method suitable for a semiconductor substrate. The above method includes interconnecting steps: forming an insulating layer over the semiconductor substrate. The above-mentioned step has a mosaic opening including an interconnecting trench and a contact hole; a metal layer is deposited, a first layer, and the first copper metal layer is filled in the mosaic opening D, and one surface extends above the above. The surface of the insulating layer; the first copper metal that is subjected to a chemical mechanical polishing method and is in the mosaic opening, and the surface of the first copper metal at the position of the mosaic opening has a depression; A second copper metal layer, the above-mentioned depressions inside; applying a chemical mechanical polishing method to obtain a flat filling surface of the metal-inlaid inner interconnect.-A method of manufacturing the copper-gold above-mentioned steel-metal embedded inner interconnect, Insulation system
4429 Ο 9 A * 五、發明說明（3) 二氧化矽層；第1銅金屬層係利用電化學沈積法 (electro-chemical deposition ;ECD)沈積而成。而上述 第2銅金屬層係利用離子金屬電漿（ion metal plasma ; IMP)沈積法沈積而成。 再者，上述鋼金屬鑲嵌式内連線的製造方法，其中沈 積上述第1銅金屬層之前，更包括在上述鎮嵌式開口的側 壁以及底部形成一阻絕層（钽層或钽化氮層）的步驟。 並且’為了使本發明的目的更容易達到，上述銅金屬 鑲嵌式内連線的製造方法，其中沈積第2鋼金屬層之前， 更包括施以一回餘刻的步驟，用以加深上述凹陷處的尺 冉贫，上迅銅金屬銀嵌式鬥逆跟的製造方法，其 積第2銅金屬層之前，更包括在上述第1鋼金屬 ^二中 |屬之别沈積 阻絕層（钽層或鈕化氮層）。 根據上述目的，本發明提供另一種鋼金屬鎮# 線的製造方法，適用於表面損傷或是具有凹陷處内 鑲後式結構，上述方法包括下列步驟：在上硫主丈:“ <衣面損傷 是具有凹陷處之銅金屬鑲嵌式結構上方形成—鋼金屬= 以修補上述損傷或填入上述凹陷處；以及對上述鋼金層 施以化學機械研磨法，以得到表面平坦的銅金屬^私^ 連線。 瓜， 以下配合圖式以及較佳實施例’以更詳細地說明本發 明。 x 圖式之簡單說明4429 Ο 9 A * V. Description of the invention (3) Silicon dioxide layer; The first copper metal layer is deposited by electro-chemical deposition (ECD). The second copper metal layer is deposited by an ion metal plasma (IMP) method. In addition, the method for manufacturing the steel-metal embedded interconnect, before depositing the first copper metal layer, further includes forming a barrier layer (tantalum layer or tantalum nitride layer) on the side wall and the bottom of the recessed opening. A step of. And 'In order to make the purpose of the present invention easier to achieve, the above-mentioned method for manufacturing a copper-metal inlaid interconnector, wherein before depositing the second steel metal layer, the method further includes applying a step for a while to deepen the depression. The manufacturing method of the high-speed copper metal silver inlaid bucket heel of Shangxun is before the second copper metal layer is deposited, and it is also included in the above-mentioned first steel metal ^ 2 | Button nitrogen layer). According to the above object, the present invention provides another method for manufacturing a steel metal town line, which is suitable for surface damage or has a recessed inlay structure. The above method includes the following steps: on the sulfur master: "< clothing surface The damage is formed over the copper metal inlaid structure with depressions-steel metal = to repair the damage or fill the depressions; and apply chemical mechanical polishing to the steel and gold layer to obtain a copper metal with a flat surface. ^ Connect. Melon, the following is a detailed description of the present invention with the drawings and preferred embodiments. X Brief description of the drawings
第6頁 4429 0 9Page 6 4429 0 9
習知技術形成銅金屬鑲嵌式内連線 第1A〜1 D圖係利用 的製程剖面流程圖。 第2A〜第2F圖係根據本發明較佳實施例以形成銅金屬 鑲嵌式内連線的製程剖面流程圖。 符號之說明 100〜半導體基底。 ' 112〜絕緣層。 114〜接觸孔。 11 6〜内連線溝槽。 鑲嵌式開口。 11 8 ~阻絕層。 1 2 0、1 2 0 a〜第1銅金屬層。 1 2 2〜阻絕層。 124〜第2銅金屬層。 RE〜凹陷處。 20 0~表面平坦之鋼金屬鑲嵌式内連線。 實施例 以下請參照第2A-2F圖之製作流程剖面圖，以說明本 發明實施例。 首先，δ青參照第2A圖，其顯示形成有例如二氧化矽構） 成之絕緣層112的半導體基底100，並且半導體基底1〇〇例 如為單晶矽基底，其上方可以形成任何所需的半導體元 件，此處同樣為了簡化起見，僅以一平整的基底1〇表示 之。而、絕緣層U2之既定位置具有包含内連線溝槽U6與接Forming copper metal inlaid interconnects using conventional techniques. Figures 1A to 1D are cross-sectional flowcharts of the process used. Figures 2A to 2F are cross-sectional flowcharts of a process for forming a copper metal inlaid interconnect according to a preferred embodiment of the present invention. Explanation of symbols 100 to semiconductor substrate. '112 ~ Insulation. 114 ~ contact holes. 11 6 ~ Interconnect trench. Inlaid opening. 11 8 ~ Barrier layer. 1 2 0, 1 2 0 a to 1st copper metal layer. 1 2 2 ~ barrier layer. 124 to the second copper metal layer. RE ~ depression. 20 0 ~ Steel metal inlaid inner wire with flat surface. EXAMPLES The following is a cross-sectional view of the manufacturing process with reference to Figures 2A-2F to illustrate examples of the present invention. First, referring to FIG. 2A, δcyan shows a semiconductor substrate 100 formed with an insulating layer 112 made of, for example, silicon dioxide, and the semiconductor substrate 100 is, for example, a single crystal silicon substrate, and any desired one can be formed thereon. The semiconductor element is also represented here only by a flat substrate 10 for the sake of simplicity. Moreover, the predetermined position of the insulating layer U2 has an interconnecting trench U6 and a connection
4429 〇 9 五、發明說明（5) ~ -- 觸孔114的鑲嵌式開口 D0，上述鑲嵌式開口 D〇至少經過兩 次的微影製程以及蝕刻步驟形成。 接著，請參照第2B圖，利用例如物理氣相沈積法 (physical vapor deposition ;PVD)在上述銅金屬鎮後式 開口 DO的側壁以及底部形成鋰（Ta)或鈕化氮（TaN)層等阻 絕層11 8 ’其亦延伸至絕緣層丨丨2的表面，阻絕層丨丨8可以 防止銅金屬在後續熱製程擴散（diffusion)至下方的半導 體基底1 0 0。 然後’請參照第2 C圖，利用物理氣相沈積法激鑛或是 以填溝能力強的電化學沈積（e 1 ect ro-chemica 1 deposition ;ECD)方式全面性地形成第i鋼金屬層12〇。 接著’請參照第2 D圖，利用化學機械研磨法對第j銅 金屬層1 2 0進行平坦化製程’直到露出絕緣層丨〗2表面為 止，以留下位於鑲嵌式開口DO之第1銅金屬12〇a，由於化 學機械研磨時之銅研漿以及後續清洗溶液的作用，使得上 述第1銅金屬120a表面存在損傷或是凹陷處㈣。 其次’請參照第2E圖，利用例如物理氣相沈積法全面 性形成一钽或是鈕化氮層構成的阻絕層丨2 2，然後，利用 例如離子金屬電漿（ion metal plasma ; IMP)沈積法形成 性質較安定的第2銅金屬層124。 、 最後，請參照第2F圖，利用化學機械研磨法對第2 金屬層124進行平坦化製程’直到露出絕緣層112表面 止，以留下部分阻絕層1 22a、以及部分第2銅金屬層 124a ’此時形成由阻絕層122a、第2銅金屬層124&、第【鋼4429 〇 9 V. Description of the invention (5) ~-The mosaic opening D0 of the contact hole 114 is formed through at least two photolithography processes and etching steps. Next, referring to FIG. 2B, a physical vapor deposition method (physical vapor deposition (PVD)) is used to form a lithium (Ta) or buttoned nitrogen (TaN) layer on the side wall and the bottom of the copper metal town-type opening DO. The layer 11 8 ′ also extends to the surface of the insulating layer 丨 2, and the barrier layer 丨 8 can prevent copper metal from diffusing in the subsequent thermal process to the semiconductor substrate 100 below. Then, please refer to FIG. 2C, use physical vapor deposition to excite the ore or use electrochemical deposition (e 1 ect ro-chemica 1 deposition; ECD) to form the i-th steel metal layer comprehensively 12〇. Next, 'Please refer to FIG. 2D, use the chemical mechanical polishing method to planarize the j-th copper metal layer 1 2 0' until the surface of the insulating layer 丨 2 is exposed, so as to leave the first copper at the mosaic opening DO The metal 120a is damaged or recessed on the surface of the first copper metal 120a due to the effect of the copper slurry during chemical mechanical polishing and the subsequent cleaning solution. Secondly, please refer to FIG. 2E, using a physical vapor deposition method to comprehensively form a barrier layer composed of tantalum or a buttoned nitrogen layer 丨 2 2, and then using, for example, ion metal plasma (IMP) deposition The second copper metal layer 124 is formed by a stable method. Finally, referring to FIG. 2F, a planarization process of the second metal layer 124 is performed by chemical mechanical polishing method until the surface of the insulating layer 112 is exposed, so as to leave part of the barrier layer 122a and part of the second copper metal layer 124a. 'At this time, the barrier layer 122a, the second copper metal layer 124 &, and the [steel
第8頁 >· 4429 Ο 9 五'發明說明（6) 金屬120a、阻絕層u8a構成的銅金屬鑲嵌式内連線2〇〇， 其不但具有平坦的表面，而且亦填補了第1銅金屬120a受 損的部分。 當然’為了使本發明的效果更為顯著，可以在形成第 2銅金屬層124之前，施以第1銅金屬層12 〇a的回蝕刻步 驟’以加深凹陷處的深度’藉此’可增進後續之銅導線 的平坦化效果。 發明特徵及效果 本發明的特徵在於，有鑑於進行第1銅金屬層〗2〇之化 學機械研磨步驟之後，會使第1銅金屬12〇a表面產生若干 受損或是凹陷處，因此，再一次進行第2銅金屬層124的沈 積’並且施以化學機械研磨製程，以得到表面平坦且修補 支相之鋼金屬鎮嵌式内連線200。藉此，可確保内連線之 導電特性’進而改善半導體積體電路元件的可靠度。 本發明雖然以離子金屬電漿沈積法形成第2銅金屬層 1 24為例，然而不以此為限，只要是有能力形成銅金屬層 之化學氣相沈積或是物理氣相沈積方式皆可選用。 雖然本發明已以較佳實施例揭露如上，鈇其並非用以 限定本發明，任何熟習此項技藝者’在不脫本發明之精 =和範圍内，當可作更動與潤飾，因此本發明之保護範圍） 虽視後附之申請專利範圍所界定者為準。Page 8 > · 4429 Ο 9 Five 'invention description (6) Copper metal inlaid interconnection 200 composed of metal 120a and barrier layer u8a, which not only has a flat surface but also fills the first copper metal 120a damaged part. Of course, 'in order to make the effect of the present invention more significant, before the second copper metal layer 124 is formed, the etch-back step of the first copper metal layer 120a' can be performed to 'deepen the depth of the depression', thereby increasing Subsequent planarization of copper wires. Features and Effects of the Invention The present invention is characterized in that, after the chemical mechanical polishing step of the first copper metal layer 20 is performed, the surface of the first copper metal 120a may be damaged or depressed, and therefore, Deposition of the second copper metal layer 124 is performed once and a chemical mechanical polishing process is performed to obtain a steel metal ballasted interconnect 200 with a flat surface and repaired branch phases. Thereby, the conductive characteristics of the interconnections can be ensured, and the reliability of the semiconductor integrated circuit element can be improved. Although the present invention takes the ionic metal plasma deposition method to form the second copper metal layer 124 as an example, it is not limited to this, as long as it is a chemical vapor deposition or physical vapor deposition method capable of forming a copper metal layer Optional. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can change and retouch without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection) Although it is subject to the scope of the patent application attached.
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