TW439186B - A partially recessed shallow trench isolation method for fabricating borderless contacts - Google Patents
A partially recessed shallow trench isolation method for fabricating borderless contacts Download PDFInfo
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4391 Ββ 五、發明說明(i) 【發明之背景】 (1 )發明之背景 本發明的一般性目的係為提供一種形成積體電路的嶄 新且經改良的方法,其係使用與鈍化性氮化物溝渠襯墊相 關之部份凹陷淺溝渠隔離(ST I )法以製造無邊際接觸。 在次微米技術中,淺溝渠隔離(ST I )已變成半導體裝 置隔離的標準方法並取代其他隔離法,亦即需要較多面積 的局部矽氧化法(LOCOS)。在傳統的淺溝渠隔離製程中, 溝渠被形成於電主動區(亦即Μ 0 SF E T閘極與源極/汲極)之 間的半導體基板中,並將M0SFET彼此電隔離。該溝渠係以 諸如氧化矽等絕緣材料填充,以提供電隔離。包含M0SFET 之電晶體的主動裝置與電阻器被製造於具有淺溝渠隔離( ST I )的"主動”區的半導體基板中,以將主動裝置之間的區 域隔離。 由於電晶體尺寸為次微米,所使用的傳統接觸構造開 始在多方面限制裝置性能。首先,若接觸孔亦為最小此寸 且清洗微小接觸孔的問題係為所顧及,則其係難以降低接 觸電阻率。此外,藉所形成的傳統接觸,該源極/汲極區 的面積無法被降低,因為該接觸孔係以分離的罩幕步驟對 齊於這些區域,且一極大的Μ額外Μ面積必須被用於誤差。 此外,該較大的"額外Μ面積亦造成增加的源極/汲極一基 板接面電容,其對於裝置速率有負面影響。無邊際接觸或 "無邊框Μ接觸將解決許多微米與次微米M0SFET接觸的問題 ,而放寬裝置基本準則設計及傳統”邊框"接觸的加工問題4391 Β β 5. Description of the invention (i) [Background of the invention] (1) Background of the invention The general purpose of the present invention is to provide a new and improved method for forming integrated circuits, which uses and passivates nitrides. Part of the trench liner is a recessed shallow trench isolation (ST I) method to create borderless contact. In sub-micron technology, shallow trench isolation (ST I) has become the standard method for semiconductor device isolation and replaces other isolation methods, that is, the local silicon oxidation (LOCOS) method that requires a larger area. In a conventional shallow trench isolation process, trenches are formed in a semiconductor substrate between electrically active regions (ie, M 0 SF E T gate and source / drain), and the MOSFETs are electrically isolated from each other. The trench is filled with an insulating material such as silicon oxide to provide electrical isolation. The active device and resistor containing the transistor of the MOSFET are manufactured in a semiconductor substrate with a "active" region of shallow trench isolation (ST I) to isolate the area between the active devices. Since the transistor size is sub-micron The traditional contact structure used began to restrict the device performance in many aspects. First, if the contact hole is also the smallest and the problem of cleaning tiny contact holes is taken into consideration, it is difficult to reduce the contact resistivity. In addition, The area of the source / drain region cannot be reduced due to the conventional contacts formed, because the contact holes are aligned with these areas in separate mask steps, and a large extra M area must be used for error. In addition, The larger " extra M area also results in increased source / drain-substrate junction capacitance, which has a negative impact on device speed. Borderless contact or " borderless M contact will address many micro and sub-micron MOSFETs Contact problems, while relaxing the basic design of the device and the traditional "frame" contact processing problems
第7頁 五、發明說明(2) 。該無邊際接觸利用源極/汲極區上的空間與面積,其將 被更詳細地說明。無邊際接觸為先進設計且有關淺溝渠隔 離(S T I )加工的一部份。 (2 )習知技藝之'說明 藉傳統淺溝渠隔離(ST I )加工,形成一無邊際接觸於 溝渠區域上係為一難題。該無邊際接觸或”無邊框M接觸係 為位在半導體裝置的主動與隔離區上並將其曝露出的接觸 ,其通常用於與形成在基板中的擴散區接觸。形成與傳統 淺溝渠隔離結合之無邊際接觸的問題包含穿經中間介電層 將接觸孔開口蝕刻,並同時避免將溝渠中的介電材料蝕刻 。通常,中間層與溝渠填充材料為氧化矽的形式。因此, 該溝渠填充氧化物可因接觸孔的蝕刻而被蝕刻並損傷。若 該溝渠隔離材料沿著溝渠壁被回蝕,則損傷效應將發生, 亦即在P / N接面邊緣的漏電及短路,特別是當該區域為導 電材料所填充時。 1998年9月15日核准之標題為"Device Isolaton Methods for a semiconductor Device"的美國專利第 5, 807, 784號(Kim等人)說明一種形成一裝置隔離層於半導體 裝置的方法,其包含形成場氧化物於淺溝渠隔離(ST I )中 的二步驟方法。第一個步驟包含將氧離子植入半導體基板 之場區域中的溝渠底部,並將該植入氧的區域氧化以形成 一場氧化層,第二個步驟包含沈積絕緣材料,以進一步填 充溝渠。Page 7 5. Description of the invention (2). This borderless contact makes use of space and area on the source / drain regions, which will be explained in more detail. Borderless contact is part of advanced design and related to shallow trench isolation (S T I) processing. (2) 'Explanation of the know-how' By the traditional shallow trench isolation (ST I) processing, forming a borderless contact with the trench area is a difficult problem. The borderless contact or "borderless M contact" is a contact that is located on the active and isolation regions of a semiconductor device and is exposed. It is generally used to contact the diffusion region formed in the substrate. Forming isolation from traditional shallow trenches The problem of combined borderless contact involves etching the opening of the contact hole through the intermediate dielectric layer while avoiding etching of the dielectric material in the trench. Usually, the intermediate layer and the trench filling material are in the form of silicon oxide. Therefore, the trench The filling oxide can be etched and damaged by the etching of the contact hole. If the trench isolation material is etched back along the trench wall, the damage effect will occur, that is, leakage and short circuit at the edge of the P / N interface, especially When the area is filled with a conductive material. U.S. Patent No. 5,807,784 entitled "Device Isolaton Methods for a Semiconductor Device" approved on September 15, 1998 (Kim et al.) Describes a method for forming a device A method for isolating a layer on a semiconductor device includes a two-step method of forming a field oxide in shallow trench isolation (ST I). The first step includes isolating oxygen Field implant region of the trench bottom in the semiconductor substrate, and oxidation of the oxygen is implanted region to form a field oxide layer, the second step includes depositing an insulating material to further fill the trench.
1998年9月8日核准之標題為"METHOD OF FILLINGThe title approved on September 8, 1998 was " METHOD OF FILLING
第8頁 43 91 8 6 五、發明說明(3) SHALLOW TRENCHES11 的美國專利第 5, 80 7, 490 號(Fiegl 等 人)說明一種在矽積體電路加工中的隔離法,其將溝渠以 填充邊際過度填充並沈積厚度小於溝渠深度的一暫置多晶 石夕層。一個氧化層被使用為拋光阻絕物。溝渠外的暫置層 被拋光,其係使用一填充層與拋光阻絕層作為化學機械拋 光(CMP)的拋光阻絕物。該拋光阻絕層與相同厚度的填充 層及暫置多晶矽層為CMP所移除,而產生表面平坦化。殘 留的暫置層被撥除,且最終的填充層拋光終止於襯墊氮化 物上。 1998年10月6日核准之標題為"Method of Forming a Trench Isolation Region"的美國專利第5,817,568號( C h a o等人)說明一種使用複溝渠形成技術以形成具有不同 寬度之個別溝渠深度的方法。該方法包含依序形成一缓衝 氧化層及拋光阻絕層於一半導體基板上。其次,該緩衝氧 化層、拋光阻絕層與半導體基板被定義以形成至少一個窄 溝渠。其次,該缓衝氧化層、拋光阻絕層與半導體基板再 次被定義以形成至少一個寬溝渠。其次,一部份的氧化層 與一部份的拋光阻絕層被移除以形成一平坦表面。最後, 該拋光阻絕層與緩衝氧化層被移除。 1 9 9 7年7月29日核准之標題為"Method for Providing Trench Isolation and Borderless Contact”的美國專利 第5,6 5 2,176號(Maniar等人)說明一種溝渠隔離法,其係 使用由氮化紹所組成的溝渠襯塾物。另一個相似的專利係 為1997年10月14日核准之標題為”Method for ProvidingPage 8 43 91 8 6 V. Description of the invention (3) US Patent No. 5, 80 7, 490 (Fiegl et al.) Of SHALLOW TRENCHES 11 describes an isolation method in silicon integrated circuit processing, which fills trenches to fill A marginal overfilling and deposition of a temporary polycrystalline layer with a thickness less than the depth of the trench. An oxide layer is used as a polishing barrier. The temporary layer outside the trench is polished, which uses a filling layer and a polishing barrier as a chemical mechanical polishing (CMP) polishing barrier. The polishing stop layer, the filling layer and the temporary polycrystalline silicon layer of the same thickness are removed by the CMP, and the surface is flattened. The remaining temporary layer is removed and the final polishing of the filling layer ends on the pad nitride. U.S. Patent No. 5,817,568 entitled "Method of Forming a Trench Isolation Region" approved on October 6, 1998 (Chao et al.) Illustrates the use of a complex trench formation technique to form individuals with different widths Method of trench depth. The method includes sequentially forming a buffer oxide layer and a polishing resist layer on a semiconductor substrate. Second, the buffer oxide layer, the polishing resist layer, and the semiconductor substrate are defined to form at least one narrow trench. Second, the buffer oxide layer, the polishing barrier layer, and the semiconductor substrate are defined again to form at least one wide trench. Secondly, a part of the oxide layer and a part of the polishing resist are removed to form a flat surface. Finally, the polishing barrier layer and the buffer oxide layer are removed. U.S. Patent No. 5,6 5 2,176 (Maniar et al.) Entitled " Method for Providing Trench Isolation and Borderless Contact " approved on July 29, 1997 (Maniar et al.) Describes a trench isolation method that uses A trench lining made of nitride. Another similar patent was approved on October 14, 1997 and entitled "Method for Providing
第9頁 4391 86 五、發明說明(4)Page 9 4391 86 V. Description of the invention (4)
Trench Isolation"的美國專利第 5,677,231號(Maniar等 人)亦說明淺溝渠隔離(ST I )與一無邊際接觸製程,其在 ST I氧化矽下方具有氮化鋁櫬墊物。在形成接觸窗期間, 使用對於氮化鋁有選擇性的触刻化學物質’該溝渠襯墊物 將保護位於溝渠角落的P-N接面。藉由保護該接面,後續 導電插塞的形成將不會造成接面電短路並維持低二極體漏 電流。 1993年12月7日核准之標題為"Process for Improving Sheet Resistance of a Integrated Circuit Device Gate11 的美國專利第 5,268,330 號(Givens等人) 說明一種包含淺溝渠隔離(STI)的製程,以及可作為無邊 際接觸之位於P - N接面上的接觸。一純化層被沈積於一積 體電路裝置上’其係使用金屬矽化物法製造。一絕緣層被 沈積。該絕緣層被平坦化且進一步抛光,以曝露出位於間 極上的鈍化層。位於閘極上的鈍化層部份被移除。位於接 面上的一溝渠藉移除絕緣層並使用該鈍化層作為餘刻阻絕 物而被形成。其次,位於接面上的一部份純化層被移除。 該閘極可被進一步金屬石夕化物化,且位於閘極上的窗口及 溝渠可被填充。位於接面上的接觸為無邊際接觸。 本發明係有關於一種使用CMP以選擇性地移除位於一 第一種材料上的一第二種材料並形成一平坦的第一種材料 表面(無第二種材料殘留)之嶄新的方法。本發明之方法 需要較少的CMP加工時間’較傳統CMP法有更低的成本並形 成一具有極佳平坦度的拋光表面。US Patent No. 5,677,231 to Trench Isolation " (Maniar et al.) Also describes a shallow trench isolation (ST I) and a borderless contact process that has an aluminum nitride pad under the ST I silicon oxide. During the formation of the contact window, the use of a selective etch chemistry for aluminum nitride ' The trench liner will protect the P-N junction at the corner of the trench. By protecting the junction, subsequent formation of conductive plugs will not cause the junction to be electrically shorted and maintain a low diode leakage current. U.S. Patent No. 5,268,330 entitled "Process for Improving Sheet Resistance of a Integrated Circuit Device Gate11" approved on December 7, 1993 (Givens et al.) Describes a process including shallow trench isolation (STI), And the contact on the P-N junction which can be used as a borderless contact. A purification layer is deposited on an integrated circuit device 'which is manufactured using a metal silicide method. An insulating layer is deposited. The insulating layer is planarized and further polished to expose a passivation layer on the interlayer. The portion of the passivation layer on the gate is removed. A trench on the interface is formed by removing the insulating layer and using the passivation layer as a remaining resist. Secondly, a part of the purification layer on the interface was removed. The gate can be further metallized, and windows and trenches on the gate can be filled. The contact on the interface is a borderless contact. The present invention relates to a novel method of using CMP to selectively remove a second material on a first material and form a flat surface of the first material (without the second material remaining). The method of the present invention requires less CMP processing time 'which has a lower cost than the conventional CMP method and forms a polished surface with excellent flatness.
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五 >發明說明 (5) 發 明 之 概 要 本 發 明 的 般 性 a 的 係 為 提 供 種 形 成 積 體 電 路 的 薪 新 且 經 改 良 的 方 法 > 其 係 使 用 與 保 護 性 氮 化 物 溝 渠 觀 墊 相 關 之 部 份 凹 陷 淺 溝 渠 隔 離 (STI )法以製造無邊際接觸 本 發 明 之 一 更 特 別 的 @ 的 係 為 提 供 一 種 在 積 體 電 路 製 造 於 半 導 體 基 板 上 期 間 之 經 改 良 的 t 邊 際 接 觸 形 成 法 該 基 板 通 常 為 單 晶 矽 〇 最 初 的 製 程 包 含 一 襯 墊 氧 化 物 其 係 藉 献 成 長 - 個 二 氧 化 矽 層 而 被 形 成 〇 其 次 "硬式罩幕11 氮 化 矽 層 被 沈 積 〇 使 用 逆 罩 幕 製 程 k 用 於 淺 溝 渠 隔 離 ( STI ) 的 淺 溝 渠 、 硬 式 罩 幕 氮 化 物 層 及 襯 墊 氧 化 物 被 刻 劃 〇 一 淺 溝 渠 被 刻 並 接 著 沈 積 _ — 厚 的 氧 化 矽 層 〇 該 厚 的 氧 化 矽 層 因 溝 渠 填 充 製 程 而 在 溝 渠 上 的 表 面 中 造 成 些 微 傾 斜 〇 該 表 面 被 平 坦 化 藉 化 學 機 械 Μ 光 ( CMP) 並 使 用 硬 式 罩 幕 氮 化 層 將 該 厚 氧 化 層 拋 光 成 平 坦 〇 該 硬 式 罩 幕 氮 化 層 作 為 抛 光 阻 絕 物 〇 在 本 發 明 的 第 « 個 實 施 例 t 上 述 及 其 他 @ 的 係 藉 使 用 製 造 部 份 凹 陷 淺 溝 渠 隔 離 ( STI ) 構 造 的 方 法 而 被 實 施 > 如 藉 下 列 方 法 所 說 明 〇 在 上 述 的 溝 渠 平 坦 化 之 後 5 藉 一 乾 式 刻 製 程 或 — 濕 式 刻 製 程 而 進 行 部 份 氧 化 矽 的 回 餘 〇 該 部 份 回 敍 步 驟 的 最 終 結 果 係 為 將 溝 渠 中 的 氧 化 物 回 至 溝 渠 中 的 1/2- 3/4 ° 本發印 3之部份回舍 的更多細節可被發 現 於 "DESCRIPTION OF THE PREFERRED EMBODIMENTS" 中 〇 在 本 發 明 的 第 二 個 實 施 例 中 上 述 及 其 他 g 的 係 藉 使 用 製 造 無 邊 際 接 觸 的 方 法 而 被 實 施 其 包 含 位 於 部 份 凹 陷 溝 渠 第11頁 43 91 8 6 五、發明說明(6) 中的氮化矽鈍化層。該保護性氮化物襯墊藉下列方法而於 本發明被完成。在上述之溝渠氧化物的部份回蝕後,僅部 份被凹陷的氧化物殘留於淺溝渠中。在本製程的該步驟, 本發明中的一關鍵性製程係為形成一個氮化矽襯墊於溝渠 中及硬式罩幕氮化物上。該氮化物襯墊藉使用氨氣與矽烷 氣體之低壓化學氣相沈積法(L P C V D )而被形成。在氮*化物 襯墊之前,一可能的緻密化步驟可於一氧化氮氣氛或氧氣 與氮氣中高溫處理。應注意地是,由氮化矽層所組成的溝 渠襯墊物將填充溝渠區域,但是在氮化層底下該溝渠已為 氧化物所部份填充。 形成氮化物襯墊後,一個厚的氧化矽層係藉高密度電 漿(HDP)系統沈積,並以該方法進行而形成一無缝ST I溝渠 填充。本製程的另一個優點係為該氮化層將保護矽半導體 不為高密度電漿製程造成的輻射所損傷。 在厚的高密度電漿(HDP)氧化物沈積後,該表面係藉 化學機械拋光(C Μ P)平坦化,且該回拋光終止於由薄襯墊 物與硬式罩幕層所組成的氮化層。 在藉化學機械拋光將表面平坦化之後,除了殘留於溝 渠中而以氧化物保護不受回蝕的氮化物襯墊以外,該氮化 層以蝕刻移除。由高密度電漿(HDP)蝕刻所沈積之淺溝渠 (ST I )氧化物將填充氮化物襯墊上的溝渠頂端部份。該氮 化物襯墊將殘留於溝渠中的二分之一。在氮化物襯墊下方 之原始部份凹陷氧化物則殘留於溝渠底部。 在本發明的第三個實施例中,上述及其他目的係藉使Fifth > Description of the invention (5) Summary of the invention The generality a of the present invention is to provide a new and improved method for forming integrated circuits > which uses a part related to a protective nitride trench observation pad A recessed shallow trench isolation (STI) method to make a non-marginal contact. One of the more specific aspects of the present invention is to provide an improved t-marginal contact formation method during the fabrication of integrated circuits on a semiconductor substrate. The substrate is usually Monocrystalline silicon. The initial process included a pad oxide which was formed by donating a silicon dioxide layer. Secondly, the "hard mask 11 silicon nitride layer was deposited. A reverse mask process k was used for Shallow trench isolation (STI), shallow trench, hard mask nitride layer, and pad oxide are scribed. A shallow trench is etched and then deposited-thick oxide Silicon layer. The thick silicon oxide layer caused a slight tilt in the surface of the trench due to the trench filling process. The surface was flattened by chemical mechanical light (CMP) and a hard mask nitride layer was used to thicken the oxide layer. Polished to a flat surface. The hard mask nitride layer is used as a polishing stopper. In the «th embodiment of the present invention, the above and other @ 's are implemented by using a method of manufacturing a partially recessed shallow trench isolation (STI) structure. > As explained by the following method: 0 After the trench is flattened as described above, 5 a part of the silicon oxide is recovered by a dry etching process or a-wet etching process. The final result of this part of the reclamation step is The oxides in the ditch return to 1 / 2- 3/4 in the ditch. More details of some of the returns in this issue 3 can be found in " DESCRIPTION OF THE PREFERRED'S " The above and other g's in the second embodiment of the present invention are implemented by using a method for manufacturing a non-border contact, which includes nitrogen in a partially recessed trench. Page 11 43 91 8 6 V. Description of the invention (6) Siliconized passivation layer. The protective nitride liner is completed in the present invention by the following method. After the etch-back of the trench oxide described above, only a part of the recessed oxide remained in the shallow trench. In this step of the process, a key process in the present invention is to form a silicon nitride liner in the trench and on the hard mask nitride. The nitride liner is formed by a low-pressure chemical vapor deposition (L P C V D) method using an ammonia gas and a silane gas. A possible densification step can be performed at high temperatures in a nitric oxide atmosphere or in oxygen and nitrogen before the nitrogen compound. It should be noted that a trench liner composed of a silicon nitride layer will fill the trench area, but the trench is partially filled with oxide under the nitride layer. After the nitride liner is formed, a thick silicon oxide layer is deposited by a high-density plasma (HDP) system and is performed in this way to form a seamless ST I trench fill. Another advantage of this process is that the nitride layer will protect the silicon semiconductor from radiation damage caused by high-density plasma processes. After the deposition of thick high-density plasma (HDP) oxide, the surface was flattened by chemical mechanical polishing (CMP), and the back polishing was terminated by nitrogen consisting of a thin pad and a hard cover化 层。 The layer. After planarizing the surface by chemical mechanical polishing, the nitrided layer is removed by etching, except for a nitride liner which remains in the trench and is protected from etchback by an oxide. A shallow trench (ST I) oxide deposited by high-density plasma (HDP) etching will fill the top of the trench on the nitride liner. The nitride liner will remain in one-half of the trench. The original portion of the recessed oxide under the nitride liner remains at the bottom of the trench. In a third embodiment of the present invention, the above and other objects are achieved by
第12頁 43 91 8 6 五、發明說明(Ό 用製造無邊際或”無邊框"接觸於基板擴散區的方法而被實 施,其係利用自行對齊並作為鈍化層的氮化物襯墊。使用 氮化物襯墊於部份凹陷的氧化物中,該接觸孔形成與對齊 法具有將被說明的優點。關鍵點係為氮化矽襯墊為自行對 齊,並作為擴散區與淺溝渠隔離邊緣的保護鈍化層。氮化 物襯墊的一主要優點係為其將形成一無邊際接觸,無須降 低多晶矽對多晶矽間距(一主要的設計優點)。此外,該 氮化物襯墊保護接面邊緣附近的淺溝渠隔離邊緣不會造成 接觸孔誤差且不受自行對準矽化物形成製程的影響。該氮 化物襯墊將溝渠隔離邊緣電絕緣,並減少場邊緣漏電流。 如上述,該氮化物襯墊亦保護矽半導體不為先前高密度電 漿製程產生的輻射所損傷。 本發明的另一個目的係為提供一種經改良之溝渠填充 形成法。在上述之複步驟ST I氧化物填充製程中,該部份 凹陷氧化物將協助填充具有高縱橫比的溝渠並協助消除 S Τ I氧化物缝與孔洞。 使用於本發明以製造裝置之傳統加工步驟被說明如下 。在形成鎢接觸或插塞/柱之前,多數個標準製程被進行 (a)多晶矽沈積、摻雜、退火並刻劃,以形成多晶矽閘極 (未表示於圖中),(b )矽化鎢形成製程,(c )未摻雜矽酸 鹽玻璃(USG)形成製程,(d)次大氣壓化學氣相沈積之硼磷 矽酸鹽玻璃形成製程(SACVD BPSG),(e)電漿輔助四乙基 正矽酸鹽氧化物(PE TEOSK未表示於圖中),以使得表面 平坦化。所有提供這些層的該標準製程皆包含形成一中間Page 12 43 91 8 6 V. Description of the invention (Ό It is implemented by the method of making a borderless or "borderless" contact with the substrate diffusion region, which uses a nitride liner that is self-aligned and serves as a passivation layer. Use The nitride liner is in a partially recessed oxide. The contact hole formation and alignment method has the advantages that will be explained. The key point is that the silicon nitride liner is self-aligned and serves as a diffusion region to isolate the edge from the shallow trench. Protects the passivation layer. A major advantage of the nitride liner is that it will form a borderless contact without reducing the polysilicon-to-polysilicon spacing (a major design advantage). In addition, the nitride liner protects the The trench isolation edge does not cause contact hole errors and is not affected by the self-aligned silicide formation process. The nitride liner electrically insulates the trench isolation edge and reduces field edge leakage current. As mentioned above, the nitride liner Protecting the silicon semiconductor from the radiation generated by the previous high-density plasma process. Another object of the present invention is to provide an improved trench filling formation. In the above-mentioned multiple-step ST I oxide filling process, the portion of the recessed oxide will assist in filling trenches with a high aspect ratio and help eliminate S T I oxide seams and holes. Traditionally used in the present invention to manufacture devices The processing steps are described below. Prior to forming tungsten contacts or plugs / pillars, most standard processes are performed (a) polycrystalline silicon deposition, doping, annealing, and scribing to form polycrystalline silicon gates (not shown in the figure), (B) tungsten silicide formation process, (c) undoped silicate glass (USG) formation process, (d) atmospheric pressure chemical vapor deposition of borophosphosilicate glass formation process (SACVD BPSG), (e) Plasma assisted tetraethyl orthosilicate oxide (PE TEOSK is not shown in the figure) to flatten the surface. All the standard processes for providing these layers include forming an intermediate
第13頁 4391 δ6 五、發明說明(8) 絕緣層(ILD)。接觸孔被定義並蝕刻後,接著以CVD鎢沈積 。鎢插塞/柱塞形成,而接觸孔的對齊誤差係為本發明的 氮化物所解決,其係為保護性且鈍化性。 【圖式之簡單說明】 本發明之目的與其他優.點將參考附圖而被說明於較佳 實施例中,其中: 第1圖的橫剖面圖舉例說明具有硬式罩幕、襯墊氧化 物與厚氧化物毯覆式沈積的淺溝渠隔離法。 第2圖的橫剖面圖舉例說明藉表面CMP的平坦化法。 第3圖的横剖面圖舉例說明本發明之一實施例的方 法,藉此部份凹陷的溝渠隔離被形成且一鈍化溝渠襯墊物 被製造。 第4圖的橫剖面圖舉例說明本發明之一實施例的方法 ,藉此一高密度電漿絕緣體被毯覆式沈積,以填充溝渠而 無孔洞與細缝產生。 第5圖的橫剖面圖舉例說明藉終止於硬式罩幕氮化物 觀墊層之表面CMP的平坦化法。 第6圖的橫剖面圖舉例說明溝渠隔離形成法,藉此該 厚的硬式罩幕氮化層被移除。 苐7圖的橫剖面圖舉例說明本發明之一實施例的方法 ,藉此MOSFET裝置的源極/汲極係使用一無邊際或”無邊 框M接觸孔而與鈍化氮化物溝渠襯墊電接觸。 圖號簡單說明 2 基板 4 襯墊氧化層Page 13 4391 δ6 V. Description of the invention (8) Insulation layer (ILD). After the contact holes are defined and etched, they are then deposited by CVD tungsten. The tungsten plug / plunger is formed, and the misalignment of the contact hole is solved by the nitride of the present invention, which is protective and passivation. [Brief description of the drawings] The purpose and other advantages of the present invention will be described in the preferred embodiment with reference to the accompanying drawings, in which: The cross-sectional view of FIG. Shallow trench isolation for thick oxide blanket overlying deposition. The cross-sectional view of FIG. 2 illustrates the planarization method by surface CMP. The cross-sectional view of FIG. 3 illustrates a method according to an embodiment of the present invention, whereby a part of a recessed trench isolation is formed and a passivated trench liner is manufactured. The cross-sectional view of FIG. 4 illustrates a method according to an embodiment of the present invention, whereby a high-density plasma insulator is blanket-deposited to fill trenches without holes and fine slits. The cross-sectional view of FIG. 5 illustrates the planarization method of the surface CMP terminated by the nitride mask layer of the hard mask. The cross-sectional view of FIG. 6 illustrates a trench isolation formation method whereby the thick hard mask nitride layer is removed. Figure 7 is a cross-sectional view illustrating a method according to an embodiment of the present invention, whereby the source / drain of a MOSFET device is electrically contacted with a passivated nitride trench liner using a borderless or "borderless" M contact hole . Brief description of drawing number 2 substrate 4 pad oxide layer
第14頁 4 3 9186 五、發明說明(9) 6 氮 化 矽 硬 式 罩幕層 8 淺 溝 渠 1 0 氧 化 矽 層 1 2 氧 化 層 1 4 虚 線 1 6 氧 化 物 1 8 氮 化 矽 襯 墊 物 1 9 虛 線 2 〇 氧 化 矽 層 2 2 氮 化 物 襯 墊 2 4 S T I 氧 化 物 2 6 氧 化 物 3 0 接 觸 孔 形 成 3 1 接 觸 孔 未 對 齊 3 2 氮 化 矽 襯 墊 3 3 源 極 / 汲 極 區 3 4 矽 化 鎢 3 5 箭 號 3 6 S T I 氧 化 物 3 8 硼 填 矽 酸 鹽 玻 璃 4 0 S T I 氧 化 層 5 0 鶴 插 塞 / 柱 塞 [ 較 佳 實 施 例 之 說 明】 本 發 明 的 主 要 實施例係為在 一 單一 -製 程 中 使 用 部 份 陷 淺 溝 渠 隔 離 ( STI )以製造無邊 際 接觸的 一 薪 新 且 經 改 的 方 法 〇 參 考 第 1圖, — -半導體基板2被 提供, 其 通 常 為 -- 單 © 矽基板。一襯墊氧化層4藉熱成長一個二氧化矽層而被形 成。一個氮化矽硬式罩幕層6被沈積。一淺溝渠8被刻劃, 且硬式罩幕氮化層及襯墊氧化物被刻劃皆使用逆罩幕製程 。一淺溝渠被蚀刻,且一厚的氧化砂層1 0被沈積,其具有 為溝渠填充製程所造成的表面些微傾斜。 第1圖所示之厚的氧化矽層係以CVD法在下列詳細製程 條件下被沈積。目標膜厚為約5000-10000埃。沈積溫度為 約40 0-8 0 0 °C。反應氣體為矽烷、氧氣、臭氧及二氯矽烷Page 14 4 3 9186 V. Description of the invention (9) 6 Silicon nitride hard cover curtain layer 8 Shallow trench 1 0 Silicon oxide layer 1 2 Oxide layer 1 4 Dashed line 1 6 Oxide 1 8 Silicon nitride liner 1 9 dashed line 2 〇 silicon oxide layer 2 2 nitride pad 2 4 STI oxide 2 6 oxide 3 0 contact hole formation 3 1 contact hole misalignment 3 2 silicon nitride pad 3 3 source / drain region 3 4 Tungsten silicide 3 5 Arrow 3 6 STI oxide 3 8 Boron filled silicate glass 4 0 STI oxide layer 5 0 Crane plug / plunger [Description of preferred embodiments] The main embodiment of the present invention is Single-process using partially sunken trench isolation (STI) to create a new and improved method for making no-border contact. Referring to Figure 1, --- semiconductor substrate 2 is provided, which is usually --- single silicon Substrate. A pad oxide layer 4 is formed by growing a silicon dioxide layer by heat. A silicon nitride hard mask layer 6 is deposited. A shallow trench 8 is scribed, and the hard mask nitride layer and the pad oxide are scribed using a reverse mask process. A shallow trench is etched and a thick layer of oxidized sand 10 is deposited, which has a slight tilt on the surface caused by the trench filling process. The thick silicon oxide layer shown in Fig. 1 is deposited by CVD method under the following detailed process conditions. The target film thickness is about 5000-10,000 Angstroms. The deposition temperature is about 40 0-8 0 ° C. Reactive gases are silane, oxygen, ozone and dichlorosilane
第15頁 43 91 8 6 五、發明說明(ίο)Page 15 43 91 8 6 V. Description of the invention (ίο)
參考第2圖,該厚的氧化層1 2係以 2圖所示幾乎與硬式罩幕6氮化層(作為回拋光’且如第 面。此時,部份氧化矽回蝕步驟將使^板光終止層)共平 式蝕刻製程開始進行。部份回蝕步驟的,式触刻製程或濕 渠中的氧化物回蝕至約虚線1 4處,如第攻終結果係為將溝 第2圖所示之形成部份凹陷溝渠的2圖所示。 於下列詳細製程條件下被蝕刻。對於择化物回钱製程係 蝕製程而言,腔室壓力約為5-50 mTQl> t ,功率約為1000-20 0 0瓦。敍刻速率約〇〇_6〇〇〇 分鐘’目標移除量為5 0 0 0- 1 0 0 0 0埃。反應氣體包含:CF4, CHF3,SiF4,,C4, Fs,Ar, 02。對於濕式蝕刻製程而言’稀 電锻蚀刻的乾式回 ’溫度約為80-200Referring to FIG. 2, the thick oxide layer 12 is shown in FIG. 2 and is almost the same as the hard mask 6 nitride layer (as back-polishing) and as shown in the figure. At this time, part of the silicon oxide etch-back step will make ^ Plate light stop layer) co-planar etching process begins. In the part of the etch-back step, the etching process or the oxide in the wet canal is etched back to about 14 lines. As shown. Etched under the following detailed process conditions. In the case of the selective chemical recovery process, the chamber pressure is about 5-50 mTQl> t, and the power is about 1000-20 00 watts. The engraving rate is about 0.00-60000 minutes' and the target removal amount is 5000-1000 Angstroms. The reaction gas contains: CF4, CHF3, SiF4 ,, C4, Fs, Ar, 02. For the wet etch process, the temperature of the ‘lean dry forging for electroless forging’ is about 80-200.
釋的氫氟酸(DHF)被用以移除約2000-4000埃,且殘留於溝 渠中的目標氧化物厚度約為1500-2500埃。 參考第3圖,在部份回蝕後,僅部份ST I用的凹陷氧化 物1 6被留置。在本製程的該階段中,一氮化矽襯墊物1 8被 形成於溝渠中以及硬式罩幕氮化物6上。該氮化物襯墊1 8 可藉使用氨氣與矽烷氣體的低壓化學氣相沈積(LPCVD)(在 約400-800 °C)或藉電漿沈積製程形成。目標膜厚約為500 -1000埃。在氮化物襯墊之前,可使用一氧化氮、氧氣及 氮氣進行緻密化步驟。此外,下列氣體亦可被選用:N2, 〇2,N2〇, N02, NO。 參考第4圖,在形成該氮化物襯墊後,一厚的氧化矽 層2 〇藉高密度電漿(HDP)系統沈積,並以該方式進行而形Released hydrofluoric acid (DHF) is used to remove about 2000-4000 Angstroms, and the target oxide remaining in the trench is about 1500-2500 Angstroms thick. Referring to FIG. 3, after part of the etch-back, only part of the recessed oxide 16 for ST I is left in place. At this stage of the process, a silicon nitride liner 18 is formed in the trench and on the hard mask nitride 6. The nitride liner 18 may be formed by low pressure chemical vapor deposition (LPCVD) using ammonia and silane gas (at about 400-800 ° C) or by plasma deposition process. The target film thickness is approximately 500-1000 Angstroms. Before the nitride liner, a densification step may be performed using nitric oxide, oxygen, and nitrogen. In addition, the following gases can be selected: N2, 〇2, N2〇, N02, NO. Referring to FIG. 4, after forming the nitride liner, a thick silicon oxide layer 20 is deposited by a high-density plasma (HDP) system and is shaped in this manner.
第16頁 43 91 8 6 五、發明說明(π) 成一無縫ST I溝渠填充。本製程的另一個優點在於該氮化 層18將保護矽半導體2不受高密度電漿的輻射損傷。 第4圖中之高密度電漿氧化層的無缝製程條件如下: PECVD反應器,溫度約3 0 0 - 5 5 0 °C,反應氣體為SiH4,Page 16 43 91 8 6 V. Description of the invention (π) Filling into a seamless ST I trench. Another advantage of this process is that the nitride layer 18 will protect the silicon semiconductor 2 from radiation damage from high-density plasma. The seamless process conditions of the high-density plasma oxide layer in Figure 4 are as follows: PECVD reactor, the temperature is about 3 0-5 5 0 ° C, the reaction gas is SiH4,
Si H2C12,02, 〇3,目標膜厚約 1 5 0 0-3 5 00 埃。 參考第5圖,在後HDP氡化物20沈積後’表面藉CMP平 坦化且回拋光終止於氮化物與氧化層中’如虛線1 9所示。 參考第6圖,在表面藉CMP平坦化後,除了殘留於溝渠 中的氮化物襯塾2 2以外,該氮化層係以触刻移除。所殘留 的S T I氧化物2 4係填充溝渠頂端。氮化物襯墊2 2約在溝渠 的中點。第6圖中之該部份凹陷氧化物2 6被繪製於溝渠底 部。經詳細選擇之正好移除上述該氮化層(非氮化物襯墊 2 2 )的最值條件為(a )選擇性的滿式姓刻製程’其係以硫酸 與過氧化氫的水溶液混合物’(b)移除整個氣化物硬式罩 幕,通常移除約1 5 0 0 - 2 0 0 0埃的說化物,(c )移除約1 0 〇 一 300埃的氧化物數量’ U)在溝渠中殘留約2500~5000埃的 氧化物數量。 參考第7圖,接觸孔形成30的多數個優點係為所示。 關鍵點在於該自行對齊鈍化氮化砍襯墊32允許連接至源極 /汲極區3 3的無邊際接觸’且未降低多晶石夕對多晶石夕間距 (未表示於圖中)。應注意地是’該接觸孔未對齊31且隔 離溝渠的邊緣為氮化物襯墊所保護。此外,該氮化物襯墊 32將於自行對齊矽化物製程期間保護場邊緣接面不會有如 箭號3 5所示之金屬矽化物保護的過度成長。為鈍化氮化物Si H2C12, 02, 〇3, the target film thickness is about 15 0-3 500 Angstroms. Referring to FIG. 5, after the deposition of the post HDP halide 20, the surface is flattened by CMP and the back polishing is terminated in the nitride and the oxide layer, as shown by the dotted line 19. Referring to FIG. 6, after the surface is planarized by CMP, the nitrided layer is removed by etching except for the nitride liner 22 remaining in the trench. The residual S T I oxide 2 4 fills the top of the trench. The nitride pad 22 is approximately at the midpoint of the trench. The portion of the recessed oxide 26 in Fig. 6 is drawn at the bottom of the trench. The value of the nitrided layer (non-nitride liner 2 2) was removed in detail to select the maximum value condition: (a) Selective full-type surname engraving process 'It is an aqueous solution mixture of sulfuric acid and hydrogen peroxide' (B) Remove the entire gaseous hard mask, usually remove about 1 500-2 0 0 angstroms, (c) remove about 100-300 angstroms of oxide amount 'U) in The number of oxides remaining in the trench is about 2500 to 5000 Angstroms. Referring to FIG. 7, most advantages of the contact hole formation 30 are shown. The key point is that the self-aligned passivation nitride cutting pad 32 allows for borderless contact to the source / drain regions 33 and does not reduce the polycrystalline silicon to polycrystalline silicon spacing (not shown in the figure). It should be noted that 'the contact hole is misaligned 31 and the edge of the isolation trench is protected by a nitride pad. In addition, the nitride pad 32 will protect the field edge junctions from excessive metal silicide protection as shown by arrow 35 during the self-aligned silicide process. Passivation nitride
第17頁 ^ 43 91 3β 五、發明說明(12) 襯墊所保護之溝渠隔離區3 5亦可避免矽化鈦製程的影響並 降低場邊緣接面漏電流。如上述,該氮化物襯墊亦將避免 矽半導體不為HDP製程的輻射所損傷。 第7圖t的接觸孔形成製程使用特殊的加工條件,以 選擇性地银刻氧化物,且未蚀刻該保護性氮化破層。一電 漿乾式蝕刻製程被用以選擇性地移除氧化物並終止於氮化 物襯墊(3 2 )上。該乾式蝕刻溫度約為8 0 - 2 0 0 °C。 參考第7圖,該部份凹陷ST I氧化物3 6將協助降低ST I 氧化物填充的縱橫比,並協助消除ST I氧化物縫隙及孔洞 。氮化物襯墊頂端為ST I氧化層40。 再次參考第7圖,在鑛接觸或插塞/柱塞形成3 0之前 ,多數個標準製程將被進行,如下列製程步驟:(a)薄閘 極氧化物形成(未表示於圖中),(b)多晶矽沈積、摻雜、 退火並刻劃,以形成多晶矽閘極(未表示於圖中),(c)多 晶矽閘極間隙壁製程,(d)進行離子植入與擴散製程以形 成源極/汲極3 3,( e )矽化鎢3 4形成製程,(f )未摻雜矽酸 鹽玻璃3 6形成製程,沈積該膜至約1 0 0 〇埃的厚度(g )次大 氣壓化學氣相沈積之硼磷矽酸鹽玻璃3 8形成製程,沈積該 膜至約4000埃的厚度(h)電漿輔助四乙基正矽酸鹽氧化物 (未表示於圖中),以使得表面平坦化。所有提供這些層 的該標準製程皆包含形成一中間絕緣層(I LD )。接觸孔被 定義並蝕刻後,接著以CVD鎢沈積。鎢插塞/柱塞5 0在接 觸孔3 0中形成,如第7圖所示。 雖然本發明已參考其較佳實施例而被特別地揭示並說Page 17 ^ 43 91 3β V. Description of the invention (12) The trench isolation area protected by the pad 35 can also avoid the influence of the titanium silicide process and reduce the leakage current at the field edge junction. As mentioned above, the nitride pad will also prevent the silicon semiconductor from being damaged by the radiation of the HDP process. The contact hole formation process of FIG. 7t uses special processing conditions to selectively etch oxides without etching the protective nitrided layer. A plasma dry etching process is used to selectively remove the oxide and terminate on the nitride liner (32). The dry-etching temperature is about 80 ° -200 ° C. Referring to FIG. 7, the partially recessed ST I oxide 36 will help reduce the aspect ratio of ST I oxide filling and help eliminate ST I oxide gaps and holes. The top of the nitride pad is an ST I oxide layer 40. Referring again to Figure 7, before the mine contact or plug / plunger formation 30, most standard processes will be performed, such as the following process steps: (a) thin gate oxide formation (not shown in the figure), (B) polycrystalline silicon deposition, doping, annealing and scoring to form a polycrystalline silicon gate (not shown in the figure), (c) a polycrystalline silicon gate spacer process, and (d) an ion implantation and diffusion process to form a source Electrode / drain electrode 3 3, (e) tungsten silicide 3 4 formation process, (f) undoped silicate glass 3 6 formation process, deposit the film to a thickness of about 100 angstroms (g) subatmospheric pressure chemistry Vapor-deposited borophosphosilicate glass 3 8 formation process, the film is deposited to a thickness of about 4000 angstroms (h) plasma-assisted tetraethyl orthosilicate oxide (not shown in the figure) to make the surface flattened. All the standard processes for providing these layers include forming an intermediate insulating layer (I LD). After the contact holes are defined and etched, they are then deposited by CVD tungsten. A tungsten plug / plunger 50 is formed in the contact hole 30, as shown in FIG. Although the invention has been particularly disclosed and described with reference to its preferred embodiments,
第18頁 43 91 8 6Page 18 43 91 8 6
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