TW432596B - A silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts - Google Patents

Abstract

An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or ""unframed"" electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.

Description

32 5 9 6 五、發明說明（1) 【發明之背景】 (1)發明之背景 本發明的一般性目的係為提供一種形成積體電路的嶄 新且經改良的方法，其係使用與鈍化性氮化物溝渠襯墊相 關之部份凹陷淺溝渠隔離（S T I )法以製造無邊際接觸。 在次微米技術中，淺溝渠隔離（ST I )已變成半導體裝 置隔離的標準方法並取代其他隔離法，亦即需要較多面積 的局部矽氧化法（LOCOS)。在傳統的淺溝渠隔離製程中， 溝渠被形成於電主動區（亦即M0SFET閘極與源極/汲極）之 間的半導體基板中，並將M0SFET彼此電隔離。該溝渠係以 諸如氡化矽等絕緣材料填充，以提供電隔離。包含M0SFET 之電晶體的主動裝置與電阻器被製造於具有淺溝渠隔離（ ST I )的"主動”區的半導體基板中，以將主動裝置之間的區 開 造 構 觸 接 統 傳 的 用 使 所 米 微 次 為 寸 尺 體 晶 ^¾ ^w, 。於 離由 隔 域 寸接 此低 小降 最以 為難 亦係 孔其 觸員 接， 若及 ’顧 先所 首為 〇 係 能題 性間 置的 裝孔 制觸 限接 面小 方微 多洗 在清 始且 區對 極驟 汲步 \幕 極罩 源的 該離 ’分 觸以 接係 統孔 傳觸 的接 成該 形為 所因 藉’ ’ 低 外降 此被 。法 率無 阻積 電面 觸的 。板 差 I 誤極 於汲 用\ 被極 須源 必的 積加 面增 1成 夕造 Μ 亦 的積 大面極一 \夕 L額 且" ’的 域大 區較 些該 這’ 於外 齊此 響采 影微 面次 負與 有米 率微 速多 置許 裝決 於解 對將基 其觸置 ，接裝 容”寬 電框放 面邊而 接無， 統 傳 及 計 設 準 本 框 邊 ” 題題 或問問 觸的工 接觸加 際接的 邊ΕΤ觸 無SF接32 5 9 6 V. Description of the invention (1) [Background of the invention] (1) Background of the invention The general purpose of the present invention is to provide a new and improved method for forming integrated circuits, which is used and passivated. A part of a recessed shallow trench isolation (STI) method associated with a nitride trench liner is used to make a borderless contact. In sub-micron technology, shallow trench isolation (ST I) has become the standard method for semiconductor device isolation and replaces other isolation methods, that is, the local silicon oxidation (LOCOS) method that requires a larger area. In the traditional shallow trench isolation process, trenches are formed in a semiconductor substrate between electrically active regions (ie, MOSFET gate and source / drain), and MOSFETs are electrically isolated from each other. The trench is filled with an insulating material such as silicon oxide to provide electrical isolation. The active device and the resistor including the transistor of the MOSFET are manufactured in a semiconductor substrate having a shallow active trench (ST I) " active " Make the so-called micrometers inch-inch body crystal ^ ¾ ^ w,. It is the most difficult to connect this low and small drop from the distance from the screen, and it is also related to the contact of the hole. The interpositional hole-making contact limit contact surface is small and slightly washed in the beginning of the Qing Dynasty and the area is polarized. The separation of the screen electrode source is connected to the system hole to make contact. This is because of the low external voltage. The method has no resistance to accumulate electricity. The board difference I is too bad to be used. \ The product must be increased by 10%, and the accumulated area is also extremely high. \ Xi L amount and " 'The domain of the region is more than it should be' To the outside world, this is the case, the negative surface is negative, and the meter has a slight speed, and the speed is more than determined. The solution depends on the solution and touch the device. ” The wide electric frame is placed on the side and not connected, and the traditional transmission and design of the frame is required. Inter working engagement and contact-free contact edge ΕΤ contact SF

^43259 6 五、發明說明（2) 。該無邊際接觸利用源極/汲極區上的空間與面積’其將 被更詳細地說明。無邊際接觸為先進設計且有關淺溝渠隔 離（S T I )加工的一部份。 (2 )習知技藝之說明 藉傳統淺溝渠隔離（ST I )加工，形成一無邊際接觸於 溝渠區域上係為一難題。該無邊際接觸或"無邊框π接觸係 為位在半導體裝置的主動與隔離區上並將其曝露出的接觸 ，其通常用於與形成在基板中的擴散區接觸。形成與傳統 淺溝渠隔離結合之無邊際接觸的問題包含穿經中間介電層 將接觸孔開口蝕刻，並同時避免將溝渠中的介電材料蝕刻 。通常，中間層與溝渠填充材料為氧化矽的形式。因此， 該溝渠填充氧化物可因接觸孔的蝕刻而被蝕刻並損傷。若 該溝渠隔離材料沿著溝渠壁被回蝕，則損傷效應將發生， 亦即在P / Ν接面邊緣的漏電及短路，特別是當該區域為導 電材料所填充時。 1998年9月15日核准之標題為11 Device Isolator! Methods for a semiconductor Device"的美國專利第 5，8 07, 784號（Kim等人）說明一種形成一裝置隔離層於半導體 裝置的方法，其包含形成場氧化物於淺溝渠隔離（ST I )中 的二步驟方法。第一個步驟包含將氧離子植入半導體基扳 之場區域中的溝渠底部，並將該植入氧的區域氧化以形成 一場氧化層。第二個步驟包含沈積絕緣材料，以進一步填 充溝渠。^ 43259 6 V. Description of Invention (2). This borderless contact makes use of the space and area on the source / drain regions' which will be explained in more detail. Borderless contact is part of advanced design and related to shallow trench isolation (S T I) processing. (2) Explanation of the know-how. Forming a borderless contact with the trench area through traditional shallow trench isolation (ST I) processing is a difficult problem. The borderless contact or " borderless π contact is a contact which is located on the active and isolation region of a semiconductor device and is exposed, which is generally used for contacting a diffusion region formed in a substrate. The problem of forming borderless contact combined with traditional shallow trench isolation involves etching the openings of the contact holes through the intermediate dielectric layer while avoiding etching of the dielectric material in the trench. Usually, the intermediate layer and trench filling material are in the form of silicon oxide. Therefore, the trench filling oxide may be etched and damaged due to the etching of the contact hole. If the trench isolation material is etched back along the trench wall, damage effects will occur, that is, leakage and short circuit at the edge of the P / N junction, especially when the area is filled with conductive material. U.S. Patent No. 5,8,07,784 (Kim et al.) Entitled 11 Device Isolator! Methods for a Semiconductor Device approved on September 15, 1998 (Kim et al.) Describes a method for forming a device isolation layer in a semiconductor device, which Includes a two-step method of forming field oxides in shallow trench isolation (ST I). The first step involves implanting oxygen ions into the bottom of the trench in the semiconductor substrate field region and oxidizing the oxygen implanted region to form a field oxide layer. The second step involves depositing insulating material to further fill the trench.

1998年9月8日核准之標題為” METHOD OF FILLINGApproved September 8, 1998 under the heading "Method of Filling"

驊43259 6 五、發明說明（3) SHALLOW TRENCHES” 的美國專利第 5, 8 0 7, 49 0 號（Fiegl 等 人）說明一種在矽積體電路加工中的隔離法，其將溝渠以 填充邊際過度填充並沈積厚度小於溝渠深度的一暫置多晶 矽層。一個氡化層被使用為拋光阻絕物。溝渠外的暫置層 被拋光，其係使用一填充層與拋光阻絕層作為化學機械拋 光（CMP)的拋光阻絕物。該拋光阻絕層與相同厚度的填充 層及暫置多晶矽層為CMP所移除，而產生表面平坦化。殘 留的暫置層被撥除，且最終的填充層拋光終止於襯墊I化 物上。 1 9 9 8年1 0月6日椋准之標題為” Method of Forming a Trench Isolation Region” 的美國專利第 5,817,568號（ Chao等人）說明一種使用複溝渠形成技術以形成具有不同 寬度之個別溝渠深度的方法。該方法包含依序形成一緩衝 氧化層及拋光阻絕層於一半導體基板上。其次，該緩衝氧 化層、拋光阻絕層與半導體基板被定義以形成至少一個窄 溝渠。其次，該緩衝氧化層、拋光阻絕層與半導體基板再 次被定義以形成至少一個寬溝渠。其次，一部份的氧化層 與一部份的拋光阻絕層被移除以形成一平坦表面。最後， 該拋光阻絕層與緩衝氧化層被移除。 1997年7月29日核准之標題為"Method for Providing Trench Isolation and Borderless Contact"的美國專利 第5,652, 176號（Maniar等人）說明一種溝渠隔離法，其係 使用由氮化I呂所組成的溝渠襯塾物。另一個相似的專利係 為1997年10月14日核准之標題為"Method for Providing r 32 5 9 6 五、發明說明（4)骅 43259 6 V. Description of the invention (3) SHALLOW TRENCHES "US Patent No. 5, 8 0 7, 49 0 (Fiegl et al.) Describes an isolation method in silicon integrated circuit processing, which fills the trenches with margins Overfill and deposit a temporary polycrystalline silicon layer with a thickness less than the depth of the trench. A hafnium layer is used as a polishing barrier. The temporary layer outside the trench is polished, which uses a filling layer and a polishing barrier as chemical mechanical polishing ( CMP) polishing stopper. The polishing stopper layer and the same thickness of the filling layer and the temporary polycrystalline silicon layer are removed by the CMP, resulting in surface flattening. The remaining temporary layer is removed and the polishing of the final filling layer is terminated U.S. Patent No. 5,817,568 (Chao et al.), Entitled "Method of Forming a Trench Isolation Region", issued on October 6, 1989, describes a method for using complex trench formation technology to A method for forming individual trench depths with different widths. The method includes sequentially forming a buffer oxide layer and a polishing resist layer on a semiconductor substrate. Second, the buffer oxide layer, The photoresist layer and the semiconductor substrate are defined to form at least one narrow trench. Second, the buffer oxide layer, the polishing resist layer and the semiconductor substrate are again defined to form at least one wide trench. Second, a part of the oxide layer and a part The polishing barrier layer was removed to form a flat surface. Finally, the polishing barrier layer and the buffer oxide layer were removed. Approved on July 29, 1997 with the title "Method for Providing Trench Isolation and Borderless Contact" in the United States Patent No. 5,652, 176 (Maniar et al.) Describes a trench isolation method using a trench lining made of nitride I. Another similar patent was approved on October 14, 1997 and is entitled " Method for Providing r 32 5 9 6 V. Description of Invention (4)

Trench Isolation11 的美國專利第 5, 677，231 號（Maniar 等 人）亦說明淺溝渠隔離（STI)與一無邊際接觸製程，其在 ST I氧化矽下方具有氮化鋁襯墊物。在形成接觸窗期間’ 使用對於氮化鋁有選擇性的蝕刻化學物質，該溝渠襯墊物 將保護位於溝渠角落的P-N接面。藉由保護該接面，後續 導電插塞的形成將不會造成接面電短路並維持低二極體漏 電流。 1993年12月7日核准之標題為1'Process for Improving Sheet Resistance of a Integrated Circuit Device Gate"的美國專利第5,2 68,3 3 0號（Givens等人）說 明一種包含淺溝渠隔離（ST I )的製程，以及可作為無邊際 接觸之位於P-N接面上的接觸。一鈍化層被沈積於一積體 電路裝置上，其係使用金屬矽化物法製造。一絕緣層被沈 積。該絕緣層被平坦化且進一步拋光，以曝露出位於閘極 上的鈍化層。位於閘極上的鈍化層部份被移除。位於接面 上的一溝渠藉移除絕緣層並使用該鈍化層作為蝕刻阻絕物 而被形成。其次，位於接面上的一部份鈍化層被移除。該 閛極可被進一步金屬矽化物化，且位於閘極上的窗口及溝 渠可被填充。位於接面上的接觸為無邊際接觸。 【發明之概要】 本發明的一般性目的係為提供一種形成積體電路的嶄 新且經改良的方法，其係使用與保護性氮化物溝渠襯墊相 關之部份凹陷淺溝渠隔離（ST I )法以製造無邊際接觸。 本發明之一更特別的目的係為提供一種在積體電路製US Patent No. 5,677,231 to Trench Isolation11 (Maniar et al.) Also describes a shallow trench isolation (STI) and a borderless contact process with an aluminum nitride liner under ST I silicon oxide. During the formation of the contact window ', using a etch chemistry that is selective to aluminum nitride, the trench liner will protect the P-N junction at the corner of the trench. By protecting the junction, subsequent formation of conductive plugs will not cause the junction to be electrically shorted and maintain a low diode leakage current. U.S. Patent No. 5,2 68,3 3 0 (Givens et al.), Entitled 1'Process for Improving Sheet Resistance of a Integrated Circuit Device Gate ", approved on December 7, 1993 (Givens et al.) Describes a method that includes shallow trench isolation (ST I) and the contact on the PN junction which can be used as a borderless contact. A passivation layer is deposited on an integrated circuit device, which is fabricated using a metal silicide method. An insulating layer is deposited. The insulating layer is planarized and further polished to expose the passivation layer on the gate. The portion of the passivation layer on the gate is removed. A trench on the interface is formed by removing the insulating layer and using the passivation layer as an etch stop. Secondly, a part of the passivation layer on the interface is removed. The gate can be further silicided, and windows and trenches on the gate can be filled. The contact on the interface is a borderless contact. [Summary of the Invention] The general purpose of the present invention is to provide a new and improved method for forming integrated circuits, which uses a partially recessed shallow trench isolation (ST I) associated with a protective nitride trench liner Law to create borderless contact. A more specific object of the present invention is to provide an integrated circuit

第10頁 ? 4 32 59 6 五、發明說明（5) 造於半導體基板上期間之經改良的無邊際接觸形成法，該 基板通常為單晶矽。最初的製程包含一襯墊氧化物’其係 藉熱成長一個二氧化矽層而被形成。其次，一 硬式罩幕" 氮化矽層被沈積。使用一逆罩幕製程，一用於淺溝渠隔離 (ST I )的淺溝渠、硬式罩幕氮化物層及襯墊氧化物被刻劃 '一淺溝渠被蝕刻，並接著沈積一厚的氧化矽層。該厚的 氧化石夕層因溝渠填充製程而在溝渠上的表面中造成些微傾 斜。該表面被平坦化，藉化學機械拋光（CMP)並使用硬式 罩幕氮化層將該厚氧化層拋光成平坦。該硬式罩幕氮化層 作為一抛光阻絕物。 在本發明的第一個實施例甲，上述及其他目的係藉使 用製造部份凹陷淺溝渠隔離（s T I)構造的方法而被實施， 如藉下列方法所說明。在上述的溝渠平坦化之後，藉一乾 式蝕刻製程或一濕式蝕刻製程而進行部份氧化矽的回蝕。 該部份回蝕步驟的最終結果係為將溝渠中的氧化物回蝕至 溝渠中的1 / 2 - 3 / 4。本發明之部份回蝕的更多細節可被發 現於"DESCRIPTION OF THE PREFERRED EMBODIMENTS"中。 在本發明的第二個實施例中，上述及其他目的係藉使 用製造無邊際接觸的方法而被實施，其包含位於部份凹陷 溝渠氧化物上的氮化矽覆蓋保護層。該鈍化氮化物覆蓋藉 下列方法而於本發明被完成。在上述之溝渠氧化物的部份 回蝕後，僅部份被凹陷的氧化物殘留於淺溝渠中。在本製 程的該步驟，本發明中的一關鍵性製程係為形成一個氮化 矽覆蓋層於溝渠中。因此，在該部份ST I氧化物回蝕及硬Page 10? 4 32 59 6 V. Description of the invention (5) An improved method for forming a borderless contact during the fabrication on a semiconductor substrate, which is usually monocrystalline silicon. The initial process included a pad oxide 'which was formed by growing a silicon dioxide layer by heat. Second, a hard mask " silicon nitride layer is deposited. Using a reverse mask process, a shallow trench for shallow trench isolation (ST I), a hard mask nitride layer, and a pad oxide are scribed. A shallow trench is etched, and then a thick silicon oxide is deposited. Floor. The thick oxidized stone layer caused a slight tilt in the surface on the trench due to the trench filling process. The surface is flattened, and the thick oxide layer is polished flat by chemical mechanical polishing (CMP) and using a hard mask nitride layer. The hard mask nitride layer acts as a polishing stop. In the first embodiment of the present invention, the above and other objects are implemented by a method of manufacturing a partially recessed shallow trench isolation (s T I) structure, as explained by the following method. After the trench is planarized, a part of the silicon oxide is etched back by a dry etching process or a wet etching process. The end result of this part of the etch-back step is to etch back the oxide in the trench to 1/2/3-4 of the trench. Further details of part of the etchback of the present invention can be found in " DESCRIPTION OF THE PREFERRED ". In a second embodiment of the present invention, the above and other objects are implemented by using a method of manufacturing a non-border contact, which includes a silicon nitride coating on a portion of a recessed trench oxide. The passivation nitride coating is completed in the present invention by the following method. After a part of the trench oxide is etched back, only a part of the recessed oxide remains in the shallow trench. At this step of the process, a key process in the present invention is to form a silicon nitride coating in the trench. Therefore, the ST I oxide is etched back and hardened in this part.

32 5 9 8 五、發明說明（6) 式罩幕移除後，一個厚的氮化矽層係藉低壓化學氣相沈積 (LPCVD)系統或高密度電漿（HDP)系統沈積，並以該方法進 行而形成一無縫STI氮化物溝渠填充。在該LPCVD或HDP氮 化物覆蓋沈積後，該表面係藉化學機械拋光（CMP)平坦化 ，且該回拋光製程終止於溝渠窗口平面上以及襯墊氧化層 上，而終止於氮化物覆蓋層中。該襯墊氧化層仍留置於適 當位置。其次，藉回蝕以部份地移除該氮化層至襯墊氧化 物正下方，而將氮化物覆蓋成形並形成。回蝕氮化層的製 程將氮化矽覆蓋以最終的形式放置於該部份凹陷ST I氧化 物上，以作為保護性鈍化層° 在本發明的第三個實施例中，上述及其他目的係藉使 用製造無邊際或M無邊框"接觸於基板擴散區的方法而被實 施，其係利用自行對齊並作為鈍化層的氮化物覆蓋。使用 氮化物覆蓋於部份凹陷的氧化物中，該接觸孔形成與對齊 法具有將被說明的優點。關鍵點係為氮化矽覆蓋為自行對 齊，並作為擴散區與淺溝渠隔離邊緣的保護鈍化層。氮化 物覆蓋的一主要優點係為其將形成一無邊際接觸，無須降 低多晶矽對多晶矽間距（一主要的設計優點）。此外，該 氮化物覆蓋保護接面邊緣附近的淺溝渠隔離邊緣不會造成 接觸孔誤差且不受自行對準矽化物形成製程的影響。該氮 化物覆蓋將溝渠隔離邊緣電絕緣，並減少場邊緣漏電流。 本發明的另一個目的係為提供一種經改良之溝渠填充 形成法。在上述之二階段ST I填充製程中（先氧化物而後氮 化物），該部份凹陷氧化物將協助填充具有高縱橫比的溝32 5 9 8 V. Description of the invention (6) After the type mask is removed, a thick silicon nitride layer is deposited by a low-pressure chemical vapor deposition (LPCVD) system or a high-density plasma (HDP) system. The method proceeds to form a seamless STI nitride trench fill. After the LPCVD or HDP nitride overlay deposition, the surface is planarized by chemical mechanical polishing (CMP), and the back polishing process ends on the trench window plane and the pad oxide layer, and ends in the nitride overlay layer. . The pad oxide remains in place. Secondly, the nitride layer is partially removed under the pad oxide by etch back, and the nitride is formed and formed. The process of etching back the nitrided layer places the silicon nitride cover in the final form on the partially recessed ST I oxide as a protective passivation layer. In the third embodiment of the present invention, the above and other purposes It is implemented by using a method of manufacturing a borderless or M borderless " contacting the substrate diffusion region, which is covered with a nitride which is self-aligned and serves as a passivation layer. The use of nitride to cover a portion of the recessed oxide has the advantage that the contact hole formation and alignment method will be described. The key point is that the silicon nitride is self-aligned and serves as a protective passivation layer for the diffusion zone and the edge of the shallow trench isolation. A major advantage of nitride coverage is that it will form a borderless contact without reducing the polysilicon-to-polysilicon spacing (a major design advantage). In addition, the nitride covering protects the shallow trench isolation edge near the edge of the junction without causing contact hole errors and is not affected by the self-aligned silicide formation process. This nitride cover electrically insulates the trench isolation edges and reduces field edge leakage currents. Another object of the present invention is to provide an improved trench filling formation method. During the two-stage ST I filling process (first oxide and then nitride), this part of the recessed oxide will help fill the trench with high aspect ratio

第12頁 Γ Β43259 6 五、發明說明（7) 渠並協助消除ST I氧化物缝與孔洞。 使用於本發明以製造裝置之傳統加工步驟被說明如下 。在形成鎢接觸或插塞/柱之前，多數個標準製程被進行 (a)多晶矽沈積、摻雜、退火並刻劃’以形成多晶矽閘極 (未表示於圖中），（b )矽化鎢形成製程，（c )未摻雜矽酸 鹽玻璃（USG )形成製程，（d)次大氣壓化學氣相沈積之硼磷 矽酸鹽玻璃形成製程（SACVD BPSG )，（ e )電漿辅助四乙基 正矽酸鹽氧化物（PE TEOS)(未表示於圖中），以使得表面 平坦化。所有提供這些層的該標準製程皆包含形成一中間 絕緣層（I LD )。接觸孔被定義並蝕刻後，接著以C VD鎢沈積 。鎢插塞/柱塞形成，而接觸孔的對齊誤差係為本發明的 氮化物所解決，其係為保護性且鈍化性。 【圖式簡單說明】 本發明之目的與其他優點將參考附圖而被說明於較佳 實施例中，其中： 第1圖的橫剖面圖舉例說明具有硬式罩幕、襯墊氧化 物與厚氧化物毯覆式沈積的淺溝渠隔離法。 苐2圖的橫剖面圖舉例說明藉表面CMP的平坦化法。 第3圖的橫剖面圖舉例說明本發明之一實施例的方法 ，藉此部份凹陷的溝渠隔離被形成且該厚硬式罩幕層被移 除（虚線），而留下氧化物襯墊於適當位置。 第4圖的橫剖面圖舉例說明本發明之一實施例的方法 ，藉此一厚的氮化層被沈積，表面以CMP平坦化至虛線處 。該氮化層在後續的製程步驟被形成無邊際或”無邊框"接Page 12 Γ Β43259 6 V. Description of the invention (7) Canals and assist in eliminating ST I oxide cracks and holes. The conventional processing steps used in the present invention to manufacture a device are explained below. Prior to forming tungsten contacts or plugs / pillars, most standard processes are performed (a) polycrystalline silicon deposition, doping, annealing, and scoring to form polycrystalline silicon gates (not shown in the figure), and (b) tungsten silicide formation Process, (c) Undoped silicate glass (USG) formation process, (d) Atmospheric pressure chemical vapor deposition of borophosphosilicate glass formation process (SACVD BPSG), (e) Plasma-assisted tetraethyl Orthosilicate oxide (PE TEOS) (not shown) to flatten the surface. All of the standard processes for providing these layers include forming an intermediate insulating layer (I LD). After the contact holes are defined and etched, they are then deposited with C VD tungsten. The tungsten plug / plunger is formed, and the misalignment of the contact hole is solved by the nitride of the present invention, which is protective and passivation. [Brief Description of the Drawings] The purpose and other advantages of the present invention will be described in the preferred embodiment with reference to the accompanying drawings, in which: The cross-sectional view of FIG. 1 illustrates a hard mask, a pad oxide, and a thick oxide. Shallow trench isolation method for blanket blanket deposition. The cross-sectional view of Fig. 2 illustrates the planarization method by surface CMP. The cross-sectional view of FIG. 3 illustrates a method of an embodiment of the present invention, whereby a partially recessed trench isolation is formed and the thick hard mask layer is removed (dashed line), leaving an oxide liner. In place. The cross-sectional view of FIG. 4 illustrates the method of one embodiment of the present invention, whereby a thick nitrided layer is deposited, and the surface is planarized to the dotted line by CMP. The nitrided layer is formed into a borderless or "borderless" interface in subsequent process steps.

第13頁 ，4 3259 6 五、發明說明（8) 觸孔用的純化溝渠覆蓋。 第5圖的橫剖面圖舉例說明本發明之一實施例的方法 ，藉此該毯覆式氮化物被回蝕以形成一用於無邊際接觸的 純化ST I覆蓋。 第6圖的橫剖面圖舉例說明本發明之一實施例的方法 ，藉此MOSFET裝置的源極/汲極係使用一無邊際或"無邊 框”接觸孔而與鈍化氮化物溝渠襯墊電接觸。 【圖號簡單說明】 2 半 導 體 基 板 4 襯 墊 氧 化 層 6 氮 化 矽 硬 式 罩 幕 層 8 Μ 溝 渠 1 0 氧 化 矽 層 1 2 氧 化 層 1 4 虚 線 1 6 凹 陷 氧 化 物 2 0 氮 化 物 2 1 箭 號 2 2 氮 化 物 覆 蓋 3 0 接 觸 孔 3 1 隔 離 溝 渠 3 2 多 晶 矽 閘 極 3 4 邊 際 接 觸 至 以 矽4匕物 3 6 矽 酸 鹽 玻 璃 3 8 硼 填 矽 酸 鹽 玻 璃 4 0 四 乙 基 正 砂酸鹽氧化物 5 1 鎢 插 塞 / 柱 塞 5 2 矽 化 物 【較佳實施例之說明】 本發明的主要實施例係為在一單一製程中使用氮化矽 覆蓋淺溝渠隔離（ST I )以製造無邊際接觸的一嶄新且經改 良的方法。 參考第1圖，一半導體基板2被提供，其通常為一單晶 石夕基板。一概塾氧化層4藉熱成長一個二氧化石夕磨而被形Page 13, 4, 3259 6 5. Description of the invention (8) Covered with purified trenches for contact holes. Figure 5 is a cross-sectional view illustrating the method of one embodiment of the present invention whereby the blanket nitride is etched back to form a purified ST I overlay for borderless contact. The cross-sectional view of FIG. 6 illustrates a method according to an embodiment of the present invention, whereby the source / drain of a MOSFET device is electrically connected to a passivated nitride trench liner using a borderless or " borderless " contact hole. [Simplified description of drawing number] 2 Semiconductor substrate 4 Pad oxide layer 6 Silicon nitride hard cover curtain layer 8 M trench 1 0 Silicon oxide layer 1 2 Oxide layer 1 4 Dashed line 1 6 Sink oxide 2 0 Nitride 2 1 Arrow 2 2 Nitride cover 3 0 Contact hole 3 1 Isolation trench 3 2 Polycrystalline silicon gate 3 4 Marginal contact with silicon 4 Dagger 3 6 Silicate glass 3 8 Boron filled silicate glass 4 0 Tetraethyl Ortho-salt oxide 5 1 Tungsten plug / Plunger 5 2 Silicide [Description of the preferred embodiment] The main embodiment of the present invention is to cover shallow trench isolation with silicon nitride in a single process (ST I ) To make a new and improved method for making borderless contact. Referring to Fig. 1, a semiconductor substrate 2 is provided, which is usually a single crystal Plate. Yigai 4 by a thermally grown oxide layer Sook dioxide Xi grinding stone is shaped

第14頁 Γ4 3 2 5 9 6 五 '發明說明¢9) 成。一個氮化矽硬式罩幕層6被沈積。一淺溝渠8被刻劃， 且硬式罩幕氮化層及襯墊氣化物被刻劃皆使用逆罩幕製程 。一淺溝渠被蝕刻’且一厚的氧化矽層1 〇被沈積，其具有 為溝渠填充製程所造成的表面些微傾斜。 第1圖所示之厚的氧化石夕層係以C V D法在下列詳細製程 條件下被沈積。目標膜厚為約5 0 0 0 - 1 0 0 0 0埃。沈積溫度為 約400-800C。反應氣體為砂烧、氧氣 '臭氧及二氯石夕烧 〇 參考第2圖’該厚的氧化層1 2係以CMP回拋光，且如第 2圖所示幾乎與硬式罩幕6氮化層（作為拋光終止層）共平 面。此時，部份氧化矽回蝕步驟將使用乾式蝕刻製程或濕 式蝕刻製程開始進行。部份回蝕步驟的最終結果係為將溝 渠中的氧化物回蝕至約虛線14處，如第2圖所示。 第2圖所示之形成部份凹陷溝渠的氧化物回蝕製程係 於下列詳細製程條件下被蝕刻。對於藉電漿蝕刻的乾式回 蝕製程而言’腔室壓力約為5 5〇 mTorr，溫度約為80-200 °C ，功率約為1000-2000瓦。蝕刻速率約為3000-6000埃/ 分鐘’目標移除量為5000-10000埃。反應氣體包含：CF4, CHF3， SiF4,，C4, F8，Ar，02。對於濕式蝕刻製程而言，稀 釋的氫氟酸（DHF)被用以移除約2000-4000埃，且殘留於溝 渠t的目標氧化物厚度約為1500-2500埃。 參考第3圖，在部份回蝕後，僅部份ST I用的凹陷氧化 物1 6被留置。除了隔離氧化物的部份移除以外，氮化矽硬 式罩幕層6 (以虛線表示）係藉選擇性蝕刻移除。該硬式罩Page 14 Γ4 3 2 5 9 6 5 'Explanation of invention ¢ 9). A silicon nitride hard mask layer 6 is deposited. A shallow trench 8 is scored, and the hard mask nitride layer and the pad gas are scored using the reverse mask process. A shallow trench is etched 'and a thick silicon oxide layer 10 is deposited, which has a slight tilt on the surface caused by the trench filling process. The thick oxide layer shown in Fig. 1 was deposited by the C V D method under the following detailed process conditions. The target film thickness is about 5 0 0-1 0 0 0 0 Angstroms. The deposition temperature is about 400-800C. The reaction gases are sand burning, oxygen 'ozone and dichlorite burning. Refer to Figure 2'. The thick oxide layer 12 is polished by CMP, and as shown in Figure 2, it is almost the same as the hard mask 6 nitride layer. (As polishing stop) coplanar. At this time, a part of the silicon oxide etch-back step will be performed using a dry etching process or a wet etching process. The end result of the partial etch-back step is to etch back the oxide in the trench to about the dotted line 14 as shown in FIG. 2. The oxide etch-back process for forming a partially recessed trench shown in FIG. 2 is etched under the following detailed process conditions. For the dry etch-back process by plasma etching, the chamber pressure is about 550 mTorr, the temperature is about 80-200 ° C, and the power is about 1000-2000 watts. The etching rate is about 3000-6000 angstroms / minute 'and the target removal amount is 5000-10000 angstroms. The reaction gas contains: CF4, CHF3, SiF4 ,, C4, F8, Ar, 02. For the wet etching process, dilute hydrofluoric acid (DHF) is used to remove about 2000-4000 angstroms, and the target oxide thickness remaining in the trench t is about 1500-2500 angstroms. Referring to FIG. 3, after part of the etch-back, only part of the recessed oxide 16 for ST I is left in place. Except for the partial removal of the isolation oxide, the silicon nitride hard mask layer 6 (indicated by a dashed line) is removed by selective etching. The hard cover

第15頁 4 3 2 5 9 6 五、發明說明（10) 暮係使用琉酸與過氧化氮溶液的水溶液混合物蝕刻。應注 意地是，該淺溝渠隔離（STI )將進行縱橫比的縮減。襯墊 氧化層4留置於適當位置，如第3圖所示。 參考第4圖’在部份STI回敍後’ „厚的氧化碎層2〇 高密度電衆（HDP)系統或藉低壓化學氣相沈積（LpcvD)沈積 ，並以該方式進行而形f -無縫STI溝渠填充。該作為溝 渠覆盖層之厚的IL化石夕層可被形成於直立爐體（Lpcv HDP CVD中。反應氣體為石夕.度、氨氣、—氧化氮及二氣:夕 烷。目標膜厚約1000-5000埃。 再次參考第4圖’在後的氣化物2〇被沈積後，表面藉 CMP平坦化且該回蚀製程係終止於虛線範圍中，並位於氣 化層2 0中。該襯墊氧化層4仍位於適當位置。 參考第5圖’在表面藉CMP平坦化後，該氮化層2〇係以 回姓部份移除至概塾氧化物4正下方。應注意地是，第5圖 中的虛線表示原始的氮化物平面20 ’而箭號21表示回蝕程 度。部份回触該氣化物的製程將一氮化物覆蓋22於琴sti 氧化物1 6上。該氮化物的選擇性較佳回蝕條件為：可被乾 式或濕式触刻’所殘留的氮化物覆蓋層厚度約為5〇〇_3〇〇〇 埃。 參考第6圖’接觸孔形成30的多數個優點係為所示。 應注意地是，該接觸孔3 0未對齊且隔離溝渠3丨的邊緣為鈍 化氮化物覆蓋2 2所保護。然而，在鎢接觸或插塞/柱塞形 成3 0前，多數個標準製程被進行：（a)薄閘極氧化物形成 (未表示於圖中），（b)多晶矽沈積、摻雜、退火並刻劃， F4 32 5 9 6 五、發明說明αι) 以形成多晶矽閘極3 2 (来表示於圖中），（c)多晶矽閘極間 隙壁3 3製程，（d )進行離子植入與擴散製程以形成源極/ 汲極5 0，（ e )矽化鎢3 4形成製程，（f )未摻雜矽酸鹽玻璃3 6 形成製程，沈積該膜至約1 0 0 0埃的厚度（g )次大氣壓化學 氣相沈積之硼磷矽酸鹽玻璃3 8形成製程，沈積該膜至約 4000埃的厚度（h)電漿輔助四乙基正矽酸鹽氧化物40 (未 表示於圖中），以使得表面平坦化。所有提供這些層的該 標準製程皆包含形成一中間絕緣層（I LD)。接觸孔被定義 並蝕刻後，接著以CVD鎢沈積。鎢插塞/塞5 1被形成，如 第6圖所示。 第6圖中之接觸孔（3 0 )形成製程係使用特殊的加工條 件，選擇性地蝕刻氧化物，而未蝕刻該保護性覆蓋氮化矽 層2 2。使用電漿乾式蝕刻（FM E)製程以選擇性地移除氧化 物，並終止於該氮化物覆蓋（2 2 )上。乾式蝕刻溫度約為8 0 -2 0 0 T：。 本發明的下列優點係為具有氮化物覆蓋於適當位置的 結果，且這些為本發明的關鍵性實施例。第6圖所示的氮 化物覆蓋2 2允許無邊際接觸至以矽化物3 4為頂的擴散區5 0 。應注意地是，接觸孔區域3 [)係明顯地不對齊於源極/汲 極擴散區5 0。該氮化物覆蓋2 2將接觸區5 2電絕緣，並在無 邊際接觸孔製程中，作為一蝕刻阻絕物。此外，該鈍化氮 化物覆蓋將避免矽化物製程的過度成長。此外，該氮化物 覆蓋在未將多晶矽對多晶矽的間距變窄的情況下獲得該無 邊際接觸，其係為獲得較大晶片設計密度及更佳晶月性能P.15 4 3 2 5 9 6 V. Description of the invention (10) The twilight is etched by using an aqueous solution of luteolinic acid and a nitrogen peroxide solution. It should be noted that this shallow trench isolation (STI) will reduce the aspect ratio. The pad oxide layer 4 is left in place, as shown in FIG. 3. Refer to Figure 4 'After Partial STI Retrospective' „Thick Oxide Fragmentation Layer 20 High Density Electricity (HDP) System or Low Pressure Chemical Vapor Deposition (LpcvD) Deposition and Shape in this way f- Seamless STI trench filling. The thick IL fossil layer as the trench cover layer can be formed in the vertical furnace body (Lpcv HDP CVD. The reaction gas is Shi Xi. Degree, ammonia,-nitrogen oxide and two gases: Xi The target film thickness is about 1000-5000 angstroms. Refer to FIG. 4 again. After the subsequent gasification 20 is deposited, the surface is planarized by CMP and the etch-back process is terminated in the dashed line range and is located in the gasification layer. 20. The pad oxide layer 4 is still in place. Refer to Figure 5 'After the surface is planarized by CMP, the nitride layer 20 is removed to the bottom of the oxide layer 4 with a surname. It should be noted that the dashed line in Figure 5 indicates the original nitride plane 20 'and the arrow 21 indicates the degree of etch-back. Part of the process of touching back the gaseous coating covers a nitride 22 on the sti oxide 1 6. The selective etch-back conditions of the nitride are preferably: residual nitrogen that can be etched dry or wet. The thickness of the object cover layer is about 500-300 Angstroms. Most of the advantages of the contact hole formation 30 with reference to FIG. 6 are shown. It should be noted that the contact hole 30 is misaligned and isolates the trench 3 The edge of 丨 is protected by a passivation nitride covering 2 2. However, before tungsten contact or plug / plunger formation 30, most standard processes are performed: (a) thin gate oxide formation (not shown in the figure) (M), (b) polycrystalline silicon deposition, doping, annealing, and scoring, F4 32 5 9 6 5. Description of the invention αι) to form polycrystalline silicon gate 3 2 (shown in the figure), (c) polycrystalline silicon gate gap Wall 33 process, (d) ion implantation and diffusion process to form source / drain 50, (e) tungsten silicide 34 process, (f) undoped silicate glass 36 process, Deposition the film to a thickness of about 1000 angstroms (g) Boron-phosphosilicate glass 38 at atmospheric pressure chemical vapor deposition process, and deposit the film to a thickness of about 4000 angstroms (h) Plasma-assisted tetraethyl Based orthosilicate oxide 40 (not shown) to flatten the surface. All standard processes for providing these layers are It includes forming an intermediate insulating layer (I LD). After the contact holes are defined and etched, they are then deposited by CVD tungsten. Tungsten plugs / plugs 51 are formed as shown in Figure 6. The contact holes in Figure 6 ( 30) The forming process uses special processing conditions to selectively etch the oxide without etching the protective covering silicon nitride layer 2 2. Plasma dry etching (FM E) process is used to selectively remove the oxide And terminated on the nitride coating (2 2). The dry etching temperature is about 80-2 0 0 T. The following advantages of the present invention are the result of having the nitride coating in place, and these are A key embodiment of the invention. The nitride cover 22 shown in Fig. 6 allows marginal contact to the diffusion region 50 with the silicide 34 as the top. It should be noted that the contact hole area 3 [) is significantly misaligned with the source / drain diffusion area 50. The nitride covering 22 electrically insulates the contact area 5 2 and acts as an etch stopper in a borderless contact hole process. In addition, the passivation nitride coverage will avoid excessive growth of the silicide process. In addition, the nitride coating achieves this marginal contact without narrowing the polysilicon-to-polysilicon spacing, which is to achieve greater chip design density and better crystal moon performance.

第17頁 ^4 32 5 9 6 _2__ 五、發明說明（12) 的關鍵因素。氮化物覆蓋2 2的另一個優點係為消除”鎖孔 形成”（未表示於圖中），當一額外的氮化矽層被使用為溝 渠襯墊時將造成該鎖孔。該額外的襯墊層具有減少多晶矽 對多晶矽間距的有害效應，並造成不佳構造（鎖孔形成） 。在高縱橫比之窄且深的溝渠中所發現的"鎖孔形成"對於 裝置具有長期可靠度影響。然而，使用本發明所述的ST I 將減少縱橫比，其將促進溝渠填充並消除ST I絕緣質缝隙 與孔洞。 第6圖之氮化物覆蓋22的其他優點包含保護該ST I氧化 物區不受多數個加工的影響。該氮化物覆蓋的一明顯優點 係為保護ST I氧化物不為發生於這些區域上的蝕刻製程所 侵蚀（例如接觸孔触刻）。如第6圖所示，氮化物覆蓋2 2的 另一個預防處置係為避免矽化物5 2因過度的S T I氧化物凹 陷而過度成長。由第6圖得知，藉由將場隔離的邊緣隔離 並保護不受蝕刻侵蝕及矽化物形成，則接面漏電流可被降 低。該漏電流的種類稱為"場邊緣漏電流N。因此，該覆蓋 氮化物將降低場隔離區的漏電流，因而改良裝置可靠度， 此為本發明所帶來的關鍵性加強。再者，本發明的關鍵係 為改良製造無邊際接觸的製程，諸如簡化製程的改良、裝 置設計密度的改良以及裝置可靠度的改良。 雖然本發明已參考其較佳實施例而被特別地揭示並說 明，但是為熟習本技藝之人士所應瞭解地是，各種在形式 上與細節上的改變可於不背離本發明的精神與範疇下為之Page 17 ^ 4 32 5 9 6 _2__ V. Key factors of the invention description (12). Another advantage of nitride covering 22 is the elimination of "keyhole formation" (not shown in the figure), which is caused when an additional silicon nitride layer is used as a trench liner. This additional backing layer has a deleterious effect of reducing polycrystalline silicon spacing on polycrystalline silicon and results in poor construction (keyhole formation). The "keyhole formation" found in narrow and deep trenches with high aspect ratios has a long-term reliability impact on the device. However, using the ST I described in the present invention will reduce the aspect ratio, which will promote trench filling and eliminate ST I insulation gaps and holes. Other advantages of the nitride overlay 22 of FIG. 6 include protecting the ST I oxide region from the majority of processing. A significant advantage of this nitride overlay is that it protects the ST I oxide from being attacked by the etch processes that occur on these areas (such as contact hole etching). As shown in Fig. 6, another preventive treatment of nitride covering 2 2 is to prevent silicide 5 2 from growing excessively due to excessive S T I oxide pitting. From Figure 6, it can be seen that by isolating the edge of the field isolation and protecting it from etch erosion and silicide formation, the junction leakage current can be reduced. This kind of leakage current is called " field edge leakage current N. Therefore, the covered nitride will reduce the leakage current in the field isolation region, thereby improving the reliability of the device, which is a key enhancement brought by the present invention. Furthermore, the key of the present invention is to improve the manufacturing process of non-border contact, such as improvement of simplified process, improvement of device design density, and improvement of device reliability. Although the present invention has been specifically disclosed and described with reference to its preferred embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. For it

第18頁Page 18

Claims (1)

3259 6 六、申請專利範圍 1 · 一種製造一部份凹陷淺溝渠隔離構造於一半導體基板 上的方法，以製備一鈍化溝渠襯墊物，該方法包含下 列步驟： 設置一半導體基板，該半導體具有一溝渠形成於其中 t 設置一襯墊氧化層，其被刻畫於半導體表面上； 設置一氮化矽硬式罩幕層，其被刻畫於半導體表面上 將該溝渠以一厚的絕緣層填充； 將該絕緣體平坦化，以獲得幾乎與硬式罩幕層同平面 的溝渠隔離區， 將該溝渠絕緣體回蝕至溝渠的1 / 2或3 / 4處； 選擇性地蝕刻並移除該硬式罩幕層，而留下襯墊氧化 物於適當的位置； 因而形成一部份凹陷淺溝渠隔離構造於一半導體上， 以製備一鈍化溝渠襯墊物。 2 .如申請專利範圍第1項所述之方法，其中該襯墊氧化 物被熱成長至1 0 0 - 3 0 0埃的厚度。 3 ‘如申請專利範圍第1項所述之方法，其中該硬式罩幕 層為厚度1 0 0 0 - 3 0 0 0埃的氮化矽，其係為化學機械拋 光（CMP)的終止層。 4 .如申請專利範圍第1項所述之方法，其中該填充溝渠 的步驟包含一厚絕緣體的沈積，其係為四乙基正矽酸 鹽，以形成厚度為5000-10000埃的氧化矽。3259 6 VI. Scope of patent application 1 · A method for manufacturing a part of a recessed shallow trench isolation structure on a semiconductor substrate to prepare a passivated trench liner, the method includes the following steps: a semiconductor substrate is provided, and the semiconductor has A trench is formed in which a pad oxide layer is provided, which is depicted on the semiconductor surface; a silicon nitride hard mask layer is provided, which is drawn on the semiconductor surface, and the trench is filled with a thick insulating layer; The insulator is flattened to obtain a trench isolation area that is almost in the same plane as the hard mask layer, and the trench insulator is etched back to 1/2 or 3/4 of the trench; the hard mask layer is selectively etched and removed And leave the pad oxide in place; thus forming a part of the recessed shallow trench isolation structure on a semiconductor to prepare a passivated trench liner. 2. The method according to item 1 of the patent application range, wherein the pad oxide is thermally grown to a thickness of 100 to 300 angstroms. 3 ‘The method described in item 1 of the scope of the patent application, wherein the hard mask layer is silicon nitride having a thickness of 100-300 angstroms, which is a stop layer of chemical mechanical polishing (CMP). 4. The method according to item 1 of the scope of patent application, wherein the step of filling the trench comprises depositing a thick insulator, which is tetraethyl orthosilicate to form silicon oxide having a thickness of 5000-10000 angstroms. 第19頁 麝4 3259 6 六、申請專利範圍 5 -如申請專利範圍第1項所述之方法，其中該平坦化溝 渠的步驟係為CMP。 6 ·如申請專利範圍第1項所述之方法，其中使用乾式活 性離子蝕刻（R I E )或濕式蝕刻製程將該以氧化矽填充 的溝渠回蝕，以製備溝渠覆蓋。 7 ·如申請專利範圍第1項所述之方法’其中該為CMP步 驟之阻絕層的硬式罩幕係為選擇性濕式蝕刻所移除， 以製備鈍化溝渠覆蓋層D 8 · —種製造一部份凹陷淺溝渠隔離構造於一半導體基板 上並形成一純化溝渠襯墊物的方法，該方法包含下列 步驟： 設置一半導體基板，該半導體具有一溝渠形成於其中Page 19 Musk 3 3259 6 VI. Patent Application Range 5-The method described in item 1 of the patent application range, wherein the step of planarizing the trench is CMP. 6. The method according to item 1 of the scope of patent application, wherein the trench filled with silicon oxide is etched back using a dry active ion etching (R I E) or wet etching process to prepare a trench cover. 7. The method according to item 1 of the scope of the patent application, wherein the hard mask which is the barrier layer of the CMP step is removed by selective wet etching to prepare a passivation trench cover layer D 8 A method for forming a partially recessed shallow trench isolation structure on a semiconductor substrate and forming a purified trench liner, the method includes the following steps: setting a semiconductor substrate having a trench formed therein 第20頁 譯43259 6 申請專利範圍 蓋 因而 渠 9 -如申 剩餘 矽， 1 0 ‘如申 渠覆 1 1 ·如申 化矽 的選 的溝渠 形成一 中之部 請專利 部份的 以形成 請專利 蓋之厚 請專利 層回餘 擇性蝕 隔離區 保護性 份凹陷 範圍第 步驟包 厚度為 範圍第 氮化矽 範圍第 以形成 刻條件 幾乎與襯墊 純化層或純 絕緣質上並 8項所述之 含一厚絕緣 500-3500埃 8項所述之 層的平坦化 8項所述之 該鈍化溝渠 :選擇性活 氧化物同平 化覆蓋層， 位於溝渠頂 方法，其中 層的沈積， 的鈍化溝渠 方法，其中 係藉CMP。 方法，其中 覆蓋層的步 性離子蝕刻 面； 其係位於溝 端壁面上。 填充該溝渠 其係為氮化 覆蓋層。 作為鈍化溝 將該厚的SL 驟包含下列 (R I E )電漿 蚀刻 12 種製造 上的 的無 設置 中 設置 設置 將該 將該 的 將該 選擇 方法， 邊際接 一半導 一概墊 一硬式 溝渠以 絕緣體 溝渠隔 溝渠絕 性地蚀 部份凹陷淺溝渠隔離構造於一半導體基板 其中一鈍化溝渠襯墊物被用以製造MOSFET 觸，該方法包含下列步驟： 體基板，該半導體具有一溝渠形成於其 氧化層，其被刻晝於半導體表面上； 罩幕層，其被刻畫於半導體表面上； 一厚的絕緣層填充； 平坦化，以獲得幾乎與硬式罩幕層同平面 離區， 緣體回蝕至溝渠的1/2或3/4處； 刻並移除該硬式罩幕層，而留下襯墊氧化Page 20 Translation 43259 6 The scope of the patent application is covered by this channel. 9-If the remaining silicon is applied, 1 'If the application channel is covered, 1 1 · If the selected channel of the application silicon is formed, the middle part of the patent is requested to form the application. The thickness of the patent cover is required to return the protective layer of the selective etching isolation area to the recessed range. The thickness of the step is the range of the silicon nitride range. The formation conditions are almost the same as those of the pad purification layer or pure insulation. The planarization of the passivation trench described in item 8 including the thickening of the layers described in item 8 of 500-3500 angstroms: selective active oxide with flattening cover, located at the top of the trench method, where the layers are deposited, Passivation trench method by CMP. Method, wherein the stepped ion-etched surface of the cover layer is located on the trench end wall surface. The trench is filled with a nitrided coating. As a passivation trench, the thick SL step includes the following (RIE) plasma etching. There are 12 manufacturing settings. The setting method is to set the selection method. The marginal connection half leads to a hard trench to an insulator trench. The trench is isolated, the ground is partially etched, and the shallow trench isolation structure is constructed on a semiconductor substrate. One of the passivation trench liners is used to make MOSFET contacts. The method includes the following steps: a bulk substrate, the semiconductor having a trench formed on its oxide layer , Which is engraved on the semiconductor surface; the cover layer, which is engraved on the semiconductor surface; a thick insulating layer filling; flattening to obtain an area that is almost in the same plane as the hard cover layer, and the edge is etched back to 1/2 or 3/4 of the trench; engraving and removing the hard mask layer, leaving the liner oxidized 第21頁 ^4 32 59 6 六、申請專利範圍 物於適當的位置； 沈積一厚的鈍化絕緣層於襯墊氧化物表面上以及溝渠 上（為部份凹陷的絕緣質所填充）； 將該厚的鈍化絕緣層平坦化，以使得具有鈍化絕緣覆 蓋的溝渠隔離區幾乎與襯墊氧化物同平面； 將半導體表面氧化，以形成MOSFET的閘極與電容器氧 化物； 將多晶矽閘極沈積、摻雜、退火並刻劃，以設置閘極 壁隔離； 形成Μ 0 S F E T之源極/沒極的擴散區； 沈積並選擇性地形成自行對齊矽化物層； 沈積並形成中間介電絕緣層； 刻劃並蝕刻接觸孔於源極/汲極Ρ - Ν接面擴散區； 以CVD沈積導電接觸金屬至接觸孔中； 因而使連接至MOSFET的源極/汲極的無邊際或無邊框 接觸使用半導體基板中之部份丨酒闻择或半凹陷溝渠隔 離物中的該鈍化覆蓋層製造 .. .. 7 ... ' * ：Τ·1 其中該鈍化溝渠 覆蓋層係為厚度500-3000埃的厚__矽。 如申請專利範圍第1 2項所述之方法，其包含在鄰接溝 渠壁的半導體基板中形成一 Ρ-Ν接面的步驟，且其中 該形成氮化矽鈍化溝渠覆蓋物的先前步驟將保護Ρ-Ν 接面不受接觸孔蝕刻步驟影響。 一種製造一部份凹陷淺溝渠隔離構造於一半導體基板 13·如申請專利範圍第12項所述之方 14 15Page 21 ^ 4 32 59 6 VI. The scope of the patent application is in the proper place; deposit a thick passivation insulating layer on the surface of the pad oxide and the trench (filled with a partially recessed insulator); The thick passivation insulation layer is flattened so that the trench isolation area with passivation insulation cover is almost in the same plane as the pad oxide; the surface of the semiconductor is oxidized to form the gate and capacitor oxides of the MOSFET; Doping, annealing and scribing to set the gate wall isolation; forming the source / dead diffusion region of the M 0 SFET; depositing and selectively forming a self-aligned silicide layer; depositing and forming an intermediate dielectric insulating layer; Scribe and etch the contact hole in the source / drain P-N junction diffusion region; deposit conductive contact metal into the contact hole by CVD; thus make the borderless or borderless contact to the source / drain of the MOSFET using semiconductors Part of the substrate 丨 The passivation cover layer in the wine or semi-recessed trench isolation is manufactured .. 7 ... '*: T · 1 where the passivation channel cover layer has a thickness of 500- 3000 angstroms thick silicon. The method as described in item 12 of the patent application scope, comprising the step of forming a P-N junction in a semiconductor substrate adjacent to the trench wall, and wherein the previous step of forming a silicon nitride passivation trench cover will protect the The -N junction is not affected by the contact hole etching step. A method for manufacturing a part of a recessed shallow trench isolation structure on a semiconductor substrate 13 · The method described in item 12 of the scope of patent application 14 15 第22頁 r P4 3259 6_ ^、申請專利範圍 上的方法，其中一鈍化溝渠襯墊物被用以製造MOSFET 的無邊際接觸，該方法包含下列步驟： 設置一半導體基板，該半導體具有一溝渠形成於其中 設置一襯墊氧化層，其被刻畫於半導體表面上； 設置一硬式罩幕層，其被刻畫於丰導體表面上； 將該溝渠以一厚的絕緣層填充； 將該絕緣體平坦化，以獲得幾乎與硬式罩幕層同平面 的溝渠隔離區， 將該溝渠二氧化矽絕緣體回蝕至溝渠的1 / 2或3 / 4處； 選擇性地蝕刻並移除該硬式罩幕層，而留下襯墊氧化 物於適當的位置； 沈積一厚的鈍化絕緣層於襯墊氧化物表面上以及溝渠 上（為部份凹陷的絕緣質所填充）； 將該厚的鈍化絕緣層平坦化，以使得具有鈍化絕緣覆 蓋的溝渠隔離區幾乎與襯墊氧化物同平面； 將矽表面氧化，以形成M0SFET的閘極與電容器絕緣體 的熱二氧化矽； 將多晶矽閘極沈積、摻雜、退火並刻劃； 設置閘極壁隔離； 形成Μ 0 S F E T之源極/没極的擴散區； 沈積並選擇性地形成自行對齊矽化物層； 沈積並形成中間介電絕緣層； 刻劃並蝕刻接觸孔於源極/汲極Ρ-Ν接面擴散區，該Page 22 r P4 3259 6_ ^ Method in the scope of patent application, in which a passivation trench liner is used to make the MOSFET's borderless contact, the method includes the following steps: a semiconductor substrate is provided, the semiconductor has a trench formation A pad oxide layer is provided therein, which is engraved on the semiconductor surface; a hard mask layer is provided, which is engraved on the surface of the abundant conductor; the trench is filled with a thick insulating layer; the insulator is flattened, To obtain a trench isolation area almost in the same plane as the hard mask layer, etch back the trench silicon dioxide insulator to 1/2 or 3/4 of the trench; selectively etch and remove the hard mask layer, and Leave the pad oxide in place; deposit a thick passivation insulating layer on the pad oxide surface and on the trench (filled with partially recessed insulation); planarize the thick passivation insulating layer, So that the trench isolation area with passivation insulation cover is almost in the same plane as the pad oxide; the surface of silicon is oxidized to form the thermal oxygen of the gate of the MOSFET and the capacitor insulator Silicon deposition; deposition, doping, annealing and scoring of polycrystalline silicon gates; setting gate wall isolation; forming source / inverted diffusion regions of M 0 SFETs; depositing and selectively forming self-aligned silicide layers; deposition And forming an intermediate dielectric insulating layer; scribe and etch the contact hole in the source / drain P-N junction diffusion region, 第23頁 酽4 3259 6 六'申請專利範園 氮化矽溝渠覆蓋層將保護溝渠角落區域； 藉CVD沈積導電金屬接觸於接觸孔中； 因而使用在部份凹陷或半凹陷的氧化矽溝渠隔離中的 該氮化矽鈍化覆蓋物製造連接至MOSFET的源極/汲 極的無邊際或無邊框接觸。 1 6 ·如申請專利範圍第1 5項所述之方法，其中包含鈍化氮 化矽溝渠覆蓋物形成的製程係使用於具有P型與η型 MOSFET閘極通道的互補式MOS(CMOS)電晶體。Page 23 酽 4 3259 6 Six-patent patent application Fanyuan silicon nitride trench cover layer will protect the corner area of the trench; conductive metal is deposited by CVD to contact the contact hole; therefore, it is used in partially or semi-recessed silicon oxide trench isolation This silicon nitride passivation overlay in makes a borderless or borderless contact to the source / drain of the MOSFET. 16 · The method according to item 15 of the scope of patent application, wherein the process including the formation of a passivation silicon nitride trench cover is used for complementary MOS (CMOS) transistors with P-type and n-type MOSFET gate channels . 第24頁Page 24