TW437014B - Multi-level stack gate flash memory - Google Patents

Abstract

The present invention comprises forming a gate oxide layer on a substrate; depositing a silicon nitride layer on the oxide layer; etching the silicon nitride layer to form an opening; forming a oxide spacer on the sidewall of the opening; using ion implantation to form a doped area; removing the spacer; using a polysilicon spacer as a floating gate on the sidewall of the opening; forming a dielectric layer on the floating gate on the silicon nitride layer for being used as an inter-gate insulation layer; forming a conductive layer on the dielectric layer as a control gate; performing a chemical mechanical polishing process or etching back process to remove the conductive layer; using photolithography and etching processes to etch the dielectric layer and silicon nitride layer for defining the pattern of the gate; performing an ion implantation by using the gate as a mask to form doped area in the substrate for being used as a drain and a source; and finally, forming an insulated spacer on the sidewall of the gate.

Description

4370 r4 五、發明說明（） 發明領域： 本發明係有關於一種半導體元件，特别是一種多重態 (multi-level)堆疊閘極之快閃記憶體，本發明之記憶胞 (memory cell)具有四種多重態，可以儲存兩個位元之資 # (four-state/two-bit)= 發明背景： 半導體製程有一種提昇晶圓構裝密度的趨勢，囡此元 件之設計便不斷朝向節省空間之觀念演進。致力於縮小各 元件之大小使得積集度提昇。爲了將元件縮小，元件之尺 寸已被縮小至次微朱或更小的範園。随著半導體的演進， 多重内連線之使用也是積體電路製造技術發展之趨勢。非 揮發性記憶體的製造亦随著趨勢縮小元件尺寸，非揮發性 記憶體包含不同型式的元件，例如PR〇 Μ (可编程唯讀記憶 體），EPROM (可抹除可編程唯讀記憶體），快閃EEPROM， 不同型式元件之趨勢均朝向於高持久性及高速度之需求方 面發展。 快閃記憶體是一種非揮發性記憶元件，包含一可以儲 存電荷的懸浮閘極以及電荷出入控制單元。可攜式電腦與 電信工業已成爲半導體積體電路設計技術的主要驅動力。 例如，快閃記憶體可以應用在電腦中的基本輸出入系統 (ΒI 0 S )，高密度非揮發性記憶體的應用範圍則包含可攜式 終端設備中的大容量記憶裝置、數位固態相機以及個人電 2 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (諳先Μ讀背_面之注患事項再填寫本頁) )------II 訂·！ ·線、 經濟部智慧財產局員工消費合作社印製 437Ό.Ί 44370 r4 V. Description of the invention () Field of the invention: The present invention relates to a semiconductor device, especially a multi-level stacked gate flash memory. The memory cell of the present invention has four This kind of multi-state can store two bits of resources # (four-state / two-bit) = Background of the Invention: The semiconductor process has a tendency to increase the density of wafer structures, so the design of this component is continuously moving towards space-saving Evolution of ideas. Committed to reducing the size of each component to increase the degree of accumulation. In order to reduce the size of the components, the size of the components has been reduced to the sub-micron size or smaller. With the evolution of semiconductors, the use of multiple interconnects is also the development trend of integrated circuit manufacturing technology. The manufacturing of non-volatile memory is also shrinking with the trend. Non-volatile memory contains different types of components, such as PROM (programmable read-only memory), EPROM (erasable programmable read-only memory) ), Flash EEPROM, the trend of different types of components is developing towards the requirements of high endurance and high speed. Flash memory is a non-volatile memory element that includes a floating gate that can store charge and a charge access control unit. The portable computer and telecommunications industries have become the main drivers of semiconductor integrated circuit design technology. For example, flash memory can be used in the computer's basic input / output system (BI 0 S), and high-density non-volatile memory can be used in mass storage devices in portable terminal devices, digital solid-state cameras, and Personal electricity 2 This paper size is in accordance with Chinese National Standard (CNS) A4 specification (210 X 297 mm) (谙 M read the back _ the note on the front and then fill out this page) -------- Order II !! Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the Ministry of Economic Affairs 437 .Ό 4

五、發明說明（ 經濟部智慧財產局員工消費合作社印製 ，爲了 快速存 低電壓 閘極進 讀記憶 穿隧效 入氧化 發層。 ί及極、 基材相 ，於抹 地時， 述之穿 體的資 ，因此 {靖先間讀背面之注意事項再填寫本頁) 监？的介面卡爭。存取辛間〇 迎合在機動計算：二：低電壓讀取運作的關鍵 取的功能成爲非揮發性=用靖求’低電功率及 伴發性Z憶體的設計趨向。目前的 快閃記憶體通常在3 &丨ς ^ r ± it ^ -ifr ^ 伏特的操作電壓下對懸浮 行无電或放電動作，於从 . 胁…一 應用於電子式可編程爲 體（ROM)均利用到竽此裎 巧乐士私度的 F〇wlerN〇rdlieim 應’其中冷電子隧穿矽與二氧化矽界面的能障而進 導電帶《電壓施於閑極，電荷隨穿薄的二氧化 舉例而：，在編程模式中，施以_正電壓於基材，而 源極懸浮’閘極接地，通道的中間電壓變成幾乎與 同，則随穿電子由梦經薄氧化層（穿隨氧化層）移入 除模式中，施以一負電壓於閘極，當源極和汲極爲接 電子則被放射出來。爲了達到良好之元件性能，上 隧氧化層必須具備有良好之品質。其次，快閃記憶 訊儲存必須依賴將電荷長時間留存於懸浮閘極之中 用以隔離懸浮閘極的介電層必須具有良好的性能。V. Description of the Invention (Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, in order to quickly store the low-voltage gate to read the memory tunneling effect into the oxidized layer. Ί and the substrate phase, described in the The body's assets, so {Jing Xianjian read the notes on the back before filling out this page) Supervision? Interface card contention. Access Xinjian 〇 Catering to mobile computing: Second: the key to low-voltage reading operation The function to be taken is non-volatile = using Jingqiu ’low electrical power and accompanying Z-memory design trends. The current flash memory usually has no power or discharge action on the floating line at an operating voltage of 3 & 丨 ^ r ± it ^ -ifr ^ volts, so it can be used as a threat. One applied to electronic programmable body ( ROM) all use the FowlerNordlieim, which is privately owned by Q & A. The cold electron tunnels through the energy barrier at the interface between silicon and silicon dioxide, and enters the conductive band. For example, in the programming mode, a positive voltage is applied to the substrate, the source is suspended, and the gate is grounded. The intermediate voltage of the channel becomes almost the same. Pass through the oxide layer) into the removal mode, a negative voltage is applied to the gate, and the electrons are emitted when the source and drain are connected. In order to achieve good device performance, the tunnel oxide layer must have good quality. Second, flash memory storage must rely on the charge remaining in the floating gate for a long time. The dielectric layer used to isolate the floating gate must have good performance.

Bergemont在其論文中提出另一種應用於可攜式電 私及電Is設備的記憶胞陣列，請參閱《l〇w Voltage NVG™: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Application” (in IEEE Trans. Electron Devices Vol. 43，p. 1510，1996)。此記憶胞 結構引用於低電壓反或閘式虚擬接地（NOR Virtual 本纸張尺度適用1f1國國家標準（CNS)A4規格（210 x 297公釐） 經濟部智慧財產局員工消費合作杜印製 f ' 4370 14 A7 ___B7_-------- 五、發明說明（） G r o u n d, N V G)快閃記憶體，具有快速存取時間。在快閃 陣列體系中，複晶發層延伸於記憶胞間的場氧化層上以提 供適足的閘極搞合率（gate coupling ratio) e NVG陣列 採用選擇元件的方式以達成快速的存取時間，每次只減少 單一環節的預行充電時間（pre-charge time)，而不處理 全部的位元線。 不論如何，在目前之堆疊閘極的快閃記憶胞中，只能 具有兩種狀態，也就是” 1 ”或” 0 ”而儲存一位元之資料，如 上所陳，目前之趨勢爲縮小元件之體積以增加記憶體之密 度，囡此本發明之重點就是在單一記憶胞中可以儲存兩位 元之資料。 發明目的及概述： 本發明之目的爲提出一種多重態、可儲存兩位元資料 之單一快閃記憶胞aBergemont proposed another memory cell array for portable electrical private and electrical Is devices in his thesis, see "10w Voltage NVG ™: A New High Performance 3 V / 5 V Flash Technology for Portable Computing and Telecommunications Application ”(in IEEE Trans. Electron Devices Vol. 43, p. 1510, 1996). This memory cell structure is referenced to a low-voltage reverse or gate-type virtual ground (NOR Virtual) This paper applies the national standard 1f1 (CNS) A4 Specifications (210 x 297 mm) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs for consumer cooperation Du F f 4370 14 A7 ___ B7 _-------- 5. Description of the invention () G round, NVG) Flash memory, with Fast access time. In the flash array system, the complex crystal layer extends on the field oxide layer between the memory cells to provide an adequate gate coupling ratio. The NVG array uses a method of selecting components to Achieve fast access time, reducing the pre-charge time of a single link at a time, without processing all bit lines. In any case, the current flash memory cells of stacked gates It can only have two states, that is, "1" or "0" and store one bit of data. As mentioned above, the current trend is to reduce the volume of components to increase the density of memory. This is the focus of the present invention That is, two bits of data can be stored in a single memory cell. Purpose and Summary of the Invention: The purpose of the present invention is to propose a single flash memory cell that can store two bits of data in multiple states.

本發明之再一目的爲提出一種單一記憶胞勿八I 吧巴含兩個 分離懸浮閘極之堆疊閘極快閃記憶體，用以儲存兩位元之 資料。 本發明包含形成閘極氧化層於基板之上，然後，—氮 化矽層沈積於氧化層之上，利用微影製程形成光阻圖案飯 本紙張尺度適用_國國家標準（CNS)A4規格（210x297公釐） f請先閱讀背面之注意事項再填寫本頁) ^--------訂----- 線、 43701 4 A7 B7 五、發明說明（ 氮化破層形成-開口以定義閘極之區域，*去除 案，您後—氧化層隨後沈積於上述之氮化矽 並回塡於開口之中。铁 # <•上 刹”…然後，利用一非等向性之蝕刻製程蝕 述<轧化層形成—可去除式間隙壁殘存於上 側發上，±生·《 I「#Ί U < 接耆，利用離子佈植以氮化矽層以及間隙辟作良 :軍幕’#雜離子進入開口下方之基板中’接著去：間隙 一捧雜的複晶矽層沈積於氮化矽層之上，以及回填於 開口&中。再執行一非等向性蝕刻以蝕刻上述之複晶矽層 以形成間隙壁作爲兩分離之懸浮閘極，形成一介電^ (dlelectric)於懸浮閘極以及氮化矽層之上作爲閘極間絶 緣層’形成—導電層於介電層之上作爲控制閘極，再執行 —化學機械研磨製程或回蝕刻製程，去除上述之導電層， 最佳爲使得導電層只留存於開口之中作爲揑制閘極，之後 利用蚀刻製程蝕刻介電層與氮化矽層定義出閘極之圖 案。再執行離子佈植技術，以閛極作爲罩幕形成摻雜區域 於基板之中作爲汲極與源極。最後製作絶緣之間隙壁於閘 極之側壁之上。 S式簡單説明： 本發明的較佳實施例將於往後之説明文字中輔以下 列圓形做更詳細的闡述： 第一囷爲根據本發明在基板上形成閘極氧化層及氮 本纸張又度適用中國國家標準（CNS)A4規格（210x 297公釐） f靖先閱讀免面之注t事項再填寫本頁} ----訂---------線、 經濟部智慧財產局員工消費合作社印製 4 v-i ο 734 A7B7 經濟部智慧財產局員工消費合作社印製Yet another object of the present invention is to provide a single-memory cell Waba I, a stacked gate flash memory with two separate suspended gates, for storing two-bit data. The invention includes forming a gate oxide layer on a substrate, and then, a silicon nitride layer is deposited on the oxide layer, and a photoresist pattern is formed by a photolithography process. The size of the paper is applicable. 210x297 mm) f Please read the notes on the back before filling in this page) ^ -------- Order ----- Line, 43701 4 A7 B7 V. Description of the invention (Nitride layer formation-opening To define the area of the gate, * remove the case, after you-the oxide layer is subsequently deposited on the above silicon nitride and reverted into the opening. Iron # " Upper brake " ... Then, using an anisotropic Etching process < Rolling layer formation—removable gap wall remains on the upper hair, ± "I" # Ί U < Connection, using ion implantation to silicon nitride layer and gaps to make good : Army curtain '#Miscellaneous ions enter the substrate below the opening' and then go: a gap of a complex polycrystalline silicon layer is deposited on the silicon nitride layer, and backfilled in the opening & then an anisotropy is performed Etching is to etch the above-mentioned polycrystalline silicon layer to form a partition wall as two separate suspended gates to form a dielectric ^ ( dlelectric) is formed on the floating gate and the silicon nitride layer as an inter-gate insulating layer-a conductive layer is used as a control gate over the dielectric layer, and then a chemical mechanical polishing process or an etch-back process is performed to remove the above The conductive layer is preferably such that the conductive layer only remains in the opening as a fabricated gate, and then the dielectric layer and the silicon nitride layer are etched by an etching process to define the gate pattern. Then an ion implantation technique is performed to reduce the The electrode is used as a mask to form a doped region in the substrate as the drain and source. Finally, an insulating spacer is made on the side wall of the gate. S-type brief description: The preferred embodiments of the present invention will be described later. The description is supplemented by the following circles for a more detailed explanation: The first one is to form the gate oxide layer and nitrogen on the substrate according to the present invention. This paper is also applicable to the Chinese National Standard (CNS) A4 specification (210x 297 mm). ) F Jing first read the face-free note t and then fill out this page} ---- Order --------- Line, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 4 vi ο 734 A7B7 Ministry of Economy Wisdom Printed by the Property Agency Staff Consumer Cooperative

本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） (請先閱讀免面之注奮事項再填寫本頁) ----訂--------- A7 437014 B7_______ 五、發明說明（） 導體晶圓剖面圖； 第十四圖爲本發明之元件符號示意圖； 第十五圖爲本發明基本記憶胞之佈局圖； 第十六圖爲本發明之編程、抹除及讀取狀怒之示意圖 以及能階示意圖。 發明詳細説明： 本發明提供一新方法以及新結構用以製造非揮發性 快閃記憶體，本發明主要特徵爲四種多重態（f〇Ur_ state)、以及可儲存雨位元資料（two_bit)之單一快閃記憶 胞。且本發明之單一記憶胞爲一種堆疊閘極快閃記憶體， 其中包含兩個分離懸浮閘極堆疊閘極快閃記憶體’有别於 傳統之單一懸浮閘極，只可以儲存單一位元。 本發明配合圖示詳細説明如下。首先提供一半導體基 板，如第一圖中所示，在取佳實施例中’基板2爲結晶面 向<100>的單晶矽。在基板2上的各元件之間形成複數個隔 離區4，此隔離區的形成可以採場氧化隔離法或渠溝隔離 法。例如場氧化區可以採用微影輿乾蝕刻製程對氮化矽與 一氧化發組合層進行蚀刻而定義。圖中利用一淺溝渠隔離 製程做一説明，通常利用一光阻圖案形成於基板2之上用 以定義一溝渠式隔離區之區域，然後以此光阻圖案做爲触 刻罩幕將晶圓2蝕刻形成一溝渠於晶圓或基板2之中，通常 溝渠之深度由基板2之表面計算約爲2〇〇〇至8000埃之 間。完成溝渠之後則將上述之光阻圖萦去除。並在完成溝 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297 --?----«*1111 ! I 訂·----I I I I (諳先閱讀免面之注t事項再填寫本I) 經濟部智慧財產局員工消費合作杜印製 7 1 4370 1 4 A7 一..一__B7___ 五、發明說明（） 渠蝕刻之後，一絶緣材料接著回填進入溝渠之中，經平坦 化處理以完成淺溝渠隔離結構4。 (請先閱讀免面之注意事項#.填寫本頁) 接著於基板2上形成由氧化矽所構成的薄閘極氧化 層6，此閘極氧化層6 —般可以在攝氏溫度约7〇〇至 1100度之下於氧環境中以熱氧化法長成。此外，也可以 採用其他方珐如化學氣相沈積法（chernicai Vapor Deposition, CVD)形成此閘極氧化層6。在本實施例中， 閘極氧化層6的厚度約爲1 5胃2 5 0埃。然後，一氮化發層 8沈積於氧化層6之上，利用微影製程形成光阻圖案蝕刻 上述之氮化矽層8形成一開口 1〇以定義閘極之區域，再 去除光阻圖案，之後可以選擇性地執行一氧化熱處理。在 最佳實施例中，此氮化矽層8可選擇SiH4、ΝΗ3、Ν2、 Ν2〇作爲反應氣體，於溫度攝氏300至800度之下形成。 以較佳實施例而言可以利用低壓化學氣相沈積法（L〇w Pressure Chemical Vapor Deposition; LPCVD) ' 電衆 增強式化學氣相沈積法（Plasma Enhance Chemical Vapor Deposition; PECVD)、或高密度電漿化學氣相沈 積法（High Density Plasma Chemical Vapor Deposition; HDPCVD)形成氮化石夕。 經濟部智慧財產局員工消費合作社印製 參閱第二圖，一氧化層12隨後沈積於上述之氮化矽層 10之上並回填於開σ 1 0之中。利用化學氣相沈積法 (chemical vapor deposition; CVD)沈積氧化層 12 於上 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經 濟 部 智 慧 財 產 局 消 費 合 作 社 印 製 '' 4370 1 4 A7 _ B7__五、發明說明（) 述之氮化矽8之上，氧化層j 2可以爲利用電漿增強式所形 成之氧化層、以次大氣壓化學氣彳目沈積法所形成之氧化層 或是利用ozone-TEOS爲反應物形成之氧化層（020116_ TEOS oxide)，ozone_TEOS 之反應溫度約爲 400 至 480 °C。然後’利用一非等向性之蝕刻製程蝕刻上述之氧化層 1 2使其形成一間隙壁1 2殘存於上述開口 1 〇之側壁之上， 如第二圖所示。接著，利用全面性離子佈植製程，以氮化 矽層8以及間隙壁12作爲一罩幕，摻雜離子進入開口 12下 方之基板2中形成N +摻雜之摻雜區域14，此示意於第四 圖。接著，如第五圖所示去除間隙壁12以及爲被遮蓋之氧 化層6以曝露出基板2，本發明可以利用稀釋之氫氟酸（η ;容液或Β Ο E溶液來去除上述之氧化珍材料。之後，再長 穿隧氧化層。 & 參閱第六圖’在沈積複晶石夕層之前，先行執行一氡 熱處理使穿隧氧化層6具有較好之品質。一摻雜的複晶 矽層16沈積於氮化矽層8，以及回填於開口 之中阳 此複晶發層16的製作可以採用pH3爲離子源，以=子 植法或是同步摻雜法將磷離子植入而成。再執行一非 性敍刻以独刻上述之複晶石夕層16，同埋，複晶石夕間隙Z 【6殘存於開口 10之側壁之上。此複晶石夕間隙壁a將； 爲kl序閘極，由側面圖可以得知，複晶矽間隙壁 爲兩部分，可以分别儲存—位元之資料，示之於第七圖。 (諝先閲讀背面之iit-事項再填寫本頁)This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) (please read the note-free items before filling out this page) ---- Order --------- A7 437014 B7_______ 5. Description of the invention () Sectional view of conductor wafers; Figure 14 is a schematic diagram of the component symbols of the invention; Figure 15 is the layout of the basic memory cell of the invention; Figure 16 is the programming and erasing of the invention Removal and reading of schematic diagrams and energy level diagrams. Detailed description of the invention: The present invention provides a new method and a new structure for manufacturing non-volatile flash memory. The main features of the present invention are four multi-states (f0Ur_state) and rain-bit metadata (two_bit). Single flash memory cell. In addition, the single memory cell of the present invention is a stacked gate flash memory, which includes two separated suspended gate stacked gate flash memories', which is different from the traditional single suspended gate and can only store a single bit. The present invention is described in detail with reference to the drawings. First, a semiconductor substrate is provided. As shown in the first figure, in the preferred embodiment, the 'substrate 2 is a single crystal silicon with a crystal face of < 100 >. A plurality of isolation regions 4 are formed between the elements on the substrate 2. The isolation regions can be formed by a field oxidation isolation method or a trench isolation method. For example, the field oxide region can be defined by using a lithography and dry etching process to etch the combined layer of silicon nitride and monoxide. In the figure, a shallow trench isolation process is used as an illustration. Generally, a photoresist pattern is formed on the substrate 2 to define a trench isolation region. Then, the photoresist pattern is used as a touch engraving mask to wafers. 2 etch to form a trench in the wafer or substrate 2. Generally, the depth of the trench is calculated from the surface of the substrate 2 to about 2000 to 8000 angstroms. After the trench is completed, the photoresist pattern described above is removed. And in the finished paper size, the Chinese national standard (CNS) A4 specification (210 X 297-? ---- «* 1111! I order · ---- IIII (谙 read the note of the face-free note before Fill out this I) Consumer cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs, printed by Du 1 7 1 4370 1 4 A7 I..1__B7 ___ V. Description of the invention () After the trench is etched, an insulating material is then backfilled into the trench and flattened. Process to complete the shallow trench isolation structure 4. (Please read the precautionary note # .Fill out this page first) Then form a thin gate oxide layer 6 made of silicon oxide on the substrate 2 and this gate oxide layer 6 — Generally, it can be grown by thermal oxidation in an oxygen environment at a temperature of about 700 to 1100 degrees Celsius. In addition, the gate can also be formed by other methods such as chemical vapor deposition (chernicai Vapor Deposition, CVD). The oxide layer 6. In this embodiment, the thickness of the gate oxide layer 6 is about 15 to 250 Angstroms. Then, a nitrided hair layer 8 is deposited on the oxide layer 6, and a photoresist is formed by a lithography process. Pattern-etch the above silicon nitride layer 8 to form an opening 10 to define the gate area, and then remove The photoresist pattern can be optionally subjected to an oxidative heat treatment. In the preferred embodiment, the silicon nitride layer 8 can be selected from SiH4, Ν3, Ν2, and Ν2〇 as a reaction gas at a temperature of 300 to 800 degrees Celsius. In the preferred embodiment, Low Pressure Chemical Vapor Deposition (LPCVD) ′ Plasma Enhance Chemical Vapor Deposition (PECVD), or High Density Plasma Chemical Vapor Deposition (HDPCVD) forms nitride nitride. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Refer to the second figure. An oxide layer 12 is then deposited on the above silicon nitride. Layer 10 is backfilled in σ 1 0. The oxide layer 12 is deposited by chemical vapor deposition (CVD). The above paper size applies Chinese National Standard (CNS) A4 (210 X 297 mm) (B) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs '' 4370 1 4 A7 _ B7__ V. Description of the invention () On the silicon nitride 8 described above, the oxide layer j 2 may It is thought that the oxide layer formed by plasma enhanced type, the oxide layer formed by the sub-atmospheric chemical gas deposition method or the oxide layer formed by using ozone-TEOS as a reactant (020116_ TEOS oxide), the reaction temperature of ozone_TEOS is about 400 to 480 ° C. Then, a non-isotropic etching process is used to etch the above-mentioned oxide layer 12 to form a partition wall 12 and remain on the side wall of the opening 10, as shown in the second figure. Next, using a comprehensive ion implantation process, using the silicon nitride layer 8 and the spacer 12 as a mask, doped ions enter the substrate 2 below the opening 12 to form an N + doped region 14. This is schematically shown in FIG. Fourth figure. Next, as shown in the fifth figure, the spacer wall 12 and the covered oxide layer 6 are exposed to expose the substrate 2. The present invention can use the diluted hydrofluoric acid (η; solution or B 0 E solution to remove the above-mentioned oxidation). After the tunneling oxide layer is grown, & refer to the sixth figure 'Before depositing the polycrystalline stone layer, first perform a heat treatment so that the tunneling oxide layer 6 has better quality. A doped compound The crystalline silicon layer 16 is deposited on the silicon nitride layer 8 and back-filled in the opening. The complex crystalline hair layer 16 can be produced by using pH 3 as an ion source and implanting phosphorus ions by a seeding method or a synchronous doping method. Then, perform a non-sexual engraving to engrav the above-mentioned polycrystalline stone layer 16, and bury them together, and the polycrystalline stone gap Z [6 remains on the side wall of the opening 10. This polycrystalline stone gap wall a Will be the kl sequence gate, as can be seen from the side view, the polycrystalline silicon spacer is two parts, which can be stored separately-bit data, shown in the seventh figure. (谞 read the iit-item on the back before (Fill in this page)

J 0 ^1 I 1* 訂----- Ψ, 4370 1 4J 0 ^ 1 I 1 * Order ----- Ψ, 4370 1 4

五、發明說明（ 經濟部智慧財產局員工消費合作社印制 接著參閲第八園 至姑 ）成一介電層（dielectric) 18於懸 序閘極1 6以及惫价^ 、I、 氬化矽層8之上作爲閘極間絶緣層 電18可以採〇Ν〇忐耳疋个 戍 組合層作爲材質。形成一導電 臂2 0於介電層·] q a 此導電層20可以採離::控制開# ’如第九圖所示。 …質。此外，金佈二：…同步掺雜的複晶 金屬層或合金層在適當之條件之下，亦 可作爲導電層的姑X . 的材枓。再執行一化學機械研磨製程或回蝕 1程’去除上述之導電層20，最佳爲使得導電層2〇 只^存於開口 1 〇之十作爲控制閑極，如第十圖所示。參 閲第十一圖，之後利用蝕刻製程蝕刻介電層1 8與氮化矽 層定義出閘極之圖案。在最佳之例子中，控制微影製 程之條件，使氮化矽層δ全數移除。 參閲十二圖，再執行 MDD(medium doped drain) 離子佈植技術’以閘極作爲罩幕形成摻雜區域於基板2 (中作爲没極與源極22。最後製作絶緣之間隙壁24於 閑極之侧壁之上，最後結果顯示於第十三圖中。其組成材 料可以爲氮化物、氧化物或類似之材料。本發明之快閃記 憶體包含：閘極氧化層6,形成於半導體基板2上，懸浮 閉極1 6位於閘極氧化層6之上且爲分離之兩部分以儲存 兩位元之資料，介電層1 8，位於懸浮閘極1 6之表面以 及兩分離懸浮閘極1 6間之半導體基板表面，控制閘極2 0 位於介電層18之上，第一摻雜區I4,位於基板2之中， 且介於兩分離懸浮閉極1 6之間及第二摻雜區域{汲極與 10 本紙張尺度適用中㈣家標iMCNS)A4規格（210 X 297公愛） ^ ^ ^-----—訂 --------線、 (請先閱讀兒面之注東事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 r 437014V. Description of the invention (printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and then refer to the eighth garden to the first) into a dielectric layer (dielectric) 18 on the suspended gate 16 and the fatigue price ^, I, silicon argon layer On top of 8 as the inter-gate insulation layer, 18 can be made of a combination layer as a material. A conductive arm 20 is formed on the dielectric layer.] Q a The conductive layer 20 can be taken off :: control open # ′ as shown in the ninth figure. …quality. In addition, the gold cloth II: ... synchronously doped polycrystalline metal layer or alloy layer can also be used as the material of the conductive layer under the appropriate conditions. Then perform a chemical mechanical polishing process or an etch-back process to remove the conductive layer 20 described above, and it is best to make the conductive layer 20 only exist in the opening 10 ten as the control idler, as shown in the tenth figure. Referring to the eleventh figure, the gate electrode pattern is defined by etching the dielectric layer 18 and the silicon nitride layer using an etching process. In the best example, the conditions of the lithography process are controlled so that the silicon nitride layer δ is completely removed. Refer to the twelve figure, and then perform the MDD (medium doped drain) ion implantation technique 'using the gate as a mask to form a doped region on the substrate 2 (the middle as the anode and the source 22. Finally, an insulating spacer 24 is made on The final result is shown on the thirteenth figure on the side wall of the idler electrode. Its composition material can be nitride, oxide or similar material. The flash memory of the present invention comprises: a gate oxide layer 6 formed on On the semiconductor substrate 2, the suspended closed electrode 16 is located on the gate oxide layer 6 and is a separate two part to store two-bit data. The dielectric layer 18 is located on the surface of the suspended gate 16 and two separated suspensions. On the surface of the semiconductor substrate between the gates 16, the control gate 20 is located on the dielectric layer 18, and the first doped region I4 is located in the substrate 2 and is between the two separated suspended closed electrodes 16 and the first Two doped regions {drain and 10 paper sizes are applicable to the Chinese standard iMCNS) A4 specification (210 X 297 public love) ^ ^ ^ ------- order -------- line, (please (Please read the note above and then fill out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs r 437014

你年t月f日修正/更正/補充 AJ ----------- B7 五、發明説明（） 源極）2 2位於基板2之中，分别鄰接分離懸浮閘極1 6之 兩側’第一捧雜區域1 4位於第二摻雜區域22之間。 第十四圖與第十五圖分别爲本發明之元件符號示意 圖與基本記憶胞之佈局圖。第十六圖則爲本發明之編程 (program)、抹除（erase)及讀取（read)狀態之示意圖以及 忐階不意圖’其各狀態之偏壓列於表一。在編程之狀態 時’本發明之懸浮閘極具有兩個，利用在汲極或源極之偏 壓狀態，可以選擇每一個懸浮閘極之資料寫入狀態。例 如，在7F意圖中爲顯示a 1懸浮閘極寫入狀態下之偏壓情 況’没極22 D在+ vPG下偏壓.，控制閘極2〇則被施以 + VCG.P偏壓，源極22S與p丼2則接地，在導帶之電子 將隧穿過穿隧氧化層之位障進入懸浮閘極A〗且陷於懸浮 閘極A1之中，而將資料寫入A1，由於A〇之通道爲载子 空乏狀態，是故無電子穿隧進入A 〇。同理，依照上述源 汲極相反偏壓之原則，可以將電子穿隧進入A 〇 ^在抹除 之狀態時，汲極22D、源極22S與P井2均被施以正偏 壓’負電壓-Vc G E則施加於控制閘極2 〇之上，在上述之 偏壓情形下不論位於A 1或A0中之負載子將被控制閘極 20之負偏壓排斥穿過穿隧氧化層進入p井2之十，完成 抹除之動作。讀取狀態之下，控制閘極2 0之偏壓爲 + VCG.R，p井2爲接地，在相1狀態下，源極22s與没 極22D則分别爲正偏壓、接地。依照通道宁有無讀取電 流’則可能有表一之四種情形’也就是（A 〇，A 1)之狹雄 本紙張尺度逍用中國國家標準（CNS > A4规格（210X297公釐) ----- --Γ--,----1装^---r----ΐτ {請先閱讀背面之注意事項再填寫本頁} 4370 1 4 你年亡月？日修正/更正/補充 A7 B7 五、發明説明（ 可能爲（0，0)、（〇，1)、（1，〇)與（1，1)。但是由於在上 述之可能情形下無法判定A 0與A 1之實際情形，例如無 電流之情形有可能爲（〇，〇)或（1，〇)。因此必須利用相2 之偏壓情形，也就是汲極與源極之偏壓反接，加以確認 A 0與A1之確實狀態。 請 ▲ 閱 讀 背 面 之 注 表一 控制閘極 汲極 源極 基板（P 井） AO A 1 葱 事 項 再 填 寫 本 頁 編程 + Vc G . Ρ + Vpg GND GND 0 1 + Vc G * P GND + Vp g GND 1 0 抹除 -Vc G . E + Ver + Ver + Vpw 0 0 I r e a d 相 0 0 No + Vc G R + V r e a d GND GND 〇 1 Yes 讀 1 1 0 No 1 1 Yes 相 0 0 No + Vc G . R GND + Vr e a d GND 0 1 No 2 1 0 Yes 1 1 Yes 經濟部智慧財產局員工消費合作社印製Correction / correction / addition of AJ on t / f date of your year ----------- B7 V. Description of the invention () Source electrode 2 2 is located in the substrate 2 and is adjacent to the separation suspension gate 1 6 The two 'first doped regions 14 are located between the second doped regions 22 on both sides. The fourteenth and fifteenth figures are schematic diagrams of element symbols and layout of basic memory cells, respectively. The sixteenth figure is a schematic diagram of the program, erase, and read states of the present invention, and the bias of each state of the first order is not shown in Table 1. In the state of programming, the floating gate of the present invention has two. By using the bias state at the drain or source, the data writing state of each floating gate can be selected. For example, in the intent of 7F, to show the bias condition of a 1 floating gate writing state, 'Muji 22 D is biased at + vPG. The control gate 20 is biased at + VCG.P, The source electrodes 22S and p 丼 2 are grounded, and the electrons in the conduction band tunnel through the barrier of the tunneling oxide layer into the suspended gate A and fall into the suspended gate A1, and write the data to A1, because A The channel of 〇 is empty, so no electrons tunnel into A 〇. In the same way, according to the principle of the opposite bias of the source and drain, the electrons can be tunneled into A 〇 ^ In the state of erasing, the drain 22D, source 22S and P well 2 are all applied with a positive bias. The voltage -Vc GE is applied to the control gate 2 0. Under the above-mentioned bias conditions, the load carriers, whether located in A 1 or A0, will be repelled by the negative bias of the control gate 20 to enter through the tunneling oxide layer. The tenth of p well 2 completes the erasing action. In the read state, the bias voltage of the control gate 20 is + VCG.R, and the p well 2 is grounded. In the phase 1 state, the source 22s and the anode 22D are positively biased and grounded, respectively. According to the channel ’s presence or absence of reading current, there may be four cases in Table I, that is, the narrow male paper size of (A 〇, A 1) uses the Chinese national standard (CNS > A4 specification (210X297 mm)- ---- --Γ-, ---- 1 installed ^ --- r ---- ΐτ {Please read the precautions on the back before filling out this page} 4370 1 4 What is the date of your death? Correction / Supplement A7 B7 V. Description of the invention (may be (0,0), (〇, 1), (1,0) and (1,1). However, it is impossible to judge A 0 and A in the above possible situation The actual situation of 1, for example, the situation without current may be (0, 0) or (1, 0). Therefore, the bias situation of phase 2, that is, the reverse bias of the drain and source, must be confirmed The actual status of A 0 and A1. ▲ Please read the note on the back of Table 1. Control gate drain source substrate (P well) AO A 1 Please fill in this page to program + Vc G. P + Vpg GND GND 0 1 + Vc G * P GND + Vp g GND 1 0 Erase-Vc G. E + Ver + Ver + Vpw 0 0 I read Phase 0 0 No + Vc GR + V read GND GND 〇1 Yes Read 1 1 0 N o 1 1 Yes Phase 0 0 No + Vc G. R GND + Vr e a d GND 0 1 No 2 1 0 Yes 1 1 Yes

以上所述僅爲本發明之較佳實施例而已，並非用以限 I 定本發明之申請專利範園；凡其它未脱離本發明所揭示之 1 精神下所完成之等效故變或修飾，均應包含在下述之申請 _ i 專利範圍内α I 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 經濟部智慧財產局員工消費合作社印製 ί ' 437 0 14 你年元另7曰降正/史正/補充 五、發明説明（） 圖號對照説明 2 基板 4 ;篆溝渠隔離結構 6 穿隧氧化層 8 氮化矽層 10 開π 12 氧化層 14 N +摻雜區域 16 懸浮間極 18 〇NO介電層 20 控制閘極 22 汲極與源極 22D '汲極 22S 源極 A 1 懸浮閘極 A0 懸浮閘極 12-Ϊ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the patent application for the present invention; all other equivalent alterations or modifications made without departing from the spirit disclosed in the present invention, All of them should be included in the following applications: i Within the scope of the patent α I This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs The other 7 is Zhengzheng / Shi Zheng / Supplementary V. Description of the invention () Drawing number comparison description 2 Substrate 4; trench isolation structure 6 tunnel oxide layer 8 silicon nitride layer 10 π 12 oxide layer 14 N + doped region 16 Suspension electrode 18 〇NO dielectric layer 20 Control gate 22 Drain and source 22D 'Drain 22S Source A 1 Suspension gate A0 Suspension gate 12-Ϊ (Please read the precautions on the back before filling in this (Page) This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)

Claims (1)

六、申請專利範圍 A8 BS C8 D8 一種在半導體基板上形成快閃記憶體的方法，該方法 上 板 基 體 導 半 該 於 : 層 驟化 步氧 列極 下閘 含成 包形 少 至 層口 化開之 氧一層 極成矽 閘形化 該以氮 於層該 層砍於 矽化層 化氮化 氮該氧 成刻成 形蝕形 ♦， 上其 之於 之 口 開 該 於. 填 回 及 以 上 中 之 壁 侧 之 D 開 該 於 壁 隙 間 1 第 成 形 以 層 化 氧 該 刻 蝕 植 佈 子 離 行 執； 幕中 罩之 爲板 .作基 矽體 化導 氮半 該該 與於 壁域 隙區 間雜 一參 第一 該第 以成 ; 形 上 以 壁於該 隙層於 間化層 一 氧砍 第隧晶 該穿複 除成成 去形形 該 氮 D 開 該 於 塡 回A; 之！一 板j 基之 體層 導矽 半化 (請先閱讀背面之注意事項再填寫本頁) 中 之 壁 側 之 口 開 該 於 壁 隙 間 二 第 成 形 以 層 矽 晶 複 該 刻 蚀 極 閘 浮 懸 爲 作 上 之 上 之 層 矽 化 IL 該 及 以 極 閘 浮 懸 該 於 層 電 介 成 形 經濟部智慧財產局員工消費合作社印製 案 圖 極 閘 ;義 極定 閘以 .，制層 上控矽 之爲化 層作氮 電層該 介電及 該導以 於該層 屠之電 電份介 導部該 成除刻 形去蝕 上 及之 ;壁 域侧 區之 雜構 摻結 二極 第閘 成該 形於 以壁 植隙 佈間 子三 離第 行成 執形 !3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ：4370 14 έΐ C8 嗍年二jpk修正/劳正/缔#._^_. 々、申請專利範圍 (請先間讀背面之注意事項再填寫本頁) 2. 如宇請專利之範圍第 1項之方法，其中在於形成該複 晶矽層之前更包含執行一氧化熱處理以提昇穿隧氧化層 之品質。 3. 如申請專利範圍第 1項之方法，其中上述之導電層包 含複晶砂層。· 4 .如申請專利範園第1項之方法，其中上述之第一間隙 壁係利用H F溶液去除。 5 .如申請專利範圍第 1項之方法，其中上述之第一間隙 壁係利用Β Ο Ε溶液去除。 6 .如申請專利範圍第 1項之方法，其中去除上述導電層 之步驟，俾使其殘留於該開口之_。 7.如申請專利範圍第 1項之方法，其中上述之介電層包 含 ΟΝΟ。 經濟部智慧財產局員工消費合作社印製 8 .如申請專利範圍第 1項之方法，其中上述之介電層包 含NO = 9 .如申請專利範圍第 1項之方法 > 其中上述之第一摻雜 區域為N +摻雜區域。 本紙張尺度適用中國國家標率（CNS ) A4規格（210X297公嫠） ：4370 1 4 C8 D8六、申請專利範圍 10.如申請專利範圍第1項之方法，其中上述之第二摻雜 區域作爲汲極與源極。 1 1. 一種多重態快閃記憶體，該多重態快閃記憶體至少包 含： 閘極氧化層，形成於半導體基板上； 懸浮閘極，位於該閘極氧化層之上且爲分離之兩部分 以儲存兩位元之資料； 介電層，位於該懸浮閘極之表面以及該兩分離懸浮閘 極間之該半導體基板表面； 控制問極，位於該介電層之上；及 第一摻雜區，位於該基根之中，且介於該兩分離懸浮 閘極間之間；及 第二摻雜區域，位於該基板之中，分别鄰接該分離懸 浮閘極之兩側，該第一摻雜區域位於該第二摻雜區域之 間。 1 2 .如申請專利範圍第1 1項之多重態快閃記憶體，其中 上述之懸浮閘極係包含複晶矽。 請 先-閱 讀 背-· 面 之 意 事 項 再 \ 填；.）I芩 頁 I I I I訂 經濟部智慧財產局員工消費合作社印製 1 3 .如申請專利範圍第i1項之多重態快閃記憶體，其中 上述之控制閘極係包含複晶碎。 1 4 .如申請專利範圍第1 1項之多重態快閃記憶體，其中 上述之介電層包含ΟΝΟ。 15 本紙張尺度適用中國國家標準（CNS)A4規格(.210 X 297公釐） ! 437014 I D8 六、申請專利範圍 1 5 .如申請專利範圍第1 1項之多重態快閃記憶體，其中 上述之介電層包含NO。 1 6 .如申請專利範圍第1 1項之多重態快閃記憶體，其中 上述之第一摻雜區域爲N +摻雜區域。 1 7 .如申請專利範圍第1 1項之多重態快閃記憶體，其中 上述之第二摻雜區域爲汲極與源極。 1 8 .如申請專利範圍第1 1項之多重態快閃記憶體，更包 含間隙壁形成於上述之懸浮閘極之側壁之上。 '_ - , 0 1 n ^^1 ^^1 n (請先閱讀r面之汰意事項再填寫本頁) 訂—-------^ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Sixth, the scope of patent application A8 BS C8 D8 A method of forming flash memory on a semiconductor substrate, the method of the upper substrate of the board should be: the step of the step of the oxygen column, the lower gate of the oxygen column contains a package shape as low as the layer mouth Open the layer of oxygen into a silicon gate, the layer of nitrogen, the layer cut in the silicide layer of nitrogen nitride, the oxygen into the etched shape, the opening of the above should be opened. Fill in and above The D on the side of the wall should be formed between the gaps. The first layer is formed by layered oxygen. The etched cloth is separated from the line; the cover in the curtain is a plate. The silicon silicide is used as a base to conduct nitrogen. The first reference is the first; the wall is formed in the gap layer and the interstitial layer is cut by an oxygen to cut through the tunnel crystal to form a shape; the nitrogen D is opened to return to A; The body-side silicon-guided half of a plate of j substrate (please read the precautions on the back before filling this page), the opening on the wall side should be formed between the gaps, and the etched gate will be suspended with a layer of silicon crystal. The upper layer of silicified IL should be printed on the gate and the gate should be suspended on the layer of dielectric forming. The Intellectual Property Bureau of the Intellectual Property Bureau of the Ministry of Economic Affairs will print a plan gate; The dielectric layer is used as a nitrogen electrical layer. The dielectric and the conductive layer in the layer are formed by etching and etching; the heterostructure of the side region of the wall is mixed with a second pole gate to form the shape. In the wall planting gap, the three lines of the cloth are in line! 3 This paper size applies to the Chinese National Standard (CNS) A4 (210 X 297 mm): 4370 14 ΐ 嗍 C8 二 year 2 jpk correction / Labor /缔 # ._ ^ _. 々 Scope of patent application (please read the precautions on the back before filling out this page) 2. If you want to apply for the method of item 1 of the scope of the patent, it is more important before forming the polycrystalline silicon layer. Includes performing an oxidation heat treatment to enhance tunneling oxygen Quality layers. 3. The method according to item 1 of the patent application scope, wherein the above-mentioned conductive layer includes a polycrystalline sand layer. 4. The method according to item 1 of the patent application park, wherein the above-mentioned first gap wall is removed using an H F solution. 5. The method according to item 1 of the scope of patent application, wherein the above-mentioned first interstitial wall is removed by using a Beta OE solution. 6. The method according to item 1 of the scope of patent application, wherein the step of removing the above-mentioned conductive layer is performed so that it remains in the opening. 7. The method of claim 1 in the scope of the patent application, wherein the above-mentioned dielectric layer includes ONO. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 8. If the method of applying for the scope of the first item of the patent, the above-mentioned dielectric layer contains NO = 9. The method of applying for the scope of the first item of the patent, > The hetero region is an N + doped region. This paper scale is applicable to China National Standards (CNS) A4 specifications (210X297 cm): 4370 1 4 C8 D8 6. Application for patent scope 10. If the method of the first scope of patent application is applied, the above-mentioned second doped region is used as Drain and source. 1 1. A multi-state flash memory, the multi-state flash memory includes at least: a gate oxide layer formed on a semiconductor substrate; a suspended gate located on the gate oxide layer and separated into two parts; To store two-bit data; a dielectric layer on the surface of the floating gate and the surface of the semiconductor substrate between the two separated floating gates; a control electrode on the dielectric layer; and a first doping A second doped region is located in the base and is between the two separated suspended gates; and a second doped region is located in the substrate and adjacent to both sides of the separated suspended gate, respectively, the first doped region The impurity region is located between the second doped regions. 12. The multi-state flash memory according to item 11 of the scope of the patent application, wherein the above-mentioned suspended gate comprises polycrystalline silicon. Please-read the back of the above-mentioned matters before you fill in;.) I page IIII order printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 3. If the multi-state flash memory of item i1 of the patent application scope, The above-mentioned control gate system includes complex crystal fragments. 14. The multi-state flash memory according to item 11 of the patent application scope, wherein the above-mentioned dielectric layer includes ONO. 15 This paper size is applicable to China National Standard (CNS) A4 (.210 X 297 mm)! 437014 I D8 VI. Application for patent scope 1 5. For multi-state flash memory of item 11 of patent scope, where The above-mentioned dielectric layer contains NO. 16. The multi-state flash memory according to item 11 of the application, wherein the first doped region is an N + doped region. 17. The multi-state flash memory according to item 11 of the patent application scope, wherein the second doped region is a drain and a source. 18. The multi-state flash memory according to item 11 of the scope of patent application, further comprising a spacer formed on the side wall of the floating gate. '_-, 0 1 n ^^ 1 ^^ 1 n (Please read the notice on the r page before filling out this page) Order —------- ^ Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Paper size applies to China National Standard (CNS) A4 (210 X 297 mm)