TW434846B - Mold die for semiconductor package - Google Patents

Mold die for semiconductor package Download PDF

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Publication number
TW434846B
TW434846B TW088118455A TW88118455A TW434846B TW 434846 B TW434846 B TW 434846B TW 088118455 A TW088118455 A TW 088118455A TW 88118455 A TW88118455 A TW 88118455A TW 434846 B TW434846 B TW 434846B
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TW
Taiwan
Prior art keywords
mold
package
lower mold
prevent
cavity
Prior art date
Application number
TW088118455A
Other languages
Chinese (zh)
Inventor
Ku-Hong Lee
Eun-Dong Kim
Tae-Keun Lee
Original Assignee
Hyundai Electronics Ind
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Publication date
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Publication of TW434846B publication Critical patent/TW434846B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/14—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
    • B29C45/14639—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
    • B29C45/14655—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29C—SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00—Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/17—Component parts, details or accessories; Auxiliary operations
    • B29C45/40—Removing or ejecting moulded articles
    • B29C45/4005—Ejector constructions; Ejector operating mechanisms
    • B29C45/401—Ejector pin constructions or mountings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields

Abstract

The present invention discloses a mold die for semiconductor package. An upper die 1 and a lower die 2 are assembled and a package 3 is disposed in a cavity formed inside the assembly of both upper and lower dies. After the package 3 is encapsulated by flowing a molding compound into the cavity, the package 3 stuck on the lower die 2 is ejected by moving upwardly eject pins 4 positioned at a surface of the lower die 2. There is formed a rugged portion 21 or an anti-sticking plate 22 on the surface of the lower die so as to prevent the generation of static electricity caused by sticking the package 3 on the surface of the lower die 2 during ejection.

Description

43484 β 五、發明說明（i) 《發明之範圍》 本發明係關於-種半導體封裝用模具，尤其是關於一 種在鑄造過程完成後取出封裝時能夠抑制產生靜電 (static electricity)的模具 〇 《發明之背景》 —般的封裝，例如球格陣列封震，係為基板上粘 半導體晶月，而以金屬導線連接半導體晶月的接合焊 與基板的構造。完成品整體以封止劑密封，而安裝於‘ 於有焊球自封止劑露出的基板下之球形區上。 、〜现 此種構造的封裝在鑄造時，係在由上模與下模組入 形成的空腔内安置半導體晶片與基板，並注入封止二* 腔内而鑄造半導體晶月與基板。 二 、第1圖表示傳統的模具，該模具係由上模丨與下 構成。上、下模1、2組合後就在盆内邱裉士、 二 3用的空腔。 交沈在，、内杨成了安置封裝體 另一方面，空腔内注入封止劑而鑄好封裝 固著於空腔表面的封裝體3,在下模降 的取出用銷針4。 升降 然而，取出用銷針4 一方面上昇，一方面從下模2 裝體3時，即瞬間的發生靜電而致破壞構成於 篮日日片上的電路，而造成問題。 τ 《發明之總論》 因此本發明的目的在提供一種半導體封裝 1 能免除封裝體固著於下模表面’而在封裝體取出時得以;方43484 β V. Description of the invention (i) "Scope of the invention" The present invention relates to a mold for semiconductor packaging, and more particularly to a mold capable of suppressing the generation of static electricity when the package is taken out after the casting process is completed. "Background" — general packaging, such as ball grid array vibration isolation, is a semiconductor wafer bonded on the substrate, and metal wires to connect the semiconductor wafer and the bonding structure of the substrate. The finished product is sealed with a sealant as a whole, and is mounted on a spherical area under the substrate where the solder ball self-sealing agent is exposed. When the package of this structure is cast, the semiconductor wafer and the substrate are placed in a cavity formed by the upper mold and the lower mold, and the semiconductor wafer and the substrate are cast by being injected into the cavity of the second seal. 2. Figure 1 shows the traditional mold, which is composed of upper mold and lower mold. After the upper and lower molds 1 and 2 are combined, they are in the cavity of Qiu Shishi and Er 3 in the basin. In the sinking, the inner yang becomes the housing for the package. On the other hand, the sealant is injected into the cavity to cast the package. The package 3 fixed to the surface of the cavity is taken out by the lower pin 4. Lifting However, on the one hand, the removal pin 4 is raised, and on the other hand, when it is mounted from the lower mold 2 to the body 3, static electricity is generated instantaneously, which destroys the circuit formed on the basket and sunscreen, causing problems. τ "Summary of Invention" Therefore, the object of the present invention is to provide a semiconductor package 1 which can dispense with the fixing of the package to the surface of the lower mold 'and can be obtained when the package is taken out;

第5頁 五、發明說明（2) 止靜電的發生。 了達成上述目的，本發明模具的構成如下： 合後配置封裝體於其内部所形成的 = ;止劑於空腔内而鐸造好封裝體後，為了取出固著广主入 表面的封裝體’配置於下槿沾叙±斯山u印固者於下模 ^ ^ M ^ 於下模的數支取出用銷針上昇π $ & :裝體。4 了防止取出時發生靜電，在下模表面：而取出 J :而減少其與封裝體的接觸面積。或亦可：，成凹 者以紙或鋼板等防止固著板。、 下模表面附 依照上揭本發明的構成，在下模表 以防止固著板，即可防止由於取出用 凹凸，或附 出封裝時靜電的發生。 針從下楔表面取 《圖示之簡單說明》 第1圖為傳統模具的斷面圖； =為本發明第i實施例的模具 ， 《 貫轭例的模具斷面圖. 《圖不中元件名稱與符號對照》 圏， 1 :上模 2 :下模 3 :封裝體 ' 4 :取出用銷針 21 :凹凸 2 2 :防止固著板 贅《較佳具體實施例之詳細描 、貫施例1 )Page 5 5. Description of the invention (2) Prevent the occurrence of static electricity. In order to achieve the above object, the structure of the mold of the present invention is as follows: After forming the package, the package is formed in the interior of the mold =; the stopper is in the cavity and the package is completed, in order to remove the package fixed to the wide main surface. 'Arranged in the lower hibiscus ± Sishan u printed solid in the lower mold ^ ^ M ^ The number of pins removed in the lower mold rose π $ &: body. 4 to prevent the occurrence of static electricity when taking out, on the surface of the lower mold: and take out J: and reduce the contact area with the package. Or you can use a paper or steel plate to prevent the fixing plate from forming recesses. The surface of the lower mold According to the structure of the invention disclosed above, the lower mold table is used to prevent the fixing plate, which can prevent the occurrence of static electricity due to the unevenness for taking out or attaching the package. The needle takes the "simple description of the diagram" from the surface of the lower wedge. Figure 1 is a cross-sectional view of a conventional mold; = This is the mold of the i-th embodiment of the present invention, "The cross-sectional view of the mold through the yoke. Comparison of names and symbols 符号, 1: upper mold 2: lower mold 3: package body 4: pin for taking out 21: unevenness 2 2: prevention of fixing plate "detailed description and implementation of preferred embodiments" 1 )

43484b43484b

第2圖為表示本發明實施例i的靜電防止鑄造模具的斷 面，。如圖所示，該模具係由上模i與下模2所構成。上、 下模2經組合後其内部乃形成安置封裝體3用的空腔。 下模2配置有數支可昇降的取出用銷針4，用以取出固基 於其表面的封裝體3〇 ^ 以取出用鎖針4從下模2表面取出封裝體3時，為了 ^靜電的發生，在下模2表面形成凹凸21，或施以合成 月曰塗佈，例如聚四氟乙烯塗佈等下模2的表面處理。凹 1的功能在減少封裝體3與下模2表面間的接觸面積，Fig. 2 is a cross-section of an antistatic casting mold according to Example i of the present invention. As shown in the figure, the mold is composed of an upper mold i and a lower mold 2. After the upper and lower molds 2 are combined, the interior thereof forms a cavity for housing the package body 3. The lower mold 2 is provided with a plurality of lifting pins 4 for removing the package body 3 based on the surface thereof. The locking pin 4 is used for removing the package body 3 from the surface of the lower mold 2 to prevent the occurrence of static electricity. , Forming irregularities 21 on the surface of the lower mold 2, or applying a synthetic coating, such as polytetrafluoroethylene coating, on the surface of the lower mold 2. The function of the recess 1 is to reduce the contact area between the package body 3 and the surface of the lower mold 2,

封裝體3固著於下模2。聚四氟乙烯的塗佈可抑下 面靜電的發生。 供表 (實施例2 ) 第3圖表示本發明實施例2的模具。如圖所示，在 2表面上附有防止固著板22 ^該板22的材質，固然應模 夠忍受鑄造作業上需要的高溫及高壓，例如由紙或〜金& 製成，但在本實施例中係使用銅板。亦即防止固著板Μ的 作用乃顧名思義，在鑄造時防止封裝體3固著於 1 面。 、「表The package body 3 is fixed to the lower mold 2. Teflon coating can suppress the occurrence of static electricity below. Table (Embodiment 2) Fig. 3 shows a mold according to Embodiment 2 of the present invention. As shown in the figure, the 2 surface is attached with a fixing plate 22 ^ The material of the plate 22, although the mold should be able to withstand the high temperature and pressure required for casting operations, such as made of paper or ~ gold & In this embodiment, a copper plate is used. That is, the role of preventing the fixing plate M is as the name implies, and it prevents the package 3 from being fixed to one side during casting. ,"table

兹比較前揭實施例1、2與傳統模具在封裝取 發生的靜電，獲得下表的結果。 不The static electricity generated in the packages of the first and second embodiments and the conventional molds are compared, and the results in the following table are obtained. Do not

五 '發明說明（4) 項目丨傳統模具 —--h〜〜 面 丨實驗 I--- 下模狀態I 光 卜一一 丁一〜 丨 #11 、725 丨靜電 1—^ _ 1電壓 丨則 、74〇 1 (V) 1—1~^ _ _ 1 #3 | -8〇〇 如上表 非常高的靜 以表面處理 顯著減低靜 另一方 降低取出用 而如過度降 所限制。由 最適當的昇 如以上 固著板22， 以取出周銷 I 表面處理 I防止固著板丨 +---i------ί ^丁---1 |凹凸|塗佈聚四|紙I鋼板I | I氟乙烯 I j | —I----1----- —I— — ----1 |+6 | +185 1 +10 | +15 | ——I----1— I— — -|----1Five 'invention description (4) Item 丨 traditional mold --- h ~ ~ surface 丨 experiment I --- lower mold state I light Bu one one small one ~ 丨 # 11 725 丨 electrostatic 1- ^ _ 1 voltage 丨 then , 74〇1 (V) 1—1 ~ ^ _ _ 1 # 3 | -8〇〇 As shown in the table above, the very high static surface treatment significantly reduces the quietness of the other side to reduce the use of the extraction as limited by excessive reduction. The most suitable lifting plate 22 is as above to take out the peripheral pins I. Surface treatment I prevent the fixing plate 丨 + --- i ------ ί ^ 丁 --- 1 | | Paper I steel sheet I | Ifluoroethylene I j | —I ---- 1 ----- —I— — ---- 1 | +6 | +185 1 +10 | +15 | ——I- --- 1— I— —-| ---- 1

l+lll +K4 I +18 I +14 I --1----1------1 — —]----l + lll + K4 I +18 I +14 I --1 ---- 1 ------ 1 — —] ----

| +13| +148 I +12 [ +11 I 所示，傳統模具的下模2在取出封裝之際發生 電電壓。但如依本發明的方法在下模2表面施 ’或附裝防止固著板22 ’則與傳統者比較，可 電電壓。 面’在實施為了獲得如上表數據的實驗時，如 銷針的昇降速度，可獲得減少靜電的缺 ，昇降速度，則因拉長鑄造過程時間，故應； 酌予比較成形時間與靜電減少率，而 ϊ 模2表面形成凹凸21，或配置防止 了免除鑄造時封裝體3固著於 針4取出封裝體3時封事體3::，表面。由是 πτ裒骽0不致於固著於下模2| +13 | +148 I +12 [+11 I As shown, the lower mold 2 of the conventional mold generates electrical voltage when the package is taken out. However, if the method of the present invention is applied to the surface of the lower mold 2 or the fixing plate 22 is attached, the voltage can be compared with the conventional one. In the experiment to obtain the data in the above table, if the pin's lifting speed can reduce the lack of static electricity, the lifting speed will lengthen the casting process time, so the molding time and the static reduction rate should be compared as appropriate. The surface of the mold 2 is formed with unevenness 21, or the configuration prevents the sealing body 3 from being fixed to the needle 4 during casting and the sealing body 3 :: when the casting body 3 is removed. Because πτ 裒 骽 0 does not stick to the lower mold 2

第8頁 五、發明說明（5) 表面，因而可防止靜電的發生。由是半導體晶片上的電路 亦不致於遭受靜電的破壞。 綜上所述，僅為本發明之較佳實施例，並非用來限定 本發明實施之範圍。即凡依本發明申請專利範圍所做之同 等變更與修飾，應皆為本發明專利範圍所涵蓋。Page 8 5. Description of the invention (5) The surface can prevent the occurrence of static electricity. Because the circuit on the semiconductor wafer is not damaged by static electricity. In summary, these are only preferred embodiments of the present invention and are not intended to limit the scope of implementation of the present invention. That is, all equivalent changes and modifications made in accordance with the scope of patent application for the present invention shall be covered by the scope of patent for the invention.

第9頁Page 9

Claims (1)

434$4 六 、申請專利範圍 —種+導體封裝用 —上模與一下描 罵具，包括： 裝體，·及 下模’兩者紐合形，^ 次 σ也成一空腔用以配置該封 能夠昇降的數支取 模表面取出配置於空^針，配置於該下模表面用以 …了防止以該 ^内的已完成封裝體， 総二 在°=亥下模表面形成^ 下模表面取出封裝體時發 觸面積的凹凸。 以減少封裝與下模表面間接 2· -種丰導體封裂用模 裝體；及 .一…_ 能夠昇降的數支取出用銷針 從該下模表面取出配置於空腔内的已完成===表面用以 為了防止以該取出用鎖針從 =、规 -上模與-下模，兩者組合=. 及 圯成—空腔用以配置該封 厂仍Α叫π山亂罝於空腔 、叫，丨j a 為了防止以該取出用銷針從下模體， 生靜電，在該下模表面塗佈可抑制骖f ^取出封裝體時發 生3如申請專利範圍第2項之抑丰\發生靜電的合成樹脂。 —，叫狀* U ; 〇 種半導體封裝用模具，包括： 模與一下模，兩者钽人 °形成-空腔甩以配置該封 所述合成樹脂^ f質為聚四氟乙烯。裝用杈具，其中 4. 一t μ ^ — 一上 裝體，及 能夠昇降的數支取出用銷針，配置於該描 從該下模表面取出配置於空腔内的已完成封、表面用以 為了防止以該取出用銷針從下模 f粗， 生靜電’ ★該下模表面附著-能防止該封裝體= :434 $ 4 6. Scope of patent application—species + conductor package—the upper mold and the following description tool, including: the body, the lower mold and the 'mold', and ^ times σ also forms a cavity to configure the seal Several lifting mold surfaces that can be raised and lowered are taken out and arranged in the empty needle, and arranged on the surface of the lower mold to prevent the completed package within the frame, and the second mold surface is formed at the angle of the lower mold. The unevenness of the contact area during the package. In order to reduce the indirection between the package and the surface of the lower mold 2-a kind of mold assembly for sealing the conductor; and ... a ..._ Several lifting pins that can be raised and lowered are taken out from the surface of the lower mold and completed in the cavity = == The surface is used to prevent the removal of the lock pin from the =, the gauge-the upper mold and the-the lower mold, the combination of the two =. The cavity is called ja. In order to prevent the static electricity from being generated from the lower mold body with the removal pin, coating on the surface of the lower mold can prevent 骖 f ^ from occurring when the package is removed. Feng \ A synthetic resin that generates static electricity. —, Called shape * U; 〇 Semiconductor packaging molds, including: mold and lower mold, both tantalum are formed-cavity is shaken to configure the package The synthetic resin ^ f is polytetrafluoroethylene. Mounting forks, of which 4. a t μ ^ — an upper body, and a number of lifting pins that can be raised and lowered, arranged on the trace to take out the completed seal and surface arranged in the cavity from the surface of the lower mold In order to prevent the removal of the pin from the lower mold f with the removal pin, static electricity is generated. ★ The surface of the lower mold is adhered-which can prevent the package body =: 六、申請專利範圍 表面的防止固著板。 5. 如申請專利範圍第4項之半導體封裝用模具，其中 所述防止固著板的材質為低。 6. 如申請專利範圍第4項之半導體封裝用模具，其中 所述防止固著板的材質為金屬。 7. 如申請專利範圍第6項之半導體封裝用模具，其中 所述金屬的材質為銅。Sixth, the scope of patent application The surface of the anti-fixation plate. 5. The mold for a semiconductor package according to item 4 of the patent application, wherein the material for preventing the fixing plate is low. 6. The mold for semiconductor packaging according to item 4 of the patent application, wherein the material of the anti-sticking plate is metal. 7. The mold for semiconductor packaging according to item 6 of the patent application, wherein the material of the metal is copper. 第11頁Page 11
TW088118455A 1998-10-28 1999-10-26 Mold die for semiconductor package TW434846B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980045447A KR100324928B1 (en) 1998-10-28 1998-10-28 Antistatic Structure of Mold for Semiconductor Package

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Publication Number Publication Date
TW434846B true TW434846B (en) 2001-05-16

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KR100400828B1 (en) * 1999-08-30 2003-10-08 앰코 테크놀로지 코리아 주식회사 mold for semiconductor package
KR100559512B1 (en) * 2000-07-08 2006-03-10 앰코 테크놀로지 코리아 주식회사 Circuit board and mold for semiconductor package
JP3859457B2 (en) 2001-03-27 2006-12-20 沖電気工業株式会社 Manufacturing method of semiconductor device
TW502412B (en) * 2001-10-12 2002-09-11 Advanced Semiconductor Eng Packaging mold with electrostatic discharge protection
CN1314108C (en) * 2002-06-28 2007-05-02 矽品精密工业股份有限公司 Semiconductor chip carrier, semiconductor package component and semiconductor package method
CN100477137C (en) * 2002-08-26 2009-04-08 日月光半导体制造股份有限公司 Encapsulation mould with the static discharge protection
JP5903920B2 (en) 2012-02-16 2016-04-13 富士通株式会社 Semiconductor device manufacturing method and electronic device manufacturing method
KR20160066206A (en) * 2014-12-02 2016-06-10 세메스 주식회사 Apparatus for molding a substrate

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JPH08309803A (en) * 1995-05-15 1996-11-26 Towa Kk Resin forming mold
JPH10242343A (en) * 1997-02-26 1998-09-11 Hitachi Ltd Semiconductor device and its manufacture
JPH10272655A (en) * 1997-03-31 1998-10-13 Nec Corp Resin sealing mold

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