CN1314108C - Semiconductor chip carrier, semiconductor package component and semiconductor package method - Google Patents
Semiconductor chip carrier, semiconductor package component and semiconductor package method Download PDFInfo
- Publication number
- CN1314108C CN1314108C CNB021231974A CN02123197A CN1314108C CN 1314108 C CN1314108 C CN 1314108C CN B021231974 A CNB021231974 A CN B021231974A CN 02123197 A CN02123197 A CN 02123197A CN 1314108 C CN1314108 C CN 1314108C
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- Prior art keywords
- semiconductor chip
- semiconductor
- chip carrier
- base material
- earthing member
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention relates to a bearing piece for a semiconductor chip, a semiconductor packaging piece and a semiconductor packaging method. At least one earthing piece is formed in a position corresponding to an ejection position of a thimble of a packaging mould on the surface of a land surface of the packaging mould; the bearing piece for a semiconductor chip moves away from the packaging mould at last in a demoulding operation; a large amount of static electricity generated on the surface of a making piece of semiconductor package is released to outside through the earthing piece in a moulding operation and a demoulding operation; the static electricity does not remain in a chip, an electrical connection piece or an electric conduction track line of the making piece of semiconductor packaging; a finished product of the packaging piece does not have the problems of electric leakage and the damaged chip, and the excellent rate of the products is efficiently enhanced.
Description
Technical field
The invention relates to a kind of semiconductor chip carrier, semiconductor package part and method for packaging semiconductor, particularly about a kind of with in molding operation and the stripping operation, being contained in a large amount of static that produced on the surface of product at semiconductor package discharges to the external world, and can not residue in semiconductor chip carrier, semiconductor package part and the method for packaging semiconductor of this semiconductor packages part inside.
Background technology
For adapting to the requirement of electronic product to conductivity and processing speed, semiconductor package part (Semiconductor Packages) should have higher input/outbound port (I/O Connections), thereby, utilize into soldered ball (Solder Balls) that the array mode lays as the electrical medium that connects of lotus root of semiconductor chip and external device (External Devices), (Ball Grid Array, BGA) semiconductor package part is into one of main product with ball grid array that high input/outbound port is provided.
Generally speaking, as shown in Figure 8, this kind ball grid array (BGA) semiconductor package 1 is to comprise having first surface and chip bearing member (ChipCarrier) 10 to second surface that should first surface basically, be arranged in the semiconductor chip 40 on the first surface of this chip bearing member 10, the electric connection part 50 that this semiconductor chip 40 and this chip bearing member 10 are electrically connected as plain conductor (MetallicBonding Wires), and as this semiconductor chip 40 of the formed coating of potting compounds such as epoxy resin (Molding Compound) and the packing colloid (Encapsulant or PackageBody) 70 of this electric connection part 50 on the first surface of this chip bearing member 10, and be arranged in this chip bearing member 10 and be not coated with on the second surface of packing colloid, the soldered ball 80 of the medium that connects as this semiconductor chip 40 and the electrical lotus root of external device.
Wherein, this chip bearing member 10 normally comprise by for example dibutene (: Bismaleimide Triazine:BT) material such as resin constitutes and has first surface and a base material 11 to second surface that should first surface; be laid on the first surface of this base material 11 conductive trace (Conductive Traces) 12 in order to electrically connect with this semiconductor chip 40; be laid on the second surface of this base material 11; in order to connect the solder ball pad (Ball Pads) 14 of establishing this soldered ball 80; the through hole (Via) 13 that this conductive trace 12 and this solder ball pad 14 are electrically connected; be located on the first surface of this base material 11; establish brilliant pad (DiePads) 16 of putting of this semiconductor chip 40 in order to connect; and so that this conductive trace 12 is laid on the first surface and second surface of this base material 11 with the part that this semiconductor chip 40 electrically connects with this solder ball pad 14 to the mode that exposes outside; in order to guarantee that 12 of this conductive traces can not produce electrical short circuit because of contacting with each other, that protects simultaneously that this conductive trace 12 avoids the influence of extraneous adverse factor refuses welding flux layer (SolderMask) 15.
The method for packing of above-mentioned ball grid array (BGA) semiconductor package 1 generally comprises the following steps:
Preparation one is chip bearing member as constituted above;
Put brilliant operation (Die Bonding), the brilliant pad of putting on the first surface of this chip bearing member connects and establishes at least one semiconductor chip;
To electrically connect part this semiconductor chip and this chip bearing member are electrically connected;
Carry out molding operation (Molding Process), coat this semiconductor chip and the packing colloid of this electric connection part on the first surface of this chip bearing member to form;
Carry out stripping operation, eject the semiconductor package of finishing mold pressing and be contained in product by being located at thimble (Eject Pin) on the encapsulating mould;
Plant ball (Ball Planting) operation, soldered ball is planted respectively on the second surface that is connected to this chip bearing member on the corresponding solder ball pad; And
Cut single job (Singulation), to form single semiconductor package part manufactured goods.
Above-mentioned molding operation and stripping operation be common must to be selected to the encapsulating mould of being invented in the 5th, 450, No. 283 United States Patent (USP)s shown in accompanying drawing 4A 100.This existing encapsulating mould 100 is by the up and down patrix (Top Mold) 110 and 120 formations of counterdie (Bottom Mold) of matched moulds.Wherein, be slidingly equipped with the many thimbles 111 that have as resilient bias such as helical spring (BiasMeans) 112 on this patrix 110, also be slidingly equipped with the many thimbles 121 that have as resilient bias such as helical spring 122 on this counterdie 120 equally.Simultaneously, be formed with die cavity (Cavity) 113 on the land area of this patrix 110, then be formed with keeper (Pilot Pin) 123 on the land area of this counterdie 120 in order to the positioning chip bearing part.
Accompanying drawing 4A is the schematic flow sheet of representing when using this existing encapsulating mould 100 to carry out above-mentioned molding operation and stripping operation to accompanying drawing 4D.Wherein, finished to put and brilliant be contained in product 1A with the semiconductor package that electrically connects and be flat on the land area of this counterdie 120, and be with after being formed on the land area that mode on the keeper 123 on the land area that location hole (Pilot Hole) 18 on the chip bearing member 10 is socketed on this counterdie 120 is positioned at this counterdie 120 in advance, be that matched moulds carries out molding operation, coat semiconductor chip and electrically connect the packing colloid 70 of part on the first surface of this chip bearing member 10 to form, shown in accompanying drawing 4B.
Then carry out stripping operation, make the semiconductor package of finishing mold pressing be contained in product 1A and deviate from by this encapsulating mould 100.This stripping operation is shown in accompanying drawing 4C, move on this patrix 110 of Schilling, when making the resilient bias 112 of this patrix 110 borrow the elastic recovery effect that the thimble 111 of this patrix 110 is stayed original position, this semiconductor package of having finished mold pressing can be contained in product 1A and eject die cavity 113 on this patrix 110, and make this semiconductor package be contained in product 1A to be stranded on the land area of this counterdie 120.
At this moment, make this counterdie 120 continue to be displaced downwardly to terminal point again, shown in accompanying drawing 4D, make the bias effect of the resilient bias 122 on these counterdies 120 of thimble 121 opposing on this counterdie 120 and the land area upper process of this counterdie 120 certainly, and the semiconductor package that oneself finishes mold pressing with this simultaneously is contained in the land area that product 1A ejects this counterdie 120, makes this semiconductor package of having finished mold pressing be contained in product 1A and gets and shift out this encapsulating mould 100 smoothly.
Yet, in above-mentioned molding operation, the packaging plastic phantom that injects the die cavity 113 of this encapsulating mould 100 fail to be convened for lack of a quorum because of with the land area that places this counterdie 120 on chip bearing member 10 lip-deeply refuse welding flux layer 15 frictions and produce a large amount of static (Electrical Static Discharge).Similarly in above-mentioned stripping operation, also can be contained in the moment that product 1A ejects this encapsulating mould 100, be contained in the static that produces huge amount on the surface of product 1A in this semiconductor package at the semiconductor package that will finish mold pressing.Because this chip bearing member that this semiconductor package of having finished mold pressing is contained in that 120 of patrix 110, the counterdies of product 1A and this encapsulating mould 100 contact with each other 10 is lip-deep refuses welding flux layer 15 and packing colloid 70 all belongs to nonconducting megohmite insulant, so above-mentioned a large amount of static can't be conducted on this encapsulating mould 100, discharge to the external world via this encapsulating mould 100 again.Thereby this static residues in semiconductor package then and is contained on chip, electric connection part or the conductive trace of product 1A, makes the subject to severe risks of damage of packaging part finished product, and causes high electric leakage ratio, causes the product fraction defective can not to be in any more.
In view of this, United States Patent (USP) the 6th, 214 has been invented just like accompanying drawing 5 to the antistatic shown in the accompanying drawing 7 residual encapsulating mould and chip bearing member for No. 645.Wherein, first embodiment of the residual chip bearing member of this antistatic is that the land area that is chip bearing member 10 and this counterdie 120 connects and forms one on the second surface of putting and expose to and refuse outside the welding flux layer 15, in order to metal coupling 20 as earthing member (Grounding Means), as shown in Figure 5, when carrying out molding operation, this metal coupling 20 must electrically connect with the land area of this counterdie 120, so that static is discharged to the external world by this counterdie 120 via this metal coupling 20.
Second embodiment of the residual chip bearing member of above-mentioned antistatic forms a metal level 23 as earthing member on the inner wall surface of the location hole 18 on this chip bearing member 10, as forming this metal level 23 in existing modes such as plating, as shown in Figure 6, when carrying out molding operation, metal level 23 on the inner wall surface of this location hole 18 must electrically connect with the keeper 123 on the land area of this counterdie 120, so that static is discharged to the external world by this counterdie 120 via this metal level 23.
The 3rd embodiment of the residual encapsulating mould of above-mentioned antistatic is convexly equipped with one in order to the protrusion 35 as earthing member on the Jiao Dao (Runner) 32 that is formed on this patrix 110, as shown in Figure 7, when carrying out molding operation, this protrusion 35 must electrically connect with the metal-to-metal adhesive road 17 that is formed on this chip bearing member 10, so that static is discharged to the external world by this patrix 110 via this protrusion 35.
In reality test mold pressing and stripping operation, the static value that the surface produced that is contained in product 1A at this semiconductor package can be found, by the residual encapsulating mould of above-mentioned antistatic and the use of chip bearing member, make finish to molding operation till, packaging plastic phantom stream really can discharge to the external world by this encapsulating mould 100 via this metal coupling 20 as earthing member, metal level 23 and protrusion 35 with the chip bearing member 10 lip-deep static of refusing welding flux layer 15 frictions and producing.
But in stripping operation, to move on this patrix 110 so that the semiconductor package that oneself finish mold pressing this is contained in product 1A when being ejected die cavity 113 on this patrix 110, shown in accompanying drawing 4C, the protrusion 35 that is convexly equipped with on the patrix 110 owing to the embodiment of the residual encapsulating mould of above-mentioned antistatic broken away from this chip bearing member 10 on the state that electrically connects of metal-to-metal adhesive road 17 lose grounding function, cause follow-uply this semiconductor package of having finished mold pressing is contained in the static that is produced when product 1A ejects this counterdie 120 can't conducts on this encapsulating mould 100 again and discharging to the external world, and residue in the chip that this semiconductor package is contained in product 1A via this encapsulating mould 100, electrically connect on part or the conductive trace.Simultaneously, because the metal-to-metal adhesive road shape that chip bearing member had of different size or form or position be difference to some extent also, so often must at the preparation of different chip bearing members have different protrusions constitute with patrix, increase purchasing and management cost of mould, and when carrying out molding operation, must change encapsulating mould with the change of product size, when having increased worker and reduce production efficiency.
In addition, the metal coupling 20 of residual chip bearing member first embodiment of above-mentioned antistatic until moving on this patrix 110 so that this semiconductor package of having finished mold pressing is contained in product 1A is ejected till the die cavity 113 on this patrix 110, though still the land area with this counterdie 120 electrically connects, but when this counterdie 120 moves down the thimble 121 that makes on this counterdie 120 when this semiconductor package of having finished mold pressing is contained in product 1A top from the land area of this counterdie 120, shown in accompanying drawing 4D, this metal coupling 20 promptly breaks away from the state that electrically connects with the land area of this counterdie 120 and loses grounding function, cause with this semiconductor package of having finished mold pressing be contained in product 1A when ejecting this counterdie 120 this semiconductor package that results from be contained in the lip-deep a large amount of static of product 1A and can't conduct on this encapsulating mould 100 and discharge to the external world via this encapsulating mould 100 again, and residue in the chip that this semiconductor package is contained in product 1A, electrically connect on part or the conductive trace.Simultaneously, because this embodiment must be added to the operation that forms on the conductive trace 12 of chip bearing member 10 as the metal coupling 20 of earthing member, increased the complexity and the manufacturing cost of overall package method.
In like manner, metal level 23 as earthing member on the inner wall surface that is formed at this location hole 18 of residual chip bearing member second embodiment of above-mentioned antistatic moves on this patrix 110, so that being contained in product 1A, this semiconductor package of having finished mold pressing is ejected till the die cavity 113 on this patrix 110, also still electrically connect with the keeper 123 of this counterdie 120, have only when this counterdie 120 and move down the thimble 121 that makes on this counterdie 120 when this semiconductor package of having finished mold pressing is contained in product 1A top from the land area of this counterdie 120, shown in accompanying drawing 4D, this metal level 23 promptly breaks away from the state that the keeper 123 with this counterdie 120 electrically connects and loses grounding function, cause with this semiconductor package of having finished mold pressing be contained in product 1A when ejecting this counterdie 120 this semiconductor package that results from be contained in the lip-deep a large amount of static of product 1A and can't conduct on this encapsulating mould 100 and discharge to the external world via this encapsulating mould 100 again, and residue in the chip that this semiconductor package is contained in product 1A, electrically connect on part or the conductive trace.Simultaneously, the positioning accuracy of location hole generally is to be made as for example 1.5 ± 0.05mm traditionally, so that the position deviation amount of packing colloid off-center point must be controlled in the scope of 0.05mm.On the inner wall surface of the location hole 18 on this chip bearing member 10, as form in existing modes such as plating this in order to metal level 23 as earthing member after, its positioning accuracy can become 1.5 ± 0.1mm, causes the position deviation amount of packing colloid also to become big thereupon, makes the rising of product fraction defective.
Summary of the invention
The object of the present invention is to provide a kind of can effectively the elimination in molding operation and stripping operation to be contained in a large amount of static that produced on the product surface in semiconductor package, make it can not to residue in chip that this semiconductor package is contained in product, electrically connect semiconductor chip carrier, semiconductor package part and method for packaging semiconductor on part or the conductive trace.
Another object of the present invention is to provide a kind of and needn't on the surface of chip bearing member, form metal coupling, and be able to effectively eliminate in molding operation and stripping operation, be contained in a large amount of static that produced on the product surface in semiconductor package, make can not residue in this semiconductor package be contained in product chip, electrically connect semiconductor chip carrier, semiconductor package part and method for packaging semiconductor on part or the conductive trace.
A further object of the present invention is to provide a kind of needn't form metal level on the location hole inner wall surface on the chip bearing member, in molding operation and stripping operation, be contained in a large amount of static that produced on the product surface and can effectively eliminate in semiconductor package, make can not residue in this semiconductor package be contained in product chip, electrically connect semiconductor chip carrier, semiconductor package part and method for packaging semiconductor on part or the conductive trace.
Another purpose of the present invention is to provide a kind of needn't be convexly equipped with protrusion on the Jiao Dao of encapsulating mould, in molding operation and stripping operation, be contained in a large amount of static that produced on the product surface and can effectively eliminate in semiconductor package, make can not residue in this semiconductor package be contained in product chip, electrically connect semiconductor chip carrier, semiconductor package part and method for packaging semiconductor on part or the conductive trace.
For reaching above-mentioned and other purpose, semiconductor chip carrier provided by the present invention is to have:
First surface;
Corresponding to this first surface and be the second surface that in stripping operation, leaves the land area of encapsulating mould at last; And
At least one earthing member that ejects the position that is formed on this second surface corresponding to the thimble of encapsulating mould.
Semiconductor package part of the present invention comprises:
Have first surface and chip bearing member corresponding to the second surface of this first surface;
Be arranged in the semiconductor chip on the first surface of this chip bearing member;
The electric connection part that this semiconductor chip and this chip bearing member are electrically connected as plain conductor;
To electrically connect the packing colloid of part on the first surface of this chip bearing member as this semiconductor chip of the formed coating of potting compounds such as epoxy resin and this; And
Be arranged in this chip bearing member and be not coated with on the second surface of packing colloid soldered ball with the medium that connects as this semiconductor chip and the electrical lotus root of external device;
Wherein, to leave on the surface of land area of encapsulating mould the position that ejects corresponding to the thimble of encapsulating mould in stripping operation at last be to be formed with at least one earthing member to this chip bearing member.
Method for packaging semiconductor of the present invention comprises the following steps:
Prepare one and have first surface, corresponding to the second surface of this first surface, and to leave at last in stripping operation on the surface of land area of encapsulating mould corresponding to the position that ejects that is located at the thimble on the encapsulating mould be the chip bearing member that is formed with at least one earthing member;
Put brilliant operation, on the first surface of this chip bearing member, connect and establish at least one semiconductor chip;
To electrically connect part this semiconductor chip and this chip bearing member are electrically connected;
Carry out molding operation, coat this semiconductor chip and the packing colloid of this electric connection part on the first surface of this chip bearing member to form;
Carry out stripping operation, the semiconductor package that the thimble on the encapsulating mould will be finished mold pressing respectively is contained in product and ejects this encapsulating mould;
Plant the ball operation, soldered ball is planted respectively on the second surface that is connected to this chip bearing member on the corresponding solder ball pad; And
Cut single job, to form single semiconductor package part finished product.
So, by the lip-deep earthing member that is formed on this chip bearing member, just can discharge to the external world via encapsulating mould from this earthing member being contained in the static that is produced on the surface of product in semiconductor package in molding operation and the stripping operation effectively, be not contained on chip, electric connection part or the conductive trace of product and can not residue in this semiconductor package, make the packaging part finished product not have electric leakage or the impaired anxiety of chip, and get the production acceptance rate that effectively promotes the packaging part finished product.
Description of drawings
Below further describe characteristics of the present invention and effect with preferable instantiation conjunction with figs..
Accompanying drawing 1A is the upward view of semiconductor chip carrier embodiment of the present invention;
Accompanying drawing 1B is the cutaway view that the 1B-1B line along accompanying drawing 1A is illustrated;
Accompanying drawing 2 is semiconductor package part embodiment of the present invention that the 2-2 line direction along accompanying drawing 1A is illustrated schematic diagrames when cutting single job as yet;
Accompanying drawing 3 is to eject the schematic diagram that the semiconductor package of finishing mold pressing is contained in product by the thimble of encapsulating mould in the mode of the earthing member that peaks at this chip bearing member in stripping operation;
Accompanying drawing 4A is to use to accompanying drawing 4D and has the schematic diagram that encapsulating mould carries out molding operation and stripping operation now;
Accompanying drawing 5 is to have now on the surface of chip bearing member to form one and expose to and refuse outside the welding flux layer, in order to the schematic diagram as the metal coupling of earthing member;
Accompanying drawing 6 is to have on the inner wall surface of the location hole on the chip bearing member schematic diagram that forms in order to as the metal level of earthing member now;
Accompanying drawing 7 is the schematic diagrames that are convexly equipped with on the Jiao Dao that has now in being formed on encapsulating mould in order to as the protrusion of earthing member; And
Accompanying drawing 8 is schematic diagrames of existing ball grid array (BGA) semiconductor package.
Symbol description
1 ball grid array (BGA) semiconductor package 1A semiconductor package is contained in product
10 semiconductor chip carriers, 100 encapsulating moulds
11 base materials, 110 patrixes
111,121 thimbles, 112,122 resilient bias
113 die cavitys, 12 conductive traces
12A ground connection trace 120 counterdies
123 keepers, 13 through holes
13A grounding through hole 14 solder ball pads
15 refuse welding flux layer 16 puts brilliant pad
17 metal-to-metal adhesive roads, 18 location holes
20 metal couplings, 40 semiconductor chips
23 metal levels 50 electrically connect part
32 glue roads, 70 packing colloids
35 protrusions, 80 soldered balls
G earthing member S line of cut
Embodiment
Shown in accompanying drawing 1A and accompanying drawing 1B, semiconductor chip carrier 10A of the present invention is to have: first surface 101; Corresponding to this first surface 101 and be the second surface 102 that in stripping operation, leaves the land area of encapsulating mould at last; And at least one earthing member G that ejects the position that is formed on this second surface 102 corresponding to the thimble of encapsulating mould.
Wherein, this chip bearing member 10A is the formation of existing chip bearing member 10 that can be as shown in Figure 8; comprise by materials such as for example BT resins and making; and have first surface and base material 11 to second surface that should first surface; be laid on the first surface of this base material 11; be used for the conductive trace 12 that electrically connects with semiconductor chip 40; be laid on the second surface of this base material 11 in order to connect the solder ball pad 14 of establishing soldered ball 80; the through hole 13 that this conductive trace 12 and this solder ball pad 14 are electrically connected; be located on the first surface of this base material 11 and establish the brilliant pad 16 of putting of this semiconductor chip 40 in order to connect; so that this conductive trace 12 is laid on the first surface and second surface of this base material 11 with the part that this semiconductor chip 40 electrically connects with this solder ball pad 14 to the mode that exposes outside; in order to guarantee that 12 of this conductive traces can not produce electrical short circuit because of contacting with each other; that protects simultaneously that this conductive trace 12 avoids the influence of extraneous adverse factor refuses welding flux layer 15; and must be when cutting single job for the line of cut S of cutter cutting; form single semiconductor package part finished product, shown in accompanying drawing 1A and accompanying drawing 2.
Simultaneously, shown in accompanying drawing 1A and accompanying drawing 1B, this earthing member G is normally formed by the coating of metals such as for example gold, copper or other electric conducting material to expose to this mode of refusing welding flux layer 15, and is electrically connected to ground connection trace (Grounding Trace) 12A on the first surface 101 of this chip bearing member 10A by grounding through hole (Grounding Via) 13A.This ground connection trace 12A is connected to as the brilliant pad 16 of putting of the earthing member on the first surface 101 of this chip bearing member 10A.
As shown in Figure 2, semiconductor package part of the present invention is to comprise: have chip bearing member 10A as constituted above; Be arranged in the semiconductor chip 40 on the first surface 101 of this chip bearing member 10A; The electric connection part 50 that this semiconductor chip 40 and this chip bearing member 10A are electrically connected as plain conductor; Electrically connect the packing colloid 70 of part 50 on the first surface 101 of this chip bearing member 10A with this semiconductor chip 40 of the formed coating of potting compounds such as epoxy resin with this; And be arranged in this chip bearing member 10A and be not coated with on the second surface 102 of packing colloid 70, with the soldered ball 80 of the medium that connects as this semiconductor chip 40 and the electrical lotus root of external device.
The present invention is to comprise the following steps: in order to form the method for packaging semiconductor of above-mentioned semiconductor package part
Prepare one and have chip bearing member 10A as constituted above;
Put brilliant operation, establish at least one semiconductor chip 40 on the first surface 101 of this chip bearing member 10A, to connect;
To electrically connect part 50 this semiconductor chip 40 and this chip bearing member 10A are electrically connected;
Carry out molding operation, coat this semiconductor chip 40 and the packing colloid 70 of this electric connection part 50 on the first surface 101 of this chip bearing member 10A to form;
Carry out stripping operation, the thimble 111 and 121 on the encapsulating mould 100 is in the mode shown in accompanying drawing 4C and accompanying drawing 4D, and the semiconductor package that will finish mold pressing respectively is contained in the patrix 110 and counterdie 120 that product ejects this encapsulating mould 100;
Plant the ball operation, soldered ball 80 is planted respectively on the second surface 102 that is connected to this chip bearing member 10A on the corresponding solder ball pad 14; And
Cut single job, to form single semiconductor package part finished product.
Wherein, this stripping operation is so that the thimble 121 on the counterdie 120 of the back demoulding peaks at the mode of the earthing member G of this chip bearing member 10A, the semiconductor package of finishing mold pressing is contained in the land area that product ejects this counterdie 120, as shown in Figure 3, so, just till can finishing with molding operation and to stripping operation effectively, be contained in a large amount of static that produced on the surface of product releases to the external world via encapsulating mould 100 from the earthing member G of this chip bearing member 10A and faces in semiconductor package, and can not residue in the chip 40 that this semiconductor package is contained in product, electrically connect on part 50 or the conductive trace, make the packaging part finished product not have electric leakage or the impaired anxiety of chip, and can effectively promote the acceptance rate of packaging part finished product.
Above-mentioned earthing member G also can select to add on the first surface 101 of this chip bearing member 10A the position that ejects corresponding to the thimble 111 of this patrix 110, to strengthen the effect that it eliminates static.
In addition, semiconductor chip carrier of the present invention, semiconductor package part and method for packaging semiconductor are except that applicable to the existing ball grid array (BGA) semiconductor package as shown in Figure 8, also applicable to the semiconductor package part of other pattern, residue in semiconductor package and be contained in problem in the product to solve static.
Simultaneously, owing to needn't on the surface of chip bearing member 10A, form metal coupling, and simplified manufacturing process, reduce the consuming time of encapsulation, and can effectively reduce cost.
Moreover, owing to needn't on the location hole inner wall surface on the chip bearing member 10A, form metal level, and avoided the position deviation quantitative change of packing colloid big, can reduce the product disqualification rate.
In addition, owing to needn't on the Jiao Dao of encapsulating mould, be convexly equipped with protrusion, and be able to needn't prepare and change under the situation of different encapsulating moulds, carry out the mold pressing manufacture process of the semiconductor package part of different types with original encapsulating mould, so can reduce the administrative expenses of packaging cost and facility.
Above-described instantiation; only be in order to illustrate every characteristics of the present invention and effect; but not in order to limit the enforceable scope of the present invention; so do not change or modify breaking away from any equivalence of finishing under the principle that claims of the present invention set forth; for example the conductive coating of this earthing member G is replaced earthing member of other pattern such as metal coupling for example etc., all should be and belong within this patent protection range.
Claims (21)
1. a semiconductor chip carrier is characterized in that, this semiconductor chip carrier has:
First surface;
Corresponding to this first surface and be the second surface that in stripping operation, leaves the land area of encapsulating mould at last; And
At least one earthing member that ejects the position that is formed on this second surface corresponding to the thimble of encapsulating mould.
2. semiconductor chip carrier as claimed in claim 1 is characterized in that it also comprises:
Have first surface and base material to second surface that should first surface;
Be laid on the first surface of this base material conductive trace in order to electrically connect with semiconductor chip;
Be laid on the second surface of this base material in order to connect the solder ball pad of establishing soldered ball;
The through hole that this conductive trace and this solder ball pad are electrically connected;
Be located on the first surface of this base material and establish the brilliant pad of putting of semiconductor chip in order to connect; And
So that the part that this conductive trace and semiconductor chip electrically connect and this solder ball pad are laid in the welding flux layer of refusing on the first surface of this base material and the second surface to the mode that exposes outside.
3. semiconductor chip carrier as claimed in claim 1 is characterized in that, this earthing member is that the coating by electric conducting material is formed.
4. semiconductor chip carrier as claimed in claim 3 is characterized in that, this earthing member is that the coating by gold is formed.
5. semiconductor chip carrier as claimed in claim 2 is characterized in that, this earthing member is to expose to this to refuse welding flux layer.
6. semiconductor chip carrier as claimed in claim 2 is characterized in that, this earthing member is to be electrically connected to ground connection trace on the first surface that is formed on this semiconductor chip carrier by being formed on grounding through hole in this base material.
7. semiconductor package part is characterized in that it comprises:
Have first surface and semiconductor chip carrier corresponding to the second surface of this first surface;
Be arranged in the semiconductor chip on the first surface of this semiconductor chip carrier;
The electric connection part that this semiconductor chip and this semiconductor chip carrier are electrically connected;
Electrically connect the packing colloid of part on the first surface of this semiconductor chip carrier with this semiconductor chip of the formed coating of potting compound and this; And
Be arranged in this semiconductor chip carrier and be not coated with soldered ball on the second surface of packing colloid;
Wherein, this semiconductor chip carrier leaves at last in stripping operation on the surface of land area of encapsulating mould, is to be formed with at least one earthing member corresponding to the position that ejects of the thimble of encapsulating mould.
8. semiconductor package part as claimed in claim 7 is characterized in that, this semiconductor chip carrier also comprises:
Have first surface and base material to second surface that should first surface;
Be laid on the first surface of this base material conductive trace in order to electrically connect with semiconductor chip;
Be laid on the second surface of this base material in order to connect the solder ball pad of establishing soldered ball;
The through hole that this conductive trace and this solder ball pad are electrically connected;
Be located on the first surface of this base material and establish the brilliant pad of putting of semiconductor chip in order to connect; And
So that the part that this conductive trace and semiconductor chip electrically connect and this solder ball pad are laid in the welding flux layer of refusing on the first surface of this base material and the second surface to the mode that exposes outside.
9. semiconductor package part as claimed in claim 7 is characterized in that, this earthing member is that the coating by electric conducting material is formed.
10. semiconductor package part as claimed in claim 9 is characterized in that, this earthing member is that the coating by gold is formed.
11. semiconductor package part as claimed in claim 8 is characterized in that, this earthing member is to expose to this to refuse welding flux layer.
12. semiconductor package part as claimed in claim 8 is characterized in that, this earthing member is to be electrically connected to ground connection trace on the first surface that is formed on this semiconductor chip carrier by being formed on grounding through hole in this base material.
13. a method for packaging semiconductor is characterized in that this method comprises the following steps:
Prepare one and have first surface, corresponding to this first surface and be the second surface that in stripping operation, leaves the land area of encapsulating mould at last, and at least one semiconductor chip carrier that is formed on this second surface corresponding to the earthing member that ejects the position of the thimble of encapsulating mould;
Put brilliant operation, establish at least one semiconductor chip on the first surface of this semiconductor chip carrier, to connect;
To electrically connect part this semiconductor chip and this semiconductor chip carrier are electrically connected;
Carry out molding operation, coat this semiconductor chip and the packing colloid of this electric connection part on the first surface of this semiconductor chip carrier to form;
Carry out stripping operation, the semiconductor package that the thimble on the encapsulating mould will be finished mold pressing respectively is contained in product and ejects this encapsulating mould;
Plant the ball operation, soldered ball is planted respectively on the second surface that is connected to this semiconductor chip carrier; And
Cut single job, to form single semiconductor package part finished product.
14. method for packaging semiconductor as claimed in claim 13 is characterized in that, the semiconductor chip carrier in this method also comprises:
Have first surface and base material to second surface that should first surface;
Be laid on the first surface of this base material conductive trace in order to electrically connect with semiconductor chip;
Be laid on the second surface of this base material in order to connect the solder ball pad of establishing soldered ball;
The through hole that this conductive trace and this solder ball pad are electrically connected;
Be located on the first surface of this base material and establish the brilliant pad of putting of semiconductor chip in order to connect; And
Make part that this conductive trace and semiconductor chip electrically connect and this solder ball pad be laid in the welding flux layer of refusing on the first surface of this base material and the second surface to the mode that exposes outside.
15. method for packaging semiconductor as claimed in claim 13 is characterized in that, this earthing member is that the coating by electric conducting material is formed.
16. method for packaging semiconductor as claimed in claim 15 is characterized in that, this earthing member is that the coating by gold is formed.
17. method for packaging semiconductor as claimed in claim 14 is characterized in that, this earthing member is to expose to this to refuse welding flux layer.
18. method for packaging semiconductor as claimed in claim 14 is characterized in that, this earthing member is to be electrically connected to ground connection trace on the first surface that is formed on this semiconductor chip carrier by being formed on grounding through hole in this base material.
19. semiconductor chip carrier as claimed in claim 1 is characterized in that, it also comprises at least one earthing member that ejects the position that is formed on this first surface corresponding to the thimble of encapsulating mould.
20. semiconductor package part as claimed in claim 7, it is characterized in that the position that ejects corresponding to the thimble of encapsulating mould on the surface of this semiconductor chip carrier non-land area that leaves encapsulating mould at last in stripping operation also is formed with at least one earthing member.
21. method for packaging semiconductor as claimed in claim 13 is characterized in that, this semiconductor chip carrier also comprises at least one earthing member that ejects the position that is formed on this first surface corresponding to the thimble of encapsulating mould.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231974A CN1314108C (en) | 2002-06-28 | 2002-06-28 | Semiconductor chip carrier, semiconductor package component and semiconductor package method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231974A CN1314108C (en) | 2002-06-28 | 2002-06-28 | Semiconductor chip carrier, semiconductor package component and semiconductor package method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1466200A CN1466200A (en) | 2004-01-07 |
| CN1314108C true CN1314108C (en) | 2007-05-02 |
Family
ID=34142312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021231974A Expired - Lifetime CN1314108C (en) | 2002-06-28 | 2002-06-28 | Semiconductor chip carrier, semiconductor package component and semiconductor package method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1314108C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101692433B (en) * | 2009-10-15 | 2012-01-25 | 友达光电股份有限公司 | Plasma etching machine and ejector pin thereof |
| CN102136459B (en) * | 2010-01-25 | 2014-02-26 | 矽品精密工业股份有限公司 | Packaging structure and manufacture method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0685112A (en) * | 1992-08-31 | 1994-03-25 | Nec Corp | Resin sealed type semiconductor device |
| JP2000133666A (en) * | 1998-10-28 | 2000-05-12 | Hyundai Electronics Ind Co Ltd | Molding die for semiconductor package |
| US6214645B1 (en) * | 1998-05-27 | 2001-04-10 | Anam Semiconductor, Inc. | Method of molding ball grid array semiconductor packages |
-
2002
- 2002-06-28 CN CNB021231974A patent/CN1314108C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0685112A (en) * | 1992-08-31 | 1994-03-25 | Nec Corp | Resin sealed type semiconductor device |
| US6214645B1 (en) * | 1998-05-27 | 2001-04-10 | Anam Semiconductor, Inc. | Method of molding ball grid array semiconductor packages |
| JP2000133666A (en) * | 1998-10-28 | 2000-05-12 | Hyundai Electronics Ind Co Ltd | Molding die for semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1466200A (en) | 2004-01-07 |
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