TW434820B - Method for producing self-aligned contact hole - Google Patents

Abstract

The present invention provides a method for producing a self-aligned contact hole on a semiconductor chip. The semiconductor chip comprises a substrate; two adjacent gates installed on the substrate; and a plurality of spacers installed on the periphery of the two gates. The substrate between the two gates is at least formed with a doped region, and the spacers between the two gates are connected to each other and cover the doped region. The method comprises forming a dielectric layer on the surface of the semiconductor chip covering the two gates and the spacers; performing a first etching process to remove the dielectric layer on the doped region to a specified depth to form a hole, the bottom of the hole being formed of a portion of the two gates and a portion of the top portion of the spacers; forming a polysilicon spacer on the inner wall of the hole covering the top regions of the two gates and the spacers; performing a second etching process to downwardly etch the dielectric layer and the spacer between the two gates along the polysilicon spacer in the hole until the surface of the doped region, thereby completing the production of the self-aligned contact hole.

Description

五、發明说明（1) 發明之領域 本發明提供一種自行對車技細 contact hole)的製作方法，尤指」 陆^11“ 體之自行對準接觸洞的製作方法β 機存取記憶 背景說明 在半導體製程中，接觸洞是用來製作積體電路中電連 接各個元件的金屬内連線。在接觸洞的製作方法中，通常 是利用微影（photol i thographic)以及乾蝕刻的方式，直 接於晶片的表面形成複數個垂直孔洞來當作接觸洞β随著 半導體製程中線寬（line width)的缩小，，接觸洞的孔徑也 隨之縮小，目前半導體製程係利用蝕刻製程對不同材料之 間的蚀刻選擇比（etching selectivity)來進行自行對準 接觸（self-aligned contact)蚀刻，以於半導體晶片上形 成接觸洞。 請參考圖一至圖三，圖一至圖三為習知於一乎導體晶 片10上製作自行對準接觸洞3 4的方法的示意圖。半導體晶 片1 0包含有一矽基底1 2，二相鄰閘極2 4設於矽基底1 2表面 之一預定區域，一摻雜區14設於閘極24之間的矽基底12 上，以及一由矽氧物所構成的介電層2 8設於矽基底1 2之上 並覆蓋住二閘極2 4。每一個閘極2 4包含有一由二氧化石夕所V. Description of the invention (1) Field of the invention The present invention provides a method for making self-aligning contact holes on vehicles, especially a method for making self-aligning contact holes of "Lu ^ 11" body. In the semiconductor process, contact holes are used to make metal interconnects that electrically connect various components in integrated circuits. In the method of making contact holes, photolithography and dry etching are usually used to directly A plurality of vertical holes are formed on the surface of the wafer as contact holes. As the line width in the semiconductor process decreases, the hole diameter of the contact hole also decreases. At present, the semiconductor process uses an etching process for different materials. The etching selectivity is used to perform self-aligned contact etching to form a contact hole on a semiconductor wafer. Please refer to FIGS. 1 to 3, which are familiar to a conductor. A schematic diagram of a method for making self-aligned contact holes 34 on the wafer 10. The semiconductor wafer 10 includes a silicon substrate 12 and two adjacent gate electrodes 24 are disposed on silicon. A predetermined region on the surface of the substrate 12, a doped region 14 is provided on the silicon substrate 12 between the gates 24, and a dielectric layer 28 made of silicon oxide is provided on the silicon substrate 12 and Cover the two gates 24. Each gate 2 4 contains one by the dioxide

第5頁 434820 五、發明說明（2) 構成之閘極氡化層16，一摻雜 物層20。此外，每一閘極24表 且每一閘極2 0之垂直側邊上均 謾層20及側壁子22皆由氮化石夕 多晶梦層1 8以及一金屬石夕化 面均覆蓋有一保護層22，而 覆蓋有一側壁子26，其中保 所構成》 I知製作自行對準接觸洞34的方法是先於介電層28之 上塗佈（coating)—層光阻層30，然後進行一黃光 (lithography)製程於光阻層3〇之中形成一圖案32以 接觸洞34的位置與尺寸，如圖二所示。接著利用光阻層3〇 作為硬罩幕（hard mask)’進行一乾蝕刻（dry etcU 製 程，沿著光阻層30中的圖案32垂直向下蝕刻介電層28，直 * L至1Μ夕基底12上的摻雜區14表面’形成一接觸洞34，最後剝 事除（strip)光阻層30，如囷三所示。 在習知的自行對準接觸蝕刻製程中！主要是利用蝕刻 製程對矽氧物與氮化矽之間的蝕刻選擇比來進行自行對準 接觸姓刻’形成接觸洞34。也就是利用調整該蝕刻製程對 介電層？8與側壁子26的蝕刻速率，使得蝕刻製程對介電 28的蝕刻速率大於對側壁子26的蝕刻速率，期使達到只姑 刻介電層28的目的。如圖三所示，由於半導體製程中線寬 ;的縮小，使得閘極24的高度相對性地增加，而且為了降低 後續形成於接觸洞34之中的導電插塞與摻雜區丨4的接觸電 阻，必須增加接觸洞34與摻雜區1 4的接觸面積，所形成的 側壁子28也相對地變薄。因此當製作接觸洞34時，在蚀刻Page 5 434820 V. Description of the invention (2) The gate halide layer 16 and a dopant layer 20 are formed. In addition, each gate 24 surface and each gate 20 on the vertical side of the homogeneous layer 20 and the side wall 22 are covered with a nitride stone polycrystalline dream layer 18 and a metal stone surface is covered with a protection The layer 22 is covered with a side wall 26. The method of making the self-aligned contact hole 34 is to coat a photoresist layer 30 on the dielectric layer 28, and then perform a A lithography process forms a pattern 32 in the photoresist layer 30 to contact the position and size of the hole 34, as shown in FIG. Next, the photoresist layer 30 is used as a hard mask to perform a dry etc (dry etcU process, and the dielectric layer 28 is etched vertically downwards along the pattern 32 in the photoresist layer 30, until the substrate is from 1 μM to 1 μM. A contact hole 34 is formed on the surface of the doped region 14 on 12, and finally the photoresist layer 30 is stripped, as shown in Fig. 3. In the conventional self-aligned contact etching process! The etching process is mainly used. The etching selection ratio between silicon oxide and silicon nitride is used for self-alignment. The contact name is engraved to form the contact hole 34. That is, the etching rate of the dielectric layer? 8 and the sidewall 26 is adjusted by adjusting the etching process, so that The etching rate of the dielectric 28 in the etching process is greater than the etching rate of the sidewalls 26, so as to achieve the purpose of only etching the dielectric layer 28. As shown in FIG. 3, due to the reduction of the line width in the semiconductor process, the gate electrode is reduced. The height of 24 is relatively increased, and in order to reduce the contact resistance between the conductive plug and the doped region 4 formed later in the contact hole 34, the contact area between the contact hole 34 and the doped region 14 must be increased to form The side walls 28 are also relatively thin. When forming the contact hole 34, etching

第6頁 五、發明說明（3) 厚度約在6000-800 0埃（angstrom，Λ )之間的 中，經過長時間的蝕刻，閘極上方的頂保護 2 6會受到破壞，尤其是頂保護層2 2及側壁子 破壞的情形最為嚴重。 這種頂保護層2 2及側壁子2 6被破壞的現 接影響到閘極24的主體結構。例如摻雜多晶 屬矽化物2 0可能會由於與後續所填入接觸洞 的距離縮小，造成用來絕緣阻隔的物質太薄 雜多晶矽層18以及金屬矽‘化物20與填入接觸 質發生漏電或短路的現象。 發明概述 因此本發明之主要目的在提供一種自行 製作方法，以解決上述習知自行對準接觸洞 題〇 本發明提供一種於一半導體晶片上製作 洞的方法。該半導體晶片包含有一基底，二 該基底之上，以及複數個侧壁子設於該二閘 閘極間之基底上至少生成有一摻雜區，而該 壁子係彼此相連且覆蓋於該摻雜區之上。本 先於該半導體晶片表面形成一介電層，覆蓋 介電層2 6過程 層2 2與側壁子 26的接合處遭 象，可能會直 矽層1 8以及金 34之導電物質 ，進而造成摻 洞34之導電物 對準接觸洞的 製作方法的問 自行對準接觸 相鄰間極設於 極周圍。該二 二閘極間之側 發明之方法 於該二閘極以 五、發明說明（4) 及該側壁子之上。然後進行〆第一蝕刻製程’去除該摻雜 區上方之介電層至一預定深度，形成一孔洞，且該孔洞之 底部係由該二閘極及該側壁子之頂部的部分區埤所構成β 接著於該孔洞之内壁形成一多晶發側壁子’復蓋於該二閘 極及該側壁子的頂部區域之上。最後進行一第二蝕刻製 程’沿著該孔洞内之多晶矽側壁子向下蝕刻該二閘極間之 介電層與該側壁子直至該摻雜區表面，完成該自行對準接 觸洞的製程。 / 由於本發明係利用蝕刻製程對該多晶矽側壁子與該氣 |化矽側壁子之間的高蝕刻選擇比來形成該自行對準接觸 洞’可以有效地避免覆蓋於該閘極周圍的該頂保護層於受 到蝕刻製程的破壞。此外，本發明亦可用在〇. 15微米以下 的製程之中，避免覆蓋於該閘極上方的該氮化矽層^到過 度蝕刻，進而確保該閘極與後續形成於該自行對準2 之中的導電插塞電隔離效果。而且本發明並不需於閑極之 間形成側壁子，減少了一道蝕刻製程，使得接觸洞二 得以簡化。 J我径 發明之詳細說明 ’ ?請參考圖四至圖九，圖四至圖九為利用本發明於一 導體晶片40上製作一自行對準接觸洞（!68的)方法示意圖。如 圖四所示，半導體晶片40包含有一矽基^底42，一主動區域Page 6 V. Description of the invention (3) In the thickness of about 6000-800 0 angstroms (angstrom, Λ), after a long time of etching, the top protection 26 above the gate will be damaged, especially the top protection The most severe damage is to the layer 22 and the side walls. The destruction of the top protective layer 22 and the side walls 26 affects the main structure of the gate electrode 24. For example, the doped polycrystalline silicon silicide 20 may reduce the distance from the contact hole filled in later, causing the material used for insulation barrier to be too thin. The heteropoly silicon layer 18 and the metal silicon 20 'and the filled contact material leak electricity. Or short circuit. SUMMARY OF THE INVENTION Therefore, the main purpose of the present invention is to provide a self-manufacturing method to solve the above-mentioned conventional self-aligning contact hole problem. The present invention provides a method for making a hole on a semiconductor wafer. The semiconductor wafer includes a substrate, two above the substrate, and a plurality of sidewalls disposed on the substrate between the two gates. At least one doped region is generated, and the walls are connected to each other and cover the doping. Above the district. A dielectric layer was formed on the surface of the semiconductor wafer, covering the junction between the dielectric layer 26, the process layer 22, and the side wall 26, which may straighten the conductive material of the silicon layer 18 and the gold 34, thereby causing doping. The method of manufacturing the conductive object alignment contact hole of the hole 34 is such that the self-aligned contact adjacent electrodes are disposed around the electrodes. The method of inventing the side between the two gates is on the two gates above the invention (4) and the side wall. Then, a "first etching process" is performed to remove the dielectric layer above the doped region to a predetermined depth to form a hole, and the bottom of the hole is formed by the two gates and a partial region on the top of the sidewall. β Next, a polycrystalline sidewall is formed on the inner wall of the hole, covering the two gates and the top area of the sidewall. Finally, a second etching process is performed to etch the dielectric layer between the two gates and the sidewalls down to the surface of the doped region along the polycrystalline silicon sidewalls in the hole to complete the self-aligning contact hole process. / As the present invention uses the etching process to form the self-aligned contact hole with a high etching selection ratio between the polycrystalline silicon sidewall and the gasified silicon sidewall, it can effectively avoid covering the top of the gate. The protective layer is damaged by the etching process. In addition, the present invention can also be used in a process below 0.15 microns to avoid over-etching the silicon nitride layer over the gate electrode, thereby ensuring that the gate electrode and the subsequent formation in the self-alignment 2 The conductive plug in the galvanic isolation effect. In addition, the present invention does not need to form a sidewall between the idler electrodes, reduces an etching process, and simplifies the contact hole two. For detailed description of the invention, please refer to FIG. 4 to FIG. 9, which are schematic diagrams of a method for making a self-aligned contact hole (! 68) on a conductor wafer 40 by using the present invention. As shown in FIG. 4, the semiconductor chip 40 includes a silicon substrate 42 and an active region.

434820 五，發明說明（5) 設4 3於碎基底4 2表面之一預定區域上，一淺溝隔離4 5設於 主動區域43外圍之矽基底42表面上，二相鄰閘極56設於主 動區域4 3表面，四個侧壁子5 8設於閘極5 6周圍，一摻雜區 4 4設於一相鄰閉極5 6之間的碎基底4 2上，以及 '—氧化碎層 4 6設於閘極5 6及矽基底4 2與側壁子5 8之間，用來釋放側壁 子58對半導體晶片40的熱應力》 側壁子5 8係由矽氧化物或氮化石夕所構成，由於半導趙 製程中線寬的縮小，使得於閘極5 6之間形成側壁子5 8變得 相當困難’因此位於閘極56之間的側壁子58係彼此相連並 覆蓋於摻雜區4 4之上。淺溝隔離4 5係用以電隔絕主動區域 43與其它設於矽基底42上的電子元件，在設計尺寸 (design rule)較大的半導體製程中可以郸用場氧化層 (f i led oxide)來代替淺溝隔離45。閘極5,6包含有一由二 氧化矽所構成之閘極氧化層48設於基底42表面之一預定區 域上’一摻雜多晶矽層50設於閘極氧化層48之上，一金屬 矽化物層5 2設於摻雜多晶矽層5 0之，以及一由氮化發所構 成的保護層5 4設於金屬矽化物層5 2之上。 請參考囷五，本發明製作接觸洞方法是先進行一低聲 化學氣相沉積（low pressure chemical vapor ’ Λ deposition，LPCVD)製程，於半導體晶片40表面形成一介 電層60，覆蓋於閘極56以及側壁子58之上。接著利用旋^ |法於介電層6 0表面形成一光阻層62，以及進行一黃光製程434820 V. Description of the invention (5) Set 4 3 on a predetermined area on the surface of the broken substrate 4 2, a shallow trench isolation 4 5 is provided on the surface of the silicon substrate 42 on the periphery of the active area 43, and two adjacent gates 56 are provided on On the surface of the active region 4 3, four side walls 5 8 are disposed around the gate electrode 5 6, a doped region 4 4 is disposed on the broken substrate 4 2 between adjacent closed electrodes 5 6, and The layer 46 is located between the gate 56 and the silicon substrate 42 and the side wall 5 8 to release the thermal stress of the side wall 58 on the semiconductor wafer 40. The side wall 5 8 is made of silicon oxide or nitride nitride. Composition, due to the reduction of the line width in the semiconducting Zhao process, it is very difficult to form the side walls 58 between the gates 56. Therefore, the side walls 58 located between the gates 56 are connected to each other and covered with doping. District 4 4 above. Shallow trench isolation 4 5 is used to electrically isolate the active area 43 from other electronic components on the silicon substrate 42. Fi semiconductors can be used in semiconductor processes with large design rules. Instead of shallow trench isolation 45. The gates 5, 6 include a gate oxide layer 48 made of silicon dioxide on a predetermined area on the surface of the substrate 42. A doped polycrystalline silicon layer 50 is disposed on the gate oxide layer 48, and a metal silicide The layer 52 is disposed on the doped polycrystalline silicon layer 50, and a protective layer 54 composed of a nitrided layer is disposed on the metal silicide layer 52. Please refer to Article 5. The method for making a contact hole according to the present invention is to first perform a low pressure chemical vapor deposition (LPCVD) process to form a dielectric layer 60 on the surface of the semiconductor wafer 40 and cover the gate electrode. 56 and sidewall 58 above. Then, a photoresist layer 62 is formed on the surface of the dielectric layer 60 by the spin method |, and a yellow light process is performed.

43482 Ο 五、發明說明（6) 於光阻層62中形成一圖案63。 程’沿著圖案63垂直向下蚀刻 電層6 0至一預定深度，再利用 完全去除’以形成一孔洞64。 側壁子58之頂部的部分區域所 部可能殘留些許的介電層6〇。 如圖六所示，進行一姓刻製 去除位於摻雜區4 4上方的介 一光阻清除製程將光阻層62 孔洞64之底部係由閘極56及 構成，此外，在孔洞6 4之底 如囷七所示，形成孔洞64之後，再進行另一乙“⑽製 程，於半導體晶片40表面形成一厚度均勻的多晶矽層65， ，蓋於介電層6 0及孔洞64内壁及底部表面。如圖八所示， k後進行一乾蝕刻製程’去除位於介電層6 〇及孔洞6 4底部 表面的多晶矽層δ 5，使殘留於閘極5 6以及側壁子5 8的頂部 區域上方之多晶矽層6 5形成一多晶矽側壁子6 6，即多晶矽 侧壁子6 6係覆蓋於閘極5 6及侧壁子5 8的頂部區域之上。此 LPCVD製程的反應溫度控制於6〇〇〜650 °C之間，反應壓力控 制於0. 3~0. 6(torr)之間，以避免形成非晶矽。而且多晶 矽層65的厚度（W)必須小於孔洞64之直徑（Y)的一半，即 W<0. 5Y(如圖七），如此後續之乾蝕刻製程才能於孔洞64的 内壁形成多晶矽壁子5 6 » 如圖九所示，最後進行一蝕刻製程，沿著孔洞6 4内壁 之多晶矽側壁子6 6向下蝕刻位於閘極5 6之間的介電層6 0及 树壁子5 8直到氧化矽層4 6的表面，再調整蝕刻製程的蝕刻 選擇比，去除氧化矽層4 6直到摻雜區4 4的表面，以形成自43482 〇 5. Description of the invention (6) A pattern 63 is formed in the photoresist layer 62. The process 60 etches the electrical layer 60 down to a predetermined depth vertically along the pattern 63, and then completely removes it to form a hole 64. A part of the area on top of the side wall member 58 may leave a little dielectric layer 60. As shown in FIG. 6, a photolithography process is performed to remove the photoresist removal process located above the doped region 4 4. The bottom of the photoresist layer 62 hole 64 is composed of the gate electrode 56 and the photoresist layer. The bottom is as shown in Figure 27. After the holes 64 are formed, another process is performed to form a polycrystalline silicon layer 65 with a uniform thickness on the surface of the semiconductor wafer 40, covering the dielectric layer 60 and the inner and bottom surfaces of the holes 64. As shown in FIG. 8, a dry etching process is performed after k ′ to remove the polycrystalline silicon layer δ 5 located on the bottom surface of the dielectric layer 60 and the hole 64, so as to remain above the top regions of the gate electrode 56 and the side wall 58. The polycrystalline silicon layer 65 forms a polycrystalline silicon sidewall 66, that is, the polycrystalline silicon sidewall 66 covers the top region of the gate 56 and the sidewall 58. The reaction temperature of this LPCVD process is controlled to 600-600 ~ Between 650 ° C, the reaction pressure is controlled between 0.3 and 0.6 (torr) to avoid the formation of amorphous silicon. The thickness (W) of the polycrystalline silicon layer 65 must be less than half the diameter (Y) of the hole 64 That is, W < 0. 5Y (as shown in Figure 7), so that the subsequent dry etching process can be performed on the holes 64. A polycrystalline silicon wall 5 6 is formed on the inner wall »As shown in FIG. 9, an etching process is finally performed, and the polysilicon sidewall 6 6 on the inner wall of the hole 6 4 is etched down to the dielectric layer 60 and the tree between the gates 5 6. The wall 5 8 reaches the surface of the silicon oxide layer 46, and then the etching selection ratio of the etching process is adjusted, and the silicon oxide layer 4 6 is removed to the surface of the doped region 4 4 to form a self

第10頁 4348 2 0 五、發明說明（7) _ 行對準接觸洞68是用來填入導電物 φ 導電插塞。由於接觸洞6 8的部份内壁是位於非導 子58及66的表面上，因此接觸洞68底部與播雜 ΐ ί ί Ϊ面積較小。為避免後續形成於接觸洞68之中的 J電插塞的電阻值上升，因此在完成接觸洞68之後可對 進行一次離子摻雜以降低摻雜區“與“插塞的 ^發明係利用蝕刻製程對多晶矽與氮化矽、氧化矽之 間的π蝕刻選擇比，來形成自行對準接觸洞68，以避免閘 極之頂保護層54與側壁子58在長時間的蝕刻過程中被破 壞。由於多晶矽與氮化矽、氧化矽的蝕刻選擇比優於氮化 矽對矽氧物的蝕刻選擇比，因此在進行自行對準蝕刻以形 成接觸洞68時，覆蓋於頂保護層54與側壁子58上方的多晶 矽側壁子6 6可以有效地避免頂保護層5 5與側壁子5 8免於受 到蝕刻製程的破壞，進而確保閘極5 6與後續形成於接觸洞 68之中的導電插塞電隔離效果。 此外，不同於習知技術 厚度來定義接觸洞38與摻雜 多晶梦側壁子66來定義接觸 進而控制後續形成於接觸洞 的接觸電阻β由於位於閘極 影響該接觸面積，因此閘極 利用閘極24之間的側，摩子28的 區1 4的接觸面積。本發明係利 洞6 8與摻雜區4 4的接觸面積， 68之中的導電插塞與摻雜區44 5 6之間的側壁子5 8的厚度並不 5 6之間的側壁子5 8可以彼此相Page 10 4348 2 0 V. Description of the invention (7) _ The row alignment contact hole 68 is used to fill a conductive object φ conductive plug. Since part of the inner wall of the contact hole 68 is located on the surfaces of the non-conductors 58 and 66, the area between the bottom of the contact hole 68 and the antennas is small. In order to prevent the resistance value of the J electrical plug formed in the contact hole 68 from increasing in the future, after the contact hole 68 is completed, an ion doping may be performed to reduce the doped region. The process selects the π etching selection ratio between polycrystalline silicon, silicon nitride, and silicon oxide to form a self-aligned contact hole 68 to prevent the gate top protective layer 54 and the side wall 58 from being damaged during a long etching process. Since the etching selection ratio of polycrystalline silicon, silicon nitride, and silicon oxide is better than the etching selection ratio of silicon nitride to silicon oxide, when the self-aligned etching is performed to form the contact hole 68, the top protective layer 54 and the side walls are covered. The polycrystalline silicon sidewalls 6 6 above 58 can effectively prevent the top protective layer 5 5 and the sidewalls 5 8 from being damaged by the etching process, thereby ensuring that the gate electrode 5 6 and subsequent conductive plugs formed in the contact holes 68 are electrically charged. Isolation effect. In addition, different from the conventional technology thickness, the contact hole 38 and the doped polycrystalline silicon sidewall 66 are used to define the contact and then control the subsequent contact resistance β formed in the contact hole. Because the gate is located at the gate to affect the contact area, the gate uses the gate. On the side between the poles 24, the contact area of the area 14 of the motorcycle 28. The present invention relates to the contact area between the hole 6 8 and the doped region 4 4. The thickness of the sidewall spacer 5 8 between the conductive plug in 68 and the doped region 44 5 6 is not the thickness of the sidewall spacer 5 between 5 6. 8 can phase each other

第11頁 434820 玉、發明說明（8) 連接並且後蓋於摻雜區44之上。側壁子58係利用一氣、化梦 沈積以及一蚀刻步麻來形成，由於側壁子58的厚度並不影 馨該接觸面積，利用本發明甚至可以將用以形成側壁子5 8 的蚀刻製程省略，因此僅需進行氮化妙沈積步驟即可，如 下一實施例所示。 請參考圖十至圈十五，圖十至圖十五為利用本發明另 一實施例於一半導體晶片7 0上製作自行對準接觸洞9 8的示 意圖。請參考圖十’與前一實施例不同的是本實施例以一 設於矽基底4 2表面並覆蓋於閘極56之侧邊與上方的氮化矽 層8 8來代替側壁子58。如圖Η--所示，在半導艘晶片70上 製作接觸洞時’首先進行一 LPCVD製程，於半導體晶片70 表面形成一介電層90，覆蓋於氮化矽層88.之上。接著利用 旋塗法於介電層90表面形成一光阻層92,以及進行一黃光 製程於光阻層92中形成一圖案93。如圖十二所示，然後進 行一姓刻製程’沿著圊案9 3垂直向下蝕刻去除位於摻雜區 44上方之介電層90—預定深度，直到氮化矽層88的表面， 再利用一光阻清除製程將光阻層92完全去除，形成一孔洞 94。孔洞94之底部係由閘極86頂部之部分的氮化矽層88所 構成’此外’在孔洞94之底部可能殘留些許的介電層90? 如圖十三所示’形成孔洞9 4之後，再進行另一 LPCVD 製程’於半導體晶片7〇表面形成一厚度均勻的多晶矽層 95’覆蓋於介電層9 〇及孔洞94内壁與底部表面。如圖十四Page 11 434820 Jade, description of the invention (8) is connected and the back cover is over the doped region 44. The side wall 58 is formed by using gas, chemical deposition and an etching step. Since the thickness of the side wall 58 does not affect the contact area, the etching process for forming the side wall 5 8 can be omitted by using the present invention. Therefore, it is only necessary to perform the nitridation deposition step, as shown in the following embodiment. Please refer to FIGS. 10 to 15. FIGS. 10 to 15 are schematic diagrams of making a self-aligned contact hole 98 on a semiconductor wafer 70 using another embodiment of the present invention. Please refer to Fig. 10 ', which is different from the previous embodiment in that the present embodiment replaces the side wall 58 with a silicon nitride layer 88, which is provided on the surface of the silicon substrate 42 and covers the sides of the gate 56 and above. As shown in Figure Η--, when a contact hole is made on the semiconductor wafer 70 ', a LPCVD process is first performed to form a dielectric layer 90 on the surface of the semiconductor wafer 70 and cover the silicon nitride layer 88. Next, a photoresist layer 92 is formed on the surface of the dielectric layer 90 by a spin coating method, and a yellow light process is performed to form a pattern 93 in the photoresist layer 92. As shown in FIG. 12, a lithography process is then performed to etch down the dielectric layer 90 above the doped region 44 to a predetermined depth along the case 9 3 vertically down to the surface of the silicon nitride layer 88, and then The photoresist layer 92 is completely removed by a photoresist removal process to form a hole 94. The bottom of the hole 94 is composed of a silicon nitride layer 88 on the top of the gate 86. In addition, a small dielectric layer 90 may remain at the bottom of the hole 94. As shown in FIG. 13, after the formation of the hole 94, Then another LPCVD process is performed to form a polycrystalline silicon layer 95 with a uniform thickness on the surface of the semiconductor wafer 70 to cover the dielectric layer 90 and the inner wall and bottom surface of the hole 94. Figure fourteen

第12頁 434820 五、發明說明（9) 所示，隨後進行一乾蚀刻製程’去除位於介電層90及孔洞 9 4底部表面的多晶矽層95’使殘留於閘極5 6以及氮化矽層 8 8頂部區域上方的多晶矽層9 5形成一側壁子9 6，即多晶矽 側壁子9 6係復蓋於閛極5 6頂部之氮化矽層8 8的上方。最後 再進行一蝕刻製程’沿著孔洞9 4内壁之多晶矽側壁子9 6向 下蝕刻閘極5 6之間殘留的介電層9 0以及氮化矽層8 8直到氧 化矽層4 6表面，再調整蝕刻製程的蝕刻選擇比，去除氧化 矽層4 6直到摻雜區4 4的表面’以形成自行對準接觸洞98, 如囷十五所示。 由於半導體設計與製造的線寬（line width)不斷縮 小，而形成在閘極5 6之間的側壁子5 8更進一步使得接觸洞 68與掺雜區44的接觸面積縮小。本發明是，在半導體晶片表 面形成一氮化矽層8 8並覆蓋閘極5 6以取代侧壁子5 8，作為 閘極5 6的保護層《利用本發明在進行蝕刻以形成接觸洞9 8 時’覆蓋於氮化矽層8 8上方的多晶矽侧壁子9 6可以有效地 避免氮化矽層8 8受到過度蝕刻，進而確保閘極8 6與後續形 成於自行對準接觸洞98之令的導電插塞電隔離效果。 相較於習知製作自行對準接觸洞38的方法，本發明利 用蝕刻製程對多晶矽與氮化矽之間的高蝕刻選擇比來形成 自行對準接觸洞98，可以有效地避免覆蓋於閘極56上方的 項保護層54免於受到蝕刻製程的破壞，確保了閘極56的主 趙結構°此外’本發明亦可用在〇1 5微米以下的製程之Page 12 434820 5. As shown in the description of the invention (9), a dry etching process is subsequently performed to remove the polycrystalline silicon layer 95 ′ located on the bottom surface of the dielectric layer 90 and the hole 9 4 so as to remain on the gate electrode 5 6 and the silicon nitride layer 8 The polycrystalline silicon layer 95 above the top region 8 forms a sidewall 96, that is, the polycrystalline silicon sidewall 96 covers the silicon nitride layer 88 on top of the anode 56. Finally, an etching process is performed along the polysilicon sidewalls 9 6 on the inner wall of the hole 9 4 to etch the remaining dielectric layer 90 and the silicon nitride layer 8 8 between the gate 56 and the silicon oxide layer 46. Then, the etching selection ratio of the etching process is adjusted, and the silicon oxide layer 46 is removed until the surface of the doped region 44 is formed to form a self-aligned contact hole 98, as shown in Fig. 15. As the line width of the semiconductor design and manufacturing continues to shrink, the sidewalls 58 formed between the gates 56 further reduce the contact area between the contact hole 68 and the doped region 44. In the present invention, a silicon nitride layer 8 8 is formed on the surface of the semiconductor wafer and covers the gate electrode 56 to replace the side wall 5 8 as a protective layer of the gate electrode 5 6. The present invention is used to etch to form a contact hole 9. At 8 o'clock, the polycrystalline silicon sidewall 9 6 overlying the silicon nitride layer 8 8 can effectively prevent the silicon nitride layer 8 8 from being over-etched, thereby ensuring that the gate electrode 8 6 and the subsequent formation of the self-aligned contact hole 98 The conductive plug is electrically isolated. Compared with the conventional method of making self-aligned contact holes 38, the present invention uses self-aligned contact holes 98 to form a self-aligned contact hole 98 using a high etching selection ratio between polycrystalline silicon and silicon nitride by an etching process, which can effectively avoid covering the gate electrode. The protective layer 54 above 56 is protected from being damaged by the etching process, which ensures the main structure of the gate electrode 56. In addition, the present invention can also be used in processes below 0.15 micron.

第13頁 434820 五、發明說明（ίο) 中’避免覆蓋於閘極5 6上方的氮化矽層8 8受到過度蝕刻，· 進而確保閘極56與後續形成於接觸洞98之中的導電插塞電 隔離效果。而且本發明並不需於閘極56之間形成側壁子， 減少了 一道蝕刻製程，使得接觸洞的製程得以簡化。 菱在丨：士所述僅為ί發明之較佳實施例，凡依本發明申請 ί 圍所做之均等變化與修飾，皆應屬本發明專利之涵 蓋範圍。Page 13 434820 5. In the description of the invention (ίο) 'Avoid the silicon nitride layer 8 8 covering the gate 5 6 from being over-etched, thereby ensuring that the gate 56 and the subsequent conductive plug formed in the contact hole 98 Electrical isolation effect. In addition, the present invention does not need to form a sidewall between the gate electrodes 56, which reduces an etching process, and simplifies the process of contact holes. The description in Ling is only a preferred embodiment of the invention, and all equivalent changes and modifications made in accordance with the application of the invention should fall within the scope of the invention patent.

第14頁 43482 0 圖式簡單說明 圖示之簡單說明 圈一至囷三為習知製作自行對準接觸洞的方法示意 圖β 圊四至圖九為本發明製作自行對準接觸洞的方法示意 圖q 圖十至圖十五為本發明之另一實施例的示意囷。 圖示之符號說明 10 半 導 體 晶 片 12 矽 基 底 14 摻 雜 區 16 閘 極 氧 化 層 18 摻 雜 多 晶 矽層 20 金 屬 ‘妙 化 物 層 22 頂 保 護 層 24 閘 極 . 26 側 壁 子 28 介 電 層 30 光 阻 層 32 圖 案 34 接 觸 洞 40 半 導 體 晶 42 矽 基 底 43 主 動 區 域 44 摻 雜 區 45 淺 溝 隔 離 46 氧 化 矽 層 48 閘 極 氧 化 層 50 摻 雜 多 晶 矽 層 52 金 屬 矽 化 物層 54 頂 保 護 層 56 閘 極 58 側 壁 子Page 14 43482 0 Schematic illustrations of the diagrams Simple illustrations Circles 1 to 3 are schematic diagrams of the methods for making self-aligned contact holes for conventional use β 4 to 9 are schematic diagrams of the methods for making self-aligned contact holes according to the invention q Figure 10 Fig. 15 to Fig. 15 are schematic diagrams of another embodiment of the present invention. Explanation of symbols in the diagram 10 Semiconductor wafer 12 Silicon substrate 14 Doped region 16 Gate oxide layer 18 Doped polycrystalline silicon layer 20 Metallic layer 22 Top protection layer 24 Gate. 26 Side wall 28 Dielectric layer 30 Photoresist layer 32 pattern 34 contact hole 40 semiconductor crystal 42 silicon substrate 43 active region 44 doped region 45 shallow trench isolation 46 silicon oxide layer 48 gate oxide layer 50 doped polycrystalline silicon layer 52 metal silicide layer 54 top protective layer 56 gate 58 sidewall child

43482 0 圖式簡單說明 60 介 電 層 62 光 阻 層 63 圊 案 64 孔 洞 6 5 多 晶 矽 層 66 側 壁 子 68 接 觸 洞 70 半 導 體 晶片 88 氮 化 矽層 90 介 電 層 92 光 阻 層 93 圖 案 94 孔 洞 95 多 晶 矽 層 96 侧 壁 子 98 接 觸 洞 第〗6頁43482 0 Brief description of the diagram 60 Dielectric layer 62 Photoresist layer 63 Case 64 Hole 6 5 Polycrystalline silicon layer 66 Side wall 68 Contact hole 70 Semiconductor wafer 88 Silicon nitride layer 90 Dielectric layer 92 Photoresist layer 93 Pattern 94 Hole 95 Polycrystalline silicon layer 96 sidewall 98 contact hole 第 6 页