TW434757B - Method for forming a ball grid array connection - Google Patents

Method for forming a ball grid array connection Download PDF

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Publication number
TW434757B
TW434757B TW089102974A TW89102974A TW434757B TW 434757 B TW434757 B TW 434757B TW 089102974 A TW089102974 A TW 089102974A TW 89102974 A TW89102974 A TW 89102974A TW 434757 B TW434757 B TW 434757B
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TW
Taiwan
Prior art keywords
solder
grid array
ball grid
bga
substrate
Prior art date
Application number
TW089102974A
Other languages
Chinese (zh)
Inventor
George Tsao
Original Assignee
George Tsao
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Priority to TW089102974A priority Critical patent/TW434757B/en
Application granted granted Critical
Publication of TW434757B publication Critical patent/TW434757B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

There is provided a method for forming a ball grid array (BGA) connection, which comprises: printing solder paste to a plurality of solder pads on the bottom surface of a BGA substrate; and re-flowing the solder paste to form a plurality of solder bumps on the plurality of solder pads on the bottom surface of the BGA substrate.

Description

434767 五、發明說明（ο * 發明領域： 本發明係有關於一種球格陣列（Ball Grid Array， BGA)封裝構造，更特別有關一種形成球格陣列連接（bga connection)的方法 * 先前技術： 隨著更輕更複雜電子裝置需求的日趨強烈，晶片的速 度及複雜性相對越來越高’因此需要更高之封裝效率 (packaging efficiency)。於是半導體晶片封裝業界發展 出球格陣列封裝技術，以符合其需求β 第1圖揭示一習用球格陣列封裝構造1〇〇，其包含一半 導體晶片110安裝於一球格陣列基板120。該晶片11〇表面 之晶片輝墊（未示於圖中）係以導線（bonding wires)112 連接至設於該基板120上表面的導電線路（conductive traces)(未示於圖中）。該基板120之下表面設有複數 個錫球銲墊124電性連接至該導電線路。該每一錫球銲墊 124已被銲上一錫球13〇用以與外界電性溝通。一封膠體 140包覆該晶片11〇、導線112以及該基板12〇上表面之一部 份（包括大部分的導電線路）。 當球格陣列基板120係以陶瓷材料製成時，其植球 (bal 1 mount ing)製程係包含下列步驟：（a)將錫球裝在一 固定件（fixture)上，該固定件具有複數個孔其排列對應 於所要之球格陣列；（b)將共晶（eutectic)錫膏印在基板 120的踢球銲塾124上；（c)將基板12〇與固定件上的錫球陣 列對齊置放於其頂部，然後回焊（只熔共晶錫膏）。當球434767 V. Description of the invention (ο * Field of the invention: The present invention relates to a Ball Grid Array (BGA) package structure, and more particularly to a method for forming a bga connection * The prior art: With the increasing demand for lighter and more complex electronic devices, the speed and complexity of the chip are relatively higher and higher. Therefore, higher packaging efficiency is required. Therefore, the semiconductor chip packaging industry has developed ball grid array packaging technology to Meet its needs β Figure 1 reveals a conventional ball grid array package structure 100, which includes a semiconductor wafer 110 mounted on a ball grid array substrate 120. A wafer glow pad (not shown in the figure) on the surface of the wafer 11 Bonding wires 112 are connected to conductive traces (not shown) provided on the upper surface of the substrate 120. A plurality of solder ball pads 124 are electrically connected on the lower surface of the substrate 120. To the conductive circuit. Each of the solder ball pads 124 has been soldered with a solder ball 13 for electrical communication with the outside world. A glue 140 covers the wafer 11 and the wires 112. And a part of the upper surface of the substrate 120 (including most of the conductive lines). When the ball grid array substrate 120 is made of ceramic material, its bal 1 mounting process includes the following steps: ( a) the solder ball is mounted on a fixture, the fixture has a plurality of holes, the arrangement of which corresponds to the desired ball grid array; (b) a kick ball with eutectic solder paste printed on the substrate 120 Solder pad 124; (c) Align the substrate 12 and the solder ball array on the fixture on top of it, and then resolder (only eutectic solder paste). When the ball

434757 五、發明說明（2) . 格陣列基板1 20係以高玻璃轉換溫度（Tg)材質（例如BT (bismaleimide-triazine)樹脂或FR-4 環氧樹脂）製成 時，其植球（ball mounting)製程係包含下列步驟：（&)將 一層助銲劑利用一印刷模板（stencii)印在基板^。的錫 球銲墊124上；（b)利用助銲劑之黏性將錫球暫時接合在 基板120的錫球銲墊124上；（c)回焊（b)之產物，使踢球永 久接合在基板120的錫球薛塾124上。一般而言，踢球係利 用自動置球技術（automatic ball placing technique)安 r 放置預先設定位置；其係利用真空吸頭（vacuuin suction head)吸起錫球並置放在預先設定位置。 前述習用植球（ball mounting)製程之缺點如下：（A) ^ 需要使用錫球導致材料成本高；（B)製程複雜導致製程成 本高’並且隨著錫球尺寸越來越小以及錫球陣列密度越來 越高’製程機器的精密度以及精確度也將越來越高而導致 機器採購成本增加；（C)錫球置放後，整個裝置在回焊前 必須保持穩定以免錫球滚動或偏移，使得製程難度較高； (D)當該習用球格陣列封裝構造1(]〇安裝至電路板150 見第2圓），由於錫球本身之弧度，外力（例如基板與晶 -片熱膨脹係數不一致（CTE mismatch)所產生之應力）容易 集中在錫球與球格陣列^板120之界面以及錫球與電路板 4 150之界面。這將使銲錫連接（s〇lder j0int)之品質及可 k 靠性大幅降低（因為在錫球/基板以及錫球/電路板界面之、 焊接強度最脆弱）。 此外，雖然錫球係利用自動置球技術安放置預先設定434757 V. Description of the invention (2). When the grid array substrate 1 20 is made of high glass transition temperature (Tg) material (such as BT (bismaleimide-triazine) resin or FR-4 epoxy resin), its ball is planted (ball The mounting process includes the following steps: (&) A layer of flux is printed on the substrate using a stencii. (B) the solder ball is temporarily bonded to the solder ball pad 124 of the substrate 120 by using the viscosity of the flux; (c) the product of (b) is re-soldered to make the kick ball permanently bonded to the solder ball pad 124; The solder balls 124 of the substrate 120 are on the substrate 120. Generally speaking, the kicking system uses an automatic ball placing technique to place the preset position; it uses a vacuum suction head to suck the solder ball and place it in the preset position. The disadvantages of the aforementioned conventional ball mounting process are as follows: (A) ^ the need for solder balls leads to high material costs; (B) the complexity of the process leads to high process costs' and as the size of the solder balls becomes smaller and smaller and the solder ball array Increasing density: The precision and accuracy of the process machine will also become higher and higher, which will increase the purchase cost of the machine; (C) After the solder ball is placed, the entire device must be stable before reflow to prevent the solder ball from rolling. Or offset, making the process more difficult; (D) When the conventional ball grid array package structure 1 (] 〇 is mounted to the circuit board 150 (see the second circle), due to the radian of the solder ball itself, external forces (such as the substrate and the crystal- The stress caused by the CTE mismatch is likely to be concentrated at the interface between the solder ball and the ball grid array ^ board 120 and the interface between the solder ball and the circuit board 4 150. This will greatly reduce the quality and reliability of solder joints (because of the weakest soldering strength at the solder ball / substrate and solder ball / circuit board interfaces). In addition, although the solder ball system uses the automatic ball placement technology to set the preset

434757434757

位置而使製程自動化以加诘拈坫嚙办 ^ ^ 點：（A)真空吸頭往往ϋίίΐΐ，然而其仍有下述缺 瑕疵品UB)越多錫球要吸〜&所有的錫球，而造成 作用使踢球黏在真空吸頭，而無法置放至 發明概要： 矣主#要#目的係提供一種在球格陣列（bga)基板下 表面之複數個銲墊形成複數個錫點突起 或至少改善前述之先前技術的問題。 具了无服 根據本發明之形成複數個錫點突起的方法，其包含： 印刷錫膏於該球格陣列（BGA)基板下表面之複數個銲墊； 以及回焊該錫膏以形成複數個錫點突起於該球格陣列 (BGA)基板下表面之複數個銲墊。可以理解的是，該球格 陣列（BG A )基板上表面已設有一半導體晶片，並且該半導 體晶片可以利用線接合（wire bonding)、膝揍式自動黏著 (Tape Automated Bonding, TAB)或覆晶接合（fnp-chip bonding)等任一方式與基板電性連接。 根據本發明之方法，其優點如下：（Α)以錫膏取代錯 f ’由於錫爹成本較低，而大幅降低材料成本；（Β)製程 簡化降低製程成本，並且錫膏印刷機器不受未來錫球尺寸 越來越小之影響，仍可照常使用；（C)錫膏可一次印刷於 所有基板上之銲墊，藉此大幅縮短生產時間（ey e 1 e time)，而增加產量；（D)錫骨印刷完成後，由於錫膏本身 具有黏著性，因此整個裝置在回焊前不需特別保持穩定，Position to automate the process in order to increase the number of points: (A) the vacuum tip is often ϋίΐΐ, but it still has the following defects UB) the more solder balls to suck ~ & all the solder balls, As a result, the kick ball sticks to the vacuum nozzle and cannot be placed in the summary of the invention: 矣 主 # 要 # The purpose is to provide a plurality of solder pads on the lower surface of the ball grid array (bga) substrate to form a plurality of solder bumps. Or at least the problems of the aforementioned prior art are improved. A method for forming a plurality of solder point protrusions according to the present invention is provided, comprising: printing a plurality of solder pads on a lower surface of the ball grid array (BGA) substrate; and re-soldering the solder paste to form a plurality of solder pads. A plurality of solder pads with solder bumps protruding from the lower surface of the ball grid array (BGA) substrate. It can be understood that a semiconductor wafer has been provided on the upper surface of the ball grid array (BG A) substrate, and the semiconductor wafer can be made by wire bonding, Tape Automated Bonding (TAB), or flip chip. Any method such as fnp-chip bonding is electrically connected to the substrate. According to the method of the present invention, its advantages are as follows: (A) Substituting solder paste for f 'due to lower cost of tin, which greatly reduces material costs; (B) process simplification reduces process costs, and solder paste printing machines are not affected by the future The effect of the smaller and smaller solder ball size can still be used as usual; (C) solder paste can be printed on the solder pads on all substrates at once, thereby greatly reducing the production time (ey e 1 e time), and increasing the yield; ( D) After the solder bone printing is completed, because the solder paste itself is adhesive, the entire device does not need to be particularly stable before re-soldering.

434767434767

因而降低製程難度；（E)當該複數個錫點突起與電路板接 合後’由於錫膏完全溶解並且與銲墊充分結合，因此使鲜 錫連接（solder joint)之品質及可靠性大幅增加。 圖示說明： 為了讓本發明之上述和其他目的、特徵、和優點能更 明顯特徵，下文特舉本發明較佳實施例’並配合所附圖 示，作詳細說明如下》 第1圏：習用球格陣列（BGA)半導體封裝構造之剖面 面 · 圖， 第2圖：第1圖之習用球格陣列（BGA)半導體封裝構造安 裝至一電路板後之剖面圖； 第3圈至第4圈：其係用以說明根據本發明較佳實施例 之在球格陣列（BGA)基板下表面複數個銲墊形成複數個錫 點突起的方法；及 第5圊：根據本發明較佳實施例之球格陣列（BGA)封裝 構造安裝至一電路板後之剖面圖。 圖號說明： 112 導線 130 錫球 160 錫赍 175 錫點突起 100 習用球格陣列封裝構造 110 半導體晶片 120 球格陣列基板 124 錫球銲墊 140封膠體 〗5〇電路板 17 0 網板 丨7 2 刮板 180 電路板 發明說明：Therefore, the difficulty of the process is reduced; (E) When the plurality of solder point protrusions are connected to the circuit board, since the solder paste is completely dissolved and fully bonded to the solder pad, the quality and reliability of the solder joint are greatly increased. Illustration: In order to make the above and other objects, features, and advantages of the present invention more obvious, the following describes the preferred embodiment of the present invention 'and the accompanying drawings for detailed description as follows. Cross-section view of a ball grid array (BGA) semiconductor package structure. Figure 2: Figure 1 is a cross-sectional view of the conventional ball grid array (BGA) semiconductor package structure mounted on a circuit board. Circles 3 to 4 : It is used to explain a method for forming a plurality of solder bumps on a plurality of pads on the lower surface of a ball grid array (BGA) substrate according to a preferred embodiment of the present invention; A cross-sectional view of a ball grid array (BGA) package structure mounted on a circuit board. Description of drawing number: 112 wire 130 solder ball 160 solder 175 solder point protrusion 100 custom ball grid array package structure 110 semiconductor wafer 120 ball grid array substrate 124 solder ball pad 140 sealing gel〗 5 circuit board 17 0 screen board 7 2 Scraper 180 Circuit board invention description:

43475 7 五、發明說明（5) 第3圖至第4圖說明根據本發明較佳實施例之在球格陣 列（BG A)基板下表面複數個銲墊形成複數個錫點突起的方 法。 值得注意的是，在大量生產時，一般係將複數個球格 陣列基板整合在一基板條（strip)上，該基板條上具有對 正孔（al ignment hole)，用以使封裝製程（包括封膠）自 動化。因此，可以理解的是，根據本發明較佳實施例之製 造方法雖大致係針對單一球格陣列基板描述，但後述之施 於單一球格陣列基板的每一步驟亦可同時實施在該基板條 上的每一個球格陣列基板。43475 7 V. Description of the Invention (5) Figures 3 to 4 illustrate a method for forming a plurality of solder bumps on the lower surface of a ball grid array (BG A) substrate according to a preferred embodiment of the present invention. It is worth noting that, in mass production, a plurality of ball grid array substrates are generally integrated on a substrate strip with an alignment hole on the substrate strip for packaging processes (including Sealing) automation. Therefore, it can be understood that although the manufacturing method according to the preferred embodiment of the present invention is roughly described with respect to a single ball grid array substrate, each step described later applied to a single ball grid array substrate can also be simultaneously implemented on the substrate strip. Each ball grid array on the substrate.

請參照第3A圖，半導體晶片係利用線接合的方式安 裝於球格陣列基板12〇並且被封膠體14〇包覆。錫膏丨6〇係 印刷於球格陣列基板1 2 〇下表面複數個陣列排列之銲墊 124。將踢膏轉至基板上特定位置最常用之技術為網版印 刷（screen printing) ’ 又稱非接觸性印刷（non_c〇ntact printing) ’因為網板17〇係與印刷表面有一些距離。該網 板1 70具有複數個開口，其排列對應於該複數個陣列排列 之鲜塾124。在印刷製程中，錫奮係被刮板（squeegee)172 播過網板1 7 0的開口，然後堆在該複數個陣列排列之銲墊 124 上。Referring to FIG. 3A, the semiconductor wafer is mounted on the ball grid array substrate 12 by wire bonding and is covered with a sealing compound 14o. The solder paste 60 is a plurality of pads 124 arranged on the lower surface of the ball grid array substrate 120 and arranged in an array. The most commonly used technique for transferring the kick paste to a specific position on the substrate is screen printing (also called non-contact printing) because the screen 17o is some distance from the printing surface. The stencil 1 70 has a plurality of openings, the arrangement of which corresponds to the plurality of arrayed arrays 124. In the printing process, the Siemens system is broadcasted by the squeegee 172 through the opening of the screen 170, and then stacked on the plurality of arrayed pads 124.

請參照第3B圖’錫膏亦可利用模版印刷（stenci j Printing)(又稱接觸性印刷（on-contact printing)) 方式形成於球格陣列基板12〇下表面複數個陣列排列之銲 塾124。當需要形成較厚之錫膏16〇時，較佳使用模版印Please refer to FIG. 3B. The solder paste can also be formed on the lower surface of the ball grid array substrate 120 by a plurality of arrayed solder pads 124 using stenci j printing (also known as on-contact printing). . When thicker solder paste 16 is needed, stencil printing is preferred.

434757 五、發明說明（6) * 刷。根據本發明’該錫膏印刷厚度不大於1 mm，較佳不大 於0·3mm 。 請參照第4囷，將印上錫膏之裝置移至一回焊爐 (reflow oven)内’然後經由回焊製程形成該複數個錫點 突起（solder paste bump)175。由於錫膏本身具有黏著 性’因此印上錫膏之裝置在回焊製程前以及回焊製程中不 需特別保持穩定，因而降低製程難度。此外，由於所印刷 的錫骨係内含助銲劑’因此回銲後錫膏中的助銲劑將與錄 錫分離而形成一層助銲劑於該複數個錫點突起之表面 (未示於圖中）。 請參照第5圖’其揭示一根據本發明之球格陣列（bga) 封裝構造安裝至一電路板180上。該電路板18〇係先以鎮爹 網版印刷（screen printing)成對應於該封裝構造底部之 錫點突起之圖案（pattern)。然後將該封裝構造對正置於 該印刷電路板上，再利用習知的表面接著技術加以回銲即 可。由於該複數個錫點突起之表面係具有一層助銲 因 此將加強銲接效果。 請再參照第2圖’當習用球格陣列封裝構造1〇〇 電路板150時，由於錫球130本身尺寸較大，因此導^ 構造100舆電路板150間具有較大之間距。 珂衣 係利用錫點突起175安裝至電路板ι80 請再參照第5圊，/本發明之球格陣列（BGA)封裝搆造 錫點突起1 7 5本 身厚度遠小於習用錫球130之高度，因 • 〜+ 構造與電路板之間距而改善產品之電氣特 短封裝 这电氟特性。因為電路434757 V. Description of Invention (6) * Brush. According to the present invention, the printing thickness of the solder paste is not more than 1 mm, and preferably not more than 0.3 mm. Referring to step 4), the solder paste printing device is moved into a reflow oven 'and the solder paste bumps 175 are formed through a reflow process. Since the solder paste itself is adhesive, the device for printing the solder paste does not need to be particularly stable before and during the reflow process, thereby reducing the difficulty of the process. In addition, since the printed tin bone system contains flux, the flux in the solder paste will be separated from the recorded solder after reflow to form a layer of flux on the surface of the plurality of solder point protrusions (not shown in the figure). . Please refer to FIG. 5 ', which discloses a ball grid array (bga) package structure mounted on a circuit board 180 according to the present invention. The circuit board 180 is first screen-printed into a pattern corresponding to the solder dot protrusions at the bottom of the package structure. The package structure is then placed on the printed circuit board and re-soldered using conventional surface bonding techniques. Since the surface of the plurality of solder point protrusions is provided with a layer of soldering flux, the soldering effect will be enhanced. Please refer to FIG. 2 again. When the conventional ball grid array package is used to construct the 100 circuit board 150, the solder ball 130 has a large size, so the structure 100 has a large distance between the circuit boards 150. Ke Yi is mounted on the circuit board using solder point protrusions 175. Please refer to Section 5 /. The ball point array (BGA) package structure of the present invention has solder point protrusions 1 7 5 which are much thinner than the conventional solder ball 130. Improved the electrical characteristics of the product's electrical ultra-short package due to the distance between the ~~ + structure and the circuit board. Because the circuit

434757 五、發明說明（7) (electrical path)越短，其阻抗（impedance)，電感 (inductance)及雜訊（noise)越小。此外，較小之電感值 使半導體封裝構造消耗較少之電能，且使晶片内部之積體 電路與導線較不易感受電源滾涌（power surges)。 根據本發明在球格陣列（BGA)基板下表面之複數個鮮塾 形成複數個錫點突起的方法，其以錫斧取代錫球，由於踢 膏成本較低，而大幅降低材料成本。此外，當該複數個錫 點突起與電路板接合後，由於錫膏完全熔解並且與銲整充 分結合’因此使鲜錫連接（solder joint)之品質及可靠性 大幅增加。 雖然本發明已以前述較佳實施例揭示，然其並非用以 Η 限定本發明’任何熟習此技藝者’在不脫離本發明之精神 和範圍内，當可作各種之更動與修改。例如，在本發明較 佳實施例争，雖然該半導體晶片係利用線接合（wire bonding)的方式電性連接至該球格陣列（BGA)基板，然而 可以理解的是該半導體晶片也可以利用膠捲式自動黏著 (Tape Automated Bonding， TAB)或覆晶接合（fUp_chip bonding)等任一方式與基板電性連接。因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。434757 V. Description of the invention (7) The shorter the electrical path, the smaller the impedance, inductance, and noise. In addition, the smaller inductance value makes the semiconductor package structure consume less power, and makes the integrated circuits and wires inside the chip less susceptible to power surges. According to the method for forming a plurality of tin dot protrusions on the lower surface of a ball grid array (BGA) substrate according to the present invention, a tin axe is used to replace the solder ball, and the cost of kicking paste is low, thereby greatly reducing the material cost. In addition, after the plurality of solder point protrusions are bonded to the circuit board, the quality and reliability of the solder joint are greatly increased because the solder paste is completely melted and fully integrated with the soldering. Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention 'anyone skilled in the art' may make various changes and modifications without departing from the spirit and scope of the present invention. For example, in the preferred embodiment of the present invention, although the semiconductor wafer is electrically connected to the ball grid array (BGA) substrate by wire bonding, it can be understood that the semiconductor wafer can also use film Any method such as Tape Automated Bonding (TAB) or fUp_chip bonding is electrically connected to the substrate. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.

Claims (1)

434757 六、申請專利範固 ' ---- i妒二ί ϋ以在一球格陣列（BGA)基板下表面之複數個得 表面# ί數個錫點突起的方法，該球格陣列（BGA)基板上 面及有—半導體晶片，該方法包含下列步称： ，刷錫膏於該球格陣列（BGA)基板下表面之複數個銲 3E* ，及 UP A、回《輝該鎮f以形成複數個錫點突起於該球格陣列 UA)基板下表命之複數個銲墊。 板下請專利範圍第1項之用以在一球格陣列（bga)基 該锡複數個銲墊形成複數個錫點突起的方法，其中 场貧含有助焊劑。 板;請專利範圍第2項之用以在一球格陣列（BGA)基 該複之複數個銲墊形成複數個錫點突起的方法，其中 取個錫點突起表面具有一層助銲劑。 4、依申 板下表面 該錫膏印 請專利範圍第1項之用以在一球袼陣列（Bga)基 之複數個銲墊形成複數個錫點突起的方法，其中 刷厚度係不大於lmme ϋ '依 板下表 該锡膏 申請專利範圍第4項之用以在一球格陣列（BGA)基 面之複數個銲墊形成複數個錫點突起的方法，其t Ep刷厚度係不大於0. 3mm » '434757 VI. Applying for a patent Fan Gu '---- i envy II ϋ using a method of obtaining a plurality of surfaces on the lower surface of a ball grid array (BGA) substrate # ί several tin dot protrusions, the ball grid array (BGA ) Above the substrate and there is a semiconductor wafer, the method includes the following steps:, brush solder paste on the bottom surface of the ball grid array (BGA) substrate a plurality of solder 3E *, and UP A, back to "glow the town f to form A plurality of solder dots protrude from the ball grid array (UA) substrate. The method of claim 1 of the sub-board patent is used to form a ball grid array (bga) based on a plurality of solder pads to form a plurality of solder point protrusions, wherein the field flux contains a flux. Board; please use the method of item 2 of the patent scope to form a plurality of solder pads on a ball grid array (BGA). The solder bumps have a layer of flux on the surface. 4. According to the solder paste printed on the lower surface of the application board, the method of item 1 of the patent scope is used to form a plurality of solder pads on a ball-gauge array (Bga) base, wherein the thickness of the brush is not greater than lmme. ϋ 'Based on the table below, the method for applying solder paste in patent application No. 4 to form a plurality of solder pads on the base surface of a ball grid array (BGA) base. The method of t Ep brush thickness is not greater than 0. 3mm »'' 4347S 7 利範圍 " ' " " 6、 一種球格陣列（BGA)封裝構造，其係包含： 一基板，具有—上表面及一下表面，該基板下表面設 有複數個銲墊； 一晶片設於該基板上表面，該晶片具有複數個晶片辉 墊位於其正面’其中該複數個晶片銲墊係分別電性連接至 該基板之複數個銲墊；及 複數個錄點突起（solder paste bump)設於該基板下 表面之複數個錫球銲墊。 7、 依申請專利範圍第6項之球格陣列（BGA)封裝構造， 其中該複數個錫點突起表面具有一層助銲劑β 8、 依申請專利範圍第6項之球格陣列（bga)封裝構造， 其中該複數個錫點突起之高度係小Mlmm。 9、 依申請專利範圍第8項之球袼陣列（bga)封裝構造， 其中該複數個錫點突起之高度係小於〇 3mm。4347S 7 Benefits " '" " 6. A ball grid array (BGA) package structure, which includes: a substrate with-an upper surface and a lower surface, the substrate is provided with a plurality of pads on the lower surface; a A wafer is provided on the upper surface of the substrate, and the wafer has a plurality of wafer glow pads on its front side, wherein the plurality of wafer pads are electrically connected to the pads of the substrate respectively; and a plurality of solder paste protrusions (solder paste) A plurality of bumps are provided on the lower surface of the substrate. 7. Ball grid array (BGA) package structure according to item 6 of the patent application, wherein the surface of the plurality of solder point protrusions has a layer of flux β 8. Ball grid array (bga) package structure according to item 6 of the patent application The height of the protrusions of the plurality of tin dots is smaller than Mlmm. 9. According to the ball grid array (bga) package structure according to item 8 of the patent application scope, wherein the height of the plurality of solder point protrusions is less than 0.3 mm. 第12頁Page 12
TW089102974A 2000-02-21 2000-02-21 Method for forming a ball grid array connection TW434757B (en)

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