TW430886B - Method for making semiconductor device with small-sized gate structure - Google Patents

Method for making semiconductor device with small-sized gate structure

Info

Publication number
TW430886B
TW430886B TW88101941A TW88101941A TW430886B TW 430886 B TW430886 B TW 430886B TW 88101941 A TW88101941 A TW 88101941A TW 88101941 A TW88101941 A TW 88101941A TW 430886 B TW430886 B TW 430886B
Authority
TW
Taiwan
Prior art keywords
spacer
dielectric layer
forming
layer
gate
Prior art date
Application number
TW88101941A
Other languages
Chinese (zh)
Inventor
Wei-Je Huang
Ruei-Jen Huang
Shiau-Ling Liu
Tsuei-Rung You
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW88101941A priority Critical patent/TW430886B/en
Application granted granted Critical
Publication of TW430886B publication Critical patent/TW430886B/en

Links

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for making a semiconductor device with a small-sized gate structure comprises two steps of spacer etching. The method comprises forming a gate oxide on the surface of a semiconductor substrate; forming a polysilicon layer on the gate oxide; forming a photoresist layer on the polysilicon layer; using the photoresist layer to define a location of the gate; anisotropically etching the photoresist layer, a portion of the polysilicon layer and the gate oxide; forming a first dielectric layer on the surface of the semiconductor substrate and the surface of the periphery of the polysilicon layer; forming a second dielectric layer on the first dielectric layer; anisotropically etching the second dielectric layer to form a first spacer on the sidewall of the gate; forming a third dielectric layer on the first spacer and the first dielectric layer; anisotropically etching the third dielectric layer to form a second spacer of the gate sidewall; and etching back to make the height of the first spacer and the second spacer lower than the height of the gate structure.
TW88101941A 1999-02-09 1999-02-09 Method for making semiconductor device with small-sized gate structure TW430886B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88101941A TW430886B (en) 1999-02-09 1999-02-09 Method for making semiconductor device with small-sized gate structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88101941A TW430886B (en) 1999-02-09 1999-02-09 Method for making semiconductor device with small-sized gate structure

Publications (1)

Publication Number Publication Date
TW430886B true TW430886B (en) 2001-04-21

Family

ID=21639650

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88101941A TW430886B (en) 1999-02-09 1999-02-09 Method for making semiconductor device with small-sized gate structure

Country Status (1)

Country Link
TW (1) TW430886B (en)

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