1: 2 4 2 8 3 A7 B7 五、發明说明（1 ) 本發明係有關於一種半導體記憶體元件（mem〇ry device)的製程，特別是記憶體元件形成雙閘極氧化層（dual gate oxide)之製程。 以下，請參照第1A圖至第IF圖*其顯示習知快閃記 憶體(flash memory)元件形成雙閘極氧化層的製程剖面圖。 首先，請參照第1A圖，提供一矽基底1〇〇，其形成 有二氧化矽構成的淺溝槽隔離物（shallow trench isolation)SI7，以區分例如記憶體區域之第1區域I與週邊 區域之第2區域Π。並且，上述矽基底1〇具有N型離子 推雜區域12。接著，利用熱成長法全面性在上述第1區域 I及第2區域π之石夕基底10上形成一氧化物構成的絕緣層 14 〇 再者’請參照第1B圖，利用微影製程(photolithography) 形成光阻罩幕（圖未顯示），再利用非等向餘刻法(anisotropic etching)或濕式蝕刻法蝕刻未被光阻罩幕的絕緣層14’以 去除第Π區域的絕緣層14,並且在第1區域I形成一露出 N型離子摻雜區域12的接觸窗18。 然後，請參照第1C圖，利用第1次高溫氧化製程， 在存在氡氣(〇2)的環境下，於裸露的梦基底10的表面形成 二氧化石夕層20。其次，利用微影製程，在第1區域I形成 光阻罩幕22 » 接著’請參照第1C圖以及1D圖，利用光阻罩幕22當作 蝕刻罩幕’並蝕刻去除未被光阻罩幕22覆蓋的二氧化矽 層20，亦卽，蝕刻二氣化矽層20貧到霪出第2區域Π的 本紙认尺度速扣屮围围家榡车（（、NS ) Μ規格（21〇χ297公釐） I n ΙΓ u 1 m n n \ ----El d fn T n I l·— I , 、T (讀先閱讀背面之注意事項再"寫本頁) 4 2 4 2 8 3 A7 ----------------—__________B7_____ 五、發明説明（2 ) 矽基底10表面為止。待蝕刻完成後，剝除光阻罩幕22， 以形成如第1D圖之剖面圖。 其次’請參照第1E圖，施以第2次高溫熱氧化製程， 在存在氧氣的環境下，於第2區域Π形成二氧化矽層24， 並且同時在第1區域I追加氧化，使二氧化矽層2〇轉變成 為二氡化矽層26 ’故其厚度大於第2區域π的二氧化矽層 24的厚度。另外’在第1記憶體區域I的二氧化矽層26 係當作隧穿氧化層使用β 接者’请參照第IF圖’沈積複晶碎層（p0iysilicon )或 是非晶矽層（amorphous silicon)，再進行選擇性蝕刻複晶矽 層或非晶矽層步驟’以在第1區域I形成漂浮閘極電極28b， 並且在第2區域Π形成週邊電路區域之閘極電極28a。 然而，第1區域I之二氧化矽層26係利用二階段熱 氧化製程形成，由於必須覆蓋光阻而後去除，導致二氧化 5夕層26遭雜質污染，無法確保品質。 再者’用以形成二氧化矽層26之第2次《熱氧化製程 之前’具有因光阻罩幕22覆蓋而產生二氧化矽層26含光 阻内雜質的問題，此將嚴重影響記憶體元件性能。 有鑑於此’本發明的目的在於提出一種形成元件雙閘 極氧化層之方法’可避免隧穿氧化層受光阻污染，且僅需 一次熱氧化步驟即可形成。 根據上述目的’本發明提供一種形成元件雙閘極氣化 層之方法’包括下列步驟：（a)提供一石夕基底，其形成有隔 離物以语合篦1菡迠盥篦2區敁.；⑻為卜怵篦1區媸之石夕 —_ 4 本纸队尺度迖ϋΡϋ國家椋卑（（-NS ) Λ4規格（210X297公赶) "一~~~' -_ _ j_ I _ _ I. 4―_ I _ _ τ 1 -- - -I ---- I - -今 1 — 1-=吞 Λ ("先閱讀背面之注意事項再楨朽本頁} A7 424283 B7 五、發明説明（3) 基底上形成一絕緣層；（c)在上述第2區域之矽基底表面形 成一當作閘極氧化層之氮氧矽化合物層，該氮氧矽化合物 層具有第1厚度；（d)選擇性蝕刻該絕緣層以形成一接觸窗； (e)施以熱氧化製程，用以在該接觸窗形成當作閘極氧化層 的二氧化矽層，該二氧化矽層具有第2厚度。 上述形成雙閛極氧化層的方法，其令該隔離物係淺溝 槽隔離物。 上述形成雙閘極氧化層的方法，其令該隔離物係局部 矽氧化物。 再者，上述形成雙閘極氧化層的方法，其中該絕緣層 係氧化層。 並且，形成雙閘極氧化層的方法，其中步驟(c)係在存 在氧化氮或氧化二氮的環境下，利用熱反應爐或快速熱製 程以形成該氮氧矽化合物層。 上述形成雙閘極氧化層的方法，其中該第1厚度小於 第2厚度。 而且，上述形成雙閘極氧化層的方法，其中該接觸窗 與一導電摻雜區域連接。 上述形成雙閘極氧化層的方法，其中該第1區域係記 憶體區域，而該第2區域係週邊區域。 再者，上述形成雙閘極氧化層的方法，其中步驟(b)之 絕緣層形成的方法，係全面性在矽基底上形成一絕緣層， 再選擇性蝕刻該絕緣層，以留下第1區域之絕緣層。 摁播卜诂日砧，太務昍描供s —錄奸揞微开杜嵌ώ # 本紙张尺度追用屮闲阄家摞卑（CNS ) Λ4規格（21 OX 297公釐） --- I l·— - (1 - - - ^ _ n _ _ I--1· _ —L m _ _ 气 I (誚先閱讀背面之注意事項再楨寫本頁) kl 4242831: 2 4 2 8 3 A7 B7 V. Description of the invention (1) The present invention relates to a process of a semiconductor memory device, in particular, the memory device forms a dual gate oxide layer. ) Of the process. Hereinafter, please refer to FIG. 1A to FIG. IF *, which are cross-sectional views showing a process for forming a double gate oxide layer by a conventional flash memory device. First, referring to FIG. 1A, a silicon substrate 100 is provided, and a shallow trench isolation SI7 made of silicon dioxide is formed to distinguish, for example, the first region I of a memory region from a peripheral region. The second area Π. The silicon substrate 10 has an N-type ion doping region 12. Next, a thermal growth method is used to comprehensively form an oxide-containing insulating layer 14 on the stone substrate 10 in the first region I and the second region π. Furthermore, please refer to FIG. 1B and use a photolithography process. ) Forming a photoresist mask (not shown), and then anisotropic etching or wet etching is used to etch the insulating layer 14 ′ that is not the photoresist mask to remove the insulating layer 14 in the Π area A contact window 18 is formed in the first region I to expose the N-type ion doped region 12. Then, referring to FIG. 1C, the first high-temperature oxidation process is used to form a stone dioxide layer 20 on the surface of the bare dream substrate 10 in the presence of radon gas (〇2). Next, a photolithography process is used to form a photoresist mask 22 in the first area I »Next, 'Please refer to FIG. 1C and FIG. 1D, use the photoresist mask 22 as an etching mask' and remove the non-photoresist mask by etching The silicon dioxide layer 20 covered by the curtain 22 is also etched, and the silicon dioxide layer 20 is etched to the extent that it is out of the second area of the paper, and the standard size of the paper is quickly deducted from the surrounding car ((, NS)). χ297 mm) I n ΙΓ u 1 mnn \ ---- El d fn T n I l · — I,, T (read the precautions on the back first and then write this page) 4 2 4 2 8 3 A7 ----------------—__________ B7_____ V. Description of the invention (2) Up to the surface of the silicon substrate 10. After the etching is completed, the photoresist mask 22 is peeled off to form a figure 1D. Secondly, please refer to FIG. 1E, apply the second high-temperature thermal oxidation process, and in the presence of oxygen, form a silicon dioxide layer 24 in the second area Π, and add it in the first area I at the same time. The silicon dioxide layer 20 is converted into a silicon dioxide layer 26 by oxidation, so its thickness is greater than the thickness of the silicon dioxide layer 24 in the second region π. In addition, the silicon dioxide in the first memory region I Layer 26 is used as the tunneling oxide layer. Β-connector 'Please refer to Figure IF' to deposit polycrystalline silicon layer (p0isilicon) or amorphous silicon layer, and then selectively etch the polycrystalline silicon layer or amorphous layer. In the silicon layer step, a floating gate electrode 28b is formed in the first region I, and a gate electrode 28a in the peripheral circuit region is formed in the second region II. However, the silicon dioxide layer 26 in the first region I uses two-stage heat The formation of the oxidation process, because the photoresist must be covered and then removed, resulting in the contamination of the oxide layer 26 with impurities, which cannot ensure the quality. Furthermore, the second "before the thermal oxidation process" used to form the silicon dioxide layer 26 has a cause The problem that the silicon dioxide layer 26 contains impurities in the photoresist is covered by the photoresist mask 22, which will seriously affect the performance of the memory device. In view of this, the object of the present invention is to propose a method for forming a double gate oxide layer of the device. 'The tunneling oxide layer can be prevented from being contaminated by photoresist, and can be formed only by one thermal oxidation step. According to the above object, the present invention provides a method for forming a double-gate gasification layer of an element' including the following steps (A) Provide a Shi Xi base, which is formed with spacers in the language 1 菡 迠 篦 2 敁 敁; ⑻ is the Shi Xi of Bu 怵 篦 1 媸 —_ 4 Paper team standards ((-NS) Λ4 specifications (210X297), " a ~~~ '-_ _ j_ I _ _ I. 4―_ I _ _ τ 1---I ---- I--this 1 — 1- = 吞 Λ (" Read the precautions on the back before dying this page} A7 424283 B7 V. Description of the invention (3) An insulating layer is formed on the substrate; (c) The surface of the silicon substrate in the second area above Forming an oxynitride layer as a gate oxide layer, the oxynitride layer having a first thickness; (d) selectively etching the insulating layer to form a contact window; (e) applying a thermal oxidation process, A silicon dioxide layer serving as a gate oxide layer is formed on the contact window, and the silicon dioxide layer has a second thickness. In the above method for forming a bi-polar oxide layer, the spacer is a shallow trench spacer. The above-mentioned method for forming a double-gate oxide layer makes the spacer a local silicon oxide. Furthermore, in the above method for forming a double-gate oxide layer, the insulating layer is an oxide layer. Moreover, in the method for forming a double-gate oxide layer, step (c) is to form the oxynitride compound layer by using a thermal reaction furnace or a rapid thermal process in an environment where nitrogen oxide or dinitrogen oxide is present. In the method for forming a double-gate oxide layer, the first thickness is smaller than the second thickness. Moreover, in the method for forming a double-gate oxide layer, the contact window is connected to a conductive doped region. In the method for forming a double-gate oxide layer, the first region is a memory region, and the second region is a peripheral region. Furthermore, in the method for forming a double-gate oxide layer, the method for forming the insulating layer in step (b) is to form an insulating layer on a silicon substrate comprehensively, and then selectively etch the insulating layer to leave the first Area insulation.摁 播 卜 诂 日 Anvil, Taiwu 昍 Description for s —Recording 揞 揞 微 开 杜 嵌 ώ # This paper is scaled to follow the size of the paper (CNS) Λ4 size (21 OX 297 mm) --- I l · —-(1---^ _ n _ _ I--1 · _ —L m _ _ Qi I (诮 Please read the notes on the back before writing this page) kl 424283
7 B 102〜導電摻雜區域； 106〜氮氧梦化合物層 no〜閘極氧化層（隧穿層）； 112b〜漂浮閘極電極； Π ~第2區域。 五、發明説明（4) 閘極氧化層之方法，包括下列步驟：（a)提供一矽基底，其 形成有淺溝槽隔離物以區分記憶體區域與週邊區域；（b)在 上述記憶體區域之矽基底上形成一絕緣層：（c)施以氧化氮 或氧化二氮之處理，用以在上述週邊區域之矽基底表面形 成一當作閘極氧化層之氮氧矽化合物層，該氮氧矽化合物 層具有第1厚度；（d)選擇性蝕刻該絕緣層以形成一接觸窗； (e)施以熱氧化製程，用以在該接觸窗形成當作閘極氧化層 的二氧化矽層，該二氧化矽層具有第2厚度。 以下配合圖式以及較佳實施例以詳細說明本發明技 術。 圖式簡單說明 第1A圖至第1F圖為顯示習知記憶體元件形成雙閘極 氧化層的製程剖面圖。 第2A圖至第2E圖為顯示本發明較佳實施例形成雙 閘極氧化層的製程剖面圖。 符號之說明 100〜珍基底； 104〜氧化絕緣層 108〜接觸窗； 112a〜閘極電極 I〜第1區域； 實施例 以下，請參照第2A圖至第2E圖，其顯示本發明較 佳實施例，本實施例利用快閃記憶體及其週邊區域之不同 本紙乐X度述川'丨，阀國家栉窣（（、NS ) Λ4規格（2】0Χ297公釐）7 B 102 ~ conductive doped region; 106 ~ nitrogen oxide compound layer no ~ gate oxide layer (tunneling layer); 112b ~ floating gate electrode; Π ~ second region. V. Description of the Invention (4) The method of gate oxide layer includes the following steps: (a) providing a silicon substrate with a shallow trench spacer formed to distinguish a memory area from a peripheral area; (b) in the above-mentioned memory An insulating layer is formed on the silicon substrate in the region: (c) a treatment with nitrogen oxide or dinitrogen oxide is used to form a silicon oxynitride compound layer on the surface of the silicon substrate in the peripheral region as a gate oxide layer, The silicon oxynitride compound layer has a first thickness; (d) the insulating layer is selectively etched to form a contact window; (e) a thermal oxidation process is performed to form a dioxide as a gate oxide layer on the contact window A silicon layer having a second thickness. The technology of the present invention will be described in detail below with reference to the drawings and preferred embodiments. Brief Description of the Drawings Figures 1A to 1F are cross-sectional views showing a process of forming a double gate oxide layer in a conventional memory device. Figures 2A to 2E are cross-sectional views showing a process of forming a double-gate oxide layer according to a preferred embodiment of the present invention. Explanation of symbols 100 to Jan substrate; 104 to oxide insulating layer 108 to contact window; 112a to gate electrode I to first region; Examples In the following, please refer to FIGS. 2A to 2E, which show the preferred implementation of the present invention. For example, in this embodiment, the flash memory and its surrounding areas are used differently to describe the paper, and the country of the valve (栉 窣, NS) Λ4 specifications (2) 0 × 297 mm
----^---,----------1T------^ , ("先閱讀背面之注意事項再楨寫本頁J 4242 8 3 C7 D7 五、創作説明（5 ) 厚度之閘極氧化層為例，以說明本發明技術，然而，本發 明的適用範圍不限於快閃記憶體。 首先，請參照第2A圖，提供一矽基底10〇，其形成 有二氧化矽構成的淺溝槽隔離物STI，以區分例如記憶體 區域之第1區域I與週邊區域之第2區域π β當然，亦可 利用局部梦氧化物(LOCOS)取代上述淺溝槽隔離物STI » 並且，上述矽基底100具有導電摻雜區域1〇2 ’其係利用 離子（例如N型離子）植入法(i〇n imp】antati〇n)所形成。接 著，在上述第1區域I之矽基底100上形成一例如氧化物 構成的絕緣層104,上述絕緣層1〇4可利用化學氣相沈積 法（chemical vapor deposition ; CVD)或是高溫熱氧化法 (thermal oxidation)全面性形成厚度介於50〜200A的氧化 層，再選擇性蝕刻該氧化層，以露出第2區域Π之矽基底 100表面，而留下第1區域j之氧化絕緣層104。 輕濟部中央梯準局員工消费合作社印製 (請先聞請背面之注意事項再填寫本頁) 然後，請參照第2B圖，利用熱反應爐或快速熱製程， 並且在存在氧化氮(NO)或氧化二氮(N20)的環境下，以在 第2區域Π形成厚度介於l〇A〜50A的氮氧矽化合物層106， 由於第1區域I的表面具有絕緣層104,氮不易穿透絕緣 層104與>6夕基底反應而僅形成極少量的氮氧硬化合物層。 再者’請參照第2C圖，利用微影製程形成光阻罩幕（圖 未顯示）’以及非等向蝕刻步驟蝕刻未被光阻罩幕的絕緣層 1〇4 ’以形成一露出導電摻雜區域1〇2的接觸窗1〇8。 然後，請參照第2D圖，施以溫度約為1000°C的熱氧 化高溫製程（熱反應爐或是快速熱製程），並且在含有氧氧 本紙張尺度適用中國國家榡準（CNS ) ( 210X297公* > A7 424283 B7---- ^ ---, ---------- 1T ------ ^, (" Read the precautions on the back before writing this page J 4242 8 3 C7 D7 V. Creation Note (5) The thickness of the gate oxide layer is taken as an example to illustrate the technology of the present invention. However, the scope of application of the present invention is not limited to flash memory. First, referring to FIG. 2A, a silicon substrate 100 is provided. A shallow trench spacer STI made of silicon dioxide is formed to distinguish, for example, the first region I of the memory region from the second region π β of the peripheral region. Of course, a local dream oxide (LOCOS) can also be used to replace the shallow trench. Trench Isolator STI »Furthermore, the silicon substrate 100 has a conductive doped region 10 2 ′, which is formed by an ion (eg, N-type ion) implantation method (io n imp) antation. An insulating layer 104 made of, for example, an oxide is formed on the silicon substrate 100 in the first region I. The insulating layer 104 can be formed by chemical vapor deposition (CVD) or high temperature thermal oxidation. ) Comprehensively form an oxide layer with a thickness of 50 ~ 200A, and then selectively etch the oxide layer to expose the second region Π The silicon substrate 100 surface, leaving the oxide insulation layer 104 in the first area j. Printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Light Industry (please listen to the precautions on the back before filling out this page) Then, please refer to Section 2B Figure, using a thermal reactor or rapid thermal process, and in the presence of nitrogen oxide (NO) or dinitrogen oxide (N20), to form a nitrogen oxysilicon compound with a thickness between 10A and 50A in the second region. The layer 106 has an insulating layer 104 on the surface of the first region I, and it is difficult for nitrogen to penetrate the insulating layer 104 and react with the substrate, and only a small amount of the oxynitride layer is formed. Furthermore, please refer to FIG. 2C, The photolithography process is used to form a photoresist mask (not shown) and the non-isotropic etching step is used to etch the insulating layer 104 that is not the photoresist mask to form a contact window 1 that exposes the conductive doped region 102. 〇 8. Then, please refer to Figure 2D, apply a thermal oxidation high temperature process (thermal reaction furnace or rapid thermal process) with a temperature of about 1000 ° C, and apply the Chinese National Standard (CNS) for the paper containing oxygen and oxygen. ) (210X297 male * > A7 424283 B7
..... · · · 一 - --r I I . --- ι· I —丨丨· 'm I m · < 五、發明说明（6) 的環境下’使接觸窗108所露出的矽基底100表面與氧反 應以形成二氧化矽構成的閘極氧化層110,其厚度介於 6〇A~15〇A之間’ 1且本實施例之閘極氧化層11〇亦即快閃 記憶體的随穿氧化層（tunnel oxide)。此時，因為第2區域 Π己形成有氮氧矽化合物層106,故氧不易穿透至ί夕基底 100，故第2區域Π僅形成極薄的二氧化矽層。 接著，請參照第2Ε圖，利用同步(in-situ)植入的化學 氣相沈積法沈積複晶碎層（polysilicon )或是非晶;g夕層 (amorphous silicon)，再進行選擇性蝕刻複晶矽層或非晶石夕 層步驟，以在第1區域I形成漂浮閘極電極112b，並且在 第2區域π形成週邊電路區域之閘極電極112a。 由於，本實施例之氮氧矽化合物層106的厚度小於二 氧化梦層所構成的閘極氧化層110’故可實現雙閉極氧化 層元件。當然’本發明不限於此’可視需要使氮氧發化合 物層106的厚度大於閘極氧化層110。 發明特徵及效果 本發明之特徵為利用氧化氮或是氧化二氮在第2區域 11形成氮氧矽化合物層，然後藉由氮氧矽化合物與二氧化 石夕不同的性質以實現元件雙閘極氧化層的目的。 本發明之隧穿氧化層未受光阻罩幕的污染，再者，— 次熱氧化製程即可形成’故可解決習知問題，得到可靠度 高的二氧化矽層，以確保記憶體元件性能。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者’在不脫離本發明之精 本紙張尺度过川屮闽阀家棉卑（d ) Λ4規格（2丨0Χ 297公釐） (讀先閲讀背面之注意事項再楨荇本頁)..... ··· 一---r II. --- ι · I — 丨 丨 'm I m · < V. Under the environment of the description of invention (6)' make the contact window 108 exposed The surface of the silicon substrate 100 reacts with oxygen to form a gate oxide layer 110 composed of silicon dioxide, the thickness of which is between 60A and 150A, and the gate oxide layer 11 of this embodiment is flash. Tunnel oxide of the memory. At this time, since the silicon oxynitride compound layer 106 has been formed in the second region Π, it is difficult for oxygen to penetrate to the substrate 100, so that only a very thin silicon dioxide layer is formed in the second region Π. Next, referring to FIG. 2E, a polysilicon layer or an amorphous silicon layer is deposited by in-situ implanted chemical vapor deposition, and then selective etching of the polycrystal is performed. In a silicon layer or an amorphous stone layer step, a floating gate electrode 112b is formed in the first region I, and a gate electrode 112a in a peripheral circuit region is formed in the second region π. Since the thickness of the oxynitride silicon compound layer 106 in this embodiment is smaller than that of the gate oxide layer 110 'composed of the dream layer, a double-closed oxide layer element can be realized. Of course, the present invention is not limited to this. The thickness of the oxynitride layer 106 may be greater than that of the gate oxide layer 110 as needed. Features and effects of the present invention The feature of the present invention is to form a oxynitride layer in the second region 11 by using nitrogen oxide or dinitrogen oxide, and then realize the double gate of the device by using different properties of the oxynitride compound and stone dioxide. The purpose of the oxide layer. The tunneling oxide layer of the present invention is not contaminated by the photoresist mask, and in addition, the secondary thermal oxidation process can form 'so it can solve the conventional problems and obtain a highly reliable silicon dioxide layer to ensure the performance of the memory element. . Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art will not pass through the Sichuan, Fujian, and Fujian Provinces of Cotton (d) Λ4 without departing from the fine paper size of the present invention. Specifications (2 丨 0 × 297 mm) (Read the precautions on the back before reading this page)
-'1T ά ! 4242 8 3 A7 B7 五、發明説明（7) 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。 9 ------------' '广------訂-----^--峨 1 (誚先閱讀背面之注意事項再楨寫本K ) 本纸张尺度迖用中阐阈家標準（CNS ) Λ4规梠（2IOXW7公釐）-'1T ά! 4242 8 3 A7 B7 5. Description of the invention (7) Within the scope of God and God, changes and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. 9 ------------ '' Guang ------ Order ----- ^-E 1 (诮 Read the notes on the back before writing K) Dimensions of this paper 迖Introducing the Chinese Standard for Standards (CNS) Λ4 gauge (2IOXW7 mm)