TW419768B - Ball grid array (BGA) semiconductor package and method of manufacturing the same - Google Patents
Ball grid array (BGA) semiconductor package and method of manufacturing the same Download PDFInfo
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- TW419768B TW419768B TW087103980A TW87103980A TW419768B TW 419768 B TW419768 B TW 419768B TW 087103980 A TW087103980 A TW 087103980A TW 87103980 A TW87103980 A TW 87103980A TW 419768 B TW419768 B TW 419768B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
經濟部中央標準局員工消費合作社印裝 419768 A7 ____B7_ 五、發明説明(ί ) 發明之背景 <發明之範圍> 本發明是有關一種球格陣列(BGA)半導體包裝及其製 造方法。 <相關技藝之說明> 半導體晶片係以在半導體包裝中的導線架來支撐,而 導線架的支腳則將半導體晶片連接至外電路,特別地,BGA 半導體包裝係通過一附在支腳的銲球連接至外電路。 同時’傳統用以作為BGA半導體包裝之「導線架係以三菱
瓦斯化學公司(Mitsubishi gas chemical co.,Ltd.)的BT 樹脂來來形成。此導線舞係利用一蝕刻一印刷電路板的方 法來形成’且具有通過一設於導線架之基片的通孔而電氣 連接的上、下部份。 然而,傳統半導體包裝的導線架之基片係以樹脂(聚 合物樹脂)所形成,其價格昂貴’需姜密集勞力,而且電 氣與熱穩定性不夠。特別地,典型的薄膜型基片會由於晶 片或周圍的元件所產生的熱而破損。 而且,金屬導線架係以半蝕刻法(half-etching)製 成,其中,在製造精細的間矩部份(fine pitch portion) 會留下一預定的部份。然而,在半姓刻中,於一厚的材料 内製造精細的間矩部份(fine pitch port ion)是很困難 的’其尺寸的穩定性會由於過度蝕刻而喪失,也可能由於 在蝕刻之後所引起的應力而產生變形》 . <發明之總論:> 3 本紙浪尺度適用中國國家標準(CNS M4規格(210X297公釐) ^ (請先閲讀背面之注意事項再填寫本育)
8 Α7 Β7 4l9T6 五、發明説明(>) 為了解決上述的問題,本發明的一目的乃在提供一 =格陣列(BGA)半導體包裝’其具有電氣與熱的穩定性,較 '、的變形,較簡單的製程與穩定的量測;以及,其製造 法0 、 — 因此,為了達成本發明上述之目的,本發明乃在提供 丰2匕3有以鮮線連接支腳至半導體晶片之網格陣列(BGA) ‘體包裝,其包括:在每個支腳上的導電墨的部份,以 ^一附在每個要連接至外基片的端子之導電墨部份的銲 球。 - ]又’本發明的製造一BGA半導體包裝的製造方法包括下 列步驟:(a)把導電墨部、份被覆在支腳上;(b)將半導體晶 1之端子引線接合至導線架的支腳並將以引線接合後的二 造以樹脂封裝;以及(c)將導電墨的部份連接至與外基片的 端子相連接的銲球。 、土 <圖示的簡單說明〉 本發明上述的目的與優點’參照下列依關所作之說 明將可更為明白,附圖者: 第1圖係-使用來作為本發明之球格陣列(㈣,半導 體包裝的導線架之平面圊; 第2圖係第1圖之a部份的放大平面圖; 第3圖係第2圖之B部份的截面圖,· 第4圖係-截面圖表示-導線架,其係採賴造的 (coined)導電墨; 第5圖係一模製的半導體包裝之截面圖; 表紙莰以適用中國圉家福準(CNS)A4__( 2敝297公装) I.-------i^.------IT----^---A: {請先閎讀背面之注意事項再填寫本頁) 經濟部中央樣準局員工消費合作社印製 41 41 經 濟 部 中 央 標 準 局 工 消 合 作 社 印 裝 B7 五、發明説明㈠) '--- =ΠίΓ勻高度之導電墨的截面圖; 表面係朗I 找顿關,其巾—模麵脂層的 =:一 Γ 一鮮球之半導體包裝的截面圖; 弟圖係—底面圖’顯示第8圖的銲球排列。 <圖示中元件名稱與符號對照〉 2〇 :導線架 21 :墊片 22 :支腳 24:絕緣帶 25 :導電墨 26 :接合帶 27 :金線 28 :銲球 29:模塑樹脂 30:半導體晶片 <較佳具體實施例的詳細描述> 依照本發明之球格陣列(B G A)所使用的導線架2 0包含 一般設一半導體晶片的墊片21,以及連接至要與外端子連 接的半導體晶片的電子端子支腳22,其情形如第1圖所示。 導線架20係使用一種化學蝕刻法或一種機械衝壓法來 形成,導線架20係以例如銅、銅合金或鎳一鐵合金的一種 金屬來製成。 請參看第2圖’一絕緣帶24係貼附在導線架20之支腳22 本紙張尺度適用中國國家標準(CNS)Α4说格(210x297公釐) iI------—------ΐτ-------Λ (諳先閏讀背面之注意事項再填寫本頁) M濟部中央標準扃男工消費合作社印製 " Α7 Β7 五、發明説明(4) 的上表面,以增強支腳22並於支腳之間維持預定之間隔。 每一個支腳22係以導電墨(conductive ink)25之一個 部份所被覆,較佳的導電液係銅 '金、銀、叙、錢或其合 金。 請參看第3圖,支架22上的導電墨25的部份有一橢圓形 的截面。導電墨25可用許多方法被覆於支架的上表面,例 如’利用絲屏印刷(silk screen printing),或利用使用 一金屬掩模(metal mask),噴射(injecti〇n)與擠出 (dispensing),或打點(dotting)法。 以上述的方法所被覆的導電墨25形成如第4圖所示的 近似直角之截面’而通過讀造製成平坦β在此時,較佳的, 導電墨25的高度是與絕緣帶24相等或較高。 較佳地,為了防止導電墨在鑄造程序變形或破壞,於 鑄造程序之前,先進行乾燥導電液的預先燒烤程序(pre一 curing)。而且,較佳地,並利用後燒烤(公⑽卜⑶以叩)來 防止導電液於鑄造程序之後變形。 如第5圖所’在铸造導電墨25以後,一半導體晶片3〇 係利用一接合帶26貼附在一晶粒墊(die pad)21的上表面。 半導體晶片30的端子並利用一金線27連接至支腳22。 然後’導線架乃被封裝於一模塑樹脂29之中,而一從 模塑樹脂29穿透的導線架支架22乃被去除,在此時,導電 墨25之一表面乃從模塑樹脂29暴露出來。 此處,如第6圖所示,當導電液的部份的高度並不均勻 而導致導電墨25不露出時,銲球28並不能與之形成電器連 ----------袭------1Γ----^---\ (諳先閲讀背面之注意事項再填寫本頁) 本紙柒尺度適用中國國家榡準(CNS ) A4規格(210.X29?公釐) 'r \ A7 B7 五、發明説明(ς:) 接。如此’如苐7圖所示,模塑樹脂層係接地, 從低於模塑樹脂層中露出。 文導電墨 ^ ^电墨25可被連接至銲球28,其情形如第8_所_ ^ 著使用β一周知的銲接方法,即可使銲球與錯接觸。不’藉 拜球28係利用模塑樹脂29與導電墨烈的表 球28係通過引線接合至半導體晶片洲之支腳與=銲 連接至一外裝置的連接端子。 I液電氣 結果,在半導體包裝之中,鲜球乃交互成列 圖所示,藉以連接至裝設於一小區域中的不_ +依本發明的半導體包裝,導電液係被覆於導線架 上’藉以維持其穩定的大小,簡化其製程,且降低其成本。、 以上關於具體實施例之描述乃僅供說明與舉例之用, 而非用以對本發明做任何限制者。本發明之精神與範嘴, 乃僅由所附申請專利範圍各項來限制,特此聲明。 f祷先閱讀背面之注意事項再填寫本頁} 訂 € 經濟部中央標举局荑工消費合作社印裝 本紙張尺纽财醜^^T^rrA4i£i"( 210
Claims (1)
- 41976b、申請專利範圍 L —種球格陣列〇bga)半導體包裝,其含有利用引線接合 法連接至一半導體晶片之支腳;包括: 设在每一個支腳上的導電墨部份;以及 一銲球,係貼附在每一個要連接至一外基片的端子的 導電墨。 2.如申請專利範圍第1項之球格陣列(BGA)半導體包裝, 其中導電墨的部份係透過鑄造法(coining)以形成平 面。 3·如申請專利範圍第1項之球格陣列(BGA)半導體包裝, 其中導電墨係以包括鋼 '銀、金、鈀、鍺或其合金的 一種選擇出來的。. 4·如申請專利範圍第1項之球格陣列(BGA)半導體包裝, 其中銲球乃彼此交叉。 5‘如宇請專利範圍第丨項之球格陣列(BGA)半導體包裝, 其更包括一闬以維持支架之間的間隙的絕緣帶。 6,如申請專利範圍第1項之球格陣列(BGA)半導體包裝, 其中鲜球係呈-行-行交叉排列,而間隔行的排列為 相同。 經濟部令央揉卒局貝工消費合作社印¾ 先閡讀背面之注意亭哼再填寫本頁) 訂 7.種製造—ββΑ半導體包裝的方法,包括下列步驟: (a) 把導電墨部份被覆在支腳上; (b) 將半導體晶片之端子引線接合至導線架的支腳並 將以51線接合後的構造以樹脂封裝;以及 (c) 將導電墨的部份連接至與外基月的端子相連接的 銲球。 419768 C8 D8 '經濟部中央橾準局貝工消費合作社印裳 六、申請專利範圍 利*圍第7項之製造方法,其中導線架等之金 屬基板(㈣丨substrate)係從包括 鐵合金的群中選擇出來的。 n 戈錄 9.如^專利範圍第7項之製造方法,其中⑷步驟包括 LC〇lng)V電墨的部份以將導電墨作成平坦者。 二項之製造方法,其嶋驟係透 。括下列方法的-種來執行的:絲屏印刷(贿郎 =了);使用—金屬掩模的方法、使用喷射 •擠出(如―)的方法,與或打點 (dotting)法者。 11‘如申請專職項之製造方法,其 作成扁平以將導電墨從模塑樹脂底下暴= 來。 12.如申請專利範圍第9項之製造方法,其中步 在進行鑄造程序之前,先進行乾燥導電墨的預先燒烤 程序,以防止導電墨錢造料變形或破損者^ 13·如申請專利範圍第12項之製造方法,其中步驟⑷包括 在鱗造導電墨的部份以後,進行一後燒烤步驟來防止 導電墨於鏵造程序後的變形者。 請 先 閎 1¾ 之 注 意 事 項 再 t 訂 本纸故尺度逍用中國國家標準(CNS ) A4規格(210父297公楚,)
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KR1019970009483A KR100243375B1 (ko) | 1997-03-20 | 1997-03-20 | 비지에이 반도체 패키지와 그 제조방법 |
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TW419768B true TW419768B (en) | 2001-01-21 |
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Application Number | Title | Priority Date | Filing Date |
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TW087103980A TW419768B (en) | 1997-03-20 | 1998-03-18 | Ball grid array (BGA) semiconductor package and method of manufacturing the same |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPH10270597A (zh) |
KR (1) | KR100243375B1 (zh) |
TW (1) | TW419768B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102023100B1 (ko) | 2018-05-15 | 2019-11-04 | 주식회사 네패스 | 반도체 패키지 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2837355B2 (ja) * | 1994-09-09 | 1998-12-16 | 川崎製鉄株式会社 | 半導体icチップのパッケージ及びその製造方法並びにリード・フレーム |
-
1997
- 1997-03-20 KR KR1019970009483A patent/KR100243375B1/ko not_active IP Right Cessation
-
1998
- 1998-03-18 TW TW087103980A patent/TW419768B/zh not_active IP Right Cessation
- 1998-03-19 JP JP10069676A patent/JPH10270597A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
KR19980073899A (ko) | 1998-11-05 |
JPH10270597A (ja) | 1998-10-09 |
KR100243375B1 (ko) | 2000-02-01 |
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