TW396617B - Manufacturing method of memory cell capacitor for dynamic random access memory in semiconductor device - Google Patents
Manufacturing method of memory cell capacitor for dynamic random access memory in semiconductor device Download PDFInfo
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- TW396617B TW396617B TW087119952A TW87119952A TW396617B TW 396617 B TW396617 B TW 396617B TW 087119952 A TW087119952 A TW 087119952A TW 87119952 A TW87119952 A TW 87119952A TW 396617 B TW396617 B TW 396617B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 239000003990 capacitor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 239000000463 material Substances 0.000 claims abstract description 107
- 238000000034 method Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 125000006850 spacer group Chemical group 0.000 claims abstract description 8
- 238000003860 storage Methods 0.000 claims description 57
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 16
- 235000015170 shellfish Nutrition 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 230000002079 cooperative effect Effects 0.000 claims description 4
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 1
- 230000003472 neutralizing effect Effects 0.000 claims 1
- 238000002955 isolation Methods 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 168
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 30
- 229910052814 silicon oxide Inorganic materials 0.000 description 22
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 239000004576 sand Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005272 metallurgy Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
4 I 62pif.doc/002 A7 B7 五、發明説明（） 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種半導體元件中動態隨機存取記憶體（DRAM) 記憶胞的製造方法，其可以形成自行對準於下層之接觸窗 開口（ contact hole )的儲存節（storage node )。 在一小面積中獲取足夠之儲存電荷的靜電容量 (capacitance)，是超大型積體電路（ULSI)之動態隨機 存取記憶體（DRAM)的技術中，最具挑戰性的設計問題 之一。由於受高密度DRAM增加的激勵，每一記憶胞 (memory cell)之電荷儲存（charge-storage)元件必須能 適用於越來越小的面積中。由於縮小記憶胞面積而造成胞 靜電容量的減少，對於增加DRAM的堆疊密度（packing-density)是一嚴重的阻礙。因此，胞靜電容量減少的問題， 必須予以解決以獲得高堆疊密度之半導體記憶元件。 爲了使靜電容量保持在可接受値，已經有許多方法被 提出。舉例來說，一種方式是使用高電容率（permittivity) 之介電材料，例如BST以做爲電容器的介電層。另一種方 式是藉由增加起伏的表面，例如堆疊（stacked)電容器而 增加電容器的表面積。此種堆疊電容器包括，例如雙重堆 疊、鰭狀堆疊（fin stacked)、柱狀、伸展堆疊（spread-stacked) 和盒型結構 （box structured) 的電容器。 既然可以利用外表面和內表面以做爲有效的電容面 積，所以柱狀結構最適合做爲三度空間之堆疊電容器，而 且特別適合做爲積體記憶胞。最近’新技術已發展出藉由 雕刻（engraving)或控制多晶矽之成核（nucleation)與長 5 本紙張尺度適用中國圉家標準（CNS ) A4^ ( 210Χ297公釐） ^------------«.— (請先閲讀背面之注意事項再填寫本頁) 、ΤΓ 經濟部中央標率局貝工消费合作社印装 4I62pif.doc/002 A7 B7 經濟部中央標率局貝工消费合作社印製 五、發明説明（） 晶的狀況，而修改多晶矽儲存電極之表面型態，進而增加 有效的表面積。在儲存節上沈積〜層半球型晶粒 (hemispherical-grain ; HSG)多晶砂層，可用以增加表面 積和靜電容量。 近年來’ lGiga位元與超過lGiga位元以上之DRAM 堆疊電容胞較引人注意，這是因爲有多種形成電容器的方 式，且由胞的區域往上延伸，因此增加了靜電容量卻無須 在基底上增加額外的面積。此種堆疊結構的製程已經變的 相當複雜，且所需之微影技術在目前或未來已經無法和非 常小的尺寸需求一致。 第2A圖至第2C圖係繪示傳統式製造DRAM胞之步驟 的流程圖。在此必須指出的是第1圖（依據本發明之實施 例之DRAM元件的佈局圖）係用以解釋習知之方法。第 2A圖至第2C圖係第1圖中沿著A1-A1’的剖面圖。 請參照第1圖和第2A圖，在半導體基底1上形成元件 隔離層3，以定義儲存節接觸窗區2a至2c和位兀線接觸 窗區（圖中未顯示）。正如眾所周知’在半導體基底1上 形成數個閘極結構（圖中未顯示）°在半導體基底1上和 字元線上形成一第一氧化矽層4a。在橫越字兀線之第一氧 化矽層上形成數個位元線BL1至BL4 ’其穿過弟一氧化砂 層4a中之接觸窗開口（圖中未顯示）’而與位元線接觸窗 區電性連接。接著在第一氧化矽層4a上和位兀線BL1至 BL4上形成一第二氧化矽層4b。 請參照第2B圖，蝕刻第一氧化矽層4a和第一氧化矽 6 (請先閲讀背面之注意事項再填寫本頁) 袭· 訂 <ΓΙ. 本紙張尺度適用中國國家標準（CNS ) A4^格（210X297公楚） A7 B7 4 I 62pif.doc/002 五、發明説明（） 層4b，而形成數個儲存節接觸窗開口 6a至6c，且暴露出 儲存節接觸窗區2a至2c。之後，在儲存節接觸窗開口 6a 至6c中和第二氧化矽層4b上，沈積由多晶矽層8所組成 之導電層。在多晶矽層8上沈積一光阻層（圖中未顯示）， 並且進行圖案化以定義儲存節區域。然後藉由使用光阻圖 案而蝕刻多晶矽層8 ’因此形成數個儲存節8a至8c，如第 2C圖所示。 之後，在儲存節8a至8c上沈積一介電薄層（圖中未 顯示）和一上電極材料層（圖中未顯示）。 在上述的方法中，通常對多晶矽層進行過蝕刻（overetch) ， 用以使每一儲存節彼此之間呈電性隔離。 在此過 飩刻的程序中，假使發生對準失誤，則有一部份塡入於接 觸窗開口之多晶矽層會被蝕刻掉，尤其是在接觸窗開口頂 端邊緣的周圍。況且，於後續的淸潔步驟中，在儲存節之 間的一部份第二氧化矽層會被移除（亦即底切現象），因 此第二氧化矽層可能無法支撐儲存節，且儲存節可能會倒 下。這些問題在極高密度的元件中變的嚴重，且這些在 lGiga位元或以上者都無法避免。 第3A圖至第3C圖係繪示依據另一習知方法，一種製 造DRAM胞電容器之步驟的流程示意圖。在第3A圖至第 3C圖中’如第2A圖至第2C圖所示之相同部份功能係用 相同之參考號碼，且省略它們的解釋。請參照第3A圖， 在形成數個接觸窗開口 6a至6c後，於儲存節接觸窗開口 6a至6c中，沈積由多晶矽層10所組成之第一導電層，因 7 本紙張尺度適用中國國家揉準（CNS ) A4祝格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)4 I 62pif.doc / 002 A7 B7 V. Description of the invention The invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a dynamic random access memory (DRAM) memory cell in a semiconductor device. It can form a storage node that aligns itself with the contact hole in the lower layer. Capacitance to obtain enough stored charge in a small area is one of the most challenging design issues in the dynamic random access memory (DRAM) technology of ultra large integrated circuit (ULSI). Due to the increased incentive of high-density DRAM, the charge-storage elements of each memory cell must be able to fit into smaller and smaller areas. The reduction of the cell's electrostatic capacity due to shrinking the memory cell area is a serious obstacle to increasing the packing-density of the DRAM. Therefore, the problem of reducing the cell capacitance must be solved to obtain a semiconductor memory element with a high stack density. In order to keep the electrostatic capacity at an acceptable level, many methods have been proposed. For example, one way is to use a high permittivity dielectric material, such as BST, as the dielectric layer of the capacitor. Another approach is to increase the surface area of the capacitor by adding undulating surfaces, such as stacked capacitors. Such stacked capacitors include, for example, double stacked, fin stacked, columnar, spread-stacked, and box structured capacitors. Since the outer and inner surfaces can be used as effective capacitor areas, the columnar structure is most suitable as a three-dimensional stacked capacitor, and it is particularly suitable as an integrated memory cell. Recently, the new technology has been developed by engraving or controlling the nucleation of polycrystalline silicon and the length of 5 papers. The Chinese paper standard (CNS) A4 ^ (210 × 297 mm) ^ ------ ------ «.— (Please read the notes on the back before filling in this page), ΤΓ Printed by the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 4I62pif.doc / 002 A7 B7 Printed by the Industrial and Consumer Cooperatives. 5. Description of the invention () The state of the polycrystalline silicon storage electrode is modified, thereby increasing the effective surface area. A layer of hemispherical-grain (HSG) polycrystalline sand is deposited on the storage node to increase the surface area and electrostatic capacity. In recent years, 'lGiga bits and DRAM stacked capacitor cells with more than lGiga bits have attracted more attention. This is because there are many ways to form capacitors and extend from the cell area, so the increased electrostatic capacity does not need to be on the substrate. Add extra area. The manufacturing process of such a stacked structure has become quite complicated, and the required lithography technology will not be consistent with the very small size requirements at present or in the future. Figures 2A to 2C are flowcharts showing the steps of conventionally manufacturing a DRAM cell. It must be noted here that FIG. 1 (layout diagram of a DRAM element according to an embodiment of the present invention) is used to explain a conventional method. Figures 2A to 2C are sectional views taken along line A1-A1 'in Figure 1. Referring to FIG. 1 and FIG. 2A, an element isolation layer 3 is formed on the semiconductor substrate 1 to define storage node contact window regions 2a to 2c and bit line contact window regions (not shown in the figure). As is well known, a plurality of gate structures are formed on the semiconductor substrate 1 (not shown). A first silicon oxide layer 4a is formed on the semiconductor substrate 1 and on the word lines. A plurality of bit lines BL1 to BL4 are formed on the first silicon oxide layer crossing the word line 'through the contact window opening (not shown) in the first sand layer 4a' to contact the bit line. Zone electrical connection. Next, a second silicon oxide layer 4b is formed on the first silicon oxide layer 4a and the bit lines BL1 to BL4. Please refer to Figure 2B, and etch the first silicon oxide layer 4a and the first silicon oxide 6 (Please read the precautions on the back before filling in this page). Order < Γ. This paper size applies Chinese National Standard (CNS) A4 ^ (210X297) Chu A7 B7 4 I 62pif.doc / 002 V. Description of the invention () Layer 4b, forming several storage node contact window openings 6a to 6c, and exposing the storage node contact window areas 2a to 2c. Thereafter, a conductive layer composed of a polycrystalline silicon layer 8 is deposited on the storage node contact window openings 6a to 6c and on the second silicon oxide layer 4b. A photoresist layer (not shown) is deposited on the polycrystalline silicon layer 8 and patterned to define a storage node area. The polycrystalline silicon layer 8 'is then etched by using a photoresist pattern, thereby forming a plurality of storage sections 8a to 8c, as shown in FIG. 2C. Thereafter, a thin dielectric layer (not shown) and an upper electrode material layer (not shown) are deposited on the storage nodes 8a to 8c. In the above method, the polycrystalline silicon layer is usually overetched to electrically isolate each storage node from each other. During this engraving procedure, if an alignment error occurs, a portion of the polycrystalline silicon layer that is embedded in the contact window opening will be etched away, especially around the top edge of the contact window opening. Moreover, in the subsequent cleaning step, a part of the second silicon oxide layer between the storage nodes will be removed (that is, an undercut phenomenon), so the second silicon oxide layer may not be able to support the storage node, and the storage Festival may fall. These problems are exacerbated in extremely high-density components, and these cannot be avoided at lGiga bits or more. Figures 3A to 3C are schematic flowcharts showing a step of manufacturing a DRAM cell capacitor according to another conventional method. In FIGS. 3A to 3C, the same parts as those shown in FIGS. 2A to 2C are assigned the same reference numbers, and their explanations are omitted. Please refer to FIG. 3A. After forming a plurality of contact window openings 6a to 6c, a first conductive layer composed of a polycrystalline silicon layer 10 is deposited in the storage node contact window openings 6a to 6c. CNS A4 Zhuge (210X297mm) (Please read the precautions on the back before filling this page)
經濟部中央標準局貝工消费合作社印製 經濟部中央揉率局貝工消费合作社印装 4 I 62pif.doc/002 Λ 7 B7 _ 五、發明説明（） 而形成數個接觸窗插塞l〇a至10c。 請參照第3B圖，在第二氧化矽層4b上和接觸窗插塞 10a至10c上形成一第三氧化矽層（圖中未顯示）。在第 三氧化矽層上沈積一光阻圖案（圖中未顯示），並且蝕刻 第三氧化矽層以形成數個儲存節的架構（圖中未顯示）， 其將爲第二導電層沈積之處。這些架構，即第二接觸窗開 口，暴露出接觸窗插塞l〇a至10c的上表面。以第二導電 層塡滿這些架構，並且進行平坦化。接著，以乾式或濕式 蝕刻移除氧化物之架構，因而形成數個儲存節12a至12c， 如第3 B圖中所示。 然而，此製造使用了兩次照光步驟，用以定義儲存節 接觸窗插塞和儲存節，這些均造成了製程的複雜性。此 外，移除氧化物架構的步驟控制不易，如果是過蝕刻，則 架構中的多晶矽可能會被蝕刻到，且嚴重時甚至會暴露出 位元線。因此，在形成上電極層的步驟時，暴露出之位元 線易於受到攻擊。 爲了避免位元線受到攻擊，可以在第二和第三氧化矽 層之間形成一蝕刻終止層，例如氮化矽層5，如第3C圖中 所示。甚至在形成蝕刻終止層5之後，於進行過蝕刻和淸 潔的程序時，會由於對準失誤而發生底切現象（參照圖中 所呈現之13)。這將導致電流遺漏（current leakage)的 增加，以及後續之電容器上電極的階梯覆蓋（step coverage )變差。 本發明係針對上述問題，因此本發明的目的之一就是 8 尺度適用中國國家標準（CNS )八4#見格（210X297:釐) ~ " (請先閲讀背面之注意事項再填寫本頁) • 1— i —1 ·Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Printed by the Shellfish Consumer Cooperative of the Central Rubbing Bureau of the Ministry of Economy. 4 I 62pif.doc / 002 Λ 7 B7 _ V. Description of the invention () and formed several contact window plugs l〇 a to 10c. Referring to FIG. 3B, a third silicon oxide layer (not shown) is formed on the second silicon oxide layer 4b and the contact window plugs 10a to 10c. A photoresist pattern (not shown) is deposited on the third silicon oxide layer, and the third silicon oxide layer is etched to form a structure of several storage nodes (not shown in the figure), which will be deposited for the second conductive layer. Office. These structures, the second contact window openings, expose the upper surfaces of the contact window plugs 10a to 10c. These structures are filled with a second conductive layer and planarized. Next, the oxide structure is removed by dry or wet etching, thereby forming several storage sections 12a to 12c, as shown in FIG. 3B. However, this manufacturing process uses two illumination steps to define the storage node, the contact window plug, and the storage node, which all complicate the process. In addition, the step of removing the oxide structure is not easy to control. If it is over-etched, the polycrystalline silicon in the structure may be etched, and bit lines may even be exposed in severe cases. Therefore, during the step of forming the upper electrode layer, the exposed bit lines are susceptible to attack. In order to prevent the bit line from being attacked, an etch stop layer such as a silicon nitride layer 5 may be formed between the second and third silicon oxide layers, as shown in FIG. 3C. Even after the etching stop layer 5 is formed, an undercut phenomenon occurs due to misalignment during the etching and cleaning processes (see 13 in the figure). This will lead to an increase in current leakage and subsequent step coverage of the electrodes on the capacitor. The present invention is directed to the above-mentioned problems, so one of the purposes of the present invention is to apply the Chinese National Standard (CNS) 8 # # 格 (210X297:)) to 8-scale ~ (Please read the precautions on the back before filling this page) • 1— i —1 ·
、1T 4l62pif.doc/002 A7 4l62pif.doc/002 A7 經濟部中央梂準局貝工消费合作社印製 五、發明说明（ 在提供-種半導體兀件中dram胞電容器的製造方法，其 可以形成相對於妾觸窗插塞之自行對準的儲存節，因此可 以避免儲存節和儲存節接觸窗開口之間的對準失誤。 依據本發明之上述和其他目的，可以藉^在二半導體 基底上形成-場效電晶體而加以瞭解。此場效電晶體包^ -閘極’其上具有—絕緣層和絕緣側壁間關，且在此場 效結構的附近具有-對源極/汲極區。在此半導體基底和此 場效電晶體上，形成由氧化砂層所構成的―第—絕緣層。 在此第-絕_上形成-位元線’此位元線與源極/汲極區 之-電性連接。然後’在此第—絕緣層上和此位元線上沈 積-第二絕緣層，此第二絕緣層係由氧化砂層所構成。在 此第二絕緣層上依序地形成H料層、—第三絕_ 和-第f材料層。每-第-材料層和第二材料層相對於第 二和第三紐顧有-__性，且職紐層由氧化 ㈣所形成時，第-材贿和第二材料層可以是氮化砂層 或多晶砂層。沈積之第三絕緣層的厚度約爲儲存節之預定 高度，而儲存節直接與靜電容量有關。在第二材料層上沈 胃-第-光阻圖案。蝕刻第二材料層和第三絕緣層，一直 到做爲蝕刻終止層的第-材料層，_形成1。 移除第一光阻圖案之後’續形成具有開口尺寸較第一光阻 圖案爲小的一第二光阻圖案。触刻第—材料H絕緣 層和第-絕緣層，以形成-第二開口，此第二開口暴露出 另-源極/汲極區。於此之第：開⑽自行對準於第一開 口。在第-開□和第二開□中’及第：材料層上形成一多 本紙張尺度適用中國國家標準（CNS ) A4祝格（210^297^.^7 (請先閲讀背面之注$項再填寫本頁) 訂 4 I 62pif.doc/002 ^7 4 I 62pif.doc/002 ^7 經濟部中央橾率局貝工消费合作社印装 五、發明説明（） 晶矽層。之後，藉由回蝕（etch-back)或化學機械硏磨法 (CMP)平坦化此導電層，直到暴露出第三絕緣層的—上 表面。然後，以濕式蝕刻移除第三絕緣層，且因而形成不 似習知之對準失誤的一儲存節。於此，假如第—材料層是 多晶矽層’需將之移除而用以隔離每—儲存節。 在本發明的另一實施例中，上述形成之第二光阻圖案 係具有一長條形的開口，且包括至少兩個儲存節接觸窗 區。在此範例中，第二材料層與長條形的光阻圖案—起做 爲蝕刻罩幕。因此’微影程序可以容易地實行，並且提供 良好的微影圖案穩定性。其他的製程步驟與上面所述之製 程的順序相同。 & 在本發明的又一實施例中，係以第二開口之導電性的 側壁間隙壁代替第二光阻圖案。也就是說，在移除第〜光 阻圖案之後，於第一開口中和第二材料層上沈積一第〜導 電層，例如多晶矽層。回蝕此第一導電層，用以在第〜開 口的側壁中形成側壁間隙壁。以此側壁間隙壁和第二材半斗 層做爲罩幕’蝕刻第一材料層、第二絕緣層和第一絕緣層， 以形成一第二開口。此後，在第一開口和第二開口中，及 第二材料層上形成一第二導電層。然後，藉由回蝕或化擧 機械硏磨法平坦化此第二導電層，直到暴露出第三絕緣層 的一上表面。之後，以濕式蝕刻移除第三絕緣層，且因而 形成不似習知之對準失誤的一儲存節。假如第一材料層S 多晶矽層，則需將之移除。在此實施例中，其優點是照光 步驟可以減少，故可以簡化製程且降低製造成本。 本紙張尺度適用中國國家標準（CNS > A4祝格（210X297公釐） ----^-------JM------訂------1 v..'-.. (請先閲讀背面之注意事項再填寫本頁} 4 1 62pif.doc/002 A 7 B7 五、發明説明（） 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉三較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖係繪示根據本發明之一較佳實施例，一種 DRAM元件的佈局圖； 第2A圖至第2C圖係繪示一種傳統式DRAM之製造流 程的剖面示意圖； 第3A圖至第3C圖係繪示另一種傳統式DRAM之製造 流程的剖面示意圖； 第4A圖至第4E圖係繪示根據本發明之第一較佳實施 例，一種半導體元件中DRAM胞電容器之製造流程，沿著 第1圖中Α1-ΑΓ的剖面示意圖； 第5圖係繪示根據本發明之另一較佳實施例，一種 DRAM結構的佈局圖；以及 第6圖係繪示沿著第5圖中A2-A2’的剖面示意圖。 圖式之標記說明： 經濟部中央樣準局負工消費合作社印装 (請先閱讀背面之注意事項再填寫本頁) 1, 100, 200 半導體基底 2a至2c 儲存節接觸窗區 2a至2d, 202a至202d 主動區 3, 103 元件隔離層 4a, 104a 第一氧化砂層 4b, 104b 第二氧化矽層 5 蝕刻終止層 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） τ---—ιίιΤιιϋίίίι Ίιΐ ΐι u-+ 4 I 62pit'.doc/002 A7 B7 五、發明説明（） 6a至6c 儲存節接觸窗開口（第二開口） 8 多晶矽層 8a至8c，12a至12c 儲存節 10a至10c 接觸窗插塞 13 底切現象 104，204 第一絕緣層 106, 206 第一材料層 108, 208 第二絕緣層 110,210 第二材料層 11 la 至 11 lc，114a 至 114c 儲存節 112 第二罩幕圖案 114 導電層 211a 至 211c 第一開口 212 導電材料層 212 側壁間隙壁 213a和213b 長條形的開口部份 213a-l 至 213a-3 第二開口 實施例 爲了實踐本發明的目的，DRAM胞電容器的製造方法 將依照所附的圖式，而詳細地加以說明。此DRAM胞電容 器可以在當今用以製造dram的場效電晶體上製造。因 此，只有瞭解本發明所必須之下層結構的細節，才會加以 描述。 請參照第1圖與第4A圖至第4E圖’以下說明本發明 本紙張尺度適用中國國家標準（CNS > Μ祝格（2丨0X297公釐> (請先閲讀背面之注意事項再填寫本頁) -s Γ 經濟部中央樣率局貝工消费合作社印製 4 I 62pif.d〇c/002 A7 B7 五、發明説明（） 之第一較佳實施例。 第1圖係繪不根據本發明之一較佳實施例，一種 DRAM元件的佈局圖。第4A圖至第4E圖係繪示根據本發 明之第一較佳實施例，一種半導體元件中DRAM胞電容器 之製造流程，沿著第1圖中Α1-ΑΓ的剖面示意圖。請參照 第1圖，在一半導體基底之預定區域中，定義數個主動區 2a至2d (第1圖中未顯示）。如同習知技藝中所知，主動 區2a至2d包括儲存節接觸窗區6a至6c和位元線接觸窗 區（圖中未標示號碼）。數個字元線WL1至WL4跨過主 動區2a至2d，數個位元線BL1至BL4與字元線WL1至 WL4相交錯，且於位元線接觸窗開口中和半導體基底之位 元線接觸窗區相接觸（圖中未顯示），但是在其他區域中， 則藉由一厚的絕緣層（第1圖中未顯示）而與半導體基底 和字元線WL1至WL4相隔離。數個儲存節111a至111c 與半導體基底之儲存節接觸窗區6a至6c相接觸，但是在 其他區域中，則藉由另一厚的絕緣層（第1圖中未顯示） 而與半導體基底、位元線BL1至BL4和字元線WL1至 WL4相隔離。 經濟部中央標率局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 請參照第4A圖，藉由元件隔離區103，在半導體基底 100中定義數個主動區2a至2c。主動區2a至2c包括第1 圖中之儲存節接觸窗區6a至6c，及位元線接觸窗區（圖 中未標示號碼）。如同習知技藝中所知，元件隔離區103 係由淺溝渠隔離法（trench isolation)或砂區域氧化法 (LOCOS)所形成。在跨過主動區2a至2c處形成數個閘 13 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4162pif.doc/002 A7 4162pif.doc/002 A7 經濟部中央揉牟局®:工消费合作社印製 B7 五、發明説明（）1. 1T 4l62pif.doc / 002 A7 4l62pif.doc / 002 A7 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, V. Description of the Invention (In the provision of a semiconductor cell manufacturing method for a dram capacitor, it can form a relative The self-aligned storage section of the touch window plug can avoid misalignment between the storage section and the storage section contact window opening. According to the above and other purposes of the present invention, it can be formed on two semiconductor substrates. -Field-effect transistor. This field-effect transistor includes ^-a gate with-an insulating layer and an insulating sidewall interposed thereon, and-a source / drain region near the field-effect structure. On this semiconductor substrate and this field-effect transistor, a "first" insulating layer composed of an oxidized sand layer is formed. A "bit line" is formed on this-insulating layer-the bit line and the source / drain region -Electrical connection. Then 'a second insulating layer is deposited on this first insulating layer and on the bit line, this second insulating layer is composed of an oxide sand layer. H is sequentially formed on this second insulating layer Material layer, the third insulation layer and the fth material layer. When the material layer and the second material layer are -__ with respect to the second and third buttons, and the duty layer is formed of hafnium oxide, the first material layer and the second material layer may be nitrided sand layers or polycrystalline Sand layer. The thickness of the deposited third insulating layer is about the predetermined height of the storage node, and the storage node is directly related to the electrostatic capacity. Sinking on the second material layer-the first-photoresist pattern. Etching the second material layer and the third The insulating layer is used as the first material layer of the etching stop layer to form 1. After removing the first photoresist pattern, a second photoresist pattern having an opening size smaller than that of the first photoresist pattern is continuously formed. The first material H insulation layer and the first insulation layer are engraved to form a second opening, and the second opening exposes another source / drain region. Here, the opening: aligns itself with the first opening . In the first and second openings, and the second and third openings: a number of paper sizes are formed on the material layer to apply the Chinese National Standard (CNS) A4 Zhuge (210 ^ 297 ^. ^ 7 (Please read the note on the back first) $ Item to fill in this page) Order 4 I 62pif.doc / 002 ^ 7 4 I 62pif.doc / 002 ^ 7 The Central Government Bureau of the Ministry of Economic Affairs Printing 5. Description of the invention () A crystalline silicon layer. Then, the conductive layer is planarized by etch-back or chemical mechanical honing method (CMP) until the upper surface of the third insulating layer is exposed. Then, the third insulating layer is removed by wet etching, and thus a storage node is formed that does not resemble a conventional misalignment. Here, if the first material layer is a polycrystalline silicon layer, it needs to be removed to isolate each —Storage section. In another embodiment of the present invention, the second photoresist pattern formed above has an elongated opening and includes at least two storage section contact window regions. In this example, the second material Layer and strip-shaped photoresist pattern—act as an etching mask. Therefore, the 'lithography process can be easily performed and provides good lithography pattern stability. The other process steps are in the same order as the processes described above. & In yet another embodiment of the present invention, the second photoresist pattern is replaced with a conductive sidewall spacer of the second opening. That is, after the first photoresist pattern is removed, a first conductive layer, such as a polycrystalline silicon layer, is deposited in the first opening and on the second material layer. This first conductive layer is etched back to form sidewall spacers in the sidewalls of the openings. The side wall spacer and the second material half-bucket layer are used as a mask 'to etch the first material layer, the second insulation layer and the first insulation layer to form a second opening. Thereafter, a second conductive layer is formed in the first opening and the second opening, and on the second material layer. Then, the second conductive layer is planarized by etchback or mechanical honing, until an upper surface of the third insulating layer is exposed. After that, the third insulating layer is removed by wet etching, and thus a storage node is formed which does not resemble a conventional misalignment. If the first material layer S polycrystalline silicon layer, it needs to be removed. In this embodiment, the advantage is that the number of illumination steps can be reduced, so that the manufacturing process can be simplified and the manufacturing cost can be reduced. This paper size applies the Chinese national standard (CNS > A4 Zhuge (210X297 mm) ---- ^ ------- JM ------ order ------ 1 v .. ' -.. (Please read the notes on the back before filling out this page} 4 1 62pif.doc / 002 A 7 B7 V. Description of the invention () In order to make the above and other objects, features, and advantages of the present invention more obvious and easier Understand that the three preferred embodiments are described in detail below in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings: FIG. 1 shows a layout of a DRAM device according to a preferred embodiment of the present invention. Figures 2A to 2C are schematic cross-sectional views showing the manufacturing process of a conventional DRAM; Figures 3A to 3C are schematic cross-sectional views showing the manufacturing process of another conventional DRAM; Figures 4A to 4 FIG. 4E is a schematic diagram showing a manufacturing process of a DRAM cell capacitor in a semiconductor device according to a first preferred embodiment of the present invention. Another preferred embodiment is a layout diagram of a DRAM structure; and FIG. 6 is a schematic cross-sectional view taken along A2-A2 ′ in FIG. 5. 。 Description of the marks on the drawings: Printed by the Consumer Procurement Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 1, 100, 200 Semiconductor substrates 2a to 2c Storage section contact window areas 2a to 2d , 202a to 202d Active area 3, 103 Element isolation layer 4a, 104a First oxidized sand layer 4b, 104b Second silicon oxide layer 5 Etching stop layer This paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) τ- --- ιΤιιιίίι Ίιΐ ΐι u- + 4 I 62pit'.doc / 002 A7 B7 V. Description of the invention (6a to 6c) Storage section contact window opening (second opening) 8 Polycrystalline silicon layer 8a to 8c, 12a to 12c storage section 10a to 10c Contact window plug 13 Undercut phenomenon 104, 204 First insulating layer 106, 206 First material layer 108, 208 Second insulating layer 110, 210 Second material layer 11 la to 11 lc, 114a to 114c Storage section 112 No. Second mask pattern 114 Conductive layers 211a to 211c First opening 212 Conductive material layer 212 Side wall spacers 213a and 213b Strip-shaped opening portions 213a-1 to 213a-3 Second opening embodiment For the purpose of practicing the present invention, DRAM cell capacitance The manufacturing method of the device will be explained in detail according to the attached drawings. This DRAM cell capacitor can be manufactured on the field effect transistor used to make a dram today. Therefore, only the details of the underlying structure necessary for the present invention will be described. Please refer to Figure 1 and Figures 4A to 4E. 'The following explains that the paper size of the present invention is applicable to the Chinese national standard (CNS > Μ 格格 (2 丨 0X297 mm >) (Please read the precautions on the back before filling in (This page) -s Γ Printed by the Central Sample Rate Bureau Shellfish Consumer Cooperative of the Ministry of Economic Affairs 4 I 62pif.d0c / 002 A7 B7 V. The first preferred embodiment of the invention description (1). A preferred embodiment of the present invention is a layout diagram of a DRAM device. Figures 4A to 4E show a manufacturing process of a DRAM cell capacitor in a semiconductor device according to a first preferred embodiment of the present invention. Schematic cross-section of A1-Al in Fig. 1. Please refer to Fig. 1. In a predetermined area of a semiconductor substrate, several active regions 2a to 2d are defined (not shown in Fig. 1). As is known in the art The active areas 2a to 2d include storage section contact window areas 6a to 6c and bit line contact window areas (the numbers are not shown in the figure). Several word lines WL1 to WL4 cross the active areas 2a to 2d, and several bits The lines BL1 to BL4 are intersected with the word lines WL1 to WL4 and neutralize the semiconductors in the bit line contact window openings. The bit line of the substrate is in contact with the window area (not shown), but in other areas, it is in contact with the semiconductor substrate and the word lines WL1 to WL4 through a thick insulating layer (not shown in Figure 1). Several storage nodes 111a to 111c are in contact with the storage node contact window areas 6a to 6c of the semiconductor substrate, but in other areas, they are in contact with each other through another thick insulating layer (not shown in Fig. 1). The semiconductor substrate, the bit lines BL1 to BL4 and the word lines WL1 to WL4 are isolated. Printed by the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). With the element isolation region 103, a plurality of active regions 2a to 2c are defined in the semiconductor substrate 100. The active regions 2a to 2c include the storage node contact window regions 6a to 6c in the first figure, and the bit line contact window regions (Fig. The number is not indicated in the number). As is known in the art, the element isolation region 103 is formed by shallow trench isolation or sand area oxidation (LOCOS). Numbers are formed across the active regions 2a to 2c Gate 13 This paper size applies to Chinese national standards CNS) A4 size (210X297 mm) 4162pif.doc / 002 A7 4162pif.doc / 002 A7 Ministry of Economic Affairs Bureau of the Central rub Mou ®: Engineering consumers' cooperative printed B7 V. description of the invention ()
極結構，並且與儲存節接觸窗區6a至6c相鄰，雖然第4A 圖中並未顯示。 在半導體基底100上和閘極結構上，形成具有位元線 BL1至BL4之第一絕緣層104。簡言之，第一氧化矽層104a 係形成於整個半導體基底1〇〇上。在第一氧化矽層上形成 數個位元線BL1至BL4與閘極結構交錯，並且在位元線接 觸窗開口中（圖中未顯示），與半導體基底1〇〇的位元線 接觸窗區相接觸，但在其他的區域中，則藉由第一氧化矽 層104a，而與半導體基底100和閘極結構相隔離。在位元 線BL1至BL4形成之後，在位元線BL1至BL4上和第一 氧化矽層104a上形成一第二氧化矽層104b。 在第二氧化矽層104b上依序地形成一第一材料層 106、一第二絕緣層108和一第二材料層110。在這裡，我 們必須注意的是第一材料層106和第二材料層110，相對 於第一絕緣層104和第二絕緣層108具有一蝕刻選擇性。 假如第二絕緣層是氧化矽層時，則第一材料層106和第二 材料層110爲氮化矽層或多晶矽層。第一材料層106和第 二材料層110的厚度約爲10nm至90nm。第二絕緣層的沈 積厚度約爲決定靜電容量之儲存節的預計高度，約爲 0.5μηι 至 1.5μηι，較佳約爲 0.8μιη 至 1·2μηι。 在第二材料層110上形成一第一罩幕圖案（圖中未顯 示），例如是光阻層。使用第一罩幕圖案，對第二材料層 110和第二絕緣層108進行蝕刻，進而形成數個第一開口 Ilia至111c，其暴露出第一材料層1〇6，如第4Β圖中所 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) I丨妓·Pole structure, and adjacent to the storage section contact window areas 6a to 6c, although not shown in Figure 4A. On the semiconductor substrate 100 and the gate structure, a first insulating layer 104 having bit lines BL1 to BL4 is formed. In short, the first silicon oxide layer 104a is formed on the entire semiconductor substrate 100. A plurality of bit lines BL1 to BL4 are formed on the first silicon oxide layer to intersect with the gate structure, and in the bit line contact window opening (not shown in the figure), the bit line contact window of the semiconductor substrate 100 Contact with each other, but in other regions, it is isolated from the semiconductor substrate 100 and the gate structure by the first silicon oxide layer 104a. After the bit lines BL1 to BL4 are formed, a second silicon oxide layer 104b is formed on the bit lines BL1 to BL4 and on the first silicon oxide layer 104a. A first material layer 106, a second insulating layer 108, and a second material layer 110 are sequentially formed on the second silicon oxide layer 104b. Here, we must note that the first material layer 106 and the second material layer 110 have an etching selectivity with respect to the first insulating layer 104 and the second insulating layer 108. If the second insulating layer is a silicon oxide layer, the first material layer 106 and the second material layer 110 are a silicon nitride layer or a polycrystalline silicon layer. The thickness of the first material layer 106 and the second material layer 110 is about 10 nm to 90 nm. The deposited thickness of the second insulating layer is about the expected height of the storage node that determines the electrostatic capacity, about 0.5 μm to 1.5 μm, and preferably about 0.8 μm to 1.2 μm. A first mask pattern (not shown) is formed on the second material layer 110, such as a photoresist layer. Using the first mask pattern, the second material layer 110 and the second insulating layer 108 are etched to form a plurality of first openings Ilia to 111c, which expose the first material layer 106, as shown in FIG. 4B. This paper size applies Chinese National Standard (CNS) A4 Zhuge (210X297 mm) (Please read the precautions on the back before filling this page) I 丨 Prostitute ·
、tT 經濟部中央揉準局貝工消费合作社印簟 4 1 62pif.doc/002 A7 _ _B7 五、發明説明（） 示。於此，第一材料層106係做爲一蝕刻終止層，且第二 材料層110可預防第一開口 111a至111c之尺寸的增加。 請參照第4C圖，形成第二罩幕圖案112，用以定義儲 存節接觸窗開口。於此，我們必須注意的事實是第二罩幕 圖案112的開口部份較第一罩幕圖案小。由比較第1圖中 之參考號碼6a至6c和111a至111c，可以很明顯地看出。 使用第二罩幕圖案112，對第一材料層106和第一絕緣層 104進行蝕刻，進而形成數個第二開口 6a至6c，其分別自 行對準於第一開口 Ilia至111c，且暴露出主動區2a至2c (更具體地說是儲存節接觸窗區6a至6c)。於此，需注 意的是爲了能使本發明更易於瞭解，第二開口 6a至6c的 參考號碼和儲存節接觸窗區相同。在第2圖和第3圖中， 第二開口 6a至6c對應於傳統的儲存節接觸窗開口。此時， 第一材料層106可預防第二開口 6a至6c之尺寸的增加。 在移除第二罩幕圖案112之後，在第一開口和第二開 口中，且在第二材料層110之上沈積一導電層Π4，例如 是多晶矽層。對導電層Π4和第二材料層110進行平坦化， 從上而下至第二絕緣層108。此平坦化程序可以回蝕刻或 化學機械硏磨法（CMP)加以實施，如第4D圖中所示。 然後，導電層以外的絕緣層108係以濕式蝕刻加以移 除，因而形成自行對準於儲存節接觸窗開口 6a至6c的數 個儲存節114a至114c，如第4E圖中所示。在此步驟中， 第一材料層106係做爲一阻障層，且爲防止底切的一蝕刻 終止層。假如第一材料層106爲多晶矽，則必須移除第一 (請先閲讀背面之注$項再填寫本頁)、 TT of the Central Bureau of the Ministry of Economic Affairs of the Central Government Bureau of Shellfish Consumer Cooperatives 4 1 62pif.doc / 002 A7 _ _B7 V. Description of the invention (). Here, the first material layer 106 is used as an etch stop layer, and the second material layer 110 can prevent the size of the first openings 111a to 111c from increasing. Referring to FIG. 4C, a second mask pattern 112 is formed to define the opening of the storage window contact window. Here, we must pay attention to the fact that the opening portion of the second mask pattern 112 is smaller than the first mask pattern. This can be clearly seen by comparing the reference numbers 6a to 6c and 111a to 111c in the first figure. The second mask pattern 112 is used to etch the first material layer 106 and the first insulating layer 104 to form a plurality of second openings 6a to 6c, which are respectively aligned with the first openings Ilia to 111c and exposed. The active areas 2a to 2c (more specifically, the storage section contact window areas 6a to 6c). Here, it should be noted that in order to make the present invention easier to understand, the reference numbers of the second openings 6a to 6c are the same as the storage section contact window area. In FIGS. 2 and 3, the second openings 6a to 6c correspond to the conventional storage node contact window openings. At this time, the first material layer 106 can prevent the size of the second openings 6a to 6c from increasing. After the second mask pattern 112 is removed, a conductive layer Π4, such as a polycrystalline silicon layer, is deposited over the second material layer 110 in the first and second openings. The conductive layer Π4 and the second material layer 110 are planarized from the top to the second insulating layer 108. This planarization process can be implemented by etch-back or chemical mechanical honing (CMP), as shown in Figure 4D. Then, the insulating layer 108 other than the conductive layer is removed by wet etching, thereby forming a plurality of storage sections 114a to 114c aligned with the storage section contact window openings 6a to 6c, as shown in Fig. 4E. In this step, the first material layer 106 is used as a barrier layer and an etch stop layer to prevent undercutting. If the first material layer 106 is polycrystalline silicon, the first must be removed (please read the note on the back before filling this page)
本紙張尺度適用中國國家標準（CNS > A4現格（210X297公釐） 鯉濟部中央標率局貝工消費合作社印製 1 62Pif.doc/002 A 7 〜_____ϋ____ 五、發明説明（） 材料層而使每一儲存節爲電性隔離。之後，沈積一介電層 (圖中未顯示）和一上電極層（圖中未顯示），因而完全 形成整個電容器。繼之在整個半導體基底上沈積一第三絕 緣層（圖中未顯示）。 其次，以習知技藝之預計的接觸窗冶金（metallurgy ’ 圖中未顯示）進行沈積和定義圖案。可以在金屬層上形成 較高階層的冶金（圖中未顯示）和保護層（passivation)， 以完成FET和DRAM元件。舉例來說，較高階層之冶金 接觸窗對上電容器電極是必須的。後續之製程依照習知技 藝的方法，形成必須之內連線冶金和保護層，用以完成本 發明之積體電路。 本發明的第二實施例係參照第5圖’其係繪示根據本 發明之第二較佳實施例’一種DRAM結構的佈局圖。與前 述第一實施例之顯著的不同在於：以第5圖中所示之第二 實施例中之新穎的罩幕圖案’取代第4C圖中所示之第二 罩幕圖案。也就是說，所形成之第二罩幕圖案具有長條形 的開口部份213a和213b’沿著字元線方向WL1’和WL2’， WL3’和WL4’，且分別位於字元線方向WL1’和WL2’之 間，與WL3’和WL4’之間。長條形的開口部份213a和213b 至少包括兩個相鄰之儲存節接觸窗區。第二實施例的描述 係參照第5圖和第6圖，而第6圖係繪示沿著第5圖中 DRAM之A2-A2’的剖面示意圖。與第一實施例中相同的製 程步驟將簡短地加以描述。 請參照第5圖和第6圖，在半導體基底200中形成數 (請先閲讀背面之注意事項再填寫本頁)This paper size applies the Chinese national standard (CNS > A4 (210X297 mm)) Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Lijing 1 62Pif.doc / 002 A 7 ～ _____ ϋ ____ 5. Description of the invention () Material layer Each storage node is electrically isolated. After that, a dielectric layer (not shown in the figure) and an upper electrode layer (not shown in the figure) are deposited, thereby completely forming the entire capacitor. Then, the entire semiconductor substrate is deposited. A third insulating layer (not shown in the figure). Secondly, the contact window metallurgy (not shown in the figure) which is known in the art is used to deposit and define the pattern. Higher-level metallurgy can be formed on the metal layer ( (Not shown in the figure) and passivation to complete the FET and DRAM components. For example, higher-level metallurgical contact windows are necessary for capacitor electrodes. Subsequent manufacturing processes must be performed in accordance with conventional methods. The inner metallurgy and protective layer are connected to complete the integrated circuit of the present invention. A second embodiment of the present invention is described with reference to FIG. 5 which shows a second preferred embodiment according to the present invention. Embodiment 'A layout diagram of a DRAM structure. A significant difference from the foregoing first embodiment is that the novel mask pattern in the second embodiment shown in FIG. 5' is used instead of the one shown in FIG. 4C. The second mask pattern. That is, the formed second mask pattern has elongated opening portions 213a and 213b 'along the character line directions WL1' and WL2 ', WL3' and WL4 ', and Located between the word line directions WL1 'and WL2', and between WL3 'and WL4'. The elongated opening portions 213a and 213b include at least two adjacent storage node contact window regions. The description is made with reference to FIGS. 5 and 6, and FIG. 6 is a schematic cross-sectional view taken along A2-A2 'of the DRAM in FIG. 5. The same process steps as those in the first embodiment will be briefly described. Please refer to FIGS. 5 and 6 to form numbers in the semiconductor substrate 200 (please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準（匚阳>八4私格（2丨0父297公釐） 4 I62pif.doc/002 經濟部中央揉準局貝工消费合作社印製 A7 B7 五、發明説明（） 個元件隔離區1〇3，用以定義數個主動區202a至202d。在 半導體基底200上形成數個閘極結構（圖中未顯示）。在 半導體基底200上沈積具有數個位元線BL1’至BL4’的第 一絕緣層204。 在第一絕緣層2〇4上依序地形成一第一材料層206、一 第二絕緣層208和一第二材料層210。使用第一罩幕圖案 (圖中未顯示），在第二材料層210和第二絕緣層208中 形成數個第一開口 211a至211c。在此步驟之前的製程與 習知相同。 請參照第5圖，在移除第一罩幕圖案之後，形成此實 施例中之新穎的第二罩幕圖案（圖中未顯示），其沿著字 元線方向且在字元線之間具有數個長條形的開口部份 213a和213b。如第5圖中所示，所形成之長條形的開口部 份213a和213b，較第一開口 211a至211c具有較小之寬 度（其係沿著位元線方向測量）。雖然此長條形的開口 213a 和213b暴露出一部份的第二材料層210，但是第二材料層 210與第二罩幕圖案一起做爲蝕刻罩幕，因而可以防止與 下層之位元線BL1’至BL4’接觸。使用第二罩幕圖案和第 二材料層210做爲蝕刻罩幕，蝕刻第一材料層206和第一 絕緣層204,以形成數個第二開口 213a-l至213a-3至半導 體基底200之儲存節接觸窗區（參考號碼不相同），如第 6圖中所示。後續的製程步驟與第一實施例相同其解釋則 省略。 由本發明的解釋可以明瞭’依據本發明的第二實施 (請先閲讀背面之注意事項再填寫本頁)This paper size applies the Chinese national standard (Liyang> 8 4 private grid (2 丨 0 father 297 mm) 4 I62pif.doc / 002 Printed by the Shellfish Consumer Cooperative of the Central Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ( ) Element isolation regions 103 are used to define a plurality of active regions 202a to 202d. A plurality of gate structures (not shown) are formed on the semiconductor substrate 200. A plurality of bit lines are deposited on the semiconductor substrate 200 The first insulating layers 204 of BL1 'to BL4'. A first material layer 206, a second insulating layer 208, and a second material layer 210 are sequentially formed on the first insulating layer 204. A first cover is used. Curtain pattern (not shown in the figure), a plurality of first openings 211a to 211c are formed in the second material layer 210 and the second insulating layer 208. The process before this step is the same as the conventional method. Please refer to FIG. After the first mask pattern is removed, a novel second mask pattern (not shown in the figure) in this embodiment is formed, which has a plurality of long strips along the direction of the character lines and between the character lines. Opening portions 213a and 213b. As shown in Fig. 5, the elongated opening portion 2 is formed 13a and 213b have a smaller width than the first openings 211a to 211c (which is measured along the bit line direction). Although the elongated openings 213a and 213b expose a part of the second material layer 210, However, the second material layer 210 is used as an etching mask together with the second mask pattern, so that it can prevent contact with the underlying bit lines BL1 'to BL4'. The second mask pattern and the second material layer 210 are used for etching The cover is etched with the first material layer 206 and the first insulating layer 204 to form a plurality of second openings 213a-1 to 213a-3 to the contact region of the storage section of the semiconductor substrate 200 (reference numbers are different), as described in Section 6 As shown in the figure. The subsequent process steps are the same as the first embodiment and their explanations are omitted. From the explanation of the present invention, it is clear that according to the second implementation of the present invention (please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準（〇泌）八4辑^(210父297公釐） 經濟部中央標準局貝工消费合作社印簟 A7 B7____ 五、發明説明（） 例，定義儲存節接觸窗開口之第二罩幕圖案’其具有較第 —實施例者爲大的開口區域，亦即長條形的開口部份。因 此，微影製程可以容易地實施，且能提供良好的微影圖案 穩定性，而不會發生“接觸窗未開”，除此之外還有前述之 第一實施例的優點。 請參照第5圖和第6圖，再進一费地描述本發明之另 一實施例。在第三實施例中，其與第一實施例和第二實施 例之主要差異在於：在第一開口之側面的壁上形成側壁間 隙壁，而不需形成第二罩幕圖案。也就是說’此側壁間隙 壁係做爲形成第二開口的罩幕。與第一實施例和第二實施 例相同製程步驟的解釋則省略。 請參照第6圖，在移除第一罩幕圖案之後，於第一開 口 211a至211c中和第二材料層210上，沈積一層厚度約 爲5nm至30nm的導電材料層212，例如多晶矽層，其相 對於第一和第二絕緣層204和208具有一蝕刻選擇性。然 後，蝕刻多晶矽層，以分別在第一開口 211a至211c中形 成側壁間隙壁212。使用側壁間隙壁212和第二材料層210 做爲蝕刻罩幕，蝕刻第一材料層206和第一絕緣層204， 以形成數個第二開口 213a-l至213a-3,其自行對準於第一 開口 211a至211c。後續之製程步驟與先前描述之第一實 施例和第二實施例相同。 本發明已參考較佳實施例，特別地加以呈現和描述， 然而熟習此技藝者應瞭解，在不脫離本發明之精神和範圍 內，形式和細節之各種變化，當可作各種之更動與潤飾， 4 1 62pif.doc/002 (請先閲讀背面之注意事項再填寫本頁) 裝·This paper size applies to Chinese National Standards (Series 0) Vol. 8 ^ (210 Father 297 mm) Seal of the Central Laboratories of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives Co., Ltd. A7 B7____ 5. Explanation of the invention () Example, defining the opening of the contact window of the storage section The second mask pattern 'has a larger opening area than the first embodiment, that is, a long opening portion. Therefore, the lithography process can be easily implemented, and it can provide good lithography pattern stability without the "contact window not opening" occurring. In addition, there are advantages of the aforementioned first embodiment. Referring to Fig. 5 and Fig. 6, another embodiment of the present invention will be described further. In the third embodiment, the main difference from the first and second embodiments is that a side wall gap wall is formed on the side wall of the first opening without forming a second mask pattern. In other words, 'this side wall gap serves as a mask forming the second opening. Explanation of the same process steps as those of the first embodiment and the second embodiment is omitted. Referring to FIG. 6, after removing the first mask pattern, a conductive material layer 212, such as a polycrystalline silicon layer, is deposited in a thickness of about 5 nm to 30 nm in the first openings 211a to 211c and on the second material layer 210. It has an etch selectivity with respect to the first and second insulating layers 204 and 208. Then, the polycrystalline silicon layer is etched to form sidewall spacers 212 in the first openings 211a to 211c, respectively. Using the sidewall spacer 212 and the second material layer 210 as an etching mask, the first material layer 206 and the first insulating layer 204 are etched to form a plurality of second openings 213a-1 to 213a-3, which are self-aligned to The first openings 211a to 211c. The subsequent process steps are the same as the first and second embodiments described previously. The present invention has been specifically presented and described with reference to the preferred embodiments. However, those skilled in the art should understand that various changes in form and details can be made without departing from the spirit and scope of the present invention. , 4 1 62pif.doc / 002 (Please read the notes on the back before filling this page)
、-|T 本紙張尺度適用中國國家標準（CNS〉A4祝格（210X297公釐） 4 I 62pif.doc/002 A7 B7 五、發明説明（） 因此本發明之保護範圍當視後附之申請專利範圍所界定 者爲準。特別是可以應用於接觸窗開口上之銲墊（bonding pad)的形成。 (請先閲讀背面之注意事項再填寫本頁) J— · 訂 經濟部中央標準局負工消费合作社印製 本紙張尺度適用中國國家標準（CNS ) A4祝格（210X297公釐） ~ ~·· rriirruitKi、-| T This paper size applies Chinese national standard (CNS> A4 Zhuge (210X297mm) 4 I 62pif.doc / 002 A7 B7 V. Description of the invention () Therefore, the scope of protection of the present invention shall be regarded as the attached patent The range is subject to definition. Especially it can be applied to the formation of bonding pads on the openings of contact windows. (Please read the precautions on the back before filling this page) J— · Order the work of the Central Standards Bureau of the Ministry of Economic Affairs The paper size printed by the consumer cooperative is applicable to the Chinese National Standard (CNS) A4 Zhuge (210X297 mm) ~ ~ ·· rriirruitKi
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Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980010708A KR100266898B1 (en) | 1998-03-27 | 1998-03-27 | A method of fabrication dram cell capacitro |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW396617B true TW396617B (en) | 2000-07-01 |
Family
ID=19535480
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW087119952A TW396617B (en) | 1998-03-27 | 1998-12-02 | Manufacturing method of memory cell capacitor for dynamic random access memory in semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH11330401A (en) |
| KR (1) | KR100266898B1 (en) |
| TW (1) | TW396617B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100308622B1 (en) * | 1999-04-12 | 2001-11-01 | 윤종용 | Dram cell capacitor and manufacturing method thereof |
| KR100500933B1 (en) * | 2003-07-24 | 2005-07-14 | 주식회사 하이닉스반도체 | Method of forming storage node of capacitor |
| CN112582261B (en) * | 2019-09-27 | 2022-03-08 | 长鑫存储技术有限公司 | Method for manufacturing memory node contact window |
-
1998
- 1998-03-27 KR KR1019980010708A patent/KR100266898B1/en not_active IP Right Cessation
- 1998-12-02 TW TW087119952A patent/TW396617B/en not_active IP Right Cessation
-
1999
- 1999-03-23 JP JP11078565A patent/JPH11330401A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| KR100266898B1 (en) | 2000-10-02 |
| JPH11330401A (en) | 1999-11-30 |
| KR19990076063A (en) | 1999-10-15 |
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