A7 B7 _ 五、發明説明（·. j_) 技術領域 由於互補式金氧半電晶體（ai〇s).電路，對系統積 體化有很大的助益；不但可與低頻信號處理電路同時實 踐於同一晶片上，也可降低電路功率之消耗。然而從前 的互補式金氧半電晶體（CMOS Transistor)不像雙載 子電晶體（Bipolar Junction Transistor)或砷化鎵電 晶體（GaAs Transistor) —般，可使用於高頻率工作環 捧。雖然電晶體之製造技術不斷地進步，然而要實踐使 互補式金氧半電晶體的除法器能工作在1 GHz的頻 率，仍是一個很重要的挑戰，而且此種需求也愈來愈需 要。 習知技術 經濟部中夬樣準局員工消費合作、社印製 (請先閱讀背面之注意事項再填寫本頁) YUAN，：[.於 1988 年汾eciro/z. Ze".，第 24 卷 第1311-1313頁報導，互補式金氧半電晶體係可被廣泛 使用於數位除法器或數位計數器，而且極爲有效之技 術。YUAN, J.等人於19的年/£紐/. SW-Waie 第$C-24卷第62-70頁報導，將單相脈波 (TSPC，True Single Phase Cl,ock)電路架構蓮用於互 補式金氧半電晶體係使用於高頻率工作環境之技術。 雖然習知之電晶體，尤其上述可工作於高頻環境 之互補式金氧半電晶體（CMOS)內部電路均採用單相脈 本《張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A 7 B7 五、發明説明（令 波（TSPC)電路架搆，但其應用都只限於單模除法器。然 而本發明“高頻互補式金氧半雙模/多模前置分頻器” 係將採用之單相脈波（TSPC)電路架構，推廣至雙模/ 多模除法器，並提出其通式的電路，此種電路及其架構 尙未見於其它國外文獻。 與相關的雙模分頻器（Dual-Modulus Pfescaler) 比 較: 經濟部中央標隼局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 就電路架構而言，目前前置分頻器（prescaler)大 多以雙載子零晶體（Bipolar)及砷化鎵電晶體電路 (GaAs)爲主流，其中少數採用互補式金氧半電晶體 (CMOS).電路。在互補式金氧半電晶體電路中，一般設計 雙模前置分頻器都只是一種固定型的電路結構，本發明 鲮模電路及多模電路的通式具備新穎性，而包括_3/4 或除4/5電路應甩於雙模電路的通式及多模電路的通 式，更與習知電晶體有極大之差異性。就設計考量而 言，本發明設計之各式雙模電路或多模電路均符合電路 架構規則。就速度而言，將互補式金氧半電晶體（CMOS) 電路應用於高頻率工作環境係一項很大的挑戰，本發明 以0.8/^m SPDM製程設計除15/16電路實驗證明其可行 性。 發明槪述 本紙張尺度適用中國國家標準（CNS ) Α·4規格（210X297公釐） 4 B7 B7 經濟部中.央標隼局員工消費合作社印製 五、發明説明（ 本發明本發明”高頻互補式金氧半雙模/多模前置分頻器〃 主要目的係揭示一種新穎之高頻互補式金氧半雙模/多 模前置分頻器，以簡單之電路設計達到該電晶體可工作 於高頻率之目標。 本發明另一目的係揭示一種新穎包括高頻互補式金 氧半雙模/雙模除法器的電路。 本發明尙有一目的揭示本電路架構係利用單相脈 波（TSPC)之P閂（P-Latch)與N閂（N-Latch)設計可工作 於高頻數位信號之前置除法器，並將它推廣應用於雙模 與多模前置分頻器。從最基本的除3/4電路或除4/5電路 出發，設計如除15/16電路；進一步推廣至各種形式之 雙模/多模前置分頻器，提出一套通用的架構。例如其 中之一可除15/16的雙模前置分頻器；以//m Sr>DM 製造，其工作頻率可達1GHz以上。 圖表說明 表1真値表 表2真値袠 表3真値表 本紙張纽適用中國國家檩隼（CNS) Α4· (21{)x297公釐） (請先閲讀背面之注意事項再填寫本頁) -訂· 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（4) 圖1習知互補式金氧半電晶體之正轉換 Transition )電路 圖2除2電路 圖3分成爲兩部份之除2電路 圖4半透式暫存器電路分析i 圖5除3電路 圖6除3電路時序信號圖 圖7快速重設之除N電路 圖8除3/4電路 圖9除3/4電路之時序信號分析圖 圖10除15/16電路 圖11靜態除2電路 圖12雙模前置分頻器之通用架構 圖13除4/5電路 圖14多模前置分頻器架構圖 圖15高頻多模前置分頻器電路圖 圖16最大操作頻率以及電壓源VDD之關係 圖17輸入頻率1024 MHz信號時之輸出信號圖 a) 除15電路之輸出信號 b) 除16電路之輸出信號 電路描述 (請先閱讀背面之注意事項再填寫本頁) -------1---AW-----^-訂* -------後' 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公犛） 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（5) YUAN，J·於1988年報導如圖1所示習知之互補 一.、、 式金氧半電晶體，共有9個電晶體，可有效地組成單相 脈波（TSPC)芷轉換閂，其中共分三級：P-C2M0S級、 N-Precharge 級及N-C2M0S 級，當輸入脈波（Clock，φ ) 爲正轉換（0sitive Transition )電路，此時如將輸 入資料閂住(Latch)，即爲反相輸出的0閂。可想而知， 若將反相輸出接至電路輸入端，即是如圖2所示之除2 電路（Divide-by-Two Circuit)。 再進一步分析，將圖2之除2電路重新組合成圖3 電路，N-Precharge級置於最前面，N-C2M0S級及P-C2M0S 級置於最後面。再將此除2電路之組成分成爲兩部份， 其一爲N-Precharge級及另一爲半透式暫存器（HT Register ; Half Transparent Register)。半透式暫存 器有六個電晶體，爲單相脈波（TSPC)技術之P閂（Ρ· Latch)與Ν閂（N-Latch)組成。如圖4所示該半透式暫 存器電路之分析，經由簡單的真値表（truth table)可 說明其動作原理。 真値表1爲節點A的工作情形，當Sin=0，cl〇ck-in=0或1時，節點A値皆爲1 ;當Sin=l，clock-in=0時， 節點A値維持原先的狀態。總之，當cl〇ck-in=l時’相 當是一個互補式金氧半電晶體（CMOS)反相器的動作形 本紙張尺度適用中國國家梯準（CNS)A4規格（210x297公釐) 7 (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央漂隼？3沒二消费合阼社'& A7 B7 五、發明説明（分 式。其次如真値表2所示，就節點B的工作情形探討， 當clock-in=0或節點A値爲1時，節點B値爲節點A値之 反相；當clock-in=l、節點A値爲0時，則節點B値維持 原先的狀態。整體而言^如真値表3所示，當Sin=0時， 不管clock-in=0或1，Sout(節點B値）肯定爲0，即它 在此種情形下是不經clock-in的時序動作，而是兩個 互補式金氧半電晶體（CMOS)反相器的延遲作用，反應 是非常迅速的。當Sin=0時，此時Sout(節點B値）進入記 憶模式，維持原先的狀態値，視clock-in有多久則其延 遲亦有多久。 YUAN, L 等人於.1993 年汾eWro/z. 第 29 卷 第 1222-1223 頁報導除3 電路（Divide - by- Three Circuit)，本發明'^高頻互補式金氧半雙模/多模前置分 頻器〃將上述架構推廣至除3電路即圖5所示。可以發現 該除3電路使用之電晶體數很少，結構很簡單，並且適於 高頻操作。接著爲了方便作更進一歩了解，輸入一個脈 波，將電路所有節點的信號進行波形分析如圖6所示之時 序信號圖。假設輸入脈波爲50% Duty Cycle，則在節點D 可獲得對稱的信號波形。 所以整個除法器電路就僅由N-Precharge級電路 與半透式暫存器兩部份構成；從此出發，若要設計除 $义度適用中國國^標準（CNS )八4規^::( 2Ι〇ί 297公釐^ ' ' ft . —.1 I II ·^1 訂^ (請先閲讀背面之注意事項再填寫本頁) ♦ 經濟部中央標隼局員工消費合作社印製 A7 ______B7__ 五、發明説明（？） N電路’則如圖7所示’需一級N-Precharge級電路與 N-1級半透式暫存器即可完成除N電路（Divide_.by_N_ Circuit)’在迴路中加入一個NM0S做爲快速重設（quick reset)，可增快速度。 我們要推導除3/4電路（Divide by 3/4 Circuit) 如圖8所示，係由一級N-Precharge級電路與三級半 透式暫存器構成。此時的單級N-Precharge電路具有雙 模作用；當MCl=7〇時，以迴路X爲工作路線成爲一種除4 電路（Divide-by-fourCircuit);當MC1=1 時，以迴路Y 爲工作路線成爲一種除3電路（Divide-by - three Circuit)。爲除3/4電路（Divide-by 3/4 Circuit) 之時序信號分析圖。 以除3電路與除4電路爲基礎，配合兩個D正反器(D Flip-Flop)組成除 15/16 電路（Divide by 15/16 Circuit) ’如圖i〇所示，其中該兩痼d正反器形成漣 波計數器（Ripple Counter)爲除 4 電路（Divide by four Circuit)。當MC=0時，則MC1=0，在除3/4電路中驅使 進行除4工作，加上兩個D正反器的除4電路，導致該 電路成爲具備除16的動作情形。反之，當MC=1時，於 MC1=0下’一個輸出CYCLE中有3/4 CYCLE屬於除4動 作；而於MCl = l下，輸出CYCLE中有1/4CYCLE屬於除 本纸張尺度適用中國國家檩準（CNS. ) A4規格（210X297公釐.） (請先閱讀背面之注意事項再填寫本頁)A7 B7 _ V. Description of the invention (·. J_) Technical field Due to the complementary metal oxide semiconductor (ai0s). Circuit, it is very helpful for the integration of the system; it can be used at the same time as the low-frequency signal processing circuit Practice on the same chip can also reduce circuit power consumption. However, the former complementary metal-oxide-semiconductor (CMOS Transistor), unlike the bipolar junction transistor (GaAs Transistor) or GaAs Transistor, can be used for high-frequency operation. Although transistor manufacturing technology continues to advance, it is still a very important challenge to implement the complementary metal-oxide-semiconductor divider to operate at a frequency of 1 GHz, and this demand is increasingly needed. Consumption cooperation and social printing by employees of the China Proofreading Bureau of the Ministry of Technology and Economy (please read the notes on the back before filling out this page) YUAN, [[in 1988 feneciro / z. Ze "., Vol. 24 It is reported on pages 1311-1313 that complementary metal-oxide-semiconductor systems can be widely used in digital dividers or digital counters, and are extremely effective technologies. YUAN, J., et al., 19 / £ NZ /. SW-Waie Vol. $ C-24, pp. 62-70, reported that a single phase pulse wave (TSPC, True Single Phase Cl, ock) circuit architecture was used Technology used in complementary metal-oxide-semiconductor systems for high-frequency operating environments. Although the conventional transistors, especially the complementary metal-oxide-semiconductor (CMOS) circuits that can work in the high-frequency environment, all use single-phase pulses. "The scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm). A 7 B7 V. Description of the invention (TSPC) circuit architecture, but its applications are limited to single-mode dividers. However, the present invention "high-frequency complementary metal-oxide half-double-mode / multi-mode prescaler" The single-phase pulse wave (TSPC) circuit architecture will be extended to the dual-mode / multi-mode divider, and a general circuit will be proposed. This circuit and its architecture have not been seen in other foreign literature. Dual-Modulus Pfescaler Comparison: Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) As far as circuit architecture is concerned, the current prescaler (prescaler ) Mostly bipolar and gallium arsenide transistor circuits (GaAs) are the mainstream, and a few of them use complementary metal-oxide-semiconductor (CMOS) circuits. In complementary metal-oxide-semiconductor circuits, , General design dual-mode front-end The device is only a fixed circuit structure. The general formula of the die-mode circuit and the multi-mode circuit of the present invention is novel, and the general formula and the multi-mode circuit including the _3 / 4 or 4/5 circuit should be dropped to the dual-mode circuit. The general formula of the circuit is greatly different from the conventional transistor. As far as design considerations are concerned, the various dual-mode circuits or multi-mode circuits designed by the present invention conform to the circuit architecture rules. In terms of speed, the complementary type Metal Oxide Semiconductor (CMOS) circuits are a great challenge for high-frequency operating environments. The present invention uses a 0.8 / ^ m SPDM process design to eliminate the 15/16 circuit experiments to prove its feasibility. INTRODUCTION INTRODUCTION TO THIS PAPER SCALE Applicable to China National Standard (CNS) Α · 4 specifications (210X297 mm) 4 B7 B7 Printed by the Ministry of Economic Affairs and the Central Consumers' Bureau Employee Consumer Cooperatives Mode / multimode prescaler〃 The main purpose is to reveal a novel high-frequency complementary metal-oxide half-double-mode / multimode prescaler. The simple circuit design can achieve that the transistor can work at high frequency. Objective. Another object of the present invention is to disclose A novel circuit including a high-frequency complementary metal-oxide half-dual-mode / dual-mode divider. The present invention has an object to disclose that the circuit architecture uses a single-phase pulse wave (TSPC) P-Latch and N-Latch ( (N-Latch) design can work before the high-frequency digital signal divider, and promote it to dual-mode and multi-mode prescaler. From the most basic divide 3/4 circuit or divide 4/5 circuit Starting out, the design is divided into 15/16 circuits, and further extended to various forms of dual-mode / multi-mode prescaler, and a common architecture is proposed. For example, one of them can be divided by 15/16 dual-mode prescaler. Device; manufactured with // m Sr> DM, its working frequency can reach more than 1GHz. Chart Description Table 1 True Form Table 2 True Form Table 3 True Form Sheet This paper New Zealand is applicable to the Chinese country (CNS) Α4 · (21 {) x297 mm) (Please read the precautions on the back before filling this page )-Ordered · Printed by the Consumer Standards Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs A7 B7 V. Description of the invention (4) Figure 1 Knows the positive transition of the complementary metal-oxide semiconductor semi-transistor) Circuit diagram 2 Divided by 2 Circuit diagram 3 divided into two parts Divide 2 circuit diagram 4 Semi-transparent register circuit analysis i Figure 5 divide 3 circuit diagram 6 divide 3 circuit timing signal diagram 7 fast reset divide N circuit diagram 8 divide 3/4 circuit diagram 9 divide 3/4 circuit timing signal Analysis diagram Figure 10 Divided 15/16 circuit Figure 11 Static Divided 2 circuit Figure 12 General architecture of dual-mode prescaler Figure 13 Divided 4/5 circuit Figure 14 Multimode prescaler architecture Figure 15 High-frequency multimode pre Frequency divider circuit diagram Figure 16 Relationship between maximum operating frequency and voltage source VDD Figure 17 Output signal diagram when input frequency is 1024 MHz signal a) Output signal except 15 circuit b) Output signal description of circuit except 16 circuit (Please read the back first (Please note this page before filling in this page) ------- 1 --- AW ----- ^-order * ------- after ' Paper size applies Chinese National Standard (CNS) A4 specification (210X297 gong) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of invention (5) YUAN, J. reported in 1988 as shown in Figure 1 Complementary one, one, and a half type metal-oxide semiconductor transistors, a total of nine transistors, can effectively form a single-phase pulse wave (TSPC) conversion latch, which is divided into three levels: P-C2M0S level, N-Precharge level and N -C2M0S level, when the input pulse (Clock, φ) is a positive transition (0sitive Transition) circuit, if the input data is latched (Latch), it is the 0 latch of the inverted output. It is conceivable that if the inverting output is connected to the circuit input terminal, it is a divide-by-two circuit as shown in FIG. 2. Further analysis, the circuit of Fig. 2 divided by 2 is recombined into the circuit of Fig. 3, the N-Precharge stage is placed at the front, the N-C2M0S stage and the P-C2M0S stage are placed at the rear. This circuit is divided into two parts, one is an N-Precharge stage and the other is a semi-transparent register (HT Register; Half Transparent Register). The semi-transparent register has six transistors, which are composed of P latch (P · Latch) and N latch (N-Latch) of single-phase pulse wave (TSPC) technology. As shown in Figure 4, the semi-transparent register circuit can be analyzed by a simple truth table. Table 1 is the working situation of node A. When Sin = 0, cloc-in = 0 or 1, node A 値 is 1; when Sin = 1, clock-in = 0, node A 値 is maintained. The original state. In short, when cloc-in = l 'is quite the action shape of a complementary metal-oxide-semiconductor (CMOS) inverter. The paper size is applicable to China National Standard (CNS) A4 (210x297 mm) 7 (Please read the precautions on the back before filling out this page.) 3 二 二 消费 合 合 社 '& A7 B7 V. Description of the invention (fractions. Secondly, as shown in Table 2 below, discuss the working situation of node B. When clock-in = 0 or node A 値 is 1 , Node B 値 is the inverse of node A 値; when clock-in = 1 and node A 値 is 0, node B 値 maintains the original state. As a whole, as shown in Table 3, when Sin = At 0, regardless of clock-in = 0 or 1, Sout (node B 値) must be 0, that is, in this case, it does not go through the timing of clock-in, but two complementary metal-oxide semiconductors (CMOS) inverter delay effect, the response is very fast. When Sin = 0, at this time Sout (node B 値) enters the memory mode, maintaining the original state 値, depending on how long the clock-in is also delayed How long. YUAN, L, et al., 1993, Fen eWro / z. Vol. 29, pages 1222-1223, reported Divide-by- Three Circuit. Modular / multimode prescaler 频 The above architecture is extended to the divide-by-3 circuit as shown in Figure 5. It can be found that the divide-by-3 circuit uses a small number of transistors, the structure is simple, and it is suitable for high For the sake of further understanding, input a pulse wave, and perform waveform analysis on the signals of all nodes of the circuit as shown in the timing signal diagram in Figure 6. Assume that the input pulse wave is 50% Duty Cycle, then at node D A symmetrical signal waveform can be obtained. Therefore, the entire divider circuit is only composed of two parts: an N-Precharge stage circuit and a semi-transparent temporary register. From this point on, the designation of the meaning of $ is applicable to the China National Standard (CNS) Rule 8: :( 2Ι〇ί 297mm ^ 'ft. —.1 I II · ^ 1 Order ^ (Please read the notes on the back before filling this page) Cooperative printed A7 ______B7__ 5. Description of the invention (?) N circuit 'is shown in Fig. 7' A N-precharge level circuit and a N-1 level semi-transparent register are required to complete the N circuit (Divide_.by_N_ Circuit) 'Adding an NMOS to the circuit as a quick reset can increase the speed. We need to derive the Divide by 3/4 Circuit as shown in Figure 8, which consists of a level N -Precharge stage circuit and three stage semi-transparent register. Single stage N-Prech at this time The arge circuit has a dual-mode effect; when MCl = 70, the circuit X is used as a working route to divide into 4 circuits (Divide-by-fourCircuit); when MC1 = 1, the circuit Y is used as a working route to become a divide into 3 circuits (Divide-by-three Circuit). It is a timing signal analysis diagram of Divide-by 3/4 Circuit. Based on the divide by 3 circuit and divide by 4 circuit, and cooperate with two D flip-flops to form a divide by 15/16 circuit (Divide by 15/16 Circuit) 'as shown in Figure i〇, where the two The d flip-flop forms a ripple counter (divide by four circuit). When MC = 0, MC1 = 0, and the division by 4 is driven in the division 3/4 circuit, and the division by 4 circuit of two D flip-flops is added, which causes the circuit to have an operation of division by 16. Conversely, when MC = 1, under MC1 = 0, 3/4 CYCLE in one output CYCLE is divided by 4; and under MCl = 1, 1/4 CYCLE in output CYCLE is included in this paper except for China National Standard (CNS.) A4 specification (210X297 mm.) (Please read the precautions on the back before filling this page)
經濟部中央標準局買工消費合作社印製 A7 B7 五、發明説明（δ) 3動作，再由除4漣波計數器電路輸出，依照公式（3 Χΐ/4+4Χ3/4)Χ4=15計算，導致該電路成爲具備除15 的動作情形。就整體雙模除15/16電路而言，能否往高 頻操作的重要關鍵爲除3/4電路，亦如除3/4電路扮演著 高頻的工作核心，再將除頻後之信號給處理輸出。 YUAN, J.於 1988 年 Weciro/z.Zeii.，第24 卷第 1311-1313 頁報導除2 電路（Divide-by-Two Circuit) 如圖2所示，由於該電路不適於低頻工作，爲區分本發 明將上述電路改良因此命名爲『動態除2電路』。本發 明改良圖2電路，在輸出端並入兩個很小寬度的電晶體 (*)如圖11所示，此種改良不致於影響整個工作情 形，反而消除『動態除2電路』於低頻的不穩定狀態， 使得工作頻率範圍增大，因此圖11之電路爲"靜態除+ 電路夕。 圖12 爲雙模分頻器（dual- modulus prescaler) 之通用架構，由一個高頻的雙模前置分頻器與（n-1)級 除2電路組成，可推廣到各種雙模除數。其核心電路也 是雙模式除頻器，將圖7應用至雙模式分頻器則可呈現 各種電路如除3/4、4/5、、、V/V+1，一般較常用電路 有除3/4、除4/5電路，其中如圖8所示除3/4電路，圖 13爲除4/5電路，當MC1 = 0,爲除4動作；當MC1=1， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） .10 .(請先閲讀背面之注意事項再填寫本頁) L©. 訂· A7 B7 五、發明説明（㈨ 爲除5動作。配合圖12’當第一個雙模前置分頻器是除 3/4電路，則輸出呈現爲除（2n+i-l)/2»+i，1 ;如果 第一個雙模前置分頻器是除4/5電路，則輸出呈現爲除 2Π+1/(2Π+1 +1) 1 1 ° 多模前置分頻器原理與雙模前置分頻器理論相 同，圖14爲多模前置分頻器架構圖’係由多模前置分 頻器核心電路、解碼電路及（η-1)級除2键波除法器電 路組成。當mcx=l ’ x=l，·.，P_1，而mCy=〇，y # X時， 爲第X模選擇；當1114全爲零時，則爲第p模選擇，所以 輸出爲[(p+2)X Qn-i-p+l] / [(Ρ+2)χ 2η·1_ρ+2]/. ·.. / (ρ+2) X 2η_1共ρ個模。其中’其核心電路如圖15 所示，爲高頻多模前置分頻器電路圖，包括一級Ν-precharge級電路，一級半透式暫存器及ρ級半透式暫 存器含快速重設電路，而單級N-precharge電路具有多 模作用，可呈現爲除3/4/、、、/(P+2)之各種電路。 當mcdx=l，即爲第X模選擇’此時即爲除U+2) ’例如 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項异填寫本莧) m —Βϋ m· mcdi=l時’即是除3。 實驗結果 本發明以除15/16電路爲實例’測試其最高操作頻 率與輸入電源電壓之關係，最大操作頻率以及電壓源 ^氏張尺度適用中國國( CNS ) A4g ( 210X297公釐7Printed by A7 B7, Buyers and Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. The description of the invention (δ) 3 actions, which are then output by the divide-by-4 ripple counter circuit, calculated according to the formula (3 χΐ / 4 + 4 × 3/4) × 4 = 15, This causes the circuit to operate with a divide by 15. As far as the overall dual-mode division 15/16 circuit is concerned, the key to whether it can operate at high frequencies is to divide the 3/4 circuit. It is also the case that the division 3/4 circuit plays the core of the high frequency operation, and then the signal Give processing output. YUAN, J. reported in 1988 Weciro / z.Zeii., Vol. 24, pp. 1311-1313, Divide-by-Two Circuit. As shown in Figure 2, this circuit is not suitable for low-frequency operation. In the present invention, the above circuit improvement is named "Dynamic Divide 2 Circuit". The present invention improves the circuit of FIG. 2 by incorporating two transistors with a small width (*) at the output end as shown in FIG. 11. This improvement does not affect the entire working situation, but eliminates the “dynamic divide 2 circuit” at low frequencies. The unstable state increases the operating frequency range, so the circuit in Figure 11 is a "static division + circuit evening". Figure 12 shows the general architecture of a dual-modulus prescaler. It consists of a high-frequency dual-mode prescaler and a (n-1) stage divide-by-2 circuit, which can be generalized to various dual-mode divisors. . Its core circuit is also a dual-mode frequency divider. Applying Figure 7 to the dual-mode frequency divider can present various circuits such as divide 3/4, 4/5 ,, V / V + 1, and generally more common circuits have divide 3 / 4 、 Division 4/5 circuit, among which the division 3/4 circuit is shown in Fig. 8, and Fig. 13 is the division 4/5 circuit. When MC1 = 0, the division is 4; when MC1 = 1, this paper scale applies to China National Standard (CNS) A4 Specification (210X297mm) .10. (Please read the precautions on the back before filling out this page) L ©. Order · A7 B7 V. Description of the invention (㈨ is for action except 5; cooperate with Figure 12 ' When the first dual-mode prescaler is a division 3/4 circuit, the output appears as division (2n + il) / 2 »+ i, 1; if the first dual-mode prescaler is division 4 / 5 circuit, the output appears as divided by 2Π + 1 / (2Π + 1 +1) 1 1 ° The principle of the multimode prescaler is the same as the theory of the dual mode prescaler. Figure 14 shows the multimode prescaler. The architecture diagram of the frequency divider is composed of a multi-mode prescaler core circuit, a decoding circuit, and a (η-1) stage division 2-key wave divider circuit. When mcx = l 'x = l, ·., P_1, and When mCy = 〇, y # X, it is the X-th mode selection; when 1114 is all zero, it is the p-th mode. Select, so the output is [(p + 2) X Qn-i-p + l] / [(Ρ + 2) χ 2η · 1_ρ + 2] /...// ρ + 2) X 2η_1 ρ total The core circuit is shown in Figure 15, which is a high-frequency multi-mode prescaler circuit diagram, including a stage N-precharge stage circuit, a stage semi-transparent register and a p-stage semi-transparent register. Quickly reset the circuit, and the single-stage N-precharge circuit has a multi-mode function, which can be presented as various circuits except 3/4 / ,,, / (P + 2). When mcdx = 1, it is the X-mode selection. In this case, it is divided by U + 2) 'For example, printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the reverse side and fill in this 苋) m —Bϋ When m · mcdi = 1, it is divided by 3. Experimental results The present invention takes a circuit divided by 15/16 as an example to test the relationship between the highest operating frequency and the input power voltage. The maximum operating frequency and voltage source are applicable to China ’s (CNS) A4g (210X297 mm7) scale.
II 經濟部中央標隼局員工消費合作杜印製 A7 B7 五、發明説明（i0) VDD之關係如圖16所示，把輸入信號頻率及VDD以圖 表顯示，當VDD愈高則可使輸入操作頻率愈高。圖17爲 輸入頻率1024 ffiz信號時之輸出信號圖形。 本發明 ''高頻互補式金氧半雙模/多模前置分頻器〃 以車兹並曼模分頻器、或多模前 1分:頻器.，因屢5將很簡單的互補式金氧半電晶體（CMOS) 電路工作於高頻之環境。此種互補式金氧半電晶體技術具 有低消耗功率及容易積體化的優點。雙模前置分頻器主要 應用於鎖相迴路頻率合成器上，藉由在除N及除N+1之間 的改變，得到一除數値。本發明中，首先提出雙模式除3/4 及除4/5分頻器，且再將此技術推廣成通用的雙模前置分 頻器架耩，因而可製作多模前置分頻器架構。本發明之雙 模/多模前置分頻器以〇.8-/zm SPDM 5V互補式金氧半電 晶體技術實作後，其工作頻率可達1 GHz以上。 圖號說明 1. . ·Ν-充電級（N-PRECHARGE) 2·..半透式暫存器（HT-REGISTER) 3.. .輸入信號點 （Sin) 4.. .輸出信號點 (Sout) 5.. .輸脈衝信號（cl〇ck-in) 本紙張尺度適用中國國家標準（CNS > A4規格u 10X297公釐） 1 9 (請先閲讀背面之注意事項再填寫本頁) L®-----r.— 訂， ---„------- A7 ___ B7 五、發明説明（11) 6.. .快速重設（quick reset) 7 . ·.除3 / 4電路（Divide-by-3/4) 8 ...除2電路（Divide-by-2 ) 9.. .模組控制信號（MC) 10 ..除4/5電路（Divide-by」4 / 5 ) 11 ..多模除法器（Mult i-modulus scaling divider) ί2..模組控制解碼器（Modulus-controlled > decoder) (請先閲讀背面之注意事項再填寫本頁) ———rri------11 _0-----rr^i 欲’ 經濟部中夬標隼局員工消費合作社印製 一張 -紙 本 標 家 一國 國 中 用 I適 Μ 瘦 公 97 2 X ο A7 B7 五、發明説明（12) 表一 輪脈衝信號II Consumption cooperation by employees of the Central Bureau of Standards of the Ministry of Economic Affairs, printed by A7 B7 V. Description of the invention (i0) The relationship between VDD is shown in Figure 16. The input signal frequency and VDD are shown in a chart. When VDD is higher, the input operation can be performed. The higher the frequency. Figure 17 shows the output signal graph when the input frequency is 1024 ffiz signal. The `` high-frequency complementary metal-oxide half-dual-mode / multi-mode pre-frequency divider of the present invention '' is based on a Schritzmann mode divider, or a multi-mode front 1-frequency divider. It will be very simple due to repeated 5 Complementary metal-oxide-semiconductor (CMOS) circuits operate in high-frequency environments. This complementary metal-oxide-semiconductor technology has the advantages of low power consumption and easy integration. The dual-mode prescaler is mainly used in phase-locked loop frequency synthesizers. By dividing between N and N + 1, a divisor 除 is obtained. In the present invention, a dual-mode divider of 3/4 and a divider of 4/5 are firstly proposed, and then this technology is generalized to a universal dual-mode pre-frequency divider frame. Therefore, a multi-mode pre-frequency divider can be manufactured. Architecture. After the dual-mode / multi-mode prescaler of the present invention is implemented with 0.8- / zm SPDM 5V complementary metal-oxide semiconductor transistor technology, its operating frequency can reach more than 1 GHz. Description of the drawing number: ··· N-PRECHARGE 2 ··· HT-REGISTER 3. · Input signal point (Sin) 4. · Output signal point (Sout ) 5 ... Pulse input signal (clOck-in) This paper size applies to Chinese national standard (CNS > A4 size u 10X297 mm) 1 9 (Please read the precautions on the back before filling this page) L® ----- r.— Order, --- „------- A7 ___ B7 V. Description of the invention (11) 6 ... Quick reset 7. .. except 3/4 Circuit (Divide-by-3 / 4) 8 ... Divide 2 circuit (Divide-by-2) 9... Module control signal (MC) 10 .. 4 4 circuit (Divide-by) 4 / 5) 11 .. Mult i-modulus scaling divider ί 2 .. Modulus-controlled > decoder (Please read the precautions on the back before filling this page) ——— rri ------ 11 _0 ----- rr ^ i I want to print a sheet from the Consumers' Cooperatives of the Ministry of Economic Affairs, China Standards and Standards Bureau. A7 B7 V. Description of the invention (12) Table one round pulse signal
(請先閱讀背面之注意事項再填寫本頁) 訂' 線 經濟部中夬標準局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 14 五、發明説明（13) 1 B 0 0 經濟部中央標準局員工消費合作杜印製 A7 B7 表二 輸脈衝信號 節點、\ 0(Please read the notes on the back before filling out this page) Order 'Consumer cooperation with employees of the China Standards Bureau of the Ministry of Online Economy Du printed this paper The size of the paper applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 14 V. Description of the invention (13) 1 B 0 0 Consumption cooperation between employees of the Central Bureau of Standards of the Ministry of Economic Affairs, printed A7 B7 Table 2 Input pulse signal node, \ 0
A 0 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)A 0 This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)
15 A7 B7 五、發明説明（ 表三 輸出信號點 輪脈衝信號 0 0 0 A 巳 Γ:-----l· |_ΘΙ — (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標隼局員工消費合作杜印製 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）1615 A7 B7 V. Explanation of the invention (Table 3 Output signal Dot wheel pulse signal 0 0 0 A 巳 Γ: ----- l · | _ΘΙ — (Please read the precautions on the back before filling this page) Standards Bureau staff consumer cooperation Du printed paper size applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) 16