JPS6365711A - Semiconductor integrated logic circuit - Google Patents
Semiconductor integrated logic circuitInfo
- Publication number
- JPS6365711A JPS6365711A JP61210246A JP21024686A JPS6365711A JP S6365711 A JPS6365711 A JP S6365711A JP 61210246 A JP61210246 A JP 61210246A JP 21024686 A JP21024686 A JP 21024686A JP S6365711 A JPS6365711 A JP S6365711A
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- flip
- output
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 238000001514 detection method Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 description 3
- MVVPIAAVGAWJNQ-DOFZRALJSA-N Arachidonoyl dopamine Chemical compound CCCCC\C=C/C\C=C/C\C=C/C\C=C/CCCC(=O)NCCC1=CC=C(O)C(O)=C1 MVVPIAAVGAWJNQ-DOFZRALJSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に、Ｃ０Ｍ５形式の
同期式７９７１７２１１回路を多数有する半導体集積論
理回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated logic circuit having a large number of C0M5 type synchronous 79717211 circuits.
従来、この種のフリップフロップ回路の一例を第４図に
示す。An example of a conventional flip-flop circuit of this type is shown in FIG.
本フリップフロップ回路においては、第５図に示すタイ
ムチャートかられかるように、データＤＡＴＡの論理レ
ベルが出力Ｑの論理レベルと同じ場合にはクロックＣＬ
Ｋが入力しても出力Ｑの論理レベルは変化しない。しか
しながら、本回路ではフリップフロップ回路の一部がク
ロックＣＬ Ｋの変化によって動作する。In this flip-flop circuit, as can be seen from the time chart shown in FIG. 5, when the logic level of the data DATA is the same as the logic level of the output Q, the clock CL
Even if K is input, the logic level of output Q does not change. However, in this circuit, a part of the flip-flop circuit operates according to changes in the clock CLK.
上述したごとく、従来の特にＣＭＯ３形式のフリップフ
ロ７１回路は、出力に変化が現われない場合においても
フリップフロップ回路の一部が動作するため、クロック
の変化によって電力が消費されることになるが、ＣＭＯ
３回路では周波数の高い場合、この本来無駄な消費電力
は大きくなり、ＣＭＯ５回路の特徴である低消費電力化
が実現できない欠点があった。As mentioned above, in the conventional flip-flop circuit, especially in the CMO3 format, a part of the flip-flop circuit operates even when no change appears in the output, so power is consumed due to changes in the clock.
With the three circuits, when the frequency is high, this originally wasteful power consumption becomes large, and there is a drawback that the low power consumption, which is a characteristic of the CMO5 circuit, cannot be realized.
本発明の回路はフリップフロップ回路の出力に対する入
力データの変化を検出する検出回路と、フリップフロッ
プ回路に供給されるクロックを検出回路が変化を検出し
たときにのみ有効化するコントロール回路を設けたこと
を特徴とする。The circuit of the present invention includes a detection circuit that detects a change in input data relative to the output of a flip-flop circuit, and a control circuit that activates the clock supplied to the flip-flop circuit only when the detection circuit detects a change. It is characterized by
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例を示す基本回路図である
。FIG. 1 is a basic circuit diagram showing a first embodiment of the present invention.
第１図を参照すると、本実施例は排他的論理和回路Ａ、
ＮＡＮＤゲートＢ、フリップフロップＣおよび微分回路
りにより構成されている。Referring to FIG. 1, this embodiment includes an exclusive OR circuit A,
It is composed of a NAND gate B, a flip-flop C, and a differentiating circuit.
排他的論理和回路ＡはデータＤＡＴＡの出力Ｑに対する
変化を検出するもので、データＤＡＴＡが出力Ｑのレベ
ルと異なるときのみ１”レベルを出力する。したがって
、クロックＣＬＫが入力するＮＡＤＡゲートＢは排他的
論理和回路Ａから出力する信号ａによって、データＤＡ
ＴＡが変化したときのみクロックＣＬＫの信号を有効と
する。The exclusive OR circuit A detects a change in the output Q of the data DATA, and outputs a 1" level only when the data DATA is different from the level of the output Q. Therefore, the NADA gate B to which the clock CLK is input is exclusive By the signal a output from the logical OR circuit A, the data DA
The clock CLK signal is made valid only when TA changes.
クロックＣＬＫが読み込まれてデータＤＡＴＡが出力Ｑ
に現われると、データＤＡＴＡと出力Ｑが同レベルにな
るので、排他的論理和回路Ａは“０″レベルに戻る。こ
れによってクロックＣＬＫは信号ａ（”Ｏ”レベル）に
よってクランプされ、再びデータＤＡＴＡが変化するま
でＮＡＮＤゲートＢを通過することはできないことにな
る。Clock CLK is read and data DATA is output Q
When this occurs, the data DATA and the output Q become the same level, so the exclusive OR circuit A returns to the "0" level. As a result, the clock CLK is clamped by the signal a ("O" level) and cannot pass through the NAND gate B until the data DATA changes again.
第２図に本実施例のタイミングチャートを示す。FIG. 2 shows a timing chart of this embodiment.
微分回路りおよびＮＡＮＤゲートＢはクロックＣＬＫの
立ち上がり時にのみ幅の狭いパルスｂを発生させる。The differentiating circuit and the NAND gate B generate a narrow pulse b only at the rising edge of the clock CLK.
第２図のタイムチャートに示すように、データＤＡＴＡ
が変化すると、今まで保持されていたフリップフロップ
Ｃの出力ＱとデータＤＡＴＡが異なることになる。この
ため、排他的論理和回路Ａは“１”レベルを出力する。As shown in the time chart of Figure 2, the data DATA
When Q changes, the output Q of the flip-flop C and the data DATA, which have been held until now, will be different. Therefore, exclusive OR circuit A outputs a "1" level.
データＤＡＴＡが読み込まれると、出力ＱとデータＤＡ
ＴＡは同値になるので出力ａは゛′０°゛レベルとなり
、パルスｂも“０°ルベルに保たれる。When data DATA is read, output Q and data DA
Since TA becomes the same value, the output a becomes the ``0'' level, and the pulse b is also maintained at the ``0'' level.
このパルスｂの“０パレベルは、次にデータＤＡＴＡが
変化するまで保たれる。再びデータＤＡＴＡが変化する
と、前に述べたようにクロックＣＬＫが有効となり、フ
リップフロップＣにパルスｂが入力され前述したような
動作を行う。This "0" level of pulse b is maintained until data DATA changes next time. When data DATA changes again, clock CLK becomes valid as described above, pulse b is input to flip-flop C, and pulse b is input to flip-flop C. Do the same actions as you did.
第３図は本発明の第２の実施例を示したものである。FIG. 3 shows a second embodiment of the invention.
本実施例は、排他的論理和回路Ａ、フリップフロップＦ
および論理積回路Ｈから成る基本回路を４個用いて４ビ
ットバイナリ−カウンターを構成したものであり、基本
回路の動作は第１の実施例と同様である。In this embodiment, an exclusive OR circuit A, a flip-flop F
A 4-bit binary counter is constructed by using four basic circuits consisting of a logical product circuit H and an AND circuit H, and the operation of the basic circuit is the same as that of the first embodiment.
この実施例においては、バイナリ−カウンターの上位桁
に当るフリップフロップはどデータの変化の頻度がクロ
ック信号変化に比して少ない。In this embodiment, the data of the flip-flops corresponding to the upper digits of the binary counter changes less frequently than the clock signal changes.
Ｑ４ 、Ｑ３ 、Ｑｚ 、Ｑｌの変化の頻度を比較する
と、１：２：４：８であるので、Ｑ４ 、 Ｑ３ 。Comparing the frequency of changes in Q4, Q3, Qz, and Ql, the ratio is 1:2:4:8, so Q4, Q3.
Ｑ２．Ｑｌの順で消費電力低減の効果を期待できる。Q2. The effect of reducing power consumption can be expected in the order of Ql.
クロックパルス発生のための微分回路Ｅは各フップフロ
ツブ回路毎に設ける必要はなく共通に使用されるためこ
こでの消費電力の増大の影響は小さい。Since the differentiating circuit E for generating clock pulses does not need to be provided for each flip-flop circuit and is used in common, the influence of increased power consumption here is small.
以上説明したように、本発明はフリップフロップ回路の
データが変化したときのみクロックを有効とする構成を
採ったため、フリップフロップ回路のクロックの変化回
数を減らすことができるようになった。特に、低消費電
力を要求されるＣＭＯ８回路で顕著な効果が期待できる
。As described above, the present invention employs a configuration in which the clock is valid only when the data of the flip-flop circuit changes, so that the number of changes in the clock of the flip-flop circuit can be reduced. In particular, remarkable effects can be expected in CMO8 circuits that require low power consumption.
第１図は本発明の第１の実施例、第２図は本実のタイミ
ングチャートをそれぞれ示す。
Ａ・・・排他的論理和回路、Ｂ・・・ＮＡＮＤゲート、
Ｃ，Ｆ・−・フリップフロップ、Ｄ、Ｅ・・・微分回路
、Ｈ・・・論理積回路。
Ｄ 第１図
第２図FIG. 1 shows a first embodiment of the present invention, and FIG. 2 shows an actual timing chart. A... Exclusive OR circuit, B... NAND gate,
C, F...Flip-flop, D, E... Differential circuit, H... Logical product circuit. D Figure 1 Figure 2
Claims (1)
を検出する検出回路と、 該フリップフロップ回路に供給されるクロックを前記検
出回路が前記変化を検出したときのみ有効化するコント
ロール回路を設けたことを特徴とする半導体集積論理回
路。[Claims] A detection circuit that detects a change in input data relative to the output of a flip-flop circuit; and a control circuit that enables a clock supplied to the flip-flop circuit only when the detection circuit detects the change. A semiconductor integrated logic circuit characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61210246A JPH0763135B2 (en) | 1986-09-05 | 1986-09-05 | Semiconductor integrated logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61210246A JPH0763135B2 (en) | 1986-09-05 | 1986-09-05 | Semiconductor integrated logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6365711A true JPS6365711A (en) | 1988-03-24 |
| JPH0763135B2 JPH0763135B2 (en) | 1995-07-05 |
Family
ID=16586203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61210246A Expired - Fee Related JPH0763135B2 (en) | 1986-09-05 | 1986-09-05 | Semiconductor integrated logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0763135B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996021272A1 (en) * | 1994-12-30 | 1996-07-11 | Intel Corporation | A pulsed flip-flop circuit |
| JP2002176354A (en) * | 2000-12-08 | 2002-06-21 | Mitsubishi Electric Corp | Semiconductor device |
| JP2005130493A (en) * | 2003-10-24 | 2005-05-19 | Samsung Electronics Co Ltd | Pass gate circuit with stable operation in transition phase of input signal, self-refresh circuit including the pass gate circuit, and method of controlling the pass gate circuit |
| US7119784B2 (en) | 1994-08-16 | 2006-10-10 | Semiconductor Energy Laboratory Co., Ltd. | Peripheral drive circuit of liquid crystal electro-optical device |
| JP2006287906A (en) * | 2005-03-31 | 2006-10-19 | Hynix Semiconductor Inc | Data latch circuit of semiconductor device |
| WO2010108810A1 (en) * | 2009-03-23 | 2010-09-30 | Oticon A/S | Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5975739A (en) * | 1982-10-25 | 1984-04-28 | Fujitsu Ltd | Power saving system of digital device |
-
1986
- 1986-09-05 JP JP61210246A patent/JPH0763135B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5975739A (en) * | 1982-10-25 | 1984-04-28 | Fujitsu Ltd | Power saving system of digital device |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7348956B2 (en) | 1994-08-16 | 2008-03-25 | Semiconductor Energy Laboratory Co., Ltd. | Peripheral driver circuit of liquid crystal electro-optical device |
| US7119784B2 (en) | 1994-08-16 | 2006-10-10 | Semiconductor Energy Laboratory Co., Ltd. | Peripheral drive circuit of liquid crystal electro-optical device |
| US5557225A (en) * | 1994-12-30 | 1996-09-17 | Intel Corporation | Pulsed flip-flop circuit |
| WO1996021272A1 (en) * | 1994-12-30 | 1996-07-11 | Intel Corporation | A pulsed flip-flop circuit |
| JP2002176354A (en) * | 2000-12-08 | 2002-06-21 | Mitsubishi Electric Corp | Semiconductor device |
| JP2005130493A (en) * | 2003-10-24 | 2005-05-19 | Samsung Electronics Co Ltd | Pass gate circuit with stable operation in transition phase of input signal, self-refresh circuit including the pass gate circuit, and method of controlling the pass gate circuit |
| JP4558438B2 (en) * | 2003-10-24 | 2010-10-06 | 三星電子株式会社 | Pass gate circuit that operates stably in transition period of input signal, self-refresh circuit including the same, and control method of pass gate circuit |
| JP2006287906A (en) * | 2005-03-31 | 2006-10-19 | Hynix Semiconductor Inc | Data latch circuit of semiconductor device |
| WO2010108810A1 (en) * | 2009-03-23 | 2010-09-30 | Oticon A/S | Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor |
| JP2012521700A (en) * | 2009-03-23 | 2012-09-13 | オティコン アクティーセルスカプ | Low power dual edge triggered storage cell with scan test support and clock gating circuit therefor |
| US8786344B2 (en) | 2009-03-23 | 2014-07-22 | Oticon A/S | Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor |
| US9041450B2 (en) | 2009-03-23 | 2015-05-26 | Oticon A/S | Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefore |
| EP2234272A3 (en) * | 2009-03-23 | 2015-09-30 | Oticon A/S | Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0763135B2 (en) | 1995-07-05 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |