TW379433B - Interconnects using metal spacers and method for forming same - Google Patents

Interconnects using metal spacers and method for forming same Download PDF

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Publication number
TW379433B
TW379433B TW086118940A TW86118940A TW379433B TW 379433 B TW379433 B TW 379433B TW 086118940 A TW086118940 A TW 086118940A TW 86118940 A TW86118940 A TW 86118940A TW 379433 B TW379433 B TW 379433B
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TW
Taiwan
Prior art keywords
layer
conductive
conductive material
spacer
making
Prior art date
Application number
TW086118940A
Other languages
Chinese (zh)
Inventor
John E Cronin
Thomas J Hartswick
Anthony K Stamper
Original Assignee
Ibm
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Publication date
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Application granted granted Critical
Publication of TW379433B publication Critical patent/TW379433B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The preferred embodiment of the present invention provides increased conductivity between interlevel interconnection lines. The preferred embodiment uses sidewall spacers on the sides of the interconnection lines to increase the contact are between interconnection lines and interconnect studs. This increase in area improves connection resistance and allows further devices scaling without unacceptable decreases in the conductivity of the connection, and without adding significant expense in the fabrication process.

Description

經濟部中央標準局員工消費合作社印製 A7 -------—--, Β7 _;_ 五、發明説明（！） 發明背景 1. 技術領域 本發明大致係關於半導體製造，特別是關於半導體製造 中之互連。 2. 背景技術 現代疋VLSI半導體處理可用於在一單晶片上製成數以 百萬計（裝置’欲連接諸裝置時VLSI設計係使用若干導 電線’諸互連線通常設於許多不同層上’一般稱之為金屬 層1、金屬層2等’互連線通常利用不同型式之層間互連 結構而接於上方或下方之其他互連線，此互連結構一般稱 為检’目前已有多種製造諸栓之不同技術。互連栓大致係 利用一分離之金屬互連層以連接諸層，而其他技術可使用 錐形通孔（tapered vias)(即絕緣物中之錐形開孔將金屬層 分隔而形成連接），互連栓已逐漸普遍，因為其結構可供做 較大之比例及因此而較大之裝置密度。 請參閱圖5 ’其說明—半導體部8〇〇，在半導體部8〇〇 中，一互連栓802連接於一第一連接線8〇4與一第二連線 8〇6之間’互連栓802由一具有鈦/氮化鈦（Ti/TiN)襯墊8〇8 之鶴（W)芯體80 1組成’但是有時亦可採用其他適當之材料 〇 理想上互連检8〇2係直接與第一連接線804與第二連接 線806相鄰接’惟’用於晶片失準之光罩通常在栓802與 連接線804、806之間產生偏移量，只要栓與連接線之間 仍有足量之連接則其大致上可接受。 -4 · 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） I I - - 1- - - ! - I , / -- —I - - ........ . (請先閱讀背面之注意事項存填寫本筲) 經濟部中央標準局員工消費合作社印製 A7 ________ - B7 . 五、發明説明（2 ) 第一、二連接線804、806大致由一高導電性金屬组成 ，例如鋁銅（AlCu)或另一導體，例如多晶矽，鋁銅選用之 原因在其良好之導電性，其另一優異處係因對鋁銅製出圖 案較為容易，即沈積及反應離子蝕刻（RIE)或方向性之蝕刻 〇 連接線804大致製造上為先全面性沈積一層鋁銅，隨後 全面性沈積一層鈦8 10，光阻隨後施加、曝光及顯像，以 留下光阻之圖案於鈦與鋁銅之層上，然後利用反應離子蝕 刻以蝕除任意光阻顯像處之鈦/鋁銅。反應離子蝕刻使用氯 基離子’其係呈化學性反應與物理性衝擊於鈦/鋁銅，僅留 下光阻所覆蓋之部份鈦/鋁銅。 反應離子蝕刻之一副作用為一聚合膜8 14形成於鈦/鋁 銅之侧壁上’此係因反應離子蚀刻期間發生光阻衰退所致 ’光阻大致含有碳，其在蝕刻過程中結合於原子以形成碳 化聚合物原子’且其本身沈積於献/鋁銅之側壁上，諸聚合 膜8 14(圖中以黑線說明）並未蝕刻，而逐漸成為一種型式之 側壁光罩。此聚合膜之優點在於防止氯氣等向性地蝕入近 垂直鈥/銘銅金屬線之側面’避免互連線中出現下切口之可 能性。 雖然鋁銅具有多項優點，但是亦有易電致遷移之缺點， 當足量之電流施加於鋁銅時，電致遷移即於鋁銅線中造成 孔隙，若孔隙太大則會形成電路開斷。 此為鈥層810為什麼製成於鋁銅連接線804上方之原因 ’鈥層用於將線拉攏及於鋁銅線中之孔隙形成開斷處提 -5- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公楚） ----------裝------訂 (請先閲讀背面之注意事項再填寫本頁) A7 .B7 經濟部中央標準局員工消費合作社印製 五、發明説明（3 ) 供另一電流路徑，相較於鋁銅則鈦具有較差之導電性，但 是其可在開始發生電致遷移之前先導通大量電流，因此欽 層8 1 0可增加鋁銅連接線804之壽命。 連接線804係透過互連栓802而連接於連接線8〇6，互 連栓可用於較其他技術大之密度中，❹使用錐形通孔， 且其填入金屬以做為下一金屬層之—部份。 互連栓通常使用鎢做為—填充材料’使用鎢係因其可利 用化學氣相沈積法（CVD)沈積入—近垂直之孔中，以構成 一栓，其他材料如利用濺鍍或蒸鍍而沈積之鋁銅不採用之 原因在其於沈積入一孔内時極易產生孔隙。鈦/鋼連接線 804形成後，一絕緣物例如二氧化矽（Si〇2)或聚亞醯胺即全 面性（blanket)沈積及利用CMP加以平坦化，如圖中之線8 15 所π。一栓開孔或孔形成於絕緣物中，將一開孔曝現於互 連線804，並藉由施加光阻、曝光及顯像光阻中之開孔、 反應離子蝕刻絕緣物、及去除不必要之光阻且令其留在氧 氣電漿中清洗。 其次，栓8〇2藉由濺鍍一薄鈦/氮化鈦（Ti/TiN)層8〇8於 孔内而形成，形成鈦/鈦氮層808係為了防止鎢CVD製程 中之氟反應於鈦而產生三氟化鈦（TiF3),此為一極高阻抗 之材料。其次’鎢以化學氧相沈積於孔内，以填充於孔， 一化學機械式研磨（CMP)用於將鎢磨成平坦狀。 第二連接線806隨後依相同於第一連接線8〇4之方式製 成，因此，第一、二連接線804、8〇6係以鎢互連栓go〗 連接，不利的是此系統有其缺失，特別是聚合膜8丨4有如 -6- 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公楚） ^------1T (請先閲讀背面之注意事項再填寫本頁) A7 A7 經濟部中央標準局員工消费合作社印裝 五、發明説明（4 ) 一絕緣物，因此，鶴检802與第一互連線804之間唯一電 力連接即是透過鈥/鈇氮層808及在區域816處之鈥層810頂 部。 在失準之狀沉中’僅一部份之鈇/敛氮層808在區域816 中接觸於一部份之飲層810 ’此外，鈦及鈦氮皆為不良之 導電性’其大致上在習知技術中尚可接受，因為諸層較薄 。惟’低導通度結合於失準時即產生問題，因為半導體裝 置密度增加而連接面積變小，諸此因素皆可增加連接之阻 抗’且在實際上達到連接之間無充分導通之狀況。 於是，吾人所需者為一種在連接線與互連栓之間達成互 連之方法與結構，且充分之導通互連係隨裝置尺寸減小而 更加確定。 發明敘述 本發明較佳實施例係在層間互連線之間提供增加之導 通度，較佳實施例利用互連線侧面上之侧壁間隔物，以掸 加互連線與互連栓之間接觸面積，此項面積之增加可改^ 連接阻柷及更加縮小裝置尺寸，在連接之導通度中無不 接受之降低。 …° 本發明之前述及其他特性、優點可由本發明一較佳實施 例之以下特別說明中獲得瞭解，其亦說明於相關圖式^她 圖式簡單說明 本發明之較佳實施例將配合附圖說明於後， 係指相同元件，及： 相问代 圖1係本發明第一貫施例之—連接線與一互連拾之哉面 本紙張尺度適财關 袭------1T (請先閱讀背面之注意事項再填寫本頁) 五、發明説明（5 ) 侧视圖； 連接線與一互連栓之截面 互連栓之截面 互連栓之截面 (請先閲讀背面之注意事項再填寫本頁) 圖2係本發明第一實施例之 立體圖； 圖3係本發明第二實施例之一連接線與一 側視圖； ^ 圖4係本發明第三實施例之一連接線與一 側視圖；及 ' 圖5係一習知技術連接線與— 運栓又截面側視圖。 實施本發明之最佳模式 本發明之較佳實施例係增加互連線與層間互連栓之間 之接觸面積’較佳實施例使側壁間隔物於互連線之例面: ’以利增加互連線與互連栓之間之接觸面積，此面積之增 加將降低連接電阻及造成半導體裝置之密度増加。 Η 請即參閱圖，圖1係本發明第一實施例之一半導體部 橫截面圖，半導體部100包含一互連拴1〇2，可連接於第 一連接線1 04與一第二連接線106之間。 經濟部中央標準局員工消費合作社印製 第一、二連接線104、106大致包含一具有良好導電性 之金屬，例如鋁銅（AlCu)或另一適當之導體，鋁銅之選定 係因為其良好之導電性’其另一優點在於因為鋁銅較易於 以一反應離子蚀刻（RIE)或方向性蚀刻製出圖案。 欲構成弟一連接線1 0 4時’需沈積一铭銅或其他適當材 料層，其次將一層妖沈積於銘銅上，一光阻之光罩沈積及 製成圖案’隨後令晶片進行反應離子蚀刻，RIE姓刻可去 除多餘之鋁銅與鈦，因而形成鋁銅連接線104及鈦層11 〇。 -8 - 本紙張尺度適用中國國家標準（CNS > A4規格（210X 297公釐） 經濟部中央樣準局員工消費合作社印製 A7 B7 五、發明説明（6 ) 反應離子蚀刻之一副作用在於聚合膜生成於鈦/鋁铜之 側壁上’其係因反應離子蝕刻期間發生光阻衰退現象而引 起’聚合膜1 14具有極為不良之導電性，且會使第一連接 線1 04絕緣於其連接之互連栓。 圖1所示之第一實施例中，侧壁間隔物12〇、122係在 絕緣物沈積之前先添加於第一連接線丨〇4，側壁間隔物特 別是侧壁間隔物122，其可於第一連接線1 〇4與互連栓i 02 <間提供另一導通路徑，尤其侧壁間隔物122可沿著其外 侧而接觸於鈦/鈦氮層丨08。圖i中，電流流動線丨5 〇顯示 沿一直接低電阻路徑而自第一連接線〖〇4流至第二連接線 1 〇6之電流方向’線丨52顯示一第二路徑例子，其係一較 问之廷阻但是分饰於一較大面積中，因此路徑之整體電阻 皆較低。 參閱圖2，半導體部之一立體圖即說明增大導通度之區 域’互連栓102連接於側壁間隔物122，再由此處連接於 第一連接線104 ’侧壁間隔物1 u沿著連接線1 〇4之整個 側壁以連接於第一連接線！ 04，電流皆沿第一連接線1 〇4 之侧壁而自第一連接線！ 〇4流至侧壁間隔物丨22。特別的 是’第一連接線i 04與側壁間隔物！ 22之間設有一大導通 區域，此導通區之尺寸可消除聚合膜丨丨4所產生之增高電 阻’因此’使用侧壁間隔物i22可增加第一連接線1 〇4與 互連栓1 02之間之連接導通度。 參閱圖1 ’在鎢沈積於侧壁間隔物〗20、122之前，鈥 與氮化鈦之沈積物係形成於晶片表面上，此鈦/鈦氮層（圖 -9- 本紙張尺度適用中國國家標準（CNS ) A4規格（2ΐ〇χ 297公釐） --------' .1 裝-- (請先閲讀背面之注意事項再填寫本頁) 訂 L. A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（7) 中未示）降低對連接線104之接觸電阻，且在側壁間隔物 120、 122之鎢進行化學氣相沈積期間可防止連接線104 受到六氟化鎢（WF6)㈣，若鎢利用另—技術沈積，例如 物理氣相沈積(PVD)’則鈦/鈦氮層即不必要，儘管其仍可 提供增加之導通度。 侧壁間隔物120、122隨後最好利用CVD或pvD先將一 :占之鎢層沈積於晶片表面上，鎢層然後以固定方向在垂 直方向蝕刻，此製程將鎢留置於第一連接線104之侧壁上 而自水平表面去除鈦/鈦氮與鎢，因而形成侧壁間隔物 122此製程為製出間隔物丨的較佳方法， 因為其可不需要其他之遮蔽步驟。 下-步驟為沈積介電材料以覆蓋第一連接線ι〇4，介電 ^料可包含二氧切或任意其他之適當材料，然後利用化 學機械式研磨（CMP)以將介電質平坦化。 下一步鄉為在介電孔中構成—孔':其中形成互連检，此 係利用俗稱之介層蝕刻製程完成，光阻於此形成圖案且顯 影形成：蝕刻光罩，介電質隨後進行一反應離子蝕刻，而 由此形成互連栓孔，反應離子蝕刻經選定以蝕刻介電質， 且遠迅速於對鈦層110或侧壁間隔物ΐ2〇、Η]。 在孔形成於介電質中後，—鈥/氮化欽（Τι/ΤιΝ)襯塾1〇8 ρ /成於孔中H 108最好為職錢沈積，使用或不使用 「準直儀㈣llmate〇,但是其他適當之方法亦可使用。其 次’互連栓102之芯體係形成於孔中’此最好利用化學氣 相沈積-金屬導體例如鎢(w)於孔内且填滿全孔而成，當 -10- 本紙張尺度適用中® S家標準（CNS ) M規格（210^^7 m I 11. ϋ«ι I I i I — 士R- -- - I ·1 I - -........ TV 0¾ 、-'ff (請先閲讀背面之注意事項再填寫本頁) A7 A7 經濟部中央標準局員工消費合作社印製 五、發明説明（8) 然’其他適當之材料及製法亦可使用。 隨後使用一化學機械式研磨（CMP)將裝置平坦化，第二 連接線106則以相同於第_連接線1〇4之方式製成，因此 ，第一、二連接線104、106利用一互連栓102連接，此 —互連栓係一層間互連結構例子，用於將連接線接至—金 屬層或另一者。 因此，圖1中之第一實施例在互連栓與連接線之間提供 一改良之導通路徑，改良之路徑係藉由一導通路徑通過侧 壁間隔物且進入互連栓而成，此改良部份即可不需要额外 之光罩步驟或其他多餘之製程變化。 請即參閱圖3，本發明之一第二實施例說明於其内，在 此實施例中，第一連接線以相同於第一實施例之方式構成 ，特別是第一連接線係先沈積一外層之鋁銅或其他適當 材料以及將一鈦層沈積於鋁銅上，光阻隨後沈積、曝光及 顯影，而令光阻之圖案留存於鋁銅層上，再以反應離子蝕 刻触去任何無光阻遮蓋之鋁銅及鈦處。 在此第二實施例中，反應離子蝕刻係於鋁鋼全部深度去 除之前即中止，反應離子蝕刻再次具有形成一聚合膜3 W 於鋁銅侧壁上之副作用，這些聚合膜3丨4(圖中以黑線表示 )並不蝕刻，且成為一種型式之侧壁光罩。聚合膜雖形成於 鋁銅之侧壁上，但是並未形成於鋁銅之水平表面上，其原 因為RIE蝕刻期間所發生之離子衝擊係垂直向下，以^止 聚合物建立於水平表面上。 一欽/欽氮層（圖中未示）最好隨後沈積以降低對連接 (請先閱讀背面之注意事項再填寫本頁} •絮· '-° -11 -Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 -----------, Β7 _; _ V. Description of the Invention (!) Background of the Invention 1. Technical Field The present invention relates generally to semiconductor manufacturing, and more particularly to semiconductor manufacturing. Interconnects in semiconductor manufacturing. 2. Background of the Invention Modern VLSI semiconductor processing can be used to make millions on a single chip (devices 'VLSI design uses a number of conductive wires when connecting devices.' Interconnects are usually provided on many different layers 'Generally referred to as metal layer 1, metal layer 2, etc.' Interconnection lines usually use different types of interlayer interconnection structures to connect other interconnection lines above or below. This interconnection structure is generally called inspection. A variety of different technologies for making plugs. Interconnect plugs generally use a separate metal interconnect layer to connect the layers, while other technologies can use tapered vias (i.e. tapered openings in insulators will Metal layers are separated to form connections), interconnect plugs have become commonplace because their structures can be used for larger proportions and therefore higher device densities. Please refer to Figure 5 'its description—semiconductor section 800. In the part 800, an interconnection plug 802 is connected between a first connection line 804 and a second connection line 806. The interconnection plug 802 is made of titanium / titanium nitride (Ti / TiN). The pad (80) of the crane (W) core 80 1 is composed of 'but sometimes also Use other appropriate materials. Ideally, the interconnection inspection 802 is directly adjacent to the first connection line 804 and the second connection line 806. However, the mask used for chip misalignment is usually connected to the bolt 802 and the connection line 804. There is an offset between 806 and 806, as long as there is a sufficient amount of connection between the bolt and the connecting line, it is generally acceptable. -4 · This paper size applies to China National Standard (CNS) A4 (210X297 mm) II--1---!-I, /-—I--........ (Please read the notes on the back and fill in this note) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ________-B7. 5. Description of the invention (2) The first and second connecting wires 804 and 806 are roughly composed of a highly conductive metal, such as aluminum copper (AlCu) or another conductor, such as polycrystalline silicon. The reason for choosing aluminum copper is Its good electrical conductivity, and another advantage is that it is easier to pattern aluminum and copper, that is, deposition and reactive ion etching (RIE) or directional etching. The connection line 804 is generally manufactured by depositing a layer of aluminum and copper first. , Followed by a comprehensive deposition of a layer of titanium 8 10, photoresist is subsequently applied, exposed and The photoresist pattern is left on the titanium and aluminum-copper layer, and then reactive ion etching is used to remove titanium / aluminum-copper at any photoresist image. Reactive ion etching uses chloride-based ions. The sexual reaction and physical impact on the titanium / aluminum-copper, leaving only a portion of the titanium / aluminum-copper covered by the photoresist. One side effect of reactive ion etching is that a polymer film 8 14 is formed on the side wall of the titanium / aluminum-copper. This is due to the photoresistance degradation that occurs during reactive ion etching. The photoresist contains carbon, which is bound to the atoms during the etching process to form carbonized polymer atoms. It also deposits itself on the side walls of Al / Cu. The film 8 14 (illustrated by the black line in the figure) is not etched, but gradually becomes a type of side wall mask. The advantage of this polymer film is that it prevents the isotropic etching of chlorine gas into the sides of the near-vertical / metal copper wires' to avoid the possibility of undercuts in the interconnect wires. Although aluminum and copper have many advantages, they also have the disadvantage of being easily electromigrated. When a sufficient amount of current is applied to aluminum and copper, electromigration causes pores in the aluminum and copper wires. If the pores are too large, the circuit will be opened. . This is the reason why “Layer 810 is made above the aluminum-copper connection line 804.” The layer is used to draw the wire and form a break in the pores in the aluminum-copper line. -5- This paper size applies to Chinese national standards (CNS ) A4 size (210X 297 Gongchu) ---------- Installation ------ Order (Please read the precautions on the back before filling this page) A7 .B7 Staff Consumption of Central Standards Bureau, Ministry of Economic Affairs Cooperative prints 5. Description of the invention (3) Provides another current path. Compared to aluminum and copper, titanium has poor conductivity, but it can conduct a large amount of current before electromigration begins, so Qin layer 8 1 0 The life of the aluminum-copper connection line 804 can be increased. The connection line 804 is connected to the connection line 806 through the interconnection bolt 802. The interconnection bolt can be used in a density higher than other technologies. A tapered through hole is used, and it is filled with metal as the next metal layer. -Part. Interconnecting plugs usually use tungsten as a filling material. The tungsten system is used because it can be deposited by chemical vapor deposition (CVD) into nearly vertical holes to form a plug. Other materials such as sputtering or evaporation The reason why the deposited aluminum copper is not used is that it is easy to generate pores when it is deposited into a hole. After the titanium / steel connecting line 804 is formed, an insulator such as silicon dioxide (SiO2) or polyurethane is blanket deposited and planarized by CMP, as shown by line 8 15 in the figure. A bolt opening or hole is formed in the insulator, an opening is exposed to the interconnection line 804, and the opening is exposed by applying photoresist, exposing and developing photoresist, reactive ion etching the insulation, and removing Unnecessary photoresist and keep it in oxygen plasma for cleaning. Secondly, the plug 802 is formed by sputtering a thin titanium / titanium nitride (Ti / TiN) layer 808 in the hole. A titanium / titanium-nitrogen layer 808 is formed in order to prevent the fluorine in the tungsten CVD process from reacting with fluorine. Titanium produces titanium trifluoride (TiF3), which is a very high-impedance material. Next, tungsten is deposited in the holes with a chemical oxygen phase to fill the holes. A chemical mechanical polishing (CMP) is used to grind tungsten into a flat shape. The second connection line 806 is then made in the same way as the first connection line 804. Therefore, the first and second connection lines 804 and 806 are connected by a tungsten interconnect bolt go. Unfortunately, this system has It is missing, especially the polymer film 8 丨 4 is as -6- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 Gongchu) ^ ------ 1T (Please read the precautions on the back before filling in this Page) A7 A7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (4) An insulator, so the only electrical connection between the Hejian 802 and the first interconnection 804 is through the nitrogen layer 808 and the top of layer 810 at area 816. In the state of inaccuracy, 'only a part of the nitrogen / condensation layer 808 contacts a part of the drinking layer 810 in the region 816'. In addition, titanium and titanium nitrogen are poor electrical conductivity. It is acceptable in the conventional technique because the layers are thin. However, the problem of 'low continuity when combined with misalignment arises because the density of the semiconductor device increases and the connection area becomes smaller. All of these factors can increase the impedance of the connection', and in practice, there is insufficient conduction between the connections. Therefore, what we need is a method and structure for achieving interconnection between connection lines and interconnection bolts, and sufficient conduction interconnection is more certain as the size of the device decreases. DESCRIPTION OF THE INVENTION The preferred embodiment of the present invention provides increased continuity between interlayer interconnects. The preferred embodiment utilizes sidewall spacers on the sides of interconnects to increase the distance between interconnects and interconnect pins. Contact area. The increase of this area can change the connection resistance and reduce the size of the device, and it will reduce the continuity of the connection. … ° The foregoing and other characteristics and advantages of the present invention can be understood from the following special description of a preferred embodiment of the present invention, which is also explained in the related drawings. ^ Her drawings briefly explain the preferred embodiments of the present invention and will be accompanied by The drawings are described below, referring to the same components, and: Fig. 1 is the first consistent embodiment of the present invention-the connection line and an interconnected surface of the paper, the paper size is appropriate ----- 1T (Please read the precautions on the back before filling out this page) V. Description of the invention (5) Side view; The cross-section of the connecting wire and the cross-section of an interconnecting bolt Note that this page is to be filled in again) Figure 2 is a perspective view of the first embodiment of the present invention; Figure 3 is a connection line and a side view of a second embodiment of the present invention; ^ Figure 4 is a connection of a third embodiment of the present invention And a side view; and FIG. 5 is a cross-sectional side view of a conventional connecting wire and a bolt. Best Mode for Carrying Out the Invention The preferred embodiment of the present invention is to increase the contact area between the interconnection line and the inter-layer interconnection plug. The contact area between the interconnect line and the interconnect plug. An increase in this area will reduce the connection resistance and increase the density of the semiconductor device. Η Please refer to the drawing, FIG. 1 is a cross-sectional view of a semiconductor portion according to a first embodiment of the present invention. The semiconductor portion 100 includes an interconnection bolt 102 that can be connected to a first connection line 104 and a second connection line. Between 106. The first and second connecting wires 104 and 106 printed by the employee's consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs generally contain a metal with good conductivity, such as aluminum copper (AlCu) or another suitable conductor. Aluminum and copper are selected because of their good Another advantage of its electrical conductivity is that aluminum and copper are more easily patterned by reactive ion etching (RIE) or directional etching. In order to form the first connection line 104, a layer of copper or other appropriate material needs to be deposited, followed by a layer of demon on copper, a photoresist mask is deposited and patterned, and then the wafer is reacted with ions. Etching and RIE can remove excess aluminum, copper, and titanium, thereby forming aluminum-copper connection lines 104 and titanium layers 11. -8-This paper size applies Chinese national standard (CNS > A4 size (210X 297mm). Printed by A7 B7, Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs. 5. Description of the invention (6) One of the side effects of reactive ion etching is polymerization The film is formed on the side wall of titanium / aluminum-copper. It is caused by the photoresistance decay phenomenon during reactive ion etching. The polymer film 1 14 has extremely poor conductivity and will insulate the first connecting wire 104 from its connection. In the first embodiment shown in FIG. 1, the sidewall spacers 120 and 122 are added to the first connection line before the insulator is deposited. The sidewall spacers, especially the sidewall spacers, are added. 122, which can provide another conduction path between the first connection line 104 and the interconnect bolt i 02 < especially the side wall spacer 122 can contact the titanium / titanium-nitrogen layer along its outer side 08. Figure In i, the current flow line 丨 5 〇 shows a direct current path flowing from the first connection line 〇 04 to the second connection line 106 ′ along a direct low resistance path 丨 52 shows an example of a second path, which is A more obstructive court but spread over a larger area, The overall resistance of this path is relatively low. Referring to FIG. 2, a perspective view of a semiconductor portion illustrates an area where the continuity is increased, 'the interconnect pin 102 is connected to the sidewall spacer 122, and then connected to the first connection line 104' The side wall spacer 1 u is connected to the first connection line along the entire side wall of the connection line 104. The current flows from the first connection line along the side wall of the first connection line 104. 〇4 Side wall spacer 丨 22. Especially, there is a large conduction area between the first connection line i 04 and the side wall spacer! 22, the size of this conduction area can eliminate the increased resistance generated by the polymer film 丨 4 'Using the side wall spacer i22 can increase the connection continuity between the first connection line 104 and the interconnecting bolt 102. See FIG. 1' Before tungsten is deposited on the side wall spacers 20 and 122, 'and nitrogen Titanium deposits are formed on the surface of the wafer. This titanium / titanium-nitrogen layer (Figure-9- This paper size applies to the Chinese National Standard (CNS) A4 specification (2ΐ〇χ 297mm) ------- -'.1 Pack-(Please read the notes on the back before filling this page) Order L. A7 B7 Central Standard of the Ministry of Economy Printed by the Consumer Cooperatives of the Prospective Bureau V. Invention Description (7)) Reduce the contact resistance of the connection line 104, and prevent the connection line 104 from being exposed to the six during the chemical vapor deposition of the sidewall spacers 120 and 122 tungsten. Tungsten fluoride (WF6) thorium, if tungsten is deposited using another technique, such as physical vapor deposition (PVD) ', a titanium / titanium-nitrogen layer is unnecessary, although it can still provide increased continuity. Sidewall spacer 120 Then, it is best to use CVD or pvD to deposit a tungsten layer on the wafer surface, and then etch the tungsten layer in a fixed direction in a vertical direction. This process leaves tungsten on the side wall of the first connection line 104. The titanium / titanium nitrogen and tungsten are removed from the horizontal surface, so that the sidewall spacer 122 is formed. This process is a better method for making spacers, because it may not require other masking steps. The next step is to deposit a dielectric material to cover the first connection line ι04. The dielectric material may include dioxygen cutting or any other suitable material, and then chemical mechanical polishing (CMP) is used to planarize the dielectric. . The next step is to form a hole in the dielectric hole: the formation of interconnection inspection, which is completed by the commonly known dielectric layer etching process, where the photoresist is patterned and developed to form: the photomask is etched, and the dielectric is subsequently performed. A reactive ion etch, thereby forming interconnect plug holes, is selected to etch the dielectric, and is much faster than the titanium layer 110 or the sidewall spacers (20, Η). After the hole is formed in the dielectric, the “Nitrogen (Ti / TιN) lining 1108 ρ / formed in the hole H 108 is best deposited for the job, with or without the use of" collimator "llmate 〇, but other appropriate methods can also be used. Secondly, the core system of the interconnect plug 102 is formed in the hole. This is best using chemical vapor deposition-a metal conductor such as tungsten (w) in the hole and fills the entire hole. As of -10-, this paper size is applicable in China® S Standard (CNS) M specification (210 ^^ 7 m I 11. ϋ «ι II i I — taxi R---I · 1 I--.. ... TV 0¾, -'ff (Please read the notes on the back before filling out this page) A7 A7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) Of course, other appropriate materials And the manufacturing method can also be used. Subsequently, a chemical mechanical polishing (CMP) is used to planarize the device, and the second connection line 106 is made in the same manner as the first connection line 104, so the first and second connection lines 104 and 106 are connected by an interconnection bolt 102. This—an interconnection bolt is an example of an inter-layer interconnection structure for connecting a connection line to—a metal layer or another. Therefore, FIG. The first embodiment of 1 provides an improved conduction path between the interconnection bolt and the connection line. The improved path is formed by a conduction path passing through the sidewall spacer and entering the interconnection bolt. This improved part is No additional mask steps or other unnecessary process changes may be required. Please refer to FIG. 3, a second embodiment of the present invention is illustrated therein. In this embodiment, the first connection line is the same as the first embodiment. The first connection line is formed by first depositing an outer layer of aluminum or copper or other suitable material and depositing a titanium layer on the aluminum and copper. The photoresist is then deposited, exposed and developed, so that the photoresist pattern remains in On the aluminum-copper layer, any aluminum-copper and titanium areas that are not covered by photoresist are touched by reactive ion etching. In this second embodiment, the reactive ion etching is stopped before the aluminum steel is completely removed, and the reactive ion etching is again It has the side effect of forming a polymer film 3 W on the aluminum-copper sidewall. These polymer films 3 丨 4 (shown by black lines in the figure) are not etched and become a type of side wall mask. Although the polymer film is formed on aluminum Copper Side Wall However, it is not formed on the horizontal surface of aluminum and copper. The reason is that the ion impact occurring during the RIE etching is vertically downward to prevent the polymer from being established on the horizontal surface. (Shown) It is best to deposit later to reduce the connection (please read the precautions on the back before filling out this page) • 絮 · '-° -11-

經濟部中央標準局員工消費合作社印裝 3 Ο 4之接觸阻抗，且在鎮之化遂洛^ # 隹灼心彳匕予軋相沈積期間利用六氟化 鶴（WF6)以防止連接線3 〇4蝕刻。 侧壁間隔物320、322隨後藉由沈積—服貼之鶴或農他 適當材料層於晶片表面上而形成，其最好再次利用—Μ 製程，鈦/鈦氮及鎢層以固定方向在垂直方向蝕刻，直到僅 餘下侧壁間隔物320、322。 在垂直方向中之方向性蝕刻隨後開始及持續，直到鎢> 鈦氮/鈦/鋁銅自線之間移除為止，侧壁間隔物32〇 、32^ 遮蔽下方之鋁銅，因此方向性之蚀刻僅自光阻或侧壁間隔 物320、322未覆蓋之區域去除鋁銅，局部蝕刻鋁銅，構 成侧壁間隔物及蝕刻其餘鋁銅之製程即製出一第一連接 線304，且有一「階級」自各鋁銅侧壁伸出。 由於在鋁銅之水平表面上無聚合膜，第一連接線階級之 頂表面可在側壁間隔物322與第一連接線3〇4之間增添額 外 < 向導通度區域3 10，此外，侧壁間隔物322係沿連接 線304之侧壁311以接至第一連接線3〇4，在第一實施例 中，聚合膜3 14形成一高電阻路徑，但是其係由側壁間隔 物322與第一連接線304之間之大尺寸導通區域來補償。 參閱圖4，其說明一第三實施例，此實施例係第二實施 例之調整，在第三實施例中，第一連接線56〇最好由沈積 一第一層519且隨後沈積一第二層521而構成，在較佳實 施例中，連接線560之第一層5 19包含鈦而連接線之第二 層52 1包含鋁銅，連接線依第二實施例方式製成圖案及蝕 刻’且蚀刻懸於或接近於連接線第一層5 19之頂部。側壁 -12- 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Employees of the Central Standards Bureau of the Ministry of Economic Affairs printed a contact impedance of 3 〇4, and used the hexafluoride crane (WF6) to prevent the connection line during the deposition of Zhenluo Suiluo ^ # 隹 火 心 彳 during pre-rolling phase deposition. 3 〇 4etching. The sidewall spacers 320, 322 are then formed by depositing a suitable material layer on the surface of the wafer, such as a crane or non-traditional material. It is best to use the -M process again. The titanium / titanium-nitrogen and tungsten layers are fixed in a vertical direction Etch in the direction until only the sidewall spacers 320, 322 remain. Directional etching in the vertical direction then starts and continues until tungsten> TiN / Ti / Al-Cu is removed from the wires, and the side wall spacers 32 and 32 ^ cover the underlying Al-Cu, so the directionality The etching only removes the aluminum and copper from the areas not covered by the photoresist or the side wall spacers 320 and 322, and locally etches the aluminum and copper to form the side wall spacers and the remaining aluminum and copper processes to produce a first connection line 304, and A "class" protrudes from each aluminum-copper sidewall. Since there is no polymer film on the horizontal surface of aluminum and copper, the top surface of the first connecting line stage can add an additional < guide through area 3 10 between the side wall spacer 322 and the first connecting line 3 04, in addition, the side The wall spacer 322 is along the side wall 311 of the connection line 304 to be connected to the first connection line 304. In the first embodiment, the polymer film 314 forms a high resistance path, but it is formed by the side wall spacer 322 and The large-sized conduction area between the first connection lines 304 is compensated. Referring to FIG. 4, a third embodiment is illustrated. This embodiment is an adjustment of the second embodiment. In the third embodiment, the first connection line 56 is preferably deposited by a first layer 519 and then a first layer 519 is deposited. It is composed of two layers 521. In the preferred embodiment, the first layer 5 19 of the connection line 560 contains titanium and the second layer 52 1 of the connection line contains aluminum copper. The connection line is patterned and etched according to the second embodiment. 'And the etching is suspended on or near the top of the first layer 5 19 of the connection line. Side wall -12- This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)

經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（10) 間隔物520、522隨後利用一適當材料例如鎢之服贴式沈 積與方向性蝕刻，以形成於連接線第二層52丨之侧壁上， 隨後再次使用方向性蝕刻而形成一連接線，其在連接線第 —層519及連接線第二層521之間過渡區之側壁中具有r 階級」。 由於水平表面上無聚合膜’在「階級」處之連接線第一 層頂表面處增添侧壁間隔物522與第一連接線560間的一 額外之高導通區域，此外，側壁間隔物522沿著連接線第 —層5 2 1之侧壁5 1 1以接於第一連接線5 6 0。如第一實施 例者’聚合膜3 14形成一高阻抗路徑，但是其係由侧壁間 隔物522與第一連接線之間之大尺寸導通區域來補償。 在第三實施例之變化中，連接線第—層5 19並非形成於 將第一連接線接至其下方連接線之一互連栓頂部，在此變 化中，「階級」之頂部係出現於互連栓與連接線第二層52 j 之間之過渡區處。 本發明之各實施例係於連接線與垂直互連栓之間提供 改良之導電性，此改良之達成可不需要多餘之處理步驟或 其他之光罩層’改良之導電性可容許元件尺寸持續縮小， 而保持充分接觸。 本發明雖已參考其較佳實施例揭示及說明，但是習於此 技者應瞭解在不脫離本發明精神範疇下仍可有型式與，細 部元件上之變化。 -13- 本紙張尺度適用中國國家標準（CNS ) A4規格（210x297公釐） -裝------訂 (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (10) The spacers 520, 522 are then deposited by a suitable material such as tungsten and directional etching to form the second layer of the connection line 52 On the side wall of 丨, a directional etch is subsequently used again to form a connection line, which has an r-class in the side wall of the transition region between the connection line first layer 519 and the connection line second layer 521. " Since there is no polymer film on the horizontal surface, an additional high-conductivity area is added between the side wall spacer 522 and the first connection line 560 at the top surface of the first layer of the connection line at the "level". In addition, the side wall spacer 522 is The side wall 5 1 1 of the first layer 5 2 1 of the connection line is connected to the first connection line 5 6 0. As in the first embodiment, the polymer film 314 forms a high-impedance path, but it is compensated by a large-sized conduction region between the sidewall spacer 522 and the first connection line. In a variation of the third embodiment, the connection line first layer 5 19 is not formed on the top of one of the interconnection bolts that connects the first connection line to the connection line below it. In this variation, the top of the "class" appears on At the transition area between the interconnect bolt and the second layer 52 j of the connection line. The embodiments of the present invention provide improved conductivity between the connection line and the vertical interconnection plug. This improvement can be achieved without the need for extra processing steps or other photomask layers. While maintaining full contact. Although the present invention has been disclosed and described with reference to its preferred embodiments, those skilled in the art should understand that there can be variations in the details of the forms and the details without departing from the spirit of the present invention. -13- This paper size applies to Chinese National Standard (CNS) A4 (210x297 mm)-Packing --- Order (Please read the precautions on the back before filling this page)

Claims (1)

A8 B8 C8 D8 1. 經濟部中央標準局員工消費合作社印策 於該 3. 如申 之步 鋁銅 4. 如申 之步 5. 如申 之步 、對 導電 側壁 6. 如申 之步 導電 六、申請專利範圍 種用於在一半導體裝置中製成 方法包含以下步驟： a) 在丰導體裝置之—基板上製成一第一層導電線； b) 在第一層導電線之一侧上製成至少一導電間隔物； c) 製成一互連結構，以接觸導電線之至少一部份及至少 一導電間隔物之至少一部份；及 d) 製成一第二層導電線且接觸於互連結構之至少一部 份。 2.如申請專利範圍第丨項之方法，其中製成第—層導電線 之步驟包含沈積一含有鋁銅之第一金屬層及一含有鈦 鋁銅上之頂層。 請專利範圍第2項之方法，其中製成第一層導電線 驟另包含沈積光阻 '對該光阻製出圖案、及蝕刻該 及該鈥。 請專利範圍第1項之方法，其中製成第—層導電線 驟包含在第一層導電線之一側壁中製成一階級。 請專利範圍第4項之方法，其中製成第一層導電線 驟包含沈積一導電材料、在該導電材料上沈積光阻 該光阻製出圖案、及蝕刻該導電材料，該蝕刻係在 材料冗全蝕穿之前即停止，藉此在第一層導電線之 中製成該階級。 請專利範圍第1項之方法’其中製成一側壁間隔物 驟包含服貼地沈積一導電材料且以方向性蝕刻該 材料。 I - 1 1 ·--- I ml ......n -'*R, - I ϋϋ —^1 ϋ^— 1^1 一 #先閲讀背面之注意事項鼻填寫本貢) -14- A8 B8 C8 D8 經濟部中央榡準局員工消費合作社印策 中請專利範圍 7·:申請專利範圍第6項之方法，其中該侧壁間隔物包含 8·如申請專利範園第1項之方法，其中製成第-層導電沒 〈步驟包含沈積-導電材料、在該導電材料上沈= ::該光阻製出圖案、及蚀刻該導電材料，在導電 穿之前該㈣即停止，藉此在第—層導 :中製出該階級’及其中製成一側壁間隔物之步驟J 地沈積-間隔物導電材料且以方向性钱； 物導電材料。 ^ 9·如申請專利_ Η之方法，其中製成第—層導電線 又步驟包含沈積一層第一導電材料與沈積—層第2導 電材料於該第一導電材料上、沈積光阻於該第二導;材 二f、對該光阻製出圖案、及蚀刻該第二導電材料:在 β第一導電材料完全蝕穿之前該蝕刻即停止，藉此在第 :層導電線之侧壁中製成一階級，及其中製出一侧壁間 隔物之步驟包含服貼地沈積一間隔物導電材料且以方 向性蝕刻該間隔物導電材料。 10.如申？專利範圍第9項之方法，其中第—導電材料包含 鈦，第二導電材料包含鋁銅及間隔物導電材料包含鎢。 如申請專利範圍第i項之方法，其中互連結構一 栓。 。1 12.如申請專利範圍第1項之方法，其中製成一第—層導電 線之步驟包含製成該第一層導電線於—底互連^頂: ’及其中一具有一頂表面之階級係設於該第—層導電 -15- 本紙張尺度適用中國國家棣準（CNS ) M胁（21〇><297公羡 n I n n n n n I , ' · I —- —丁 —— I--n . n 、T^^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標隼局員工消費合作社印製 A8 B8 C8 , D8 六、申請專利範圍 線與該底互連栓之介面處，及其中製成至少一導電間隔 物之步驟包含製成一間隔物以接觸該階級之頂表面。 13. —種半導體裝置互連結構，用於在半導體裝置上改善一 第一層導電線及一第二層導電線之間之一層間互連導 電性，互連結構包含： a) 至少一導電侧壁間隔物，設於第一層導電線之一侧上 ;及 b) —層間互連，係接觸第一導電線之至少一部份及至少 一導電侧壁間隔物之至少一部份，且將該第一導電線 連接至該第二導電線。 14. 如申請專利範圍第13項之半導體裝置互連結構，其中 第一層導電線包含一含有鋁銅之第一金屬層及一含有 欽於該銘銅上之頂層。 15. 如申請專利範圍第1 3項之半導體裝置互連結構，第一 層導電線包含一設於第一層導電線侧壁上之一階級。 16. 如申請專利範圍第1 5項之半導體裝置互連結構，其中 第一層導電線包含一沈積與蝕刻而成之導電材料，及其 中階級係藉由導電材料完全蝕穿之前即停止蝕刻與導 電性侧壁間隔物製成之後再重行開始蝕刻而製成。 17. 如申請專利範圍第1 3項之半導體裝置互連結構，其中 導電性側壁間隔物包含一方向性蝕刻之服貼沈積式導 電材料。 18. 如申請專利範圍第1 7項之半導體裝置互連結構，其中 該側壁間隔物包含鎢。 -16- 本紙張尺度適用中國國家標準（CNS ) A4現格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. 經濟部中央標隼局員工消費合作社印裝 A8 B8 C8 D8 六、申請專利範圍 19. 如申請專利範圍第1 3項之半導體裝置互連結構，其中 第一層導電線包含一層第一導電材料及一層設於該第 一導電材料上之第二導電材料。 20. 如申請專利範圍第1 9項之半導體裝置互連結構，其中 該層第一導電材料延伸至該第二導電材料之一侧以外 ，而在第一導電材料之一侧中製成一階級。 21. 如申請專利範圍第20項之半導體裝置互連結構，其中 第一導電材料包含鈦，第二導電材料包含鋁銅，及侧壁 間隔物包含鶴。 22. 如申請專利範圍第20項之半導體裝置互連結構，第一 層導電線係設於一底互連栓頂部，及其中第一層導電線 與該底互連栓之介面處製出一階級，階級具有一頂表面 ，及其中該至少一導電性侧壁間隔物接觸於該階級之 頂表面。 23. —種在一半導體裝置中製成一層間互連之方法，該方法 包含以下步驟： a) 藉由沈積至少一導電材料、在該導電材料上沈積光阻 、對該光阻製出圖案、及蝕刻該導電材料，以製成一 第一層導電線於半導體裝置之一基板上，在該導電材 料完全蝕穿之前即停止該蝕刻，藉此製成該階級於第 一層導電線之侧壁中； b) 藉由服貼性沈積一間隔物導電材料及方向性蝕刻該 間隔物導電材料，以製成至少一導電性間隔物於第一 層導電線之一侧上； _- 17-_ 本紙張尺度適用中國國家揉準（CNS ) A4規格（210 X 297公釐） ' 訂^、 (請先閱讀背面之注意事項再填寫本頁) 六、申請專利範圍 A8 B8 C8 D8 份 部 一 少 至 之L 泉及 電.， 導份 於部 觸一 接少 以至 ，之 構物 結隔 連間 互電 間導 層一 1 少 成至 製及 少 至 之 構 結 連 互 間 層 於 觸 接 且 線 電 導 層 二 #弟 。 一份 成部 製一 (請先閏讀背面之注意事項再填寫本頁) 裝- 訂 铲 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS〉A4現格（210 X 297公釐）A8 B8 C8 D8 1. The Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs has printed the policy. 3. Ruobu step aluminum copper 4. Ruobu step 5. Ruobu step, the conductive sidewall 6. Ruobu step conductive 6 2. A method for applying a patent for manufacturing a semiconductor device includes the following steps: a) making a first layer of conductive wire on the substrate of the abundant conductor device; b) on one side of the first layer of conductive wire Making at least one conductive spacer; c) making an interconnect structure to contact at least a part of the conductive wire and at least a part of the at least one conductive spacer; and d) making a second layer of conductive wire and In contact with at least a portion of the interconnect structure. 2. The method according to item 丨 of the patent application, wherein the step of forming the first-layer conductive wire includes depositing a first metal layer containing aluminum copper and a top layer containing titanium aluminum copper. The method of claim 2, wherein the step of making the first layer of conductive wires further includes depositing a photoresist to 'pattern the photoresist, and etching the photoresist. The method of claim 1, wherein the step of forming the first layer of conductive wires includes forming a first layer in one of the side walls of the first layer of conductive wires. The method of claim 4, wherein the step of making the first layer of conductive wires includes depositing a conductive material, depositing a photoresist on the conductive material to form a pattern, and etching the conductive material. The etching is performed on the material. Redundant etch stops immediately before this stage is created in the first layer of conductive wire. The method of claim 1, wherein the step of making a sidewall spacer comprises depositing a conductive material conformally and etching the material in a directional manner. I-1 1 · --- I ml ...... n-'* R,-I ϋϋ — ^ 1 ϋ ^ — 1 ^ 1 ## Please read the notes on the back first and fill in this tribute) -14- A8 B8 C8 D8 In the policy of the Consumer Cooperatives of the Central Bureau of quasi-government of the Ministry of Economic Affairs, the patent scope 7: Method of applying for the scope of the patent No. 6 wherein the side wall spacer contains the method of No. 1. The step of making the first-layer conductive layer includes depositing a conductive material, sinking the conductive material = ::: the photoresist creates a pattern, and etching the conductive material, and the conductive material is stopped before the conductive material passes through, thereby In the first layer guide: the step of making the class' and the step J in which a side wall spacer is made is to deposit a spacer conductive material and direct the money; a conductive material. ^ 9 · As in the method of applying for patent _, the method of making a first layer of conductive wire includes depositing a layer of a first conductive material and depositing a layer of a second conductive material on the first conductive material, and depositing a photoresist on the first conductive material. Second conductor; material two f, patterning the photoresist, and etching the second conductive material: the etching stops before the β first conductive material is completely etched, thereby being in the sidewall of the first layer of conductive wire Forming a class and the steps of making a sidewall spacer therein include depositing a spacer conductive material conformally and etching the spacer conductive material in a directional manner. 10. As applied? The method of item 9 of the patent, wherein the first conductive material comprises titanium, the second conductive material comprises aluminum copper and the spacer conductive material comprises tungsten. For example, the method of applying for item i of the patent scope, wherein the interconnection structure is a bolt. . 1 12. The method according to item 1 of the scope of patent application, wherein the step of making a first-layer conductive wire includes making the first-layer conductive wire at the bottom interconnect ^ top: 'and one of them having a top surface The class is based on the first layer of conductive -15- This paper size is applicable to China National Standards (CNS) M threat (21〇) < 297 public envy n I nnnnn I, '· I —- — 丁 —— I --n. n, T ^^ (Please read the notes on the back before filling this page) Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, A8 B8 C8, D8 VI. Patent application line and the bottom interconnecting bolt The interface, and the step of forming at least one conductive spacer therein includes forming a spacer to contact the top surface of the class. 13. A semiconductor device interconnect structure for improving a first layer on a semiconductor device An inter-layer interconnection conductivity between the conductive line and a second layer of conductive lines, the interconnect structure includes: a) at least one conductive sidewall spacer provided on one side of the first layer of conductive lines; and b) — Interlayer interconnection, which contacts at least a part of the first conductive line and at least one conductive sidewall At least a portion of the spacers, and the first conductive lines connected to the second conductive line. 14. The semiconductor device interconnect structure as claimed in claim 13, wherein the first layer of conductive wires includes a first metal layer containing aluminum and copper and a top layer containing copper on the copper. 15. For the semiconductor device interconnection structure of the scope of application for patent item 13, the first layer of conductive lines includes a layer provided on the side wall of the first layer of conductive lines. 16. For example, the semiconductor device interconnect structure of claim 15 in which the first layer of conductive lines includes a conductive material deposited and etched, and its middle class is stopped before the conductive material is completely etched. After the conductive sidewall spacers are made, they are etched again after the etching is started. 17. The semiconductor device interconnect structure of item 13 of the patent application scope, wherein the conductive sidewall spacer comprises a directionally-etched conformal deposition conductive material. 18. The semiconductor device interconnection structure of claim 17 in the patent application scope, wherein the sidewall spacer comprises tungsten. -16- This paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling out this page). Packing. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs, A8 B8 C8 D8 VI. Application scope of patent 19. For the semiconductor device interconnection structure of the application scope of item 13, the first layer of conductive wire includes a layer of first conductive material and a layer of second conductive material provided on the first conductive material . 20. The semiconductor device interconnect structure of claim 19, wherein the layer of the first conductive material extends beyond one side of the second conductive material, and a class is formed in one side of the first conductive material . 21. The semiconductor device interconnect structure of claim 20, wherein the first conductive material includes titanium, the second conductive material includes aluminum and copper, and the sidewall spacer includes a crane. 22. For a semiconductor device interconnect structure with the scope of application for patent No. 20, the first layer of conductive wires is provided on the top of a bottom interconnect plug, and an interface between the first layer of conductive wires and the bottom interconnect plug is produced. The class has a top surface and the at least one conductive sidewall spacer contacts the top surface of the class. 23. —A method of making an interconnection between layers in a semiconductor device, the method comprising the following steps: a) by depositing at least one conductive material, depositing a photoresist on the conductive material, and patterning the photoresist And etch the conductive material to make a first layer of conductive wire on a substrate of a semiconductor device, stop the etching before the conductive material is completely etched, thereby making the layer on the first layer of conductive wire In the sidewall; b) depositing a spacer conductive material by conformal deposition and directionally etching the spacer conductive material to make at least one conductive spacer on one side of the first layer of conductive wires; _- 17 -_ This paper size applies to China National Standards (CNS) A4 (210 X 297 mm) 'Order ^, (Please read the notes on the back before filling this page) VI. Application scope of patents A8 B8 C8 D8 A small number of L springs and electricity. The structure is connected to the conductive layer of the structure. The conductive layer of the structure is connected to the conductive layer of the structure. Connected to the line conductivity layer ## 弟. One copy of the system (please read the precautions on the back before filling out this page) Binding-Printed by the Central Consumers Bureau of the Ministry of Economic Affairs Printed on the paper by the Consumer Cooperative of China Standards (CNS> A4) (210 X 297 mm)
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US5808364A (en) 1998-09-15
JPH10289949A (en) 1998-10-27
KR100301644B1 (en) 2001-10-19
JP2970757B2 (en) 1999-11-02
MY117252A (en) 2004-06-30
SG63828A1 (en) 1999-03-30
US5926738A (en) 1999-07-20
KR19980079710A (en) 1998-11-25

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